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mmc: sunxi: Support the new mode

PATCH Superseded Maxime Ripard 2 participants 4 messages Jul 12, 2017 – Jul 17, 2017

Subsystems (4)
Arm (32-bit) Arm sub-architectures MMC, SD and SDIO Arm/Allwinner sunXi SoC support

v1 of 2 Superseded Latest is v2 →

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Maxime Ripard

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#0 lore raw

PATCH 1/2 mmc: sunxi: Support the new mode

Almost all of the newer Allwinner SoCs have a new operating mode for the eMMC clocks that needs to be enabled in both the clock and the MMC controller.

Add support for it through a Kconfig option

Signed-off-by Maxime Ripard <[email protected]>
---
 arch/arm/include/asm/arch-sunxi/mmc.h |  9 ++++++---
 drivers/mmc/Kconfig                   |  3 +++
 drivers/mmc/sunxi_mmc.c               | 26 +++++++++++++++++++++++---
 3 files changed, 32 insertions(+), 6 deletions(-)
arch/arm/include/asm/arch-sunxi/mmc.h +6 -3
index cb52e648731c..0c2d496295ff 100644
@@ -35,16 +35,19 @@ struct sunxi_mmc {
 	u32 cbcr;		/* 0x48 CIU byte count */
 	u32 bbcr;		/* 0x4c BIU byte count */
 	u32 dbgc;		/* 0x50 debug enable */
-	u32 res0[11];
+	u32 res0;		/* 0x54 reserved */
+	u32 a12a;		/* 0x58 Auto command 12 argument */
+	u32 ntsr;		/* 0x5c	New timing set register */
+	u32 res1[8];
 	u32 dmac;		/* 0x80 internal DMA control */
 	u32 dlba;		/* 0x84 internal DMA descr list base address */
 	u32 idst;		/* 0x88 internal DMA status */
 	u32 idie;		/* 0x8c internal DMA interrupt enable */
 	u32 chda;		/* 0x90 */
 	u32 cbda;		/* 0x94 */
-	u32 res1[26];
+	u32 res2[26];
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-	u32 res2[64];
+	u32 res3[64];
 #endif
 	u32 fifo;		/* 0x100 / 0x200 FIFO access address */
 };
drivers/mmc/Kconfig +3 -0
index 82b8d756867c..203f59547100 100644
@@ -368,6 +368,9 @@ config MMC_SUNXI
 	  This selects support for the SD/MMC Host Controller on
 	  Allwinner sunxi SoCs.
 
+config MMC_SUNXI_HAS_NEW_MODE
+	bool
+
 config GENERIC_ATMEL_MCI
 	bool "Atmel Multimedia Card Interface support"
 	depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91
drivers/mmc/sunxi_mmc.c +23 -3
index fd3fc2af40a0..68750f3832b6 100644
@@ -87,6 +87,20 @@ static int mmc_resource_init(int sdc_no)
 static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
 {
 	unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
+	bool new_mode = false;
+	u32 val = 0;
+
+#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
+	if (mmchost->mmc_no == 2)
+		new_mode = true;
+#endif
+
+	/*
+	 * The MMC clock has an extra /2 post-divider when operating in the new
+	 * mode.
+	 */
+	if (new_mode)
+		hz = hz * 2;
 
 	if (hz <= 24000000) {
 		pll = CCM_MMC_CTRL_OSCM24;

@@ -143,9 +157,15 @@ static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
 #endif
 	}
 
-	writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) |
-	       CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
-	       CCM_MMC_CTRL_M(div), mmchost->mclkreg);
+	if (new_mode) {
+		val = BIT(30);
+		writel(BIT(31), &mmchost->reg->ntsr);
+	} else {
+		val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
+	}
+
+	writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_M(div) | val,
+	       mmchost->mclkreg);
 
 	debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
 	      mmchost->mmc_no, hz, pll_hz, 1u << n, div,
Signature · 1 line
2.13.0
author
#1 lore raw

PATCH 2/2 sunxi: Enable MMC new mode for A83T

The eMMC controller for the A83T uses the new operating mode. Enable it.

Signed-off-by Maxime Ripard <[email protected]>
---
 arch/arm/mach-sunxi/Kconfig | 1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-sunxi/Kconfig +1 -0
index bd3e7d3b3f20..867ef51918be 100644
@@ -122,6 +122,7 @@ config MACH_SUN8I_A83T
 	bool "sun8i (Allwinner A83T)"
 	select CPU_V7
 	select SUNXI_GEN_SUN6I
+	select MMC_SUNXI_HAS_NEW_MODE
 	select SUPPORT_SPL
 
 config MACH_SUN8I_H3
Signature · 1 line
2.13.0
#2 lore raw

PATCH 1/2 mmc: sunxi: Support the new mode

In reply to Maxime Ripard
Quoted 3 lines · On Wed, 12 Jul 2017 16:48:37 +0200 Maxime Ripard…

Almost all of the newer Allwinner SoCs have a new operating mode for the eMMC clocks that needs to be enabled in both the clock and the MMC controller.

Can we have a bit better description in the commit message about what is new about this mode? Does it bring us some visible improvements for the end users? Why do we need to enable it?

Quoted 56 lines

Add support for it through a Kconfig option

Signed-off-by Maxime Ripard <[email protected]>
---
 arch/arm/include/asm/arch-sunxi/mmc.h |  9 ++++++---
 drivers/mmc/Kconfig                   |  3 +++
 drivers/mmc/sunxi_mmc.c               | 26 +++++++++++++++++++++++---
 3 files changed, 32 insertions(+), 6 deletions(-)
arch/arm/include/asm/arch-sunxi/mmc.h +6 -3
index cb52e648731c..0c2d496295ff 100644
@@ -35,16 +35,19 @@ struct sunxi_mmc {
 	u32 cbcr;		/* 0x48 CIU byte count */
 	u32 bbcr;		/* 0x4c BIU byte count */
 	u32 dbgc;		/* 0x50 debug enable */
-	u32 res0[11];
+	u32 res0;		/* 0x54 reserved */
+	u32 a12a;		/* 0x58 Auto command 12 argument */
+	u32 ntsr;		/* 0x5c	New timing set register */
+	u32 res1[8];
 	u32 dmac;		/* 0x80 internal DMA control */
 	u32 dlba;		/* 0x84 internal DMA descr list base address */
 	u32 idst;		/* 0x88 internal DMA status */
 	u32 idie;		/* 0x8c internal DMA interrupt enable */
 	u32 chda;		/* 0x90 */
 	u32 cbda;		/* 0x94 */
-	u32 res1[26];
+	u32 res2[26];
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-	u32 res2[64];
+	u32 res3[64];
 #endif
 	u32 fifo;		/* 0x100 / 0x200 FIFO access address */
 };
drivers/mmc/Kconfig +3 -0
index 82b8d756867c..203f59547100 100644
@@ -368,6 +368,9 @@ config MMC_SUNXI
 	  This selects support for the SD/MMC Host Controller on
 	  Allwinner sunxi SoCs.
 
+config MMC_SUNXI_HAS_NEW_MODE
+	bool
+
 config GENERIC_ATMEL_MCI
 	bool "Atmel Multimedia Card Interface support"
 	depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91
drivers/mmc/sunxi_mmc.c +0 -0
index fd3fc2af40a0..68750f3832b6 100644

drivers/mmc/sunxi_mmc.c static int mmc_resource_init(int sdc_no) · line 96

Quoted 10 lines
drivers/mmc/sunxi_mmc.c +7 -0
@@ -87,6 +87,20 @@ static int mmc_resource_init(int sdc_no)
 static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
 {
 	unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
+	bool new_mode = false;
+	u32 val = 0;
+
+#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
+	if (mmchost->mmc_no == 2)
+		new_mode = true;
+#endif

Please change this ifdef to use:

if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE))

Quoted 11 lines
drivers/mmc/sunxi_mmc.c +7 -0
+
+	/*
+	 * The MMC clock has an extra /2 post-divider when operating in the new
+	 * mode.
+	 */
+	if (new_mode)
+		hz = hz * 2;
 
 	if (hz <= 24000000) {
 		pll = CCM_MMC_CTRL_OSCM24;

drivers/mmc/sunxi_mmc.c static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz) · line 161

Quoted 8 lines
drivers/mmc/sunxi_mmc.c +2 -3
@@ -143,9 +157,15 @@ static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
 #endif
 	}
 
-	writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) |
-	       CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
-	       CCM_MMC_CTRL_M(div), mmchost->mclkreg);
+	if (new_mode) {
+		val = BIT(30);

Does this BIT(30) have a name?

drivers/mmc/sunxi_mmc.c static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz) · line 162

Quoted 1 line
drivers/mmc/sunxi_mmc.c +1 -0
+		writel(BIT(31), &mmchost->reg->ntsr);

The same question here.

Quoted 9 lines
drivers/mmc/sunxi_mmc.c +6 -0
+	} else {
+		val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
+	}
+
+	writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_M(div) | val,
+	       mmchost->mclkreg);
 
 	debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
 	      mmchost->mmc_no, hz, pll_hz, 1u << n, div,
Signature · 2 lines
Best regards,
Siarhei Siamashka
author
#3 lore raw

PATCH 1/2 mmc: sunxi: Support the new mode

Quoted 10 lines · Siarhei Siamashka
Quoted 3 lines · On Wed, 12 Jul 2017 16:48:37 +0200 Maxime Ripard…

Almost all of the newer Allwinner SoCs have a new operating mode for the eMMC clocks that needs to be enabled in both the clock and the MMC controller.

Can we have a bit better description in the commit message about what is new about this mode? Does it bring us some visible improvements for the end users? Why do we need to enable it?

I wish I could detail what exactly changes between the old and new mode, but I have no idea. It seems to be different enough that it makes eMMC works on the A83T. We also had some commands that were failing in SDIO on the A64 if not switched to the new mode. But that's just empirical.

Quoted 69 lines
Quoted 56 lines

Add support for it through a Kconfig option

Signed-off-by Maxime Ripard <[email protected]>
---
 arch/arm/include/asm/arch-sunxi/mmc.h |  9 ++++++---
 drivers/mmc/Kconfig                   |  3 +++
 drivers/mmc/sunxi_mmc.c               | 26 +++++++++++++++++++++++---
 3 files changed, 32 insertions(+), 6 deletions(-)
arch/arm/include/asm/arch-sunxi/mmc.h +6 -3
index cb52e648731c..0c2d496295ff 100644
@@ -35,16 +35,19 @@ struct sunxi_mmc {
 	u32 cbcr;		/* 0x48 CIU byte count */
 	u32 bbcr;		/* 0x4c BIU byte count */
 	u32 dbgc;		/* 0x50 debug enable */
-	u32 res0[11];
+	u32 res0;		/* 0x54 reserved */
+	u32 a12a;		/* 0x58 Auto command 12 argument */
+	u32 ntsr;		/* 0x5c	New timing set register */
+	u32 res1[8];
 	u32 dmac;		/* 0x80 internal DMA control */
 	u32 dlba;		/* 0x84 internal DMA descr list base address */
 	u32 idst;		/* 0x88 internal DMA status */
 	u32 idie;		/* 0x8c internal DMA interrupt enable */
 	u32 chda;		/* 0x90 */
 	u32 cbda;		/* 0x94 */
-	u32 res1[26];
+	u32 res2[26];
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-	u32 res2[64];
+	u32 res3[64];
 #endif
 	u32 fifo;		/* 0x100 / 0x200 FIFO access address */
 };
drivers/mmc/Kconfig +3 -0
index 82b8d756867c..203f59547100 100644
@@ -368,6 +368,9 @@ config MMC_SUNXI
 	  This selects support for the SD/MMC Host Controller on
 	  Allwinner sunxi SoCs.
 
+config MMC_SUNXI_HAS_NEW_MODE
+	bool
+
 config GENERIC_ATMEL_MCI
 	bool "Atmel Multimedia Card Interface support"
 	depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91
drivers/mmc/sunxi_mmc.c +0 -0
index fd3fc2af40a0..68750f3832b6 100644

drivers/mmc/sunxi_mmc.c static int mmc_resource_init(int sdc_no) · line 96

Quoted 10 lines
drivers/mmc/sunxi_mmc.c +7 -0
@@ -87,6 +87,20 @@ static int mmc_resource_init(int sdc_no)
 static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
 {
 	unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
+	bool new_mode = false;
+	u32 val = 0;
+
+#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
+	if (mmchost->mmc_no == 2)
+		new_mode = true;
+#endif

Please change this ifdef to use:

Quoted 1 line

if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE))

Ok.

Quoted 22 lines
Quoted 11 lines
drivers/mmc/sunxi_mmc.c +7 -0
+
+	/*
+	 * The MMC clock has an extra /2 post-divider when operating in the new
+	 * mode.
+	 */
+	if (new_mode)
+		hz = hz * 2;
 
 	if (hz <= 24000000) {
 		pll = CCM_MMC_CTRL_OSCM24;

drivers/mmc/sunxi_mmc.c static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz) · line 161

Quoted 8 lines
drivers/mmc/sunxi_mmc.c +2 -3
@@ -143,9 +157,15 @@ static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
 #endif
 	}
 
-	writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) |
-	       CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
-	       CCM_MMC_CTRL_M(div), mmchost->mclkreg);
+	if (new_mode) {
+		val = BIT(30);

Does this BIT(30) have a name?

Quoted 3 lines

drivers/mmc/sunxi_mmc.c static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz) · line 162

Quoted 1 line
drivers/mmc/sunxi_mmc.c +1 -0
+		writel(BIT(31), &mmchost->reg->ntsr);

The same question here.

I'll add defines. Thanks!
Maxime

Signature · 10 lines
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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