infra: add support for MIPS NaN

PATCH New Vicente Olivert Riera 2 participants 11 messages Jun 28, 2017 – Jul 18, 2017

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Vicente Olivert Riera

author

2017-06-28 15:17 UTC #0 lore raw

PATCH v6 1/4 infra: add support for MIPS NaN

MIPS supports two different NaN encodings, legacy and 2008. Information about MIPS NaN encodings can be found here:

https://sourceware.org/binutils/docs/as/MIPS-NaN-Encodings.html

NaN legacy is the only option available for R2 cores and older. NaN 2008 is the only option available for R6 cores.
R5 cores can have either NaN legacy or NaN 2008, depending on the implementation. So, if the user selects a generic R5 target architecture variant, we show a choice menu with both options available. For well known R5 cores we directly select the NaN enconding they use.

Signed-off-by Vicente Olivert Riera <[email protected]>

---
Changes v4 -> v6:
- Nothing
Changes v3 -> v4:
- Do not have a default list for NAN options. Instead, select them from the BR2_MIPS_CPU_* options. (Arnout)
- uclibc/Config.in: use the new NAN options from arch/Config.in.mips
Changes v2 -> v3:
- Nothing
Changes v1 -> v2:
- Define config symbol in arch/Config.in
- Change string "NAN" to "NaN"

---
 arch/Config.in                                     |  3 ++
 arch/Config.in.mips                                | 36 ++++++++++++++++++++++
 package/gcc/gcc.mk                                 |  7 +++++
 package/uclibc/Config.in                           |  4 +--
 .../toolchain-external/pkg-toolchain-external.mk   |  5 +++
 toolchain/toolchain-wrapper.c                      |  3 ++
 6 files changed, 56 insertions(+), 2 deletions(-)

arch/Config.in +3 -0

index 50377a9af..e921879d0 100644
@@ -264,6 +264,9 @@ config BR2_GCC_TARGET_ARCH
 config BR2_GCC_TARGET_ABI
 	string
 
+config BR2_GCC_TARGET_NAN
+	string
+
 config BR2_GCC_TARGET_CPU
 	string

arch/Config.in.mips +36 -0

index 4e9ad12ad..76ae44714 100644
@@ -1,20 +1,26 @@
 # mips default CPU ISAs
 config BR2_MIPS_CPU_MIPS32
 	bool
+	select BR2_MIPS_NAN_LEGACY
 config BR2_MIPS_CPU_MIPS32R2
 	bool
+	select BR2_MIPS_NAN_LEGACY
 config BR2_MIPS_CPU_MIPS32R5
 	bool
 config BR2_MIPS_CPU_MIPS32R6
 	bool
+	select BR2_MIPS_NAN_2008
 config BR2_MIPS_CPU_MIPS64
 	bool
+	select BR2_MIPS_NAN_LEGACY
 config BR2_MIPS_CPU_MIPS64R2
 	bool
+	select BR2_MIPS_NAN_LEGACY
 config BR2_MIPS_CPU_MIPS64R5
 	bool
 config BR2_MIPS_CPU_MIPS64R6
 	bool
+	select BR2_MIPS_NAN_2008
 
 choice
 	prompt "Target Architecture Variant"

@@ -51,6 +57,7 @@ config BR2_mips_m5150
 	bool "M5150"
 	depends on !BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS32R5
+	select BR2_MIPS_NAN_2008
 config BR2_mips_m6250
 	bool "M6250"
 	depends on !BR2_ARCH_IS_64

@@ -59,6 +66,7 @@ config BR2_mips_p5600
 	bool "P5600"
 	depends on !BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS32R5
+	select BR2_MIPS_NAN_2008
 config BR2_mips_xburst
 	bool "XBurst"
 	depends on !BR2_ARCH_IS_64

@@ -126,6 +134,34 @@ config BR2_MIPS_SOFT_FLOAT
 	  floating point functions, then everything will need to be
 	  compiled with soft floating point support (-msoft-float).
 
+config BR2_MIPS_NAN_LEGACY
+	bool
+
+config BR2_MIPS_NAN_2008
+	bool
+
+choice
+	prompt "Target NaN"
+	depends on BR2_mips_32r5 || BR2_mips_64r5
+	default BR2_MIPS_ENABLE_NAN_2008
+
+	help
+	  NaN encoding to be used
+
+config BR2_MIPS_ENABLE_NAN_LEGACY
+	bool "legacy"
+	select BR2_MIPS_NAN_LEGACY
+
+config BR2_MIPS_ENABLE_NAN_2008
+	bool "2008"
+	depends on !BR2_MIPS_SOFT_FLOAT
+	select BR2_MIPS_NAN_2008
+endchoice
+
+config BR2_GCC_TARGET_NAN
+	default "legacy"	if BR2_MIPS_NAN_LEGACY
+	default "2008"		if BR2_MIPS_NAN_2008
+
 config BR2_ARCH
 	default "mips"		if BR2_mips
 	default "mipsel"	if BR2_mipsel

package/gcc/gcc.mk +7 -0

index b52f9456b..c0249cd50 100644
@@ -204,6 +204,9 @@ endif
 ifneq ($(call qstrip,$(BR2_GCC_TARGET_ABI)),)
 HOST_GCC_COMMON_CONF_OPTS += --with-abi=$(BR2_GCC_TARGET_ABI)
 endif
+ifneq ($(call qstrip,$(BR2_GCC_TARGET_NAN)),)
+HOST_GCC_COMMON_CONF_OPTS += --with-nan=$(BR2_GCC_TARGET_NAN)
+endif
 ifneq ($(call qstrip,$(BR2_GCC_TARGET_CPU)),)
 ifneq ($(call qstrip,$(BR2_GCC_TARGET_CPU_REVISION)),)
 HOST_GCC_COMMON_CONF_OPTS += --with-cpu=$(call qstrip,$(BR2_GCC_TARGET_CPU)-$(BR2_GCC_TARGET_CPU_REVISION))

@@ -254,6 +257,7 @@ HOST_GCC_COMMON_WRAPPER_TARGET_CPU := $(call qstrip,$(BR2_GCC_TARGET_CPU)-$(BR2_
 endif
 HOST_GCC_COMMON_WRAPPER_TARGET_ARCH := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
 HOST_GCC_COMMON_WRAPPER_TARGET_ABI := $(call qstrip,$(BR2_GCC_TARGET_ABI))
+HOST_GCC_COMMON_WRAPPER_TARGET_NAN := $(call qstrip,$(BR2_GCC_TARGET_NAN))
 HOST_GCC_COMMON_WRAPPER_TARGET_FPU := $(call qstrip,$(BR2_GCC_TARGET_FPU))
 HOST_GCC_COMMON_WRAPPER_TARGET_FLOAT_ABI := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))
 HOST_GCC_COMMON_WRAPPER_TARGET_MODE := $(call qstrip,$(BR2_GCC_TARGET_MODE))

@@ -267,6 +271,9 @@ endif
 ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_ABI),)
 HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_ABI='"$(HOST_GCC_COMMON_WRAPPER_TARGET_ABI)"'
 endif
+ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_NAN),)
+HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_NAN='"$(HOST_GCC_COMMON_WRAPPER_TARGET_NAN)"'
+endif
 ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_FPU),)
 HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_FPU='"$(HOST_GCC_COMMON_WRAPPER_TARGET_FPU)"'
 endif

package/uclibc/Config.in +2 -2

index b0b0b010f..3b4f91da9 100644
@@ -123,8 +123,8 @@ config BR2_UCLIBC_MIPS_ABI
 
 config BR2_UCLIBC_MIPS_NAN
 	string
-	default "LEGACY" if BR2_MIPS_CPU_MIPS32 || BR2_MIPS_CPU_MIPS64
-	default "2008" if BR2_MIPS_CPU_MIPS32R6 || BR2_MIPS_CPU_MIPS64R6
+	default "LEGACY" if BR2_MIPS_NAN_LEGACY
+	default "2008" if BR2_MIPS_NAN_2008
 	depends on BR2_UCLIBC_TARGET_ARCH = "mips"
 
 config BR2_UCLIBC_SH_TYPE

toolchain/toolchain-external/pkg-toolchain-external.mk +5 -0

index 826934505..29c0aade1 100644
@@ -156,6 +156,7 @@ CC_TARGET_CPU_ := $(call qstrip,$(BR2_GCC_TARGET_CPU)-$(BR2_GCC_TARGET_CPU_REVIS
 endif
 CC_TARGET_ARCH_ := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
 CC_TARGET_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_ABI))
+CC_TARGET_NAN_ := $(call qstrip,$(BR2_GCC_TARGET_NAN))
 CC_TARGET_FPU_ := $(call qstrip,$(BR2_GCC_TARGET_FPU))
 CC_TARGET_FLOAT_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))
 CC_TARGET_MODE_ := $(call qstrip,$(BR2_GCC_TARGET_MODE))

@@ -178,6 +179,10 @@ ifneq ($(CC_TARGET_ABI_),)
 TOOLCHAIN_EXTERNAL_CFLAGS += -mabi=$(CC_TARGET_ABI_)
 TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_ABI='"$(CC_TARGET_ABI_)"'
 endif
+ifneq ($(CC_TARGET_NAN_),)
+TOOLCHAIN_EXTERNAL_CFLAGS += -mnan=$(CC_TARGET_NAN_)
+TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_NAN='"$(CC_TARGET_NAN_)"'
+endif
 ifneq ($(CC_TARGET_FPU_),)
 TOOLCHAIN_EXTERNAL_CFLAGS += -mfpu=$(CC_TARGET_FPU_)
 TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_FPU='"$(CC_TARGET_FPU_)"'

toolchain/toolchain-wrapper.c +3 -0

index 100aa181c..28066e425 100644
@@ -51,6 +51,9 @@ static char *predef_args[] = {
 #ifdef BR_ABI
 	"-mabi=" BR_ABI,
 #endif
+#ifdef BR_NAN
+	"-mnan=" BR_NAN,
+#endif
 #ifdef BR_FPU
 	"-mfpu=" BR_FPU,
 #endif

Signature · 1 line

2.13.0

Vicente Olivert Riera

author

2017-06-28 15:17 UTC #1 lore raw

PATCH v6 2/4 infra: add support for MIPS32 FP mode

MIPS32 support different FP modes (32,xx,64), so give the user the opportunity to choose between them. That will cause host-gcc to be built using the --with-fp-32=[32|xx|64] configure option. Also the -mfp[32|xx|64] gcc option will be added to TARGET_CFLAGS and to the toolchain wrapper.

FP mode option shouldn't be used for soft-float, so we add logic in the toolchain wrapper if -msoft-float is among the arguments in order to not append the -fp[[32|xx|64] option, otherwise the compilation may fail.

Information about FP modes here:

- https://sourceware.org/binutils/docs/as/MIPS-Options.html
- https://dmz-portal.imgtec.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking#5._Generating_modeless_code

Signed-off-by Vicente Olivert Riera <[email protected]>

---
Changes v3 -> v6:
- Nothing.
Changes v2 -> v3:
- Change toolchain-wrapper.c to not add FP32 mode option when -msoft-float is used.
Changes v1 -> v2:
- Nothing. Patch introduced in v2.

---
 arch/Config.in                                     |  3 +++
 arch/Config.in.mips                                | 25 ++++++++++++++++++++++
 package/gcc/gcc.mk                                 |  7 ++++++
 .../toolchain-external/pkg-toolchain-external.mk   |  5 +++++
 toolchain/toolchain-wrapper.c                      | 10 +++++++++
 5 files changed, 50 insertions(+)

arch/Config.in +3 -0

index e921879d0..f385745e4 100644
@@ -267,6 +267,9 @@ config BR2_GCC_TARGET_ABI
 config BR2_GCC_TARGET_NAN
 	string
 
+config BR2_GCC_TARGET_FP32_MODE
+	string
+
 config BR2_GCC_TARGET_CPU
 	string

arch/Config.in.mips +25 -0

index 76ae44714..b779fc7f5 100644
@@ -134,6 +134,31 @@ config BR2_MIPS_SOFT_FLOAT
 	  floating point functions, then everything will need to be
 	  compiled with soft floating point support (-msoft-float).
 
+choice
+	prompt "FP mode"
+	depends on !BR2_ARCH_IS_64 && !BR2_MIPS_SOFT_FLOAT
+	default BR2_MIPS_FP32_MODE_XX
+
+	help
+	  FP mode to be used
+
+config BR2_MIPS_FP32_MODE_32
+	bool "32"
+	depends on !BR2_MIPS_CPU_MIPS32R6
+
+config BR2_MIPS_FP32_MODE_XX
+	bool "xx"
+
+config BR2_MIPS_FP32_MODE_64
+	bool "64"
+	depends on !BR2_MIPS_CPU_MIPS32
+endchoice
+
+config BR2_GCC_TARGET_FP32_MODE
+	default "32"	if BR2_MIPS_FP32_MODE_32
+	default "xx"	if BR2_MIPS_FP32_MODE_XX
+	default "64"	if BR2_MIPS_FP32_MODE_64
+
 config BR2_MIPS_NAN_LEGACY
 	bool

package/gcc/gcc.mk +7 -0

index c0249cd50..4edcf5280 100644
@@ -207,6 +207,9 @@ endif
 ifneq ($(call qstrip,$(BR2_GCC_TARGET_NAN)),)
 HOST_GCC_COMMON_CONF_OPTS += --with-nan=$(BR2_GCC_TARGET_NAN)
 endif
+ifneq ($(call qstrip,$(BR2_GCC_TARGET_FP32_MODE)),)
+HOST_GCC_COMMON_CONF_OPTS += --with-fp-32=$(BR2_GCC_TARGET_FP32_MODE)
+endif
 ifneq ($(call qstrip,$(BR2_GCC_TARGET_CPU)),)
 ifneq ($(call qstrip,$(BR2_GCC_TARGET_CPU_REVISION)),)
 HOST_GCC_COMMON_CONF_OPTS += --with-cpu=$(call qstrip,$(BR2_GCC_TARGET_CPU)-$(BR2_GCC_TARGET_CPU_REVISION))

@@ -258,6 +261,7 @@ endif
 HOST_GCC_COMMON_WRAPPER_TARGET_ARCH := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
 HOST_GCC_COMMON_WRAPPER_TARGET_ABI := $(call qstrip,$(BR2_GCC_TARGET_ABI))
 HOST_GCC_COMMON_WRAPPER_TARGET_NAN := $(call qstrip,$(BR2_GCC_TARGET_NAN))
+HOST_GCC_COMMON_WRAPPER_TARGET_FP32_MODE := $(call qstrip,$(BR2_GCC_TARGET_FP32_MODE))
 HOST_GCC_COMMON_WRAPPER_TARGET_FPU := $(call qstrip,$(BR2_GCC_TARGET_FPU))
 HOST_GCC_COMMON_WRAPPER_TARGET_FLOAT_ABI := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))
 HOST_GCC_COMMON_WRAPPER_TARGET_MODE := $(call qstrip,$(BR2_GCC_TARGET_MODE))

@@ -274,6 +278,9 @@ endif
 ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_NAN),)
 HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_NAN='"$(HOST_GCC_COMMON_WRAPPER_TARGET_NAN)"'
 endif
+ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_FP32_MODE),)
+HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_FP32_MODE='"$(HOST_GCC_COMMON_WRAPPER_TARGET_FP32_MODE)"'
+endif
 ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_FPU),)
 HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_FPU='"$(HOST_GCC_COMMON_WRAPPER_TARGET_FPU)"'
 endif

toolchain/toolchain-external/pkg-toolchain-external.mk +5 -0

index 29c0aade1..ccb298bec 100644
@@ -157,6 +157,7 @@ endif
 CC_TARGET_ARCH_ := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
 CC_TARGET_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_ABI))
 CC_TARGET_NAN_ := $(call qstrip,$(BR2_GCC_TARGET_NAN))
+CC_TARGET_FP32_MODE_ := $(call qstrip,$(BR2_GCC_TARGET_FP32_MODE))
 CC_TARGET_FPU_ := $(call qstrip,$(BR2_GCC_TARGET_FPU))
 CC_TARGET_FLOAT_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))
 CC_TARGET_MODE_ := $(call qstrip,$(BR2_GCC_TARGET_MODE))

@@ -183,6 +184,10 @@ ifneq ($(CC_TARGET_NAN_),)
 TOOLCHAIN_EXTERNAL_CFLAGS += -mnan=$(CC_TARGET_NAN_)
 TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_NAN='"$(CC_TARGET_NAN_)"'
 endif
+ifneq ($(CC_TARGET_FP32_MODE_),)
+TOOLCHAIN_EXTERNAL_CFLAGS += -mfp$(CC_TARGET_FP32_MODE_)
+TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_FP32_MODE='"$(CC_TARGET_FP32_MODE_)"'
+endif
 ifneq ($(CC_TARGET_FPU_),)
 TOOLCHAIN_EXTERNAL_CFLAGS += -mfpu=$(CC_TARGET_FPU_)
 TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_FPU='"$(CC_TARGET_FPU_)"'

toolchain/toolchain-wrapper.c +10 -0

index 28066e425..761e72541 100644
@@ -254,6 +254,16 @@ int main(int argc, char **argv)
 		*cur++ = "-mfloat-abi=" BR_FLOAT_ABI;
 #endif
 
+#ifdef BR_FP32_MODE
+	/* add fp32 mode if soft-float is not args or hard-float overrides soft-float */
+	int add_fp32_mode = 1;
+	for (i = 1; i < argc; i++) {
+		if (strcmp(argv[i], "-msoft-float") == 0) add_fp32_mode = 0;
+		else if (strcmp(argv[i], "-mhard-float") == 0) add_fp32_mode = 1;
+	}
+	if (add_fp32_mode == 1) *cur++ = "-mfp" BR_FP32_MODE;
+#endif
+
 #if defined(BR_ARCH) || \
     defined(BR_CPU)
 	/* Add our -march/cpu flags, but only if none of

Signature · 1 line

2.13.0

Thomas Petazzoni

Applied

2017-07-16 15:32 UTC #2 lore raw

PATCH v6 2/4 infra: add support for MIPS32 FP mode

Hello,

Quoted 24 lines · Vicente Olivert Riera

MIPS32 support different FP modes (32,xx,64), so give the user the opportunity to choose between them. That will cause host-gcc to be built using the --with-fp-32=[32|xx|64] configure option. Also the -mfp[32|xx|64] gcc option will be added to TARGET_CFLAGS and to the toolchain wrapper.
FP mode option shouldn't be used for soft-float, so we add logic in the toolchain wrapper if -msoft-float is among the arguments in order to not append the -fp[[32|xx|64] option, otherwise the compilation may fail.
Information about FP modes here:
- https://sourceware.org/binutils/docs/as/MIPS-Options.html
- https://dmz-portal.imgtec.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking#5._Generating_modeless_code
Signed-off-by Vicente Olivert Riera <[email protected]>
---
Changes v3 -> v6:
- Nothing.
Changes v2 -> v3:
- Change toolchain-wrapper.c to not add FP32 mode option when -msoft-float is used.
Changes v1 -> v2:
- Nothing. Patch introduced in v2.

Quoted 7 lines

---
 arch/Config.in                                     |  3 +++
 arch/Config.in.mips                                | 25 ++++++++++++++++++++++
 package/gcc/gcc.mk                                 |  7 ++++++
 .../toolchain-external/pkg-toolchain-external.mk   |  5 +++++
 toolchain/toolchain-wrapper.c                      | 10 +++++++++
 5 files changed, 50 insertions(+)

I've applied your patch. Here as well, a follow-up patch to improve the Config.in help text would be good.

Also, the gcc documentation says:

--without-odd-spreg-32

On MIPS targets, set the -mno-odd-spreg option by default when using the o32 ABI. This is normally used in conjunction with --with-fp-32=64 in order to target the o32 FP64A ABI extension.

Should we use this additional option when FP32 mode is 64 ?

Thanks!

Thomas

Signature · 3 lines

Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Vicente Olivert Riera

author

2017-06-28 15:17 UTC #3 lore raw

PATCH v6 3/4 infra: add MIPS DSP support

In reply to Vicente Olivert Riera

This patch adds support for the MIPS DSP ASE. They come in three versions, DSP (r1), DSPr2 and DSPr3. Each one of them is a superset of the other, so selecting DSPr2 will imply DSP (r1) as well, and selecting DSPr3 will imply both DSP (r1) and DSPr2 as well.

For generic target architecture variants we let the user choose between the different compatible versions. For well known cores the user can only choose the DSP version that specific core would implement, or none, since implementing the DSP module in a core may be optional.

DSP (r1) and DSPr2 are available since MIPS release version 2. DSPr3 is only available since MIPS release version 6.

Signed-off-by Vicente Olivert Riera <[email protected]>

---
Changes v5 -> v6:
- Ensure -mno-dsp is used when no DSP support is selected.
Changes v4 -> v5:
- Add BR2_GCC_TARGET_DSP in arch/Config.in
Changes v1 -> v4:
- Nothing. Patch introduced in v3.

---
 arch/Config.in                                     |  3 +
 arch/Config.in.mips                                | 70 ++++++++++++++++++++++
 .../toolchain-external/pkg-toolchain-external.mk   |  5 ++
 toolchain/toolchain-wrapper.c                      |  3 +
 4 files changed, 81 insertions(+)

arch/Config.in +3 -0

index f385745e4..1183e8fda 100644
@@ -270,6 +270,9 @@ config BR2_GCC_TARGET_NAN
 config BR2_GCC_TARGET_FP32_MODE
 	string
 
+config BR2_GCC_TARGET_DSP
+	string
+
 config BR2_GCC_TARGET_CPU
 	string

arch/Config.in.mips +70 -0

123 lines not on this page · raw message

toolchain/toolchain-external/pkg-toolchain-external.mk +5 -0

index ccb298bec..ce3a48db8 100644
@@ -157,6 +157,7 @@ endif
 CC_TARGET_ARCH_ := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
 CC_TARGET_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_ABI))
 CC_TARGET_NAN_ := $(call qstrip,$(BR2_GCC_TARGET_NAN))
+CC_TARGET_DSP_ := $(call qstrip,$(BR2_GCC_TARGET_DSP))
 CC_TARGET_FP32_MODE_ := $(call qstrip,$(BR2_GCC_TARGET_FP32_MODE))
 CC_TARGET_FPU_ := $(call qstrip,$(BR2_GCC_TARGET_FPU))
 CC_TARGET_FLOAT_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))

@@ -184,6 +185,10 @@ ifneq ($(CC_TARGET_NAN_),)
 TOOLCHAIN_EXTERNAL_CFLAGS += -mnan=$(CC_TARGET_NAN_)
 TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_NAN='"$(CC_TARGET_NAN_)"'
 endif
+ifneq ($(CC_TARGET_DSP_),)
+TOOLCHAIN_EXTERNAL_CFLAGS += -m$(CC_TARGET_DSP_)
+TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_DSP='"$(CC_TARGET_DSP_)"'
+endif
 ifneq ($(CC_TARGET_FP32_MODE_),)
 TOOLCHAIN_EXTERNAL_CFLAGS += -mfp$(CC_TARGET_FP32_MODE_)
 TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_FP32_MODE='"$(CC_TARGET_FP32_MODE_)"'

toolchain/toolchain-wrapper.c +3 -0

index 761e72541..670e00884 100644
@@ -54,6 +54,9 @@ static char *predef_args[] = {
 #ifdef BR_NAN
 	"-mnan=" BR_NAN,
 #endif
+#ifdef BR_DSP
+	"-m" BR_DSP,
+#endif
 #ifdef BR_FPU
 	"-mfpu=" BR_FPU,
 #endif

Signature · 1 line

2.13.0

Vicente Olivert Riera

author

2017-06-28 15:17 UTC #4 lore raw

PATCH v6 4/4 infra: add support for MIPS MSA

In reply to Vicente Olivert Riera

This patch adds support for MIPS SIMD Architecture (MSA) extension. This feature is available since MIPS release version 5 and is mutually exclusive with the MIPS DSP extension.

Signed-off-by Vicente Olivert Riera <[email protected]>

---
Changes v5 -> v6:
- Define BR2_GCC_TARGET_MSA and make use of it. This way we will ensure that -mno-msa is used when MSA support is not selected.
Changes v1 -> v5:
- Nothing. Patch introduced in v3.

---
 arch/Config.in                                     |  3 +++
 arch/Config.in.mips                                | 25 ++++++++++++++++++++++
 .../toolchain-external/pkg-toolchain-external.mk   |  5 +++++
 toolchain/toolchain-wrapper.c                      |  3 +++
 4 files changed, 36 insertions(+)

arch/Config.in +3 -0

index 1183e8fda..e69d9f5d6 100644
@@ -273,6 +273,9 @@ config BR2_GCC_TARGET_FP32_MODE
 config BR2_GCC_TARGET_DSP
 	string
 
+config BR2_GCC_TARGET_MSA
+	string
+
 config BR2_GCC_TARGET_CPU
 	string

arch/Config.in.mips +25 -0

index 16132aa1d..7a267b0d4 100644
@@ -29,6 +29,8 @@ config BR2_MIPS_CPU_HAS_DSP_R2
 	bool
 config BR2_MIPS_CPU_HAS_DSP_R3
 	bool
+config BR2_MIPS_CPU_HAS_MSA
+	bool
 
 # some cpu features are optional depending on the core
 config BR2_MIPS_CPU_MAYBE_HAS_DSP_R1

@@ -37,6 +39,8 @@ config BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
 	bool
 config BR2_MIPS_CPU_MAYBE_HAS_DSP_R3
 	bool
+config BR2_MIPS_CPU_MAYBE_HAS_MSA
+	bool
 
 choice
 	prompt "Target Architecture Variant"

@@ -65,6 +69,7 @@ config BR2_mips_32r5
 	select BR2_MIPS_CPU_MIPS32R5
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 config BR2_mips_32r6
 	bool "Generic MIPS32R6"
 	depends on !BR2_ARCH_IS_64

@@ -72,6 +77,7 @@ config BR2_mips_32r6
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R3
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 config BR2_mips_interaptiv
 	bool "interAptiv"
 	depends on !BR2_ARCH_IS_64

@@ -93,6 +99,7 @@ config BR2_mips_p5600
 	depends on !BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS32R5
 	select BR2_MIPS_NAN_2008
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 config BR2_mips_xburst
 	bool "XBurst"
 	depends on !BR2_ARCH_IS_64

@@ -122,6 +129,7 @@ config BR2_mips_64r5
 	select BR2_MIPS_CPU_MIPS64R5
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 config BR2_mips_64r6
 	bool "Generic MIPS64R6"
 	depends on BR2_ARCH_IS_64

@@ -129,14 +137,17 @@ config BR2_mips_64r6
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R3
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 config BR2_mips_i6400
 	bool "I6400"
 	depends on BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS64R6
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 config BR2_mips_p6600
 	bool "P6600"
 	depends on BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS64R6
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 endchoice

@@ -257,6 +268,20 @@ config BR2_GCC_TARGET_DSP
 	default "dspr2"		if BR2_MIPS_CPU_HAS_DSP_R2
 	default "dspr3"		if BR2_MIPS_CPU_HAS_DSP_R3
 
+config BR2_MIPS_ENABLE_MSA
+	bool "Enable MSA extension support"
+	depends on BR2_MIPS_CPU_MAYBE_HAS_MSA && BR2_MIPS_FP32_MODE_64
+	depends on !(BR2_MIPS_CPU_HAS_DSP_R1 || BR2_MIPS_CPU_HAS_DSP_R2 || BR2_MIPS_CPU_HAS_DSP_R3)
+	select BR2_MIPS_CPU_HAS_MSA
+	help
+	  For some CPU cores, the MSA extension is optional.
+	  Select this option if you are certain your particular
+	  implementation has MSA support and you want to use it.
+
+config BR2_GCC_TARGET_MSA
+	default "no-msa"	if !BR2_MIPS_CPU_HAS_MSA
+	default "msa"		if BR2_MIPS_CPU_HAS_MSA
+
 config BR2_ARCH
 	default "mips"		if BR2_mips
 	default "mipsel"	if BR2_mipsel

toolchain/toolchain-external/pkg-toolchain-external.mk +5 -0

index ce3a48db8..821734f1c 100644
@@ -158,6 +158,7 @@ CC_TARGET_ARCH_ := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
 CC_TARGET_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_ABI))
 CC_TARGET_NAN_ := $(call qstrip,$(BR2_GCC_TARGET_NAN))
 CC_TARGET_DSP_ := $(call qstrip,$(BR2_GCC_TARGET_DSP))
+CC_TARGET_MSA_ := $(call qstrip,$(BR2_GCC_TARGET_MSA))
 CC_TARGET_FP32_MODE_ := $(call qstrip,$(BR2_GCC_TARGET_FP32_MODE))
 CC_TARGET_FPU_ := $(call qstrip,$(BR2_GCC_TARGET_FPU))
 CC_TARGET_FLOAT_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))

@@ -189,6 +190,10 @@ ifneq ($(CC_TARGET_DSP_),)
 TOOLCHAIN_EXTERNAL_CFLAGS += -m$(CC_TARGET_DSP_)
 TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_DSP='"$(CC_TARGET_DSP_)"'
 endif
+ifneq ($(CC_TARGET_MSA_),)
+TOOLCHAIN_EXTERNAL_CFLAGS += -m$(CC_TARGET_MSA_)
+TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_MSA='"$(CC_TARGET_MSA_)"'
+endif
 ifneq ($(CC_TARGET_FP32_MODE_),)
 TOOLCHAIN_EXTERNAL_CFLAGS += -mfp$(CC_TARGET_FP32_MODE_)
 TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_FP32_MODE='"$(CC_TARGET_FP32_MODE_)"'

toolchain/toolchain-wrapper.c +3 -0

index 670e00884..5ee22219a 100644
@@ -57,6 +57,9 @@ static char *predef_args[] = {
 #ifdef BR_DSP
 	"-m" BR_DSP,
 #endif
+#ifdef BR_MSA
+	"-m" BR_MSA,
+#endif
 #ifdef BR_FPU
 	"-mfpu=" BR_FPU,
 #endif

Signature · 1 line

2.13.0

Thomas Petazzoni

Applied

2017-07-16 14:40 UTC #5 lore raw

PATCH v6 1/4 infra: add support for MIPS NaN

In reply to Vicente Olivert Riera

Hello,

Quoted 25 lines · Vicente Olivert Riera

MIPS supports two different NaN encodings, legacy and 2008. Information about MIPS NaN encodings can be found here:
https://sourceware.org/binutils/docs/as/MIPS-NaN-Encodings.html
NaN legacy is the only option available for R2 cores and older. NaN 2008 is the only option available for R6 cores.
R5 cores can have either NaN legacy or NaN 2008, depending on the implementation. So, if the user selects a generic R5 target architecture variant, we show a choice menu with both options available. For well known R5 cores we directly select the NaN enconding they use.
Signed-off-by Vicente Olivert Riera <[email protected]>
---
Changes v4 -> v6:
- Nothing
Changes v3 -> v4:
- Do not have a default list for NAN options. Instead, select them from the BR2_MIPS_CPU_* options. (Arnout)
- uclibc/Config.in: use the new NAN options from arch/Config.in.mips
Changes v2 -> v3:
- Nothing
Changes v1 -> v2:
- Define config symbol in arch/Config.in
- Change string "NAN" to "NaN"

Quoted 8 lines

---
 arch/Config.in                                     |  3 ++
 arch/Config.in.mips                                | 36 ++++++++++++++++++++++
 package/gcc/gcc.mk                                 |  7 +++++
 package/uclibc/Config.in                           |  4 +--
 .../toolchain-external/pkg-toolchain-external.mk   |  5 +++
 toolchain/toolchain-wrapper.c                      |  3 ++
 6 files changed, 56 insertions(+), 2 deletions(-)

Applied to master, thanks!

Thomas

Signature · 3 lines

Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Thomas Petazzoni

2017-07-17 09:34 UTC #6 lore raw

PATCH v6 1/4 infra: add support for MIPS NaN

Hello,

Quoted 1 line · Thomas Petazzoni

Applied to master, thanks!

This patch is causing some build failures with external toolchains:

http://autobuild.buildroot.net/results/ca1/ca1b769709f2566789e0030221c6837af95459f3/build-end.log

http://autobuild.buildroot.net/results/970/9700c17425c9a10e4f0b72a0932268274068e64a/build-end.log

Is it because the gcc of this external toolchain is too old ? What can we do about this ?

Best regards,

Thomas

Signature · 3 lines

Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Vicente Olivert Riera

author

2017-07-17 12:03 UTC #7 lore raw

PATCH v6 1/4 infra: add support for MIPS NaN

Hello Thomas,

Quoted 6 lines · Thomas Petazzoni

Hello,
Quoted 1 line · Thomas Petazzoni
Applied to master, thanks!

Quoted 7 lines

This patch is causing some build failures with external toolchains:
http://autobuild.buildroot.net/results/ca1/ca1b769709f2566789e0030221c6837af95459f3/build-end.log
http://autobuild.buildroot.net/results/970/9700c17425c9a10e4f0b72a0932268274068e64a/build-end.log
Is it because the gcc of this external toolchain is too old ?

Yes, the -mnan= option was introduced in gcc 4.9.0 by this commit:

0bd32132d471995f3e333138363d1d928a9dde60

The gcc of that external toolchain is 4.8.2.

Quoted 1 line

What can we do about this ?

I guess we could use an option called BR2_GCC_SUPPORTS_MNAN in order to avoid adding the -mnan option to the CFLAGS and to the tc-wrapper if the external toolchain hasn't selected that option. For internal toolchain, since the oldest gcc version we support is 4.9.4, then it should be always selected.

Vincent

Quoted 5 lines

Best regards,
Thomas

Thomas Petazzoni

2017-07-17 12:11 UTC #8 lore raw

PATCH v6 1/4 infra: add support for MIPS NaN

Hello,

Quoted 7 lines · Vicente Olivert Riera

Quoted 1 line
Is it because the gcc of this external toolchain is too old ?
Yes, the -mnan= option was introduced in gcc 4.9.0 by this commit:
0bd32132d471995f3e333138363d1d928a9dde60
The gcc of that external toolchain is 4.8.2.

OK, that explains it.

Quoted 7 lines

Quoted 1 line
What can we do about this ?
I guess we could use an option called BR2_GCC_SUPPORTS_MNAN in order to avoid adding the -mnan option to the CFLAGS and to the tc-wrapper if the external toolchain hasn't selected that option. For internal toolchain, since the oldest gcc version we support is 4.9.4, then it should be always selected.

Sounds good to me. I guess those older gcc versions (4.8 and before) anyway only supported the legacy NaN encoding, and therefore behave as if -mnan=legacy is passed, correct?

You might also want to check if the same problem will happen (or not) for the FP32 mode, and the DSP/MSA options :)

Thanks!

Thomas

Signature · 3 lines

Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Vicente Olivert Riera

author

2017-07-18 10:40 UTC #9 lore raw

PATCH v6 1/4 infra: add support for MIPS NaN

Hi Thomas,

Quoted 22 lines · Thomas Petazzoni

Hello,
Quoted 7 lines · Vicente Olivert Riera
Quoted 1 line
Is it because the gcc of this external toolchain is too old ?
Yes, the -mnan= option was introduced in gcc 4.9.0 by this commit:
0bd32132d471995f3e333138363d1d928a9dde60
The gcc of that external toolchain is 4.8.2.
OK, that explains it.
Quoted 7 lines
Quoted 1 line
What can we do about this ?
I guess we could use an option called BR2_GCC_SUPPORTS_MNAN in order to avoid adding the -mnan option to the CFLAGS and to the tc-wrapper if the external toolchain hasn't selected that option. For internal toolchain, since the oldest gcc version we support is 4.9.4, then it should be always selected.

Quoted 3 lines

Sounds good to me. I guess those older gcc versions (4.8 and before) anyway only supported the legacy NaN encoding, and therefore behave as if -mnan=legacy is passed, correct?

Correct.

Quoted 2 lines

You might also want to check if the same problem will happen (or not) for the FP32 mode, and the DSP/MSA options :)

I'll check it out, yes.

Thanks,

Vincent

Quoted 4 lines

Thanks!
Thomas

Thomas Petazzoni

2017-07-16 14:46 UTC #10 lore raw

PATCH v6 1/4 infra: add support for MIPS NaN

In reply to Vicente Olivert Riera

Hello,

arch/Config.in.mips config BR2_MIPS_SOFT_FLOAT · line 149

Quoted 7 lines · Vicente Olivert Riera

arch/Config.in.mips +7 -0

+choice
+	prompt "Target NaN"
+	depends on BR2_mips_32r5 || BR2_mips_64r5
+	default BR2_MIPS_ENABLE_NAN_2008
+
+	help
+	  NaN encoding to be used

In fact, it would be good here to have a much more detailed help text, perhaps by re-using bits of your commit log.

Same for the FP32 patch.

Could you send follow-up patches improving those help texts?

Thanks,

Thomas

Signature · 3 lines

Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com