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ARM: dts: socfpga: update documentation for clock bindings

PATCH New Dinh Nguyen 3 participants 6 messages Jul 7, 2017 – Jul 21, 2017

Subsystems (4)
Device tree bindings Common clk Arm/socfpga architecture Arm/socfpga clock framework support
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Dinh Nguyen

author maintainer
#0 lore raw

PATCH 1/4 ARM: dts: socfpga: update documentation for clock bindings

Update the bindings document for the Arria10 and Stratix10 clock bindings.

Signed-off-by Dinh Nguyen <[email protected]>
---
 Documentation/devicetree/bindings/clock/altr_socfpga.txt | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
Documentation/devicetree/bindings/clock/altr_socfpga.txt +14 -0
index f72e80e..1c32658 100644
@@ -12,6 +12,20 @@ Required properties:
 	"altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
 		can get gated.
 
+	For Arria10:
+	"altr,socfpga-a10-pll-clock" - for a PLL clock
+	"altr,socfpga-a10-perip-clock" - The peripheral clock divided from the
+		PLL clock.
+	"altr,socfpga-a10-gate-clk" - Clocks that directly feed peripherals and
+		can get gated.
+
+	For Stratix10:
+	"altr,socfpga-s10-pll-clock" - for a PLL clock
+	"altr,socfpga-s10-perip-clock" - The peripheral clock divided from the
+		PLL clock.
+	"altr,socfpga-s10-gate-clk" - Clocks that directly feed peripherals and
+		can get gated.
+
 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
 - clocks : shall be the input parent clock phandle for the clock. This is
 	either an oscillator or a pll output.
Signature · 1 line
2.7.4
author maintainer
#1 lore raw

PATCH 2/4 ARM: dts: socfpga: add a bypass-reg binding for Stratix10

Add a 'bypass-reg' binding property for the Stratix10 clock. There are quite a few clocks on the Stratix10 platform that have a separate bypass setting from the clock's original parent.

The 'bypass-reg' binding contains the bypass register offset from the clock manager's base address and a bit index.

Signed-off-by Dinh Nguyen <[email protected]>
---
 Documentation/devicetree/bindings/clock/altr_socfpga.txt | 3 +++
 1 file changed, 3 insertions(+)
Documentation/devicetree/bindings/clock/altr_socfpga.txt +3 -0
index 1c32658..9e2754a 100644
@@ -42,3 +42,6 @@ Optional properties:
 	value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
 	hold/delay times that is needed for the SD/MMC CIU clock. The values of both
 	can be 0-315 degrees, in 45 degree increments.
+- bypass-reg : There are a few clocks on the Stratix10 platform that can be
+	bypassed from their original parents to a separate clock. This binding
+	property contains the bypass register and the bit index.
Signature · 1 line
2.7.4
author maintainer
#2 lore raw

PATCH 3/4 arm64: dts: add complete clock tree for SoCFPGA Stratix10

In reply to Dinh Nguyen

Add the complete clock tree for SoCFPGA Stratix10 chip. The clocking on Stratix10 is similar to the SoCFPGA Arria10/Cyclone5 platforms, so reuse the same kind of clock structure as the previous platforms.

Signed-off-by Dinh Nguyen <[email protected]>
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 461 +++++++++++++++++++++-
 1 file changed, 460 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +460 -1
index a0aa26e..1b035ed 100644
@@ -89,9 +89,468 @@
 		interrupt-parent = <&intc>;
 		ranges = <0 0 0 0xffffffff>;
 
-		clkmgr at ffd1000 {
+		clkmgr at ffd10000 {
 			compatible = "altr,clk-mgr";
 			reg = <0xffd10000 0x1000>;
+
+			clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
+					#clock-cells = <0>;
+					compatible = "fixed-clock";
+				};
+
+				cb_intosc_ls_clk: cb_intosc_ls_clk {
+					#clock-cells = <0>;
+					compatible = "fixed-clock";
+				};
+
+				f2s_free_clk: f2s_free_clk {
+					#clock-cells = <0>;
+					compatible = "fixed-clock";
+				};
+
+				osc1: osc1 {
+					#clock-cells = <0>;
+					compatible = "fixed-clock";
+				};
+
+				main_pll: main_pll at 44 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-pll-clock";
+					clocks = <&osc1>, <&cb_intosc_hs_div2_clk>,
+						 <&f2s_free_clk>;
+					reg = <0x74>;
+
+					main_mpu_base_clk: main_mpu_base_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&main_pll>;
+						div-reg = <0x84 0 8>;
+					};
+
+					main_noc_base_clk: main_noc_base_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&main_pll>;
+						div-reg = <0x88 0 8>;
+					};
+
+					main_emaca_clk: main_emaca_clk at 68 {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&main_pll>;
+						reg = <0x50>;
+					};
+
+					main_emacb_clk: main_emacb_clk at 6c {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&main_pll>;
+						reg = <0x54>;
+					};
+
+					main_emac_ptp_clk: main_emac_ptp_clk at 70 {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&main_pll>;
+						reg = <0x58>;
+					};
+
+					main_gpio_db_clk: main_gpio_db_clk at 74 {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&main_pll>;
+						reg = <0x5c>;
+					};
+
+					main_sdmmc_clk: main_sdmmc_clk at 78 {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk"
+;
+						clocks = <&main_pll>;
+						reg = <0x60>;
+					};
+
+					main_s2f_usr0_clk: main_s2f_usr0_clk at 7c {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&main_pll>;
+						reg = <0x64>;
+					};
+
+					main_s2f_usr1_clk: main_s2f_usr1_clk at 80 {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&main_pll>;
+						reg = <0x68>;
+					};
+
+					main_psi_ref_clk: main_psi_ref_clk at 84 {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&main_pll>;
+						reg = <0x6c>;
+					};
+				};
+
+				periph_pll: periph_pll at e4 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-pll-clock";
+					clocks = <&osc1>, <&cb_intosc_hs_div2_clk>,
+						 <&f2s_free_clk>;
+					reg = <0xe4>;
+
+					peri_mpu_base_clk: peri_mpu_base_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&periph_pll>;
+						reg = <0xf4 0 8>;
+					};
+
+					peri_noc_base_clk: peri_noc_base_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&periph_pll>;
+						reg = <0xf8 0 8>;
+					};
+
+					peri_emaca_clk: peri_emaca_clk at e8 {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&main_pll>, <&periph_pll>,
+							 <&osc1>, <&cb_intosc_hs_div2_clk>,							    <&f2s_free_clk>;
+						reg = <0xbc>;
+					};
+
+					peri_emacb_clk: peri_emacb_clk at ec {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&main_pll>, <&periph_pll>,
+							 <&osc1>, <&cb_intosc_hs_div2_clk>,							    <&f2s_free_clk>;
+						reg = <0xc0>;
+					};
+
+					peri_emac_ptp_clk: peri_emac_ptp_clk at f0 {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&main_pll>, <&periph_pll>,
+							 <&osc1>, <&cb_intosc_hs_div2_clk>,							    <&f2s_free_clk>;
+						reg = <0xc4>;
+					};
+
+					peri_gpio_db_clk: peri_gpio_db_clk at f4 {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&main_pll>, <&periph_pll>,
+							 <&osc1>, <&cb_intosc_hs_div2_clk>,							    <&f2s_free_clk>;
+						reg = <0xc8>;
+					};
+
+					peri_sdmmc_clk: peri_sdmmc_clk at f8 {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&main_pll>, <&periph_pll>,
+							 <&osc1>, <&cb_intosc_hs_div2_clk>,							    <&f2s_free_clk>;
+						reg = <0xcc>;
+					};
+
+					peri_s2f_usr0_clk: peri_s2f_usr0_clk at fc {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&periph_pll>;
+						reg = <0xd0>;
+					};
+
+					peri_s2f_usr1_clk: peri_s2f_usr1_clk at 100 {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&main_pll>, <&periph_pll>,
+							 <&osc1>, <&cb_intosc_hs_div2_clk>,							    <&f2s_free_clk>;
+						reg = <0xd4>;
+					};
+
+					peri_psi_ref_clk: peri_psi_ref_clk at 104 {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-s10-perip-clk";
+						clocks = <&main_pll>, <&periph_pll>,
+							 <&osc1>, <&cb_intosc_hs_div2_clk>,							    <&f2s_free_clk>;
+						reg = <0xd8>;
+					};
+				};
+
+				boot_clk: boot_clk at 0 {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-perip-clk";
+					clocks = <&osc1>, <&cb_intosc_hs_div2_clk>;
+					reg = <0x0>;
+				};
+
+				mpu_free_clk: mpu_free_clk at 48 {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-perip-clk";
+					clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
+						 <&osc1>, <&cb_intosc_hs_div2_clk>,
+						 <&f2s_free_clk>;
+					reg = <0x48>;
+				};
+
+				noc_free_clk: noc_free_clk at 4c {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-perip-clk";
+					clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
+						 <&osc1>, <&cb_intosc_hs_div2_clk>,
+						 <&f2s_free_clk>;
+					reg = <0x4c>;
+				};
+
+				s2f_user0_free_clk: s2f_user0_free_clk at 104 {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-perip-clk";
+					clocks = <&main_s2f_usr0_clk>, <&peri_s2f_usr0_clk>,
+						 <&osc1>, <&cb_intosc_hs_div2_clk>,
+						 <&f2s_free_clk>;
+					reg = <0x64>;
+				};
+
+				l4_sys_free_clk: l4_sys_free_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-perip-clk";
+					clocks = <&noc_free_clk>;
+					fixed-divider = <4>;
+				};
+
+				noc_clk: noc_clk at 30 {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-perip-clk";
+					clocks = <&boot_clk>, <&noc_free_clk>;
+					bypass-reg = <0x3c 1>;
+				};
+
+				emaca_free_clk: emaca_free_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-perip-clk";
+					clocks = <&boot_clk>, <&main_emaca_clk>;
+					bypass-reg = <0xb0 0>;
+				};
+
+				emacb_free_clk: emacb_free_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-perip-clk";
+					clocks = <&boot_clk>, <&main_emacb_clk>;
+					bypass-reg = <0xb0 1>;
+				};
+
+				emac_ptp_free_clk: emac_ptp_free_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-perip-clk";
+					clocks = <&boot_clk>, <&peri_emac_ptp_clk>;
+					bypass-reg = <0xb0 2>;
+				};
+
+				gpio_db_free_clk: gpio_db_free_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-perip-clk";
+					clocks = <&boot_clk>, <&peri_gpio_db_clk>;
+					bypass-reg = <0xb0 3>;
+				};
+
+				sdmmc_free_clk: sdmmc_free_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-perip-clk";
+					clocks = <&boot_clk>, <&peri_sdmmc_clk>;
+					bypass-reg = <0xb0 4>;
+				};
+
+				s2f_user1_free_clk: s2f_user1_free_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-perip-clk";
+					clocks = <&boot_clk>, <&peri_s2f_usr1_clk>;
+					bypass-reg = <0xb0 5>;
+				};
+
+				psi_ref_free_clk: psi_ref_free_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-perip-clk";
+					clocks = <&boot_clk>, <&peri_psi_ref_clk>;
+					bypass-reg = <0xb0 6>;
+				};
+
+				mpu_clk: mpu_clk at 30 {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&boot_clk>, <&mpu_free_clk>;
+					bypass-reg = <0x3c 0>;
+					clk-gate = <0x30 0>;
+				};
+
+				mpu_periph_clk: mpu_periph_clk at 30 {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&mpu_clk>;
+					fixed-divider = <4>;
+					clk-gate = <0x30 0>;
+				};
+
+				mpu_l2ram_clk: mpu_l2ram_clk at 30 {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&mpu_clk>;
+					fixed-divider = <2>;
+					clk-gate = <0x30 0>;
+				};
+
+				l4_main_clk: l4_main_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&noc_clk>;
+					div-reg = <0x70 0 2>;
+					clk-gate = <0x30 1>;
+				};
+
+				l4_mp_clk: l4_mp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&noc_clk>;
+					div-reg= <0x70 8 2>;
+					clk-gate = <0x30 2>;
+				};
+
+				l4_sp_clk: l4_sp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&noc_clk>;
+					div-reg= <0x70 16 2>;
+					clk-gate = <0x30 3>;
+				};
+
+				cs_at_clk: cs_at_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&noc_clk>;
+					div-reg= <0x70 24 2>;
+					clk-gate = <0x30 4>;
+				};
+
+				cs_trace_clk: cs_trace_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&noc_clk>;
+					div-reg= <0x70 26 2>;
+					clk-gate = <0x30 4>;
+				};
+
+				cs_pdbg_clk: cs_pdbg_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&cs_at_clk>;
+					div-reg= <0x70 28 1>;
+					clk-gate = <0x30 4>;
+				};
+
+				cs_timer_clk: cs_timer_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&noc_clk>;
+					clk-gate = <0x30 5>;
+				};
+
+				s2f_user0_clk: s2f_user0_clk at 3c {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&boot_clk>, <&f2s_free_clk>;
+					bypass-reg = <0x3c 2>;
+					clk-gate = <0x30 6>;
+				};
+
+				emac0_clk: emac0_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&emaca_free_clk>, <&emacb_free_clk>;
+					bypass-reg = <0xdc 26>;
+					clk-gate = <0xa4 0>;
+				};
+
+				emac1_clk: emac1_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&emaca_free_clk>, <&emacb_free_clk>;
+					bypass-reg = <0xdc 27>;
+					clk-gate = <0xa4 1>;
+				};
+
+				emac2_clk: emac2_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&emaca_free_clk>, <&emacb_free_clk>;
+					bypass-reg = <0xdc 28>;
+					clk-gate = <0xa4 2>;
+				};
+
+				emac_ptp_clk: emac_ptp_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&emac_ptp_free_clk>;
+					clk-gate = <0xa4 3>;
+				};
+
+				gpio_db_clk: gpio_db_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&gpio_db_free_clk>;
+					div-reg = <0xe0>;
+					clk-gate = <0xa4 4>;
+				};
+
+				sdmmc_clk: sdmmc_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&sdmmc_free_clk>;
+					fixed-divider = <4>;
+					clk-gate = <0xa4 5>;
+				};
+
+				s2f_usr1_clk: s2f_usr1_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&s2f_user1_free_clk>;
+					clk-gate = <0xa4 6>;
+				};
+
+				psi_ref_clk: psi_ref_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&psi_ref_free_clk>;
+					clk-gate = <0xa4 7>;
+				};
+
+				usb_clk: usb_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&l4_mp_clk>;
+					clk-gate = <0xa4 8>;
+				};
+
+				spi_m_clk: spi_m_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&l4_mp_clk>;
+					clk-gate = <0xa4 9>;
+				};
+
+				nand_clk: nand_clk {
+					#clock-cells = <0>;
+					compatible = "altr,socfpga-s10-gate-clk";
+					clocks = <&l4_main_clk>;
+					clk-gate = <0xa4 10>;
+				};
+			};
 		};
 
 		gmac0: ethernet at ff800000 {
Signature · 1 line
2.7.4
author maintainer
#3 lore raw

PATCH 4/4 clk: socfpga: Add a clock driver for the SoCFPGA Stratix10 platform

In reply to Dinh Nguyen

Add a clock driver the SoCFPGA Stratix10 platform. The Stratix10 SOC is an ARM64 base and the clock tree is very similar to the SOCFPGA ARM32 platforms.

Signed-off-by Dinh Nguyen <[email protected]>
---
 drivers/clk/Makefile                 |   1 +
 drivers/clk/socfpga/Makefile         |   4 +
 drivers/clk/socfpga/clk-gate-s10.c   | 214 +++++++++++++++++++++++++++++++++++
 drivers/clk/socfpga/clk-periph-s10.c | 165 +++++++++++++++++++++++++++
 drivers/clk/socfpga/clk-pll-s10.c    | 146 ++++++++++++++++++++++++
 drivers/clk/socfpga/clk.c            |   9 ++
 drivers/clk/socfpga/clk.h            |   8 ++
 7 files changed, 547 insertions(+)
 create mode 100644 drivers/clk/socfpga/clk-gate-s10.c
 create mode 100644 drivers/clk/socfpga/clk-periph-s10.c
 create mode 100644 drivers/clk/socfpga/clk-pll-s10.c
drivers/clk/Makefile +1 -0
index c19983a..1ce3b10 100644
@@ -80,6 +80,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip/
 obj-$(CONFIG_COMMON_CLK_SAMSUNG)	+= samsung/
 obj-$(CONFIG_ARCH_SIRF)			+= sirf/
 obj-$(CONFIG_ARCH_SOCFPGA)		+= socfpga/
+obj-$(CONFIG_ARCH_STRATIX10)		+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)		+= spear/
 obj-$(CONFIG_ARCH_STI)			+= st/
 obj-$(CONFIG_ARCH_SUNXI)		+= sunxi/
drivers/clk/socfpga/Makefile +4 -0
index d8bb239..602e2b9 100644
@@ -1,5 +1,9 @@
 obj-y += clk.o
+ifeq ($(CONFIG_ARCH_SOCFPGA),y)
 obj-y += clk-gate.o
 obj-y += clk-pll.o
 obj-y += clk-periph.o
 obj-y += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
+else
+obj-y += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
+endif
drivers/clk/socfpga/clk-gate-s10.c new file +214 -0

214 lines not on this page · raw message

drivers/clk/socfpga/clk-periph-s10.c new file +165 -0

165 lines not on this page · raw message

drivers/clk/socfpga/clk-pll-s10.c new file +146 -0

146 lines not on this page · raw message

drivers/clk/socfpga/clk.c +9 -0
index 7564d2e..abb374b 100644
@@ -21,6 +21,7 @@
 
 #include "clk.h"
 
+#ifdef CONFIG_ARCH_SOCFPGA
 CLK_OF_DECLARE(socfpga_pll_clk, "altr,socfpga-pll-clock", socfpga_pll_init);
 CLK_OF_DECLARE(socfpga_perip_clk, "altr,socfpga-perip-clk", socfpga_periph_init);
 CLK_OF_DECLARE(socfpga_gate_clk, "altr,socfpga-gate-clk", socfpga_gate_init);

@@ -30,3 +31,11 @@ CLK_OF_DECLARE(socfpga_a10_perip_clk, "altr,socfpga-a10-perip-clk",
 	       socfpga_a10_periph_init);
 CLK_OF_DECLARE(socfpga_a10_gate_clk, "altr,socfpga-a10-gate-clk",
 	       socfpga_a10_gate_init);
+#elif CONFIG_ARCH_STRATIX10
+CLK_OF_DECLARE(socfpga_s10_pll_clk, "altr,socfpga-s10-pll-clock",
+	       socfpga_s10_pll_init);
+CLK_OF_DECLARE(socfpga_s10_perip_clk, "altr,socfpga-s10-perip-clk",
+	       socfpga_s10_periph_init);
+CLK_OF_DECLARE(socfpga_s10_gate_clk, "altr,socfpga-s10-gate-clk",
+	       socfpga_s10_gate_init);
+#endif
drivers/clk/socfpga/clk.h +8 -0
index 814c724..7eeb140 100644
@@ -34,6 +34,7 @@
 
 extern void __iomem *clk_mgr_base_addr;
 extern void __iomem *clk_mgr_a10_base_addr;
+extern void __iomem *clk_mgr_s10_base_addr;
 
 void __init socfpga_pll_init(struct device_node *node);
 void __init socfpga_periph_init(struct device_node *node);

@@ -41,6 +42,9 @@ void __init socfpga_gate_init(struct device_node *node);
 void socfpga_a10_pll_init(struct device_node *node);
 void socfpga_a10_periph_init(struct device_node *node);
 void socfpga_a10_gate_init(struct device_node *node);
+void socfpga_s10_pll_init(struct device_node *node);
+void socfpga_s10_periph_init(struct device_node *node);
+void socfpga_s10_gate_init(struct device_node *node);
 
 struct socfpga_pll {
 	struct clk_gate	hw;

@@ -51,9 +55,11 @@ struct socfpga_gate_clk {
 	char *parent_name;
 	u32 fixed_div;
 	void __iomem *div_reg;
+	void __iomem *bypass_reg;
 	struct regmap *sys_mgr_base_addr;
 	u32 width;	/* only valid if div_reg != 0 */
 	u32 shift;	/* only valid if div_reg != 0 */
+	u32 bypass_shift;      /* only valid if bypass_reg != 0 */
 	u32 clk_phase[2];
 };
 

@@ -62,8 +68,10 @@ struct socfpga_periph_clk {
 	char *parent_name;
 	u32 fixed_div;
 	void __iomem *div_reg;
+	void __iomem *bypass_reg;
 	u32 width;      /* only valid if div_reg != 0 */
 	u32 shift;      /* only valid if div_reg != 0 */
+	u32 bypass_shift;      /* only valid if bypass_reg != 0 */
 };
 
 #endif /* SOCFPGA_CLK_H */
Signature · 1 line
2.7.4
maintainer
#4 lore raw

PATCH 1/4 ARM: dts: socfpga: update documentation for clock bindings

In reply to Dinh Nguyen
Quoted 18 lines · Dinh Nguyen

Update the bindings document for the Arria10 and Stratix10 clock bindings.

Signed-off-by Dinh Nguyen <[email protected]>
---
 Documentation/devicetree/bindings/clock/altr_socfpga.txt | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
Documentation/devicetree/bindings/clock/altr_socfpga.txt +3 -0
index f72e80e..1c32658 100644
@@ -12,6 +12,20 @@ Required properties:
 	"altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
 		can get gated.
 
+	For Arria10:
+	"altr,socfpga-a10-pll-clock" - for a PLL clock
+	"altr,socfpga-a10-perip-clock" - The peripheral clock divided from the

Documentation/devicetree/bindings/clock/altr_socfpga.txt Required properties: · line 27

Quoted 10 lines
Documentation/devicetree/bindings/clock/altr_socfpga.txt +10 -0
+		PLL clock.
+	"altr,socfpga-a10-gate-clk" - Clocks that directly feed peripherals and
+		can get gated.
+
+	For Stratix10:
+	"altr,socfpga-s10-pll-clock" - for a PLL clock
+	"altr,socfpga-s10-perip-clock" - The peripheral clock divided from the
+		PLL clock.
+	"altr,socfpga-s10-gate-clk" - Clocks that directly feed peripherals and
+		can get gated.

We're generally not doing a clock per node clock providers on new platforms and doing a single (or few) clock controller nodes instead. It doesn't look like there's much or any reuse here from older platforms which would be the main reason to keep this style.

Rob

#5 lore raw

PATCH 1/4 ARM: dts: socfpga: update documentation for clock bindings

Quoted 26 lines · Rob Herring
Quoted 25 lines · Dinh Nguyen

Update the bindings document for the Arria10 and Stratix10 clock bindings.

Signed-off-by Dinh Nguyen <[email protected]>
---
 Documentation/devicetree/bindings/clock/altr_socfpga.txt | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
Documentation/devicetree/bindings/clock/altr_socfpga.txt +10 -0
index f72e80e..1c32658 100644
@@ -12,6 +12,20 @@ Required properties:
 	"altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
 		can get gated.
 
+	For Arria10:
+	"altr,socfpga-a10-pll-clock" - for a PLL clock
+	"altr,socfpga-a10-perip-clock" - The peripheral clock divided from the
+		PLL clock.
+	"altr,socfpga-a10-gate-clk" - Clocks that directly feed peripherals and
+		can get gated.
+
+	For Stratix10:
+	"altr,socfpga-s10-pll-clock" - for a PLL clock
+	"altr,socfpga-s10-perip-clock" - The peripheral clock divided from the
Quoted 8 lines

Documentation/devicetree/bindings/clock/altr_socfpga.txt Required properties: · line 27

Quoted 3 lines
Documentation/devicetree/bindings/clock/altr_socfpga.txt +3 -0
+		PLL clock.
+	"altr,socfpga-s10-gate-clk" - Clocks that directly feed peripherals and
+		can get gated.

We're generally not doing a clock per node clock providers on new platforms and doing a single (or few) clock controller nodes instead. It doesn't look like there's much or any reuse here from older platforms which would be the main reason to keep this style.

Agreed. Can this be rewritten to new style binding?

Signature · 2 lines
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