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crypto: caam - add Job Ring support for DPAA2 parts

PATCH New Horia Geantă 3 participants 11 messages Jul 18, 2017 – Aug 5, 2017

Subsystems (4)
Device tree bindings Arm i.MX and Layerscape Crypto API Freescale CAAM (Cryptographic Acceleration and Assurance Module) driver
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Horia Geantă

author maintainer
#0 lore raw

cover crypto: caam - add Job Ring support for DPAA2 parts

This patch set adds support for CAAM's legacy Job Ring backend / interface on platforms having DPAA2 (Datapath Acceleration Architecture v2), like LS1088A or LS2088A.

I would like to get the DT patches through the crypto list (to make sure they don't end up merged before driver support).

Thanks,
Horia

Horia Geant? (4):
crypto: caam/jr - add support for DPAA2 parts
arm64: dts: freescale: ls208xa: share aliases node
arm64: dts: freescale: ls208xa: add crypto node
arm64: dts: freescale: ls1088a: add crypto node

 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi     | 43 ++++++++++++
 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts  |  5 --
 arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts  |  5 --
 arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts |  5 --
 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts  |  5 --
 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts  |  5 --
 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi     | 46 ++++++++++++
 drivers/crypto/caam/caamhash.c                     |  7 +-
 drivers/crypto/caam/ctrl.c                         | 45 +++++++-----
 drivers/crypto/caam/ctrl.h                         |  2 +
 drivers/crypto/caam/jr.c                           |  7 +-
 drivers/crypto/caam/regs.h                         |  1 +
 drivers/crypto/caam/sg_sw_qm2.h                    | 81 ++++++++++++++++++++++
 drivers/crypto/caam/sg_sw_sec4.h                   | 30 ++++++--
 14 files changed, 237 insertions(+), 50 deletions(-)
 create mode 100644 drivers/crypto/caam/sg_sw_qm2.h
Signature · 1 line
2.12.0.264.gd6db3f216544
author maintainer
#1 lore raw

PATCH 1/4 crypto: caam/jr - add support for DPAA2 parts

Add support for using the caam/jr backend on DPAA2-based SoCs. These have some particularities we have to account for:
-HW S/G format is different
-Management Complex (MC) firmware initializes / manages (partially) the CAAM block: MCFGR, QI enablement in QICTL, RNG

Signed-off-by Horia Geant? <[email protected]>
---
 drivers/crypto/caam/caamhash.c   |  7 ++--
 drivers/crypto/caam/ctrl.c       | 45 ++++++++++++++--------
 drivers/crypto/caam/ctrl.h       |  2 +
 drivers/crypto/caam/jr.c         |  7 +++-
 drivers/crypto/caam/regs.h       |  1 +
 drivers/crypto/caam/sg_sw_qm2.h  | 81 ++++++++++++++++++++++++++++++++++++++++
 drivers/crypto/caam/sg_sw_sec4.h | 30 +++++++++++++--
 7 files changed, 148 insertions(+), 25 deletions(-)
 create mode 100644 drivers/crypto/caam/sg_sw_qm2.h
drivers/crypto/caam/caamhash.c +3 -4
index 910ec61cae09..698580b60b2f 100644
@@ -791,8 +791,8 @@ static int ahash_update_ctx(struct ahash_request *req)
 							 to_hash - *buflen,
 							 *next_buflen, 0);
 		} else {
-			(edesc->sec4_sg + sec4_sg_src_index - 1)->len |=
-				cpu_to_caam32(SEC4_SG_LEN_FIN);
+			sg_to_sec4_set_last(edesc->sec4_sg + sec4_sg_src_index -
+					    1);
 		}
 
 		desc = edesc->hw_desc;

@@ -882,8 +882,7 @@ static int ahash_final_ctx(struct ahash_request *req)
 	if (ret)
 		goto unmap_ctx;
 
-	(edesc->sec4_sg + sec4_sg_src_index - 1)->len |=
-		cpu_to_caam32(SEC4_SG_LEN_FIN);
+	sg_to_sec4_set_last(edesc->sec4_sg + sec4_sg_src_index - 1);
 
 	edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
 					    sec4_sg_bytes, DMA_TO_DEVICE);
drivers/crypto/caam/ctrl.c +29 -16

89 lines not on this page · raw message

drivers/crypto/caam/ctrl.h +2 -0
index cac5402a46eb..7e7bf68c9ef5 100644
@@ -10,4 +10,6 @@
 /* Prototypes for backend-level services exposed to APIs */
 int caam_get_era(void);
 
+extern bool caam_dpaa2;
+
 #endif /* CTRL_H */
drivers/crypto/caam/jr.c +6 -1
index 1ccfb317d468..d258953ff488 100644
@@ -9,6 +9,7 @@
 #include <linux/of_address.h>
 
 #include "compat.h"
+#include "ctrl.h"
 #include "regs.h"
 #include "jr.h"
 #include "desc.h"

@@ -499,7 +500,11 @@ static int caam_jr_probe(struct platform_device *pdev)
 	jrpriv->rregs = (struct caam_job_ring __iomem __force *)ctrl;
 
 	if (sizeof(dma_addr_t) == sizeof(u64)) {
-		if (of_device_is_compatible(nprop, "fsl,sec-v5.0-job-ring"))
+		if (caam_dpaa2)
+			error = dma_set_mask_and_coherent(jrdev,
+							  DMA_BIT_MASK(49));
+		else if (of_device_is_compatible(nprop,
+						 "fsl,sec-v5.0-job-ring"))
 			error = dma_set_mask_and_coherent(jrdev,
 							  DMA_BIT_MASK(40));
 		else
drivers/crypto/caam/regs.h +1 -0
index 84d2f838a063..2b5efff9ec3c 100644
@@ -293,6 +293,7 @@ struct caam_perfmon {
 	u32 cha_rev_ls;		/* CRNR - CHA Rev No. Least significant half*/
 #define CTPR_MS_QI_SHIFT	25
 #define CTPR_MS_QI_MASK		(0x1ull << CTPR_MS_QI_SHIFT)
+#define CTPR_MS_DPAA2		BIT(13)
 #define CTPR_MS_VIRT_EN_INCL	0x00000001
 #define CTPR_MS_VIRT_EN_POR	0x00000002
 #define CTPR_MS_PG_SZ_MASK	0x10
drivers/crypto/caam/sg_sw_qm2.h new file +81 -0

81 lines not on this page · raw message

drivers/crypto/caam/sg_sw_sec4.h +26 -4
index 2f6bf162bb6c..936b1b630058 100644
@@ -5,7 +5,13 @@
  *
  */
 
+#ifndef _SG_SW_SEC4_H_
+#define _SG_SW_SEC4_H_
+
+#include "ctrl.h"
 #include "regs.h"
+#include "sg_sw_qm2.h"
+#include "../../../drivers/staging/fsl-mc/include/dpaa2-fd.h"
 
 struct sec4_sg_entry {
 	u64 ptr;

@@ -19,9 +25,15 @@ struct sec4_sg_entry {
 static inline void dma_to_sec4_sg_one(struct sec4_sg_entry *sec4_sg_ptr,
 				      dma_addr_t dma, u32 len, u16 offset)
 {
-	sec4_sg_ptr->ptr = cpu_to_caam_dma64(dma);
-	sec4_sg_ptr->len = cpu_to_caam32(len);
-	sec4_sg_ptr->bpid_offset = cpu_to_caam32(offset & SEC4_SG_OFFSET_MASK);
+	if (caam_dpaa2) {
+		dma_to_qm_sg_one((struct dpaa2_sg_entry *)sec4_sg_ptr, dma, len,
+				 offset);
+	} else {
+		sec4_sg_ptr->ptr = cpu_to_caam_dma64(dma);
+		sec4_sg_ptr->len = cpu_to_caam32(len);
+		sec4_sg_ptr->bpid_offset = cpu_to_caam32(offset &
+							 SEC4_SG_OFFSET_MASK);
+	}
 #ifdef DEBUG
 	print_hex_dump(KERN_ERR, "sec4_sg_ptr@: ",
 		       DUMP_PREFIX_ADDRESS, 16, 4, sec4_sg_ptr,

@@ -47,6 +59,14 @@ sg_to_sec4_sg(struct scatterlist *sg, int sg_count,
 	return sec4_sg_ptr - 1;
 }
 
+static inline void sg_to_sec4_set_last(struct sec4_sg_entry *sec4_sg_ptr)
+{
+	if (caam_dpaa2)
+		dpaa2_sg_set_final((struct dpaa2_sg_entry *)sec4_sg_ptr, true);
+	else
+		sec4_sg_ptr->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);
+}
+
 /*
  * convert scatterlist to h/w link table format
  * scatterlist must have been previously dma mapped

@@ -56,5 +76,7 @@ static inline void sg_to_sec4_sg_last(struct scatterlist *sg, int sg_count,
 				      u16 offset)
 {
 	sec4_sg_ptr = sg_to_sec4_sg(sg, sg_count, sec4_sg_ptr, offset);
-	sec4_sg_ptr->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);
+	sg_to_sec4_set_last(sec4_sg_ptr);
 }
+
+#endif /* _SG_SW_SEC4_H_ */
Signature · 1 line
2.12.0.264.gd6db3f216544
maintainer
#2 lore raw

PATCH 1/4 crypto: caam/jr - add support for DPAA2 parts

Quoted 7 lines · Horia Geant?

Add support for using the caam/jr backend on DPAA2-based SoCs. These have some particularities we have to account for:

(quoted diff) +0 -2
-HW S/G format is different
-Management Complex (MC) firmware initializes / manages (partially)

the CAAM block: MCFGR, QI enablement in QICTL, RNG

Signed-off-by Horia Geant? <[email protected]>

Patch applied. Thanks.

Signature · 3 lines
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
author maintainer
#3 lore raw

PATCH 2/4 arm64: dts: freescale: ls208xa: share aliases node

In reply to Horia Geantă

aliases node is identical for all boards, thus move it to the common file ls208xa.dtsi.

Signed-off-by Horia Geant? <[email protected]>
---
 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts  | 5 -----
 arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts  | 5 -----
 arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 5 -----
 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts  | 5 -----
 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts  | 5 -----
 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi     | 5 +++++
 6 files changed, 5 insertions(+), 25 deletions(-)
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts +0 -5
index ed209cd57283..3c99608b9b45 100644
@@ -55,11 +55,6 @@
 	model = "Freescale Layerscape 2080a QDS Board";
 	compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
 
-	aliases {
-		serial0 = &serial0;
-		serial1 = &serial1;
-	};
-
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts +0 -5
index 67ec3f9c81a1..a4e7de9f70d8 100644
@@ -55,11 +55,6 @@
 	model = "Freescale Layerscape 2080a RDB Board";
 	compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
 
-	aliases {
-		serial0 = &serial0;
-		serial1 = &serial1;
-	};
-
 	chosen {
 		stdout-path = "serial1:115200n8";
 	};
arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts +0 -5
index 3ee718f0aaf8..fbbb73e571c0 100644
@@ -52,11 +52,6 @@
 	model = "Freescale Layerscape 2080a software Simulator model";
 	compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
 
-	aliases {
-		serial0 = &serial0;
-		serial1 = &serial1;
-	};
-
 	ethernet at 2210000 {
 		compatible = "smsc,lan91c111";
 		reg = <0x0 0x2210000 0x0 0x100>;
arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts +0 -5
index 4a1df5ce3229..eaee5b1c3a44 100644
@@ -54,11 +54,6 @@
 	model = "Freescale Layerscape 2088A QDS Board";
 	compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
 
-	aliases {
-		serial0 = &serial0;
-		serial1 = &serial1;
-	};
-
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts +0 -5
index a76d4b4debd1..c411442cac62 100644
@@ -54,11 +54,6 @@
 	model = "Freescale Layerscape 2088A RDB Board";
 	compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
 
-	aliases {
-		serial0 = &serial0;
-		serial1 = &serial1;
-	};
-
 	chosen {
 		stdout-path = "serial1:115200n8";
 	};
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +5 -0
index 94cdd3045037..f135b987d13b 100644
@@ -53,6 +53,11 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+	};
+
 	cpu: cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
Signature · 1 line
2.12.0.264.gd6db3f216544
author maintainer
#4 lore raw

PATCH 3/4 arm64: dts: freescale: ls208xa: add crypto node

In reply to Horia Geantă

LS208xA has a SEC v5.1 security engine.

Signed-off-by Horia Geant? <[email protected]>
---
 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 41 ++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +41 -0
index f135b987d13b..fc1234dc90f9 100644
@@ -46,6 +46,7 @@
  */
 
 #include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
 	compatible = "fsl,ls2080a";

@@ -54,6 +55,7 @@
 	#size-cells = <2>;
 
 	aliases {
+		crypto = &crypto;
 		serial0 = &serial0;
 		serial1 = &serial1;
 	};

@@ -306,6 +308,45 @@
 			clock-names = "apb_pclk", "wdog_clk";
 		};
 
+		crypto: crypto at 8000000 {
+			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+			fsl,sec-era = <8>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x00 0x8000000 0x100000>;
+			reg = <0x00 0x8000000 0x0 0x100000>;
+			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+			dma-coherent;
+
+			sec_jr0: jr at 10000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x10000 0x10000>;
+				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr1: jr at 20000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x20000 0x10000>;
+				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr2: jr at 30000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x30000 0x10000>;
+				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr3: jr at 40000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x40000 0x10000>;
+				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		fsl_mc: fsl-mc at 80c000000 {
 			compatible = "fsl,qoriq-mc";
 			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
Signature · 1 line
2.12.0.264.gd6db3f216544
author maintainer
#5 lore raw

PATCH 4/4 arm64: dts: freescale: ls1088a: add crypto node

In reply to Horia Geantă

LS1088A has a SEC v5.3 security engine.

Signed-off-by Horia Geant? <[email protected]>
---
 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 43 ++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +43 -0
index c144d06a6e33..6c22d75bc504 100644
@@ -52,6 +52,10 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	aliases {
+		crypto = &crypto;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

@@ -369,6 +373,45 @@
 			dma-coherent;
 			status = "disabled";
 		};
+
+		crypto: crypto at 8000000 {
+			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+			fsl,sec-era = <8>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x00 0x8000000 0x100000>;
+			reg = <0x00 0x8000000 0x0 0x100000>;
+			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+			dma-coherent;
+
+			sec_jr0: jr at 10000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x10000 0x10000>;
+				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr1: jr at 20000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x20000 0x10000>;
+				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr2: jr at 30000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x30000 0x10000>;
+				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr3: jr at 40000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x40000 0x10000>;
+				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
 	};
 
 };
Signature · 1 line
2.12.0.264.gd6db3f216544
#6 lore raw

cover crypto: caam - add Job Ring support for DPAA2 parts

In reply to Horia Geantă
Quoted 6 lines · Horia Geant?

This patch set adds support for CAAM's legacy Job Ring backend / interface on platforms having DPAA2 (Datapath Acceleration Architecture v2), like LS1088A or LS2088A.

I would like to get the DT patches through the crypto list (to make sure they don't end up merged before driver support).

Unless it's really urgent (usually critical bug fix), the DTS patches should go through arm-soc tree. We usually take DTS patches after the driver counterpart has been accepted by subsystem maintainers, or in the best case, has landed on mainline.

Shawn

author maintainer
#7 lore raw

cover crypto: caam - add Job Ring support for DPAA2 parts

Quoted 5 lines · Shawn Guo
Quoted 4 lines · Horia Geant?

This patch set adds support for CAAM's legacy Job Ring backend / interface on platforms having DPAA2 (Datapath Acceleration Architecture v2), like LS1088A or LS2088A.

Quoted 7 lines
Quoted 2 lines

I would like to get the DT patches through the crypto list (to make sure they don't end up merged before driver support).

Unless it's really urgent (usually critical bug fix), the DTS patches should go through arm-soc tree. We usually take DTS patches after the driver counterpart has been accepted by subsystem maintainers, or in the best case, has landed on mainline.

Thanks for the clarification.

Do I have to re-post the DTS patches once the driver is accepted or a ping should suffice or...?

Horia

#8 lore raw

cover crypto: caam - add Job Ring support for DPAA2 parts

Quoted 14 lines · Horia Geant?
Quoted 5 lines · Shawn Guo
Quoted 4 lines · Horia Geant?

This patch set adds support for CAAM's legacy Job Ring backend / interface on platforms having DPAA2 (Datapath Acceleration Architecture v2), like LS1088A or LS2088A.

Quoted 7 lines
Quoted 2 lines

I would like to get the DT patches through the crypto list (to make sure they don't end up merged before driver support).

Unless it's really urgent (usually critical bug fix), the DTS patches should go through arm-soc tree. We usually take DTS patches after the driver counterpart has been accepted by subsystem maintainers, or in the best case, has landed on mainline.

Quoted 4 lines

Thanks for the clarification.

Do I have to re-post the DTS patches once the driver is accepted or a ping should suffice or...?

A ping is sufficient.

Shawn

author maintainer
#9 lore raw

cover crypto: caam - add Job Ring support for DPAA2 parts

Quoted 15 lines · Shawn Guo
Quoted 14 lines · Horia Geant?
Quoted 12 lines · Shawn Guo
Quoted 6 lines · Horia Geant?

This patch set adds support for CAAM's legacy Job Ring backend / interface on platforms having DPAA2 (Datapath Acceleration Architecture v2), like LS1088A or LS2088A.

I would like to get the DT patches through the crypto list (to make sure they don't end up merged before driver support).

Unless it's really urgent (usually critical bug fix), the DTS patches should go through arm-soc tree. We usually take DTS patches after the driver counterpart has been accepted by subsystem maintainers, or in the best case, has landed on mainline.

Quoted 6 lines
Quoted 4 lines

Thanks for the clarification.

Do I have to re-post the DTS patches once the driver is accepted or a ping should suffice or...?

A ping is sufficient.

Shawn,

Driver support (patch 1/4) has just been applied to the cryptodev-2.6 tree:
297b9cebd2fc crypto: caam/jr - add support for DPAA2 parts

Could you please pick up the DTS patches (2-4/4) in this series?

Thanks,
Horia

#10 lore raw

cover crypto: caam - add Job Ring support for DPAA2 parts

In reply to Horia Geantă
Quoted 7 lines · Horia Geant?

This patch set adds support for CAAM's legacy Job Ring backend / interface on platforms having DPAA2 (Datapath Acceleration Architecture v2), like LS1088A or LS2088A.

I would like to get the DT patches through the crypto list (to make sure they don't end up merged before driver support).

Quoted 8 lines

Thanks,
Horia

Horia Geant? (4):
crypto: caam/jr - add support for DPAA2 parts
arm64: dts: freescale: ls208xa: share aliases node
arm64: dts: freescale: ls208xa: add crypto node
arm64: dts: freescale: ls1088a: add crypto node

Applied 3 dts patches, thanks.