ARM: dts: marvell: fix PCI bus dtc warnings
Subsystems (6)
Rob Herring
maintainerPATCH v2 1/1 ARM: dts: marvell: fix PCI bus dtc warnings
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>
Cc Bjorn Helgaas <[email protected]>
Cc Jason Cooper <[email protected]>
Cc Andrew Lunn <[email protected]>
Cc Gregory Clement <[email protected]>
Cc Sebastian Hesselbarth <[email protected]>
---
v2:
- rebase on v4.13-rc2
Documentation/devicetree/bindings/pci/mvebu-pci.txt | 2 +- arch/arm/boot/dts/armada-370.dtsi | 4 +++- arch/arm/boot/dts/armada-375.dtsi | 4 +++- arch/arm/boot/dts/armada-380.dtsi | 5 ++++- arch/arm/boot/dts/armada-385-db-ap.dts | 2 +- arch/arm/boot/dts/armada-385-turris-omnia.dts | 2 +- arch/arm/boot/dts/armada-385.dtsi | 6 +++++- arch/arm/boot/dts/armada-388-clearfog.dts | 2 +- arch/arm/boot/dts/armada-388-clearfog.dtsi | 2 +- arch/arm/boot/dts/armada-388-db.dts | 2 +- arch/arm/boot/dts/armada-388-gp.dts | 2 +- arch/arm/boot/dts/armada-388-rd.dts | 2 +- arch/arm/boot/dts/armada-390-db.dts | 2 +- arch/arm/boot/dts/armada-395-gp.dts | 2 +- arch/arm/boot/dts/armada-398-db.dts | 2 +- arch/arm/boot/dts/armada-39x.dtsi | 6 +++++- arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 3 ++- arch/arm/boot/dts/armada-xp-db.dts | 2 +- arch/arm/boot/dts/armada-xp-gp.dts | 2 +- arch/arm/boot/dts/armada-xp-mv78230.dtsi | 7 ++++++- arch/arm/boot/dts/armada-xp-mv78260.dtsi | 11 ++++++++++- arch/arm/boot/dts/armada-xp-mv78460.dtsi | 14 ++++++++++++-- arch/arm/boot/dts/dove-d3plug.dts | 4 ++-- arch/arm/boot/dts/dove.dtsi | 8 +++++--- arch/arm/boot/dts/kirkwood-6192.dtsi | 3 ++- arch/arm/boot/dts/kirkwood-6281.dtsi | 3 ++- arch/arm/boot/dts/kirkwood-6282.dtsi | 4 +++- arch/arm/boot/dts/kirkwood-98dx4122.dtsi | 3 ++- 28 files changed, 79 insertions(+), 32 deletions(-)
Documentation/devicetree/bindings/pci/mvebu-pci.txt +1 -1
@@ -286,7 +286,7 @@ pcie-controller { status = "disabled"; }; - pcie at 10,0 { + pcie at a,0 { device_type = "pci"; assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; reg = <0x5000 0 0 0 0>;
arch/arm/boot/dts/armada-370.dtsi +3 -1
@@ -72,7 +72,7 @@ reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>; }; - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";
@@ -100,6 +100,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;
@@ -117,6 +118,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>;
arch/arm/boot/dts/armada-375.dtsi +3 -1
@@ -582,7 +582,7 @@ }; }; - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";
@@ -610,6 +610,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;
@@ -627,6 +628,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;
arch/arm/boot/dts/armada-380.dtsi +4 -1
@@ -71,7 +71,7 @@ }; }; - pcie-controller { + pcie { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";
@@ -104,6 +104,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;
@@ -122,6 +123,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <1>;
@@ -140,6 +142,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <2>;
arch/arm/boot/dts/armada-385-db-ap.dts +1 -1
@@ -209,7 +209,7 @@ status = "okay"; }; - pcie-controller { + pcie { status = "okay"; /*
arch/arm/boot/dts/armada-385-turris-omnia.dts +1 -1
@@ -96,7 +96,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; pcie at 1,0 {
arch/arm/boot/dts/armada-385.dtsi +5 -1
@@ -70,7 +70,7 @@ }; soc { - pciec: pcie-controller { + pciec: pcie { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";
@@ -109,6 +109,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;
@@ -127,6 +128,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <1>;
@@ -145,6 +147,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <2>;
@@ -166,6 +169,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <3>;
arch/arm/boot/dts/armada-388-clearfog.dts +1 -1
@@ -62,7 +62,7 @@ }; }; - pcie-controller { + pcie { pcie at 3,0 { /* Port 2, Lane 0. CON2, nearest CPU. */ reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
arch/arm/boot/dts/armada-388-clearfog.dtsi +1 -1
@@ -104,7 +104,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /* * The two PCIe units are accessible through
arch/arm/boot/dts/armada-388-db.dts +1 -1
@@ -172,7 +172,7 @@ status = "okay"; }; - pcie-controller { + pcie { status = "okay"; /* * The two PCIe units are accessible through
arch/arm/boot/dts/armada-388-gp.dts +1 -1
@@ -240,7 +240,7 @@ status = "okay"; }; - pcie-controller { + pcie { status = "okay"; /* * One PCIe units is accessible through
arch/arm/boot/dts/armada-388-rd.dts +1 -1
@@ -117,7 +117,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /* * One PCIe units is accessible through
arch/arm/boot/dts/armada-390-db.dts +1 -1
@@ -123,7 +123,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /* CON30 */
arch/arm/boot/dts/armada-395-gp.dts +1 -1
@@ -139,7 +139,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /*
arch/arm/boot/dts/armada-398-db.dts +1 -1
@@ -118,7 +118,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; pcie at 1,0 {
arch/arm/boot/dts/armada-39x.dtsi +5 -1
@@ -442,7 +442,7 @@ }; }; - pcie-controller { + pcie { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";
@@ -481,6 +481,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;
@@ -499,6 +500,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <1>;
@@ -517,6 +519,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <2>;
@@ -538,6 +541,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <3>;
arch/arm/boot/dts/armada-xp-98dx3236.dtsi +2 -1
@@ -91,7 +91,7 @@ /* * 98DX3236 has 1 x1 PCIe unit Gen2.0 */ - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci";
@@ -116,6 +116,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;
arch/arm/boot/dts/armada-xp-db.dts +1 -1
@@ -242,7 +242,7 @@ /* Port 2, Lane 0 */ status = "okay"; }; - pcie at 10,0 { + pcie at a,0 { /* Port 3, Lane 0 */ status = "okay"; };
arch/arm/boot/dts/armada-xp-gp.dts +1 -1
@@ -227,7 +227,7 @@ /* Port 2, Lane 0 */ status = "okay"; }; - pcie at 10,0 { + pcie at a,0 { /* Port 3, Lane 0 */ status = "okay"; };
arch/arm/boot/dts/armada-xp-mv78230.dtsi +6 -1
@@ -86,7 +86,7 @@ * configured as x4 or quad x1 lanes. One unit is * x1 only. */ - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci";
@@ -123,6 +123,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;
@@ -140,6 +141,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 59>; marvell,pcie-port = <0>;
@@ -157,6 +159,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 60>; marvell,pcie-port = <0>;
@@ -174,6 +177,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 61>; marvell,pcie-port = <0>;
@@ -191,6 +195,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>;
arch/arm/boot/dts/armada-xp-mv78260.dtsi +10 -1
@@ -87,7 +87,7 @@ * configured as x4 or quad x1 lanes. One unit is * x4 only. */ - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci";
@@ -138,6 +138,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;
@@ -155,6 +156,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 59>; marvell,pcie-port = <0>;
@@ -172,6 +174,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 60>; marvell,pcie-port = <0>;
@@ -189,6 +192,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 61>; marvell,pcie-port = <0>;
@@ -206,6 +210,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>;
@@ -223,6 +228,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 0x81000000 0 0 0x81000000 0x6 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 63>; marvell,pcie-port = <1>;
@@ -240,6 +246,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 0x81000000 0 0 0x81000000 0x7 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 64>; marvell,pcie-port = <1>;
@@ -257,6 +264,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 0x81000000 0 0 0x81000000 0x8 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 65>; marvell,pcie-port = <1>;
@@ -274,6 +282,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 0x81000000 0 0 0x81000000 0x9 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 99>; marvell,pcie-port = <2>;
arch/arm/boot/dts/armada-xp-mv78460.dtsi +12 -2
@@ -104,7 +104,7 @@ * configured as x4 or quad x1 lanes. Two units are * x4/x1. */ - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci";
@@ -159,6 +159,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;
@@ -176,6 +177,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 59>; marvell,pcie-port = <0>;
@@ -193,6 +195,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 60>; marvell,pcie-port = <0>;
@@ -210,6 +213,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 61>; marvell,pcie-port = <0>;
@@ -227,6 +231,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>;
@@ -244,6 +249,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 0x81000000 0 0 0x81000000 0x6 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 63>; marvell,pcie-port = <1>;
@@ -261,6 +267,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 0x81000000 0 0 0x81000000 0x7 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 64>; marvell,pcie-port = <1>;
@@ -278,6 +285,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 0x81000000 0 0 0x81000000 0x8 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 65>; marvell,pcie-port = <1>;
@@ -295,6 +303,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 0x81000000 0 0 0x81000000 0x9 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 99>; marvell,pcie-port = <2>;
@@ -303,7 +312,7 @@ status = "disabled"; }; - pcie10: pcie at 10,0 { + pcie10: pcie at a,0 { device_type = "pci"; assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; reg = <0x5000 0 0 0 0>;
@@ -312,6 +321,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 0x81000000 0 0 0x81000000 0xa 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 103>; marvell,pcie-port = <3>;
arch/arm/boot/dts/dove-d3plug.dts +2 -2
@@ -88,7 +88,7 @@ &pcie { status = "okay"; /* Fresco Logic USB3.0 xHCI controller */ - pcie-port at 0 { + pcie at 1 { status = "okay"; reset-gpios = <&gpio0 26 1>; reset-delay-us = <20000>;
@@ -96,7 +96,7 @@ pinctrl-names = "default"; }; /* Mini-PCIe slot */ - pcie-port at 1 { + pcie at 2 { status = "okay"; reset-gpios = <&gpio0 25 1>; };
arch/arm/boot/dts/dove.dtsi +5 -3
@@ -89,7 +89,7 @@ MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */ MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */ - pcie: pcie-controller { + pcie: pcie { compatible = "marvell,dove-pcie"; status = "disabled"; device_type = "pci";
@@ -106,7 +106,7 @@ 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ - pcie0: pcie-port at 0 { + pcie0: pcie at 1 { device_type = "pci"; status = "disabled"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
@@ -118,13 +118,14 @@ #size-cells = <2>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 16>; }; - pcie1: pcie-port at 1 { + pcie1: pcie at 2 { device_type = "pci"; status = "disabled"; assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
@@ -136,6 +137,7 @@ #size-cells = <2>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>;
arch/arm/boot/dts/kirkwood-6192.dtsi +2 -1
@@ -1,6 +1,6 @@ / { mbus at f1000000 { - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci";
@@ -24,6 +24,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 9>; marvell,pcie-port = <0>;
arch/arm/boot/dts/kirkwood-6281.dtsi +2 -1
@@ -1,6 +1,6 @@ / { mbus at f1000000 { - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci";
@@ -24,6 +24,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 9>; marvell,pcie-port = <0>;
arch/arm/boot/dts/kirkwood-6282.dtsi +3 -1
@@ -1,6 +1,6 @@ / { mbus at f1000000 { - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci";
@@ -28,6 +28,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 9>; marvell,pcie-port = <0>;
@@ -45,6 +46,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 10>; marvell,pcie-port = <1>;
arch/arm/boot/dts/kirkwood-98dx4122.dtsi +2 -1
@@ -1,6 +1,6 @@ / { mbus at f1000000 { - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci";
@@ -24,6 +24,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 9>; marvell,pcie-port = <0>;
Signature · 1 line
2.11.0
Rob Herring
maintainerPATCH v2 1/1 ARM: dts: exynos: fix PCI bus dtc warnings
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>
Cc Kukjin Kim <[email protected]>
Cc Krzysztof Kozlowski <[email protected]>
Cc Javier Martinez Canillas <[email protected]>
Cc linux-samsung-soc at vger.kernel.org
---
v2:
- rebase on v4.13-rc2
arch/arm/boot/dts/exynos5440.dtsi | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/boot/dts/exynos5440.dtsi +2 -0
@@ -317,6 +317,7 @@ phys = <&pcie_phy0>; ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ + bus-range = <0x00 0xff>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 53>;
@@ -339,6 +340,7 @@ phys = <&pcie_phy1>; ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ + bus-range = <0x00 0xff>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 56>;
Signature · 1 line
2.11.0
PATCH v2 1/1 ARM: dts: exynos: fix PCI bus dtc warnings
Quoted 7 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>Cc Kukjin Kim <[email protected]>Cc Krzysztof Kozlowski <[email protected]>Cc Javier Martinez Canillas <[email protected]>Cc linux-samsung-soc at vger.kernel.org
Quoted 7 lines
---
v2:
- rebase on v4.13-rc2arch/arm/boot/dts/exynos5440.dtsi | 2 ++ 1 file changed, 2 insertions(+)
Thanks, applied.
Best regards,
Krzysztof
Rob Herring
maintainerPATCH v2 1/1 ARM: dts: spear13xx: fix PCI bus dtc warnings
In reply to Rob Herringdtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>
Acked-by Viresh Kumar <[email protected]>
Cc Shiraz Hashim <[email protected]>
---
v2:
- rebase on v4.13-rc2
Please take via sub-arch tree.
arch/arm/boot/dts/spear1310.dtsi | 3 +++ arch/arm/boot/dts/spear1340.dtsi | 1 + 2 files changed, 4 insertions(+)
arch/arm/boot/dts/spear1310.dtsi +3 -0
@@ -98,6 +98,7 @@ device_type = "pci"; ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + bus-range = <0x00 0xff>; status = "disabled"; };
@@ -116,6 +117,7 @@ device_type = "pci"; ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ + bus-range = <0x00 0xff>; status = "disabled"; };
@@ -134,6 +136,7 @@ device_type = "pci"; ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + bus-range = <0x00 0xff>; status = "disabled"; };
arch/arm/boot/dts/spear1340.dtsi +1 -0
@@ -63,6 +63,7 @@ device_type = "pci"; ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + bus-range = <0x00 0xff>; status = "disabled"; };
Signature · 1 line
2.11.0
Arnd Bergmann
AppliedPATCH v2 1/1 ARM: dts: spear13xx: fix PCI bus dtc warnings
Quoted 5 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>Acked-by Viresh Kumar <[email protected]>Cc Shiraz Hashim <[email protected]>
Applied to next/dt, thanks!
Arnd
Rob Herring
maintainerPATCH v2 1/1 ARM: dts: versatile: fix PCI bus dtc warnings
In reply to Rob Herringdtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>
Cc Russell King <[email protected]>
---
v2:
- rebase on v4.13-rc2
arm-soc, Please apply as Versatile has no maintainer.
arch/arm/boot/dts/versatile-pb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/versatile-pb.dts +1 -1
@@ -39,7 +39,7 @@ clock-names = "apb_pclk"; }; - pci-controller at 10001000 { + pci at 10001000 { compatible = "arm,versatile-pci"; device_type = "pci"; reg = <0x10001000 0x1000
Signature · 1 line
2.11.0
Arnd Bergmann
AppliedPATCH v2 1/1 ARM: dts: versatile: fix PCI bus dtc warnings
Quoted 4 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>Cc Russell King <[email protected]>
Applied to next/dt, thanks!
Arnd
Rob Herring
maintainerPATCH v2 1/1 arm64: dts: apm: fix PCI bus dtc warnings
In reply to Rob Herringdtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>
Cc Duc Dang <[email protected]>
---
v2:
- rebase on v4.13-rc2
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 2 ++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 5 +++++ 2 files changed, 7 insertions(+)
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +2 -0
@@ -626,6 +626,7 @@ 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4
@@ -651,6 +652,7 @@ 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4
arch/arm64/boot/dts/apm/apm-storm.dtsi +5 -0
@@ -626,6 +626,7 @@ 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
@@ -651,6 +652,7 @@ 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
@@ -676,6 +678,7 @@ 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
@@ -701,6 +704,7 @@ 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
@@ -726,6 +730,7 @@ 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
Signature · 1 line
2.11.0
Arnd Bergmann
AppliedPATCH v2 1/1 arm64: dts: apm: fix PCI bus dtc warnings
Quoted 4 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>Cc Duc Dang <[email protected]>
Applied to next/dt64, thanks!
Arnd
Rob Herring
maintainerPATCH v2 1/1 arm64: dts: xilinx: fix PCI bus dtc warnings
In reply to Rob Herringdtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>
Cc Michal Simek <[email protected]>
Cc "S?ren Brinkmann" <[email protected]>
---
v2:
- rebase on v4.13-rc2
Michal, you said you applied v1, but it looks like it never was.
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 1 + 1 file changed, 1 insertion(+)
arch/arm64/boot/dts/xilinx/zynqmp.dtsi +1 -0
@@ -221,6 +221,7 @@ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>; /* prefetchable memory */ + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
Signature · 1 line
2.11.0
PATCH v2 1/1 arm64: dts: xilinx: fix PCI bus dtc warnings
Quoted 10 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>Cc Michal Simek <[email protected]>Cc "S?ren Brinkmann" <[email protected]>---
v2:
- rebase on v4.13-rc2Michal, you said you applied v1, but it looks like it never was.
I have this in my branch but it wasn't merged to arm-soc tree yet.
https://github.com/Xilinx/linux-xlnx/commits/zynqmp/dt
Thanks,
Michal
Rob Herring
maintainerPATCH v2 1/1 arm64: dts: cavium: fix PCI bus dtc warnings
In reply to Rob Herringdtc recently added PCI bus checks. Fix these warnings:
arch/arm64/boot/dts/cavium/thunder2-99xx.dtb: Warning (pci_bridge): Node /pci missing bus-range for PCI bridge arch/arm64/boot/dts/cavium/thunder2-99xx.dtb: Warning (unit_address_vs_reg): Node /pci has a reg or ranges property, but no unit name
Signed-off-by Rob Herring <[email protected]>
Cc Jayachandran C <[email protected]>
---
v2:
- Reapply broadcom vulkan changes to thunder2.
arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi +2 -1
@@ -98,7 +98,7 @@ clock-output-names = "clk125mhz"; }; - pci { + pci at 30000000 { compatible = "pci-host-ecam-generic"; device_type = "pci"; #interrupt-cells = <1>;
@@ -118,6 +118,7 @@ ranges = <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; + bus-range = <0 0xff>; interrupt-map-mask = <0 0 0 7>; interrupt-map = /* addr pin ic icaddr icintr */
Signature · 1 line
2.11.0
PATCH v2 1/1 arm64: dts: cavium: fix PCI bus dtc warnings
Quoted 28 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings:
arch/arm64/boot/dts/cavium/thunder2-99xx.dtb: Warning (pci_bridge): Node /pci missing bus-range for PCI bridgearch/arm64/boot/dts/cavium/thunder2-99xx.dtb: Warning (unit_address_vs_reg): Node /pci has a reg or ranges property, but no unit nameSigned-off-by Rob Herring <[email protected]>Cc Jayachandran C <[email protected]>---
v2:
- Reapply broadcom vulkan changes to thunder2.arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi +1
-1@@ -98,7 +98,7 @@ clock-output-names = "clk125mhz"; }; - pci { + pci at 30000000 { compatible = "pci-host-ecam-generic"; device_type = "pci"; #interrupt-cells = <1>;
arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi line 124
Quoted 7 lines
arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi +1
-0@@ -118,6 +118,7 @@ ranges = <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; + bus-range = <0 0xff>; interrupt-map-mask = <0 0 0 7>; interrupt-map = /* addr pin ic icaddr icintr */
Thanks for fixing this up.
Acked-by Jayachandran C <[email protected]>
The unit name issue is there with memory node on thunder2-99xx.dts as well, I can fix this up if you are not planning to.
JC
Rob Herring
maintainerPATCH v2 1/1 arm64: dts: cavium: fix PCI bus dtc warnings
Quoted 39 lines · Jayachandran C
Quoted 28 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings:
arch/arm64/boot/dts/cavium/thunder2-99xx.dtb: Warning (pci_bridge): Node /pci missing bus-range for PCI bridgearch/arm64/boot/dts/cavium/thunder2-99xx.dtb: Warning (unit_address_vs_reg): Node /pci has a reg or ranges property, but no unit nameSigned-off-by Rob Herring <[email protected]>Cc Jayachandran C <[email protected]>---
v2:
- Reapply broadcom vulkan changes to thunder2.arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi +1
-1@@ -98,7 +98,7 @@ clock-output-names = "clk125mhz"; }; - pci { + pci at 30000000 { compatible = "pci-host-ecam-generic"; device_type = "pci"; #interrupt-cells = <1>;arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi line 124
Quoted 7 lines
arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi +1
-0@@ -118,6 +118,7 @@ ranges = <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; + bus-range = <0 0xff>; interrupt-map-mask = <0 0 0 7>; interrupt-map = /* addr pin ic icaddr icintr */Thanks for fixing this up.
Quoted 4 lines
Acked-by Jayachandran C <[email protected]>The unit name issue is there with memory node on
thunder2-99xx.dtsas well, I can fix this up if you are not planning to.
Please do. There are lots more warnings (tree wide) and I don't plan to fix all of them.
Rob
PATCH 1/1 arm64: dts: cavium: fix memory node dtc warnings
Newer dtc versions generate a warning for thunder2-99xx.dts of the form:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
Fixup the memory node name to avoid this.
Signed-off-by Jayachandran C <[email protected]>
--- arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/cavium/thunder2-99xx.dts +1 -1
@@ -18,7 +18,7 @@ model = "Cavium ThunderX2 CN99XX"; compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; - memory { + memory at 80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */
Signature · 1 line
2.7.4
PATCH v2 1/1 ARM: dts: marvell: fix PCI bus dtc warnings
In reply to Rob HerringHi Rob,
Quoted 8 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>Cc Bjorn Helgaas <[email protected]>Cc Jason Cooper <[email protected]>Cc Andrew Lunn <[email protected]>Cc Gregory Clement <[email protected]>Cc Sebastian Hesselbarth <[email protected]>
Applied on mvebu/dt
Thanks,
Gregory
Quoted 808 lines
---
v2:
- rebase on v4.13-rc2Documentation/devicetree/bindings/pci/mvebu-pci.txt | 2 +- arch/arm/boot/dts/armada-370.dtsi | 4 +++- arch/arm/boot/dts/armada-375.dtsi | 4 +++- arch/arm/boot/dts/armada-380.dtsi | 5 ++++- arch/arm/boot/dts/armada-385-db-ap.dts | 2 +- arch/arm/boot/dts/armada-385-turris-omnia.dts | 2 +- arch/arm/boot/dts/armada-385.dtsi | 6 +++++- arch/arm/boot/dts/armada-388-clearfog.dts | 2 +- arch/arm/boot/dts/armada-388-clearfog.dtsi | 2 +- arch/arm/boot/dts/armada-388-db.dts | 2 +- arch/arm/boot/dts/armada-388-gp.dts | 2 +- arch/arm/boot/dts/armada-388-rd.dts | 2 +- arch/arm/boot/dts/armada-390-db.dts | 2 +- arch/arm/boot/dts/armada-395-gp.dts | 2 +- arch/arm/boot/dts/armada-398-db.dts | 2 +- arch/arm/boot/dts/armada-39x.dtsi | 6 +++++- arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 3 ++- arch/arm/boot/dts/armada-xp-db.dts | 2 +- arch/arm/boot/dts/armada-xp-gp.dts | 2 +- arch/arm/boot/dts/armada-xp-mv78230.dtsi | 7 ++++++- arch/arm/boot/dts/armada-xp-mv78260.dtsi | 11 ++++++++++- arch/arm/boot/dts/armada-xp-mv78460.dtsi | 14 ++++++++++++-- arch/arm/boot/dts/dove-d3plug.dts | 4 ++-- arch/arm/boot/dts/dove.dtsi | 8 +++++--- arch/arm/boot/dts/kirkwood-6192.dtsi | 3 ++- arch/arm/boot/dts/kirkwood-6281.dtsi | 3 ++- arch/arm/boot/dts/kirkwood-6282.dtsi | 4 +++- arch/arm/boot/dts/kirkwood-98dx4122.dtsi | 3 ++- 28 files changed, 79 insertions(+), 32 deletions(-)Documentation/devicetree/bindings/pci/mvebu-pci.txt +1
-1@@ -286,7 +286,7 @@ pcie-controller { status = "disabled"; }; - pcie at 10,0 { + pcie at a,0 { device_type = "pci"; assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; reg = <0x5000 0 0 0 0>;arch/arm/boot/dts/armada-370.dtsi +3
-1@@ -72,7 +72,7 @@ reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>; }; - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";@@ -100,6 +100,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;@@ -117,6 +118,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>;arch/arm/boot/dts/armada-375.dtsi +3
-1@@ -582,7 +582,7 @@ }; }; - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";@@ -610,6 +610,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;@@ -627,6 +628,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;arch/arm/boot/dts/armada-380.dtsi +4
-1@@ -71,7 +71,7 @@ }; }; - pcie-controller { + pcie { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";@@ -104,6 +104,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;@@ -122,6 +123,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <1>;@@ -140,6 +142,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <2>;arch/arm/boot/dts/armada-385-db-ap.dts +1
-1@@ -209,7 +209,7 @@ status = "okay"; }; - pcie-controller { + pcie { status = "okay"; /*arch/arm/boot/dts/armada-385-turris-omnia.dts +1
-1@@ -96,7 +96,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; pcie at 1,0 {arch/arm/boot/dts/armada-385.dtsi +5
-1@@ -70,7 +70,7 @@ }; soc { - pciec: pcie-controller { + pciec: pcie { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";@@ -109,6 +109,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;@@ -127,6 +128,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <1>;@@ -145,6 +147,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <2>;@@ -166,6 +169,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <3>;arch/arm/boot/dts/armada-388-clearfog.dts +1
-1@@ -62,7 +62,7 @@ }; }; - pcie-controller { + pcie { pcie at 3,0 { /* Port 2, Lane 0. CON2, nearest CPU. */ reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;arch/arm/boot/dts/armada-388-clearfog.dtsi +1
-1@@ -104,7 +104,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /* * The two PCIe units are accessible througharch/arm/boot/dts/armada-388-db.dts +1
-1@@ -172,7 +172,7 @@ status = "okay"; }; - pcie-controller { + pcie { status = "okay"; /* * The two PCIe units are accessible througharch/arm/boot/dts/armada-388-gp.dts +1
-1@@ -240,7 +240,7 @@ status = "okay"; }; - pcie-controller { + pcie { status = "okay"; /* * One PCIe units is accessible througharch/arm/boot/dts/armada-388-rd.dts +1
-1@@ -117,7 +117,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /* * One PCIe units is accessible througharch/arm/boot/dts/armada-390-db.dts +1
-1@@ -123,7 +123,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /* CON30 */arch/arm/boot/dts/armada-395-gp.dts +1
-1@@ -139,7 +139,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /*arch/arm/boot/dts/armada-398-db.dts +1
-1@@ -118,7 +118,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; pcie at 1,0 {arch/arm/boot/dts/armada-39x.dtsi +5
-1@@ -442,7 +442,7 @@ }; }; - pcie-controller { + pcie { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";@@ -481,6 +481,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;@@ -499,6 +500,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <1>;@@ -517,6 +519,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <2>;@@ -538,6 +541,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <3>;arch/arm/boot/dts/armada-xp-98dx3236.dtsi +2
-1@@ -91,7 +91,7 @@ /* * 98DX3236 has 1 x1 PCIe unit Gen2.0 */ - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci";@@ -116,6 +116,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;arch/arm/boot/dts/armada-xp-db.dts +1
-1@@ -242,7 +242,7 @@ /* Port 2, Lane 0 */ status = "okay"; }; - pcie at 10,0 { + pcie at a,0 { /* Port 3, Lane 0 */ status = "okay"; };arch/arm/boot/dts/armada-xp-gp.dts +1
-1@@ -227,7 +227,7 @@ /* Port 2, Lane 0 */ status = "okay"; }; - pcie at 10,0 { + pcie at a,0 { /* Port 3, Lane 0 */ status = "okay"; };arch/arm/boot/dts/armada-xp-mv78230.dtsi +6
-1@@ -86,7 +86,7 @@ * configured as x4 or quad x1 lanes. One unit is * x1 only. */ - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci";@@ -123,6 +123,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;@@ -140,6 +141,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 59>; marvell,pcie-port = <0>;@@ -157,6 +159,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 60>; marvell,pcie-port = <0>;@@ -174,6 +177,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 61>; marvell,pcie-port = <0>;@@ -191,6 +195,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>;arch/arm/boot/dts/armada-xp-mv78260.dtsi +10
-1@@ -87,7 +87,7 @@ * configured as x4 or quad x1 lanes. One unit is * x4 only. */ - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci";@@ -138,6 +138,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;@@ -155,6 +156,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 59>; marvell,pcie-port = <0>;@@ -172,6 +174,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 60>; marvell,pcie-port = <0>;@@ -189,6 +192,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 61>; marvell,pcie-port = <0>;@@ -206,6 +210,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>;@@ -223,6 +228,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 0x81000000 0 0 0x81000000 0x6 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 63>; marvell,pcie-port = <1>;@@ -240,6 +246,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 0x81000000 0 0 0x81000000 0x7 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 64>; marvell,pcie-port = <1>;@@ -257,6 +264,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 0x81000000 0 0 0x81000000 0x8 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 65>; marvell,pcie-port = <1>;@@ -274,6 +282,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 0x81000000 0 0 0x81000000 0x9 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 99>; marvell,pcie-port = <2>;arch/arm/boot/dts/armada-xp-mv78460.dtsi +12
-2@@ -104,7 +104,7 @@ * configured as x4 or quad x1 lanes. Two units are * x4/x1. */ - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci";@@ -159,6 +159,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;@@ -176,6 +177,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 59>; marvell,pcie-port = <0>;@@ -193,6 +195,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 60>; marvell,pcie-port = <0>;@@ -210,6 +213,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 61>; marvell,pcie-port = <0>;@@ -227,6 +231,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>;@@ -244,6 +249,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 0x81000000 0 0 0x81000000 0x6 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 63>; marvell,pcie-port = <1>;@@ -261,6 +267,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 0x81000000 0 0 0x81000000 0x7 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 64>; marvell,pcie-port = <1>;@@ -278,6 +285,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 0x81000000 0 0 0x81000000 0x8 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 65>; marvell,pcie-port = <1>;@@ -295,6 +303,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 0x81000000 0 0 0x81000000 0x9 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 99>; marvell,pcie-port = <2>;@@ -303,7 +312,7 @@ status = "disabled"; }; - pcie10: pcie at 10,0 { + pcie10: pcie at a,0 { device_type = "pci"; assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; reg = <0x5000 0 0 0 0>;@@ -312,6 +321,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 0x81000000 0 0 0x81000000 0xa 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 103>; marvell,pcie-port = <3>;arch/arm/boot/dts/dove-d3plug.dts +2
-2@@ -88,7 +88,7 @@ &pcie { status = "okay"; /* Fresco Logic USB3.0 xHCI controller */ - pcie-port at 0 { + pcie at 1 { status = "okay"; reset-gpios = <&gpio0 26 1>; reset-delay-us = <20000>;@@ -96,7 +96,7 @@ pinctrl-names = "default"; }; /* Mini-PCIe slot */ - pcie-port at 1 { + pcie at 2 { status = "okay"; reset-gpios = <&gpio0 25 1>; };arch/arm/boot/dts/dove.dtsi +5
-3@@ -89,7 +89,7 @@ MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */ MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */ - pcie: pcie-controller { + pcie: pcie { compatible = "marvell,dove-pcie"; status = "disabled"; device_type = "pci";@@ -106,7 +106,7 @@ 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ - pcie0: pcie-port at 0 { + pcie0: pcie at 1 { device_type = "pci"; status = "disabled"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;@@ -118,13 +118,14 @@ #size-cells = <2>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 16>; }; - pcie1: pcie-port at 1 { + pcie1: pcie at 2 { device_type = "pci"; status = "disabled"; assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;@@ -136,6 +137,7 @@ #size-cells = <2>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>;arch/arm/boot/dts/kirkwood-6192.dtsi +2
-1@@ -1,6 +1,6 @@ / { mbus at f1000000 { - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci";@@ -24,6 +24,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 9>; marvell,pcie-port = <0>;arch/arm/boot/dts/kirkwood-6281.dtsi +2
-1@@ -1,6 +1,6 @@ / { mbus at f1000000 { - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci";@@ -24,6 +24,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 9>; marvell,pcie-port = <0>;arch/arm/boot/dts/kirkwood-6282.dtsi +3
-1@@ -1,6 +1,6 @@ / { mbus at f1000000 { - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci";@@ -28,6 +28,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 9>; marvell,pcie-port = <0>;@@ -45,6 +46,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 10>; marvell,pcie-port = <1>;arch/arm/boot/dts/kirkwood-98dx4122.dtsi +2
-1@@ -1,6 +1,6 @@ / { mbus at f1000000 { - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci";@@ -24,6 +24,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 9>; marvell,pcie-port = <0>;Signature · 1 line
2.11.0
Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com