Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7
Subsystems (16)
PATCH v3 50/66 rockchip: rk3368: add DRAM controller driver with DRAM initialisation
In reply to Dr. Philipp TomsichHi Philipp:
Quoted 5 lines · Dr. Philipp Tomsich
Andy,
The functionality of the new driver should be equivalent for the non-TPL case. All the code from the original driver is still present in the new driver for non-TPL (see
rk3368_dmc_probe).
Yes, it's so good that the new rk3368 dmc driver also has this
function.
I also need to add a xxx-u-boot.dtsi for the other rk3368 based boards.
Quoted 2,969 lines
Seeing that -19 is
-ENODEV, I suspect that something went wrong in the DM binding/probing: did you set 'status = “okay”’ for the DMC?Regards,
Phil.Quoted 2,959 lines · Andy Yan
Hi Philipp:
Quoted 1,745 lines · Philipp Tomsich
This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip(where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually).At this stage, only the following feature-set is supported:
- DDR3
- 32-bit configuration (i.e. fully populated)
- dual-rank (i.e. no auto-detection of ranks)
- DDR3-1600K speed-binThis driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the
os_reg2in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code).Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time).
The RK3368 also has the
DDRC0_CON0(DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation.
As part of this change,DDRC0_CON0is also added to the GRF structure definition (at offset0x600).Signed-off-by Philipp Tomsich <[email protected]>Reviewed-by Simon Glass <[email protected]>---
Changes in v3:
- correctly states the location of the driver in the commit messageChanges in v2: None
arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++ arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 + arch/arm/mach-rockchip/rk3368/Makefile | 1 - arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 -- .../clock/rockchip,rk3368-dmc.txt | 67 ++ drivers/ram/Makefile | 2 + drivers/ram/rockchip/Makefile | 7 + drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++ include/dt-bindings/memory/rk3368-dmc.h | 30 + 9 files changed, 1286 insertions(+), 61 deletions(-)create mode 100644
arch/arm/include/asm/arch-rockchip/ddr_rk3368.hdelete mode 100644arch/arm/mach-rockchip/rk3368/sdram_rk3368.ccreate mode 100644doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txtcreate mode 100644drivers/ram/rockchip/Makefile
create mode 100644drivers/ram/rockchip/dmc-rk3368.c
create mode 100644include/dt-bindings/memory/rk3368-dmc.harch/arm/include/asm/arch-rockchip/ddr_rk3368.h new file +79
-0@@ -0,0 +1,187 @@ +/* +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_DDR_RK3368_H__ +#define __ASM_ARCH_DDR_RK3368_H__ + +/* + * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only + * in a few details. Most notably, it has an additional field to track + * tREFI in controller cycles (i.e. trefi_mem_ddr3). + */ +struct rk3368_ddr_pctl { + u32 scfg; + u32 sctl; + u32 stat; + u32 intrstat; + u32 reserved0[12]; + u32 mcmd; + u32 powctl; + u32 powstat; + u32 cmdtstat; + u32 cmdtstaten; + u32 reserved1[3]; + u32 mrrcfg0; + u32 mrrstat0; + u32 mrrstat1; + u32 reserved2[4]; + u32 mcfg1; + u32 mcfg; + u32 ppcfg; + u32 mstat; + u32 lpddr2zqcfg; + u32 reserved3; + u32 dtupdes; + u32 dtuna; + u32 dtune; + u32 dtuprd0; + u32 dtuprd1; + u32 dtuprd2; + u32 dtuprd3; + u32 dtuawdt; + u32 reserved4[3]; + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tHi Philipp:
Quoted 267 lines · Philipp Tomsich
This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip(where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually).At this stage, only the following feature-set is supported:
- DDR3
- 32-bit configuration (i.e. fully populated)
- dual-rank (i.e. no auto-detection of ranks)
- DDR3-1600K speed-binThis driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the
os_reg2in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code).Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time).
The RK3368 also has the
DDRC0_CON0(DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation.
As part of this change,DDRC0_CON0is also added to the GRF structure definition (at offset0x600).Signed-off-by Philipp Tomsich <[email protected]>Reviewed-by Simon Glass <[email protected]>---
Changes in v3:
- correctly states the location of the driver in the commit messageChanges in v2: None
arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++ arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 + arch/arm/mach-rockchip/rk3368/Makefile | 1 - arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 -- .../clock/rockchip,rk3368-dmc.txt | 67 ++ drivers/ram/Makefile | 2 + drivers/ram/rockchip/Makefile | 7 + drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++ include/dt-bindings/memory/rk3368-dmc.h | 30 + 9 files changed, 1286 insertions(+), 61 deletions(-)create mode 100644
arch/arm/include/asm/arch-rockchip/ddr_rk3368.hdelete mode 100644arch/arm/mach-rockchip/rk3368/sdram_rk3368.ccreate mode 100644doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txtcreate mode 100644drivers/ram/rockchip/Makefile
create mode 100644drivers/ram/rockchip/dmc-rk3368.c
create mode 100644include/dt-bindings/memory/rk3368-dmc.harch/arm/include/asm/arch-rockchip/ddr_rk3368.h new file +187
-0@@ -0,0 +1,187 @@ +/* +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_DDR_RK3368_H__ +#define __ASM_ARCH_DDR_RK3368_H__ + +/* +* The RK3368 DDR PCTL differs from the incarnation in the RK3288 only +* in a few details. Most notably, it has an additional field to track +* tREFI in controller cycles (i.e. trefi_mem_ddr3). +*/ +struct rk3368_ddr_pctl { +u32 scfg; +u32 sctl; +u32 stat; +u32 intrstat; +u32 reserved0[12 ]; +u32 mcmd; +u32 powctl; +u32 powstat; +u32 cmdtstat; +u32 cmdtstaten; +u32 reserved1[3 ]; +u32 mrrcfg0; +u32 mrrstat0; +u32 mrrstat1; +u32 reserved2[4 ]; +u32 mcfg1; +u32 mcfg; +u32 ppcfg; +u32 mstat; +u32 lpddr2zqcfg; +u32 reserved3; +u32 dtupdes; +u32 dtuna; +u32 dtune; +u32 dtuprd0; +u32 dtuprd1; +u32 dtuprd2; +u32 dtuprd3; +u32 dtuawdt; +u32 reserved4[3 ]; +u32 togcnt1u; +u32 tinit; +u32 trsth; +u32 togcnt100n; +u32 trefi; +u32 tmrd; +u32 trfc; +u32 trp; +u32 trtw; +u32 tal; +u32 tcl; +u32 tcwl; +u32 tras; +u32 trc; +u32 trcd; +u32 trrd; +u32 trtp; +u32 twr; +u32 twtr; +u32 texsr; +u32 txp; +u32 txpdll; +u32 tzqcs; +u32 tzqcsi; +u32 tdqs; +u32 tcksre; +u32 tcksrx; +u32 tcke; +u32 tmod; +u32 trstl; +u32 tzqcl; +u32 tmrr; +u32 tckesr; +u32 tdpd; +u32 trefi_mem_ddr3; +u32 reserved5[45 ]; +u32 dtuwactl; +u32 dturactl; +u32 dtucfg; +u32 dtuectl; +u32 dtuwd0; +u32 dtuwd1; +u32 dtuwd2; +u32 dtuwd3; +u32 dtuwdm; +u32 dturd0; +u32 dturd1; +u32 dturd2; +u32 dturd3; +u32 dtulfsrwd; +u32 dtulfsrrd; +u32 dtueaf; +u32 dfitctrldelay; +u32 dfiodtcfg; +u32 dfiodtcfg1; +u32 dfiodtrankmap; +u32 dfitphywrdata; +u32 dfitphywrlat; +u32 reserved7[2 ]; +u32 dfitrddataen; +u32 dfitphyrdlat; +u32 reserved8[2 ]; +u32 dfitphyupdtype0; +u32 dfitphyupdtype1; +u32 dfitphyupdtype2; +u32 dfitphyupdtype3; +u32 dfitctrlupdmin; +u32 dfitctrlupdmax; +u32 dfitctrlupddly; +u32 reserved9; +u32 dfiupdcfg; +u32 dfitrefmski; +u32 dfitctrlupdi; +u32 reserved10[4 ]; +u32 dfitrcfg0; +u32 dfitrstat0; +u32 dfitrwrlvlen; +u32 dfitrrdlvlen; +u32 dfitrrdlvlgateen; +u32 dfiststat0; +u32 dfistcfg0; +u32 dfistcfg1; +u32 reserved11; +u32 dfitdramclken; +u32 dfitdramclkdis; +u32 dfistcfg2; +u32 dfistparclr; +u32 dfistparlog; +u32 reserved12[3 ]; +u32 dfilpcfg0; +u32 reserved13[3 ]; +u32 dfitrwrlvlresp0; +u32 dfitrwrlvlresp1; +u32 dfitrwrlvlresp2; +u32 dfitrrdlvlresp0; +u32 dfitrrdlvlresp1; +u32 dfitrrdlvlresp2; +u32 dfitrwrlvldelay0; +u32 dfitrwrlvldelay1; +u32 dfitrwrlvldelay2; +u32 dfitrrdlvldelay0; +u32 dfitrrdlvldelay1; +u32 dfitrrdlvldelay2; +u32 dfitrrdlvlgatedelay0; +u32 dfitrrdlvlgatedelay1; +u32 dfitrrdlvlgatedelay2; +u32 dfitrcmd; +u32 reserved14[46 ]; +u32 ipvr; +u32 iptr; +}; +check_member (rk3368_ddr_pctl, iptr,0x03fc ); + +struct rk3368_ddrphy { +u32 reg[0x100 ]; +}; +check_member (rk3368_ddrphy, reg[0xff ],0x03fc ); + +struct rk3368_msch { +u32 coreid; +u32 revisionid; +u32 ddrconf; +u32 ddrtiming; +u32 ddrmode; +u32 readlatency; +u32 reserved1[8 ]; +u32 activate; +u32 devtodev; +}; +check_member (rk3368_msch, devtodev,0x003c ); + +/* GRF_SOC_CON0 */ +enum { +NOC_RSP_ERR_STALL =BIT (9 ), +MOBILE_DDR_SEL =BIT (4 ), +DDR0_16BIT_EN =BIT (3 ), +MSCH0_MAINDDR3_DDR3 =BIT (2 ), +MSCH0_MAINPARTIALPOP =BIT (1 ), +UPCTL_C_ACTIVE =BIT (0 ), +}; + +#endif arch/arm/include/asm/arch-rockchip/grf_rk3368.h +3
-0@@ -76,8 +76,11 @@ struct rk3368_grf {u32 soc_con15;u32 soc_con16;u32 soc_con17; +u32 reserved5[0x6e ]; +u32 ddrc0_con0; };check_member (rk3368_grf, soc_con17,0x444 ); +check_member (rk3368_grf, ddrc0_con0,0x600 );struct rk3368_pmu_grf {u32 gpio0a_iomux;arch/arm/mach-rockchip/rk3368/Makefile +0
-0arch/arm/mach-rockchip/rk3368/Makefile line 8
Quoted 5 lines
arch/arm/mach-rockchip/rk3368/Makefile +0
-1@@ -5,5 +5,4 @@ # obj-y += clk_rk3368.o obj-y += rk3368.o -obj-y += sdram_rk3368.o obj-y += syscon_rk3368.othe current PX5 EVB and Sheep board(they don't use spl now) depend on
thesdram_rk3368driver to get the sdram capacity, and so is the geekbox.
They will be broken when this driver removed.We got the boot failed log on PX5 like bellow:
Quoted 1,184 lines
arch/arm/mach-rockchip/rk3368/sdram_rk3368.c deleted +0
-60@@ -1,60 +0,0 @@ -/* -* (C) Copyright 2016 Rockchip Electronics Co., Ltd. -* -* SPDX-License-Identifier: GPL-2.0 -*/ - -#include <common.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/sdram_common.h> - -DECLARE_GLOBAL_DATA_PTR ; -struct dram_info { -struct ram_info info; -struct rk3368_pmu_grf *pmugrf; -}; - -static int rk3368_dmc_probe (struct udevice *dev) -{ -struct dram_info *priv =dev_get_priv (dev); - - priv->pmugrf =syscon_get_first_range (ROCKCHIP_SYSCON_PMUGRF ); -debug ("%s: grf=%p\n" , __func__, priv->pmugrf); - priv->info.base =CONFIG_SYS_SDRAM_BASE ; - priv->info.size =rockchip_sdram_size ( - (phys_addr_t)&priv->pmugrf->os_reg[2 ]); - -return 0 ; -} - -static int rk3368_dmc_get_info (struct udevice *dev,struct ram_info *info) -{ -struct dram_info *priv =dev_get_priv (dev); - - *info = priv->info; - -return 0 ; -} - -static struct ram_ops rk3368_dmc_ops = { - .get_info = rk3368_dmc_get_info, -}; - - -static const struct udevice_id rk3368_dmc_ids[] = { - { .compatible ="rockchip,rk3368-dmc" }, - { } -}; - -U_BOOT_DRIVER (dmc_rk3368) = { - .name ="rockchip_rk3368_dmc" , - .id =UCLASS_RAM , - .of_match = rk3368_dmc_ids, - .ops = &rk3368_dmc_ops, - .probe = rk3368_dmc_probe, - .priv_auto_alloc_size =sizeof (struct dram_info ), -};doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt new file +67
-0@@ -0,0 +1,67 @@ +RK3368 dynamic memory controller driver +======================================= + +The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation +during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on +the following key configuration data: + (a) a target-frequency (i.e. operating point) for the memory operation + (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware + (c) a memory-schedule (i.e. mapping from physical addresses to the address + pins of the memory bus) + +Required properties +------------------- + +- compatible: "rockchip,rk3368-dmc" +- reg + protocol controller (PCTL) address and PHY controller (DDRPHY) address +- rockchip,ddr-speed-bin + the DDR3 device's speed-bin (as specified according to JESD-79) + DDR3_800D (5-5-5) + DDR3_800E (6-6-6) + DDR3_1066E (6-6-6) + DDR3_1066F (7-7-7) + DDR3_1066G (8-8-8) + DDR3_1333F (7-7-7) + DDR3_1333G (8-8-8) + DDR3_1333H (9-9-9) + DDR3_1333J (10-10-10) + DDR3_1600G (8-8-8) + DDR3_1600H (9-9-9) + DDR3_1600J (10-10-10) + DDR3_1600K (11-11-11) + DDR3_1866J (10-10-10) + DDR3_1866K (11-11-11) + DDR3_1866L (12-12-12) + DDR3_1866M (13-13-13) + DDR3_2133K (11-11-11) + DDR3_2133L (12-12-12) + DDR3_2133M (13-13-13) + DDR3_2133N (14-14-14) +- rockchip,ddr-frequency: + target DDR clock frequency in Hz (not all frequencies may be supported, + as there's some cooperation from the clock-driver required) +- rockchip,memory-schedule: + controls the decoding of physical addresses to DRAM addressing (i.e. how + the physical address maps onto the address pins/chip-select of the device) + DMC_MSCH_CBDR: column -> bank -> device -> row + DMC_MSCH_CBRD: column -> band -> row -> device + DMC_MSCH_CRBD: column -> row -> band -> device + +Example (for DDR3-1600K and 800MHz) +----------------------------------- + + #include <dt-bindings/memory/rk3368-dmc.h> + + dmc: dmc at ff610000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3368-dmc"; + reg = <0 0xff610000 0 0x400 + 0 0xff620000 0 0x400>; + }; + + &dmc { + rockchip,ddr-speed-bin = <DDR3_1600K>; + rockchip,ddr-frequency = <800000000>; + rockchip,memory-schedule = <DMC_MSCH_CBRD>; + };drivers/ram/Makefile +2
-0@@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o + +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/drivers/ram/rockchip/Makefile new file +7
-0@@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.odrivers/ram/rockchip/dmc-rk3368.c new file +990
-0@@ -0,0 +1,990 @@ +/* +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dt-bindings/memory/rk3368-dmc.h> +#include <dt-structs.h> +#include <ram.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3368.h> +#include <asm/arch/grf_rk3368.h> +#include <asm/arch/ddr_rk3368.h> +#include <asm/arch/sdram.h> +#include <asm/arch/sdram_common.h> + +DECLARE_GLOBAL_DATA_PTR ; + +struct dram_info { +struct ram_info info; +struct clk ddr_clk; +struct rk3368_cru *cru; +struct rk3368_grf *grf; +struct rk3368_ddr_pctl *pctl; +struct rk3368_ddrphy *phy; +struct rk3368_pmu_grf *pmugrf; +struct rk3368_msch *msch; +}; + +struct rk3368_sdram_params { +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +struct dtd_rockchip_rk3368_dmc of_plat; +#endif +struct rk3288_sdram_pctl_timing pctl_timing; +u32 trefi_mem_ddr3; +struct rk3288_sdram_channel chan; +struct regmap *map; +u32 ddr_freq; +u32 memory_schedule; +u32 ddr_speed_bin; +u32 tfaw_mult; +}; + +/* PTCL bits */ +enum { +/* PCTL_DFISTCFG0 */ +DFI_INIT_START =BIT (0 ), +DFI_DATA_BYTE_DISABLE_EN =BIT (2 ), + +/* PCTL_DFISTCFG1 */ +DFI_DRAM_CLK_SR_EN =BIT (0 ), +DFI_DRAM_CLK_DPD_EN =BIT (1 ), +ODT_LEN_BL8_W_SHIFT =16 , + +/* PCTL_DFISTCFG2 */ +DFI_PARITY_INTR_EN =BIT (0 ), +DFI_PARITY_EN =BIT (1 ), + +/* PCTL_DFILPCFG0 */ +TLP_RESP_TIME_SHIFT =16 , +LP_SR_EN =BIT (8 ), +LP_PD_EN =BIT (0 ), + +/* PCTL_DFIODTCFG */ +RANK0_ODT_WRITE_SEL =BIT (3 ), +RANK1_ODT_WRITE_SEL =BIT (11 ), + +/* PCTL_SCFG */ +HW_LOW_POWER_EN =BIT (0 ), + +/* PCTL_MCMD */ +START_CMD =BIT (31 ), +MCMD_RANK0 =BIT (20 ), +MCMD_RANK1 =BIT (21 ), +DESELECT_CMD =0 , +PREA_CMD , +REF_CMD , +MRS_CMD , +ZQCS_CMD , +ZQCL_CMD , +RSTL_CMD , +MRR_CMD =8 , +DPDE_CMD , + +/* PCTL_POWCTL */ +POWER_UP_START =BIT (0 ), + +/* PCTL_POWSTAT */ +POWER_UP_DONE =BIT (0 ), + +/* PCTL_SCTL */ +INIT_STATE =0 , +CFG_STATE , +GO_STATE , +SLEEP_STATE , +WAKEUP_STATE , + +/* PCTL_STAT */ +LP_TRIG_SHIFT =4 , +LP_TRIG_MASK =7 , +PCTL_STAT_MSK =7 , +INIT_MEM =0 , +CONFIG , +CONFIG_REQ , +ACCESS , +ACCESS_REQ , +LOW_POWER , +LOW_POWER_ENTRY_REQ , +LOW_POWER_EXIT_REQ , + +/* PCTL_MCFG */ +DDR2_DDR3_BL_8 =BIT (0 ), +DDR3_EN =BIT (5 ), +TFAW_TRRD_MULT4 = (0 <<18 ), +TFAW_TRRD_MULT5 = (1 <<18 ), +TFAW_TRRD_MULT6 = (2 <<18 ), +}; + +#define DDR3_MR0_WR (n) \ + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9)) +#define DDR3_MR0_CL (n) \ + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2)) +#define DDR3_MR0_BL8 \ + (0 << 0) +#define DDR3_MR0_DLL_RESET \ + (1 << 8) +#define DDR3_MR1_RTT120OHM \ + ((0 << 9) | (1 << 6) | (0 << 2)) +#define DDR3_MR2_TWL (n) \ + (((n - 5) & 0x7) << 3) + + +#ifdef CONFIG_TPL_BUILD + +static void ddr_set_noc_spr_err_stall (struct rk3368_grf *grf,bool enable) +{ +if (enable) +rk_setreg (&grf->ddrc0_con0,NOC_RSP_ERR_STALL ); +else +rk_clrreg (&grf->ddrc0_con0,NOC_RSP_ERR_STALL ); +} + +static void ddr_set_ddr3_mode (struct rk3368_grf *grf,bool ddr3_mode) +{ +if (ddr3_mode) +rk_setreg (&grf->ddrc0_con0,MSCH0_MAINDDR3_DDR3 ); +else +rk_clrreg (&grf->ddrc0_con0,MSCH0_MAINDDR3_DDR3 ); +} + +static void ddrphy_config (struct rk3368_ddrphy *phy, +u32 tcl,u32 tal,u32 tcwl) +{ +int i; + +/* Set to DDR3 mode */ +clrsetbits_le32 (&phy->reg[1 ],0x3 ,0x0 ); + +/* DDRPHY_REGB: CL, AL */ +clrsetbits_le32 (&phy->reg[0xb ],0xff , tcl <<4 | tal); +/* DDRPHY_REGC: CWL */ +clrsetbits_le32 (&phy->reg[0xc ],0x0f , tcwl); + +/* Update drive-strength */ +writel (0xcc , &phy->reg[0x11 ]); +writel (0xaa , &phy->reg[0x16 ]); +/* +* Update NRCOMP/PRCOMP for all 4 channels (for details of all +* affected registers refer to the documentation of DDRPHY_REG20 +* and DDRPHY_REG21 in the RK3368 TRM. +*/ +for (i =0 ; i <4 ; ++i) { +writel (0xcc , &phy->reg[0x20 + i *0x10 ]); +writel (0x44 , &phy->reg[0x21 + i *0x10 ]); + } + +/* Enable write-leveling calibration bypass */ +setbits_le32 (&phy->reg[2 ],BIT (3 )); +} + +static void copy_to_reg (u32 *dest,const u32 *src,u32 n) +{ +int i; + +for (i =0 ; i < n /sizeof (u32); i++) +writel (*src++, dest++); +} + +static void send_command (struct rk3368_ddr_pctl *pctl,u32 rank,u32 cmd) +{ +u32 mcmd =START_CMD | cmd | rank; + +debug ("%s: writing %x to MCMD\n" , __func__, mcmd); +writel (mcmd, &pctl->mcmd); +while (readl (&pctl->mcmd) &START_CMD ) +/* spin */ ; +} + +static void send_mrs (struct rk3368_ddr_pctl *pctl, +u32 rank,u32 mr_num,u32 mr_data) +{ +u32 mcmd =START_CMD |MRS_CMD | rank | (mr_num <<17 ) | (mr_data <<4 ); + +debug ("%s: writing %x to MCMD\n" , __func__, mcmd); +writel (mcmd, &pctl->mcmd); +while (readl (&pctl->mcmd) &START_CMD ) +/* spin */ ; +} + +static int memory_init (struct rk3368_ddr_pctl *pctl, +struct rk3368_sdram_params *params) +{ +u32 mr[4 ]; +const ulong timeout_ms =500 ; +ulong tmp; + +/* +* Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and +* wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register +* of PCTL. +*/ +writel (POWER_UP_START , &pctl->powctl); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: POWER_UP_START did not complete in %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while (!(readl (&pctl->powstat) &POWER_UP_DONE )); + +/* Configure MR0 through MR3 */ + mr[0 ] =DDR3_MR0_WR (params->pctl_timing.twr) | +DDR3_MR0_CL (params->pctl_timing.tcl) | +DDR3_MR0_DLL_RESET ; + mr[1 ] =DDR3_MR1_RTT120OHM ; + mr[2 ] =DDR3_MR2_TWL (params->pctl_timing.tcwl); + mr[3 ] =0 ; + +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.2 Initialization (DDR3 Initialization Sequence)" +*/ +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,DESELECT_CMD ); +udelay (1 ); +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,PREA_CMD ); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,2 , mr[2 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,3 , mr[3 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,1 , mr[1 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,0 , mr[0 ]); +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,ZQCL_CMD ); + +return 0 ; +} + +static void move_to_config_state (struct rk3368_ddr_pctl *pctl) +{ +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.1 State transition of PCTL (Moving to Config State)" +*/ +u32 state =readl (&pctl->stat) &PCTL_STAT_MSK ; + +switch (state) { +case LOW_POWER : +writel (WAKEUP_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=ACCESS ) +/* spin */ ; + +/* fall-through */ +case ACCESS : +case INIT_MEM : +writel (CFG_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=CONFIG ) +/* spin */ ; +break ; + +case CONFIG : +return ; + +default : +break ; + } +} + +static void move_to_access_state (struct rk3368_ddr_pctl *pctl) +{ +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.1 State transition of PCTL (Moving to Access State)" +*/ +u32 state =readl (&pctl->stat) &PCTL_STAT_MSK ; + +switch (state) { +case LOW_POWER : +if (((readl (&pctl->stat) >>LP_TRIG_SHIFT ) & +LP_TRIG_MASK ) ==1 ) +return ; + +writel (WAKEUP_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=ACCESS ) +/* spin */ ; + +/* fall-through */ +case INIT_MEM : +writel (CFG_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=CONFIG ) +/* spin */ ; + +/* fall-through */ +case CONFIG : +writel (GO_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) ==CONFIG ) +/* spin */ ; +break ; + +case ACCESS : +return ; + +default : +break ; + } +} + +static void ddrctl_reset (struct rk3368_cru *cru) +{ +const u32 ctl_reset =BIT (3 ) |BIT (2 ); +const u32 phy_reset =BIT (1 ) |BIT (0 ); + +rk_setreg (&cru->softrst_con[10 ], ctl_reset | phy_reset); +udelay (1 ); +rk_clrreg (&cru->softrst_con[10 ], ctl_reset | phy_reset); +} + +static void ddrphy_reset (struct rk3368_ddrphy *ddrphy) +{ +clrbits_le32 (&ddrphy->reg[0 ],BIT (3 ) |BIT (2 )); +udelay (1 ); +setbits_le32 (&ddrphy->reg[0 ],BIT (3 ) |BIT (2 )); +} + +static void ddrphy_config_delays (struct rk3368_ddrphy *ddrphy,u32 freq) +{ +u32 dqs_dll_delay; + +setbits_le32 (&ddrphy->reg[0x13 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x14 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x26 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x27 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x36 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x37 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x46 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x47 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x56 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x57 ],BIT (3 )); + +if (freq <=400000000 ) +setbits_le32 (&ddrphy->reg[0xa4 ],0x1f ); +else +clrbits_le32 (&ddrphy->reg[0xa4 ],0x1f ); + +if (freq <681000000 ) + dqs_dll_delay =3 ;/* 67.5 degree delay */ +else + dqs_dll_delay =2 ;/* 45 degree delay */ + +writel (dqs_dll_delay, &ddrphy->reg[0x28 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x38 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x48 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x58 ]); +} + +static int dfi_cfg (struct rk3368_ddr_pctl *pctl) +{ +const ulong timeout_ms =200 ; +ulong tmp; + +writel (DFI_DATA_BYTE_DISABLE_EN , &pctl->dfistcfg0); + +writel (DFI_DRAM_CLK_SR_EN |DFI_DRAM_CLK_DPD_EN , + &pctl->dfistcfg1); +writel (DFI_PARITY_INTR_EN |DFI_PARITY_EN , &pctl->dfistcfg2); +writel (7 <<TLP_RESP_TIME_SHIFT |LP_SR_EN |LP_PD_EN , + &pctl->dfilpcfg0); + +writel (1 , &pctl->dfitphyupdtype0); + +writel (0x1f , &pctl->dfitphyrdlat); +writel (0 , &pctl->dfitphywrdata); +writel (0 , &pctl->dfiupdcfg);/* phyupd and ctrlupd disabled */ + +setbits_le32 (&pctl->dfistcfg0,DFI_INIT_START ); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: DFI init did not complete within %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while ((readl (&pctl->dfiststat0) &1 ) ==0 ); + +return 0 ; +} + +static inline u32 ps_to_tCK (const u32 ps,const ulong freq) +{ +const ulong MHz =1000000 ; +return DIV_ROUND_UP (ps * freq,1000000 * MHz); +} + +static inline u32 ns_to_tCK (const u32 ns,const ulong freq) +{ +return ps_to_tCK (ns *1000 , freq); +} + +static inline u32 tCK_to_ps (const ulong tCK,const ulong freq) +{ +const ulong MHz =1000000 ; +return DIV_ROUND_UP (tCK *1000000 * MHz, freq); +} + +static int pctl_calc_timings (struct rk3368_sdram_params *params, +ulong freq) +{ +struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing; +const ulong MHz =1000000 ; +u32 tccd; +u32 tfaw_as_ps; + +if (params->ddr_speed_bin !=DDR3_1600K ) { +error ("%s: unimplemented DDR3 speed bin %d\n" , + __func__, params->ddr_speed_bin); +return -1 ; + } + +/* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */ + pctl_timing->togcnt1u =DIV_ROUND_UP (freq,2 * MHz); + pctl_timing->togcnt100n =DIV_ROUND_UP (freq /10 ,2 * MHz); + + pctl_timing->tinit =200 ;/* 200 usec */ + pctl_timing->trsth =500 ;/* 500 usec */ + pctl_timing->trefi =78 ;/* 7.8usec = 78 * 100ns */ + params->trefi_mem_ddr3 =ns_to_tCK (pctl_timing->trefi *100 , freq); + +if (freq <= (400 * MHz)) { + pctl_timing->tcl =6 ; + pctl_timing->tcwl =10 ; + }else if (freq <= (533 * MHz)) { + pctl_timing->tcl =8 ; + pctl_timing->tcwl =6 ; + }else if (freq <= (666 * MHz)) { + pctl_timing->tcl =10 ; + pctl_timing->tcwl =7 ; + }else { + pctl_timing->tcl =11 ; + pctl_timing->tcwl =8 ; + } + + pctl_timing->tmrd =4 ;/* 4 tCK (all speed bins) */ + pctl_timing->trfc =ns_to_tCK (350 , freq);/* tRFC: 350 (max) @ 8GBit */ + pctl_timing->trp =max (4u ,ps_to_tCK (13750 , freq)); +/* +* JESD-79: +* READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL +*/ + tccd =4 ; + pctl_timing->trtw = pctl_timing->tcl + tccd/2 +2 - pctl_timing->tcwl; + pctl_timing->tal =0 ; + pctl_timing->tras =ps_to_tCK (35000 , freq); + pctl_timing->trc =ps_to_tCK (48750 , freq); + pctl_timing->trcd =ps_to_tCK (13750 , freq); + pctl_timing->trrd =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->trtp =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->twr =ps_to_tCK (15000 , freq); +/* The DDR3 mode-register does only support even values for tWR > 8. */ +if (pctl_timing->twr >8 ) + pctl_timing->twr = (pctl_timing->twr +1 ) & ~1 ; + pctl_timing->twtr =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->texsr =512 ;/* tEXSR(max) is tDLLLK */ + pctl_timing->txp =max (3u ,ps_to_tCK (6000 , freq)); + pctl_timing->txpdll =max (10u ,ps_to_tCK (24000 , freq)); + pctl_timing->tzqcs =max (64u ,ps_to_tCK (80000 , freq)); + pctl_timing->tzqcsi =10000 ;/* as used by Rockchip */ + pctl_timing->tdqs =1 ;/* fixed for DDR3 */ + pctl_timing->tcksre =max (5u ,ps_to_tCK (10000 , freq)); + pctl_timing->tcksrx =max (5u ,ps_to_tCK (10000 , freq)); + pctl_timing->tcke =max (3u ,ps_to_tCK (5000 , freq)); + pctl_timing->tmod =max (12u ,ps_to_tCK (15000 , freq)); + pctl_timing->trstl =ns_to_tCK (100 , freq); + pctl_timing->tzqcl =max (256u ,ps_to_tCK (320000 , freq));/* tZQoper */ + pctl_timing->tmrr =0 ; + pctl_timing->tckesr = pctl_timing->tcke +1 ;/* JESD-79: tCKE + 1tCK */ + pctl_timing->tdpd =0 ;/* RK3368 TRM: "allowed values for DDR3: 0" */ + + +/* +* The controller can represent tFAW as 4x, 5x or 6x tRRD only. +* We want to use the smallest multiplier that satisfies the tFAW +* requirements of the given speed-bin. If necessary, we stretch out +* tRRD to allow us to operate on a 6x multiplier for tFAW. +*/ + tfaw_as_ps =40000 ;/* 40ns: tFAW for DDR3-1600K, 2KB page-size */ +if (tCK_to_ps (pctl_timing->trrd *6 , freq) < tfaw_as_ps) { +/* If tFAW is > 6 x tRRD, we need to stretch tRRD */ + pctl_timing->trrd =ps_to_tCK (DIV_ROUND_UP (40000 ,6 ), freq); + params->tfaw_mult =TFAW_TRRD_MULT6 ; + }else if (tCK_to_ps (pctl_timing->trrd *5 , freq) < tfaw_as_ps) { + params->tfaw_mult =TFAW_TRRD_MULT6 ; + }else if (tCK_to_ps (pctl_timing->trrd *4 , freq) < tfaw_as_ps) { + params->tfaw_mult =TFAW_TRRD_MULT5 ; + }else { + params->tfaw_mult =TFAW_TRRD_MULT4 ; + } + +return 0 ; +} + +static void pctl_cfg (struct rk3368_ddr_pctl *pctl, +struct rk3368_sdram_params *params, +struct rk3368_grf *grf) +{ +/* Configure PCTL timing registers */ + params->pctl_timing.trefi |=BIT (31 );/* see PCTL_TREFI */ +copy_to_reg (&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u, +sizeof (params->pctl_timing)); +writel (params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3); + +/* Set up ODT write selector and ODT write length */ +writel ((RANK0_ODT_WRITE_SEL |RANK1_ODT_WRITE_SEL ), &pctl->dfiodtcfg); +writel (7 <<ODT_LEN_BL8_W_SHIFT , &pctl->dfiodtcfg1); + +/* Set up the CL/CWL-dependent timings of DFI */ +writel ((params->pctl_timing.tcl -1 ) /2 -1 , &pctl->dfitrddataen); +writel ((params->pctl_timing.tcwl -1 ) /2 -1 , &pctl->dfitphywrlat); + +/* DDR3 */ +writel (params->tfaw_mult |DDR3_EN |DDR2_DDR3_BL_8 , &pctl->mcfg); +writel (0x001c0004 , &grf->ddrc0_con0); + +setbits_le32 (&pctl->scfg,HW_LOW_POWER_EN ); +} + +static int ddrphy_data_training (struct rk3368_ddr_pctl *pctl, +struct rk3368_ddrphy *ddrphy) +{ +const u32 trefi =readl (&pctl->trefi); +const ulong timeout_ms =500 ; +ulong tmp; + +/* disable auto-refresh */ +writel (0 |BIT (31 ), &pctl->trefi); + +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x20 ); +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x21 ); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: did not complete within %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while ((readl (&ddrphy->reg[0xff ]) &0xf ) !=0xf ); + +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,PREA_CMD ); +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x20 ); +/* resume auto-refresh */ +writel (trefi |BIT (31 ), &pctl->trefi); + +return 0 ; +} + +static int sdram_col_row_detect (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_sdram_params *params =dev_get_platdata (dev); +struct rk3368_ddr_pctl *pctl = priv->pctl; +struct rk3368_msch *msch = priv->msch; +const u32 test_pattern =0x5aa5f00f ; +int row, col; +uintptr_t addr; + +move_to_config_state (pctl); +writel (6 , &msch->ddrconf); +move_to_access_state (pctl); + +/* Detect col */ +for (col =11 ; col >=9 ; col--) { +writel (0 ,CONFIG_SYS_SDRAM_BASE ); + addr =CONFIG_SYS_SDRAM_BASE + + (1 << (col + params->chan.bw -1 )); +writel (test_pattern, addr); +if ((readl (addr) == test_pattern) && + (readl (CONFIG_SYS_SDRAM_BASE ) ==0 )) +break ; + } + +if (col ==8 ) { +error ("%s: col detect error\n" , __func__); +return -EINVAL ; + } + +move_to_config_state (pctl); +writel (15 , &msch->ddrconf); +move_to_access_state (pctl); + +/* Detect row*/ +for (row =16 ; row >=12 ; row--) { +writel (0 ,CONFIG_SYS_SDRAM_BASE ); + addr =CONFIG_SYS_SDRAM_BASE + (1 << (row +15 -1 )); +writel (test_pattern, addr); +if ((readl (addr) == test_pattern) && + (readl (CONFIG_SYS_SDRAM_BASE ) ==0 )) +break ; + } + +if (row ==11 ) { +error ("%s: row detect error\n" , __func__); +return -EINVAL ; + } + +/* Record results */ +debug ("%s: col %d, row %d\n" , __func__, col, row); + params->chan.col = col; + params->chan.cs0_row = row; + params->chan.cs1_row = row; + params->chan.row_3_4 =0 ; + +return 0 ; +} + +static int msch_niu_config (struct rk3368_msch *msch, +struct rk3368_sdram_params *params) +{ +int i; +const u8 cols = params->chan.col - ((params->chan.bw ==2 ) ?0 :1 ); +const u8 rows = params->chan.cs0_row; + +/* +* The DDR address-translation table always assumes a 32bit +* bus and the comparison below takes care of adjusting for +* a 16bit bus (i.e. one column-address is consumed). +*/ +const struct { +u8 rows; +u8 columns; +u8 type; + } ddrconf_table[] = { +/* +* C-B-R-D patterns are first. For these we require an +* exact match for the columns and rows (as there's +* one entry per possible configuration). +*/ + [0 ] = { .rows =13 , .columns =10 , .type =DMC_MSCH_CBRD }, + [1 ] = { .rows =14 , .columns =10 , .type =DMC_MSCH_CBRD }, + [2 ] = { .rows =15 , .columns =10 , .type =DMC_MSCH_CBRD }, + [3 ] = { .rows =16 , .columns =10 , .type =DMC_MSCH_CBRD }, + [4 ] = { .rows =14 , .columns =11 , .type =DMC_MSCH_CBRD }, + [5 ] = { .rows =15 , .columns =11 , .type =DMC_MSCH_CBRD }, + [6 ] = { .rows =16 , .columns =11 , .type =DMC_MSCH_CBRD }, + [7 ] = { .rows =13 , .columns =9 , .type =DMC_MSCH_CBRD }, + [8 ] = { .rows =14 , .columns =9 , .type =DMC_MSCH_CBRD }, + [9 ] = { .rows =15 , .columns =9 , .type =DMC_MSCH_CBRD }, + [10 ] = { .rows =16 , .columns =9 , .type =DMC_MSCH_CBRD }, +/* +* 11 through 13 are C-R-B-D patterns. These are +* matched for an exact number of columns and to +* ensure that the hardware uses at least as many rows +* as the pattern requires (i.e. we make sure that +* there's no gaps up until we hit the device/chip-select; +* however, these patterns can accept up to 16 rows, +* as the row-address continues right after the CS +* switching) +*/ + [11 ] = { .rows =15 , .columns =10 , .type =DMC_MSCH_CRBD }, + [12 ] = { .rows =14 , .columns =11 , .type =DMC_MSCH_CRBD }, + [13 ] = { .rows =13 , .columns =10 , .type =DMC_MSCH_CRBD }, +/* +* 14 and 15 are catch-all variants using a C-B-D-R +* scheme (i.e. alternating the chip-select every time +* C-B overflows) and stuffing the remaining C-bits +* into the top. Matching needs to make sure that the +* number of columns is either an exact match (i.e. we +* can use less the the maximum number of rows) -or- +* that the columns exceed what is given in this table +* and the rows are an exact match (in which case the +* remaining C-bits will be stuffed onto the top after +* the device/chip-select switches). +*/ + [14 ] = { .rows =16 , .columns =10 , .type =DMC_MSCH_CBDR }, + [15 ] = { .rows =16 , .columns =9 , .type =DMC_MSCH_CBDR }, + }; + +/* +* For C-B-R-D, we need an exact match (i.e. both for the number of +* columns and rows), while for C-B-D-R, only the the number of +* columns needs to match. +*/ +for (i =0 ; i <ARRAY_SIZE (ddrconf_table); i++) { +bool match = false; + +/* If this entry if for a different matcher, then skip it */ +if (ddrconf_table[i].type != params->memory_schedule) +continue ; + +/* +* Match according to the rules (exact/inexact/at-least) +* documented in the ddrconf_table above. +*/ +switch (params->memory_schedule) { +case DMC_MSCH_CBRD : + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows == rows); +break ; + +case DMC_MSCH_CRBD : + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows <= rows); +break ; + +case DMC_MSCH_CBDR : + match = (ddrconf_table[i].columns == cols) || + ((ddrconf_table[i].columns <= cols) && + (ddrconf_table[i].rows == rows)); +break ; + +default : +break ; + } + +if (match) { +debug ("%s: setting ddrconf 0x%x\n" , __func__, i); +writel (i, &msch->ddrconf); +return 0 ; + } + } + +error ("%s: ddrconf (NIU config) not found\n" , __func__); +return -EINVAL ; +} + +static void dram_all_config (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_pmu_grf *pmugrf = priv->pmugrf; +struct rk3368_sdram_params *params =dev_get_platdata (dev); +const struct rk3288_sdram_channel *info = ¶ms->chan; +u32 sys_reg =0 ; +const int chan =0 ; + + sys_reg |=DDR3 <<SYS_REG_DDRTYPE_SHIFT ; + sys_reg |=0 <<SYS_REG_NUM_CH_SHIFT ; + + sys_reg |= info->row_3_4 <<SYS_REG_ROW_3_4_SHIFT (chan); + sys_reg |=1 <<SYS_REG_CHINFO_SHIFT (chan); + sys_reg |= (info->rank -1 ) <<SYS_REG_RANK_SHIFT (chan); + sys_reg |= (info->col -9 ) <<SYS_REG_COL_SHIFT (chan); + sys_reg |= info->bk ==3 ?0 :1 <<SYS_REG_BK_SHIFT (chan); + sys_reg |= (info->cs0_row -13 ) <<SYS_REG_CS0_ROW_SHIFT (chan); + sys_reg |= (info->cs1_row -13 ) <<SYS_REG_CS1_ROW_SHIFT (chan); + sys_reg |= (2 >> info->bw) <<SYS_REG_BW_SHIFT (chan); + sys_reg |= (2 >> info->dbw) <<SYS_REG_DBW_SHIFT (chan); + +writel (sys_reg, &pmugrf->os_reg[2 ]); +} + +static int setup_sdram (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_sdram_params *params =dev_get_platdata (dev); + +struct rk3368_ddr_pctl *pctl = priv->pctl; +struct rk3368_ddrphy *ddrphy = priv->phy; +struct rk3368_cru *cru = priv->cru; +struct rk3368_grf *grf = priv->grf; +struct rk3368_msch *msch = priv->msch; + +int ret; + +/* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */ + ret =clk_set_rate (&priv->ddr_clk,2 * params->ddr_freq); +if (ret <0 ) { +debug ("%s: could not set DDR clock: %d\n" , __func__, ret); +return ret; + } + +/* Update the read-latency for the RK3368 */ +writel (0x32 , &msch->readlatency); + +/* Initialise the DDR PCTL and DDR PHY */ +ddrctl_reset (cru); +ddrphy_reset (ddrphy); +ddrphy_config_delays (ddrphy, params->ddr_freq); +dfi_cfg (pctl); +/* Configure relative system information of grf_ddrc0_con0 register */ +ddr_set_ddr3_mode (grf, true); +ddr_set_noc_spr_err_stall (grf, true); +/* Calculate timings */ +pctl_calc_timings (params, params->ddr_freq); +/* Initialise the device timings in protocol controller */ +pctl_cfg (pctl, params, grf); +/* Configure AL, CL ... information of PHY registers */ +ddrphy_config (ddrphy, + params->pctl_timing.tcl, + params->pctl_timing.tal, + params->pctl_timing.tcwl); + +/* Initialize DRAM and configure with mode-register values */ + ret =memory_init (pctl, params); +if (ret) + goto error; + +move_to_config_state (pctl); +/* Perform data-training */ +ddrphy_data_training (pctl, ddrphy); +move_to_access_state (pctl); + +/* TODO(prt): could detect rank in training... */ + params->chan.rank =2 ; +/* TODO(prt): bus width is not auto-detected (yet)... */ + params->chan.bw =2 ;/* 32bit wide bus */ + params->chan.dbw = params->chan.dbw;/* 32bit wide bus */ + +/* DDR3 is always 8 bank */ + params->chan.bk =3 ; +/* Detect col and row number */ + ret =sdram_col_row_detect (dev); +if (ret) + goto error; + +/* Configure NIU DDR configuration */ + ret =msch_niu_config (msch, params); +if (ret) + goto error; + +/* set up OS_REG to communicate w/ next stage and OS */ +dram_all_config (dev); + +return 0 ; + +error: +printf ("DRAM init failed!\n" ); +hang (); +} +#endif + +static int rk3368_dmc_ofdata_to_platdata (struct udevice *dev) +{ +int ret =0 ; + +#if !CONFIG_IS_ENABLED (OF_PLATDATA ) +struct rk3368_sdram_params *plat =dev_get_platdata (dev); + + ret =regmap_init_mem (dev, &plat->map); +if (ret) +return ret; +#endif + +return ret; +} + +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +static int conv_of_platdata (struct udevice *dev) +{ +struct rk3368_sdram_params *plat =dev_get_platdata (dev); +struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat; +int ret; + + plat->ddr_freq = of_plat->rockchip_ddr_frequency; + plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin; + plat->memory_schedule = of_plat->rockchip_memory_schedule; + + ret =regmap_init_mem_platdata (dev, of_plat->reg, +ARRAY_SIZE (of_plat->reg) /2 , + &plat->map); +if (ret) +return ret; + +return 0 ; +} +#endif + +static int rk3368_dmc_probe (struct udevice *dev) +{ +#ifdef CONFIG_TPL_BUILD +struct rk3368_sdram_params *plat =dev_get_platdata (dev); +struct rk3368_ddr_pctl *pctl; +struct rk3368_ddrphy *ddrphy; +struct rk3368_cru *cru; +struct rk3368_grf *grf; +struct rk3368_msch *msch; +int ret; +struct udevice *dev_clk; +#endif +struct dram_info *priv =dev_get_priv (dev); + +#if CONFIG_IS_ENABLED (OF_PLATDATA ) + ret =conv_of_platdata (dev); +if (ret) +return ret; +#endif + + priv->pmugrf =syscon_get_first_range (ROCKCHIP_SYSCON_PMUGRF ); +debug ("%s: pmugrf=%p\n" , __func__, priv->pmugrf); + +#ifdef CONFIG_TPL_BUILD + pctl =regmap_get_range (plat->map,0 ); + ddrphy =regmap_get_range (plat->map,1 ); + msch =syscon_get_first_range (ROCKCHIP_SYSCON_MSCH ); + grf =syscon_get_first_range (ROCKCHIP_SYSCON_GRF ); + + priv->pctl = pctl; + priv->phy = ddrphy; + priv->msch = msch; + priv->grf = grf; + + ret =rockchip_get_clk (&dev_clk); +if (ret) +return ret; + priv->ddr_clk.id =CLK_DDR ; + ret =clk_request (dev_clk, &priv->ddr_clk); +if (ret) +return ret; + + cru =rockchip_get_cru (); + priv->cru = cru; +if (IS_ERR (priv->cru)) +return PTR_ERR (priv->cru); + + ret =setup_sdram (dev); +if (ret) +return ret; +#endif + + priv->info.base =0 ; + priv->info.size = +rockchip_sdram_size ((phys_addr_t)&priv->pmugrf->os_reg[2 ]); + +/* +* we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff +* is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is +* inaccessible for some IP controller. +*/ + priv->info.size =min (priv->info.size, (size_t )0xfe000000 ); + +return 0 ; +} + +static int rk3368_dmc_get_info (struct udevice *dev,struct ram_info *info) +{ +struct dram_info *priv =dev_get_priv (dev); + + *info = priv->info; +return 0 ; +} + +static struct ram_ops rk3368_dmc_ops = { + .get_info = rk3368_dmc_get_info, +}; + + +static const struct udevice_id rk3368_dmc_ids[] = { + { .compatible ="rockchip,rk3368-dmc" }, + { } +}; + +U_BOOT_DRIVER (dmc_rk3368) = { + .name ="rockchip_rk3368_dmc" , + .id =UCLASS_RAM , + .of_match = rk3368_dmc_ids, + .ops = &rk3368_dmc_ops, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size =sizeof (struct dram_info ), + .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size =sizeof (struct dram_info ), + .platdata_auto_alloc_size =sizeof (struct rk3368_sdram_params ), +};include/dt-bindings/memory/rk3368-dmc.h new file +20
-0@@ -0,0 +1,30 @@ +#ifndef DT_BINDINGS_RK3368_DMC_H +#define DT_BINDINGS_RK3368_DMC_H + +#define DMC_MSCH_CBDR 0x0 +#define DMC_MSCH_CBRD 0x1 +#define DMC_MSCH_CRBD 0x2 + +#define DDR3_800D 0 +#define DDR3_800E 1 +#define DDR3_1066E 2 +#define DDR3_1066F 3 +#define DDR3_1066G 4 +#define DDR3_1333F 5 +#define DDR3_1333G 6 +#define DDR3_1333H 7 +#define DDR3_1333J 8 +#define DDR3_1600G 9 +#define DDR3_1600H 10 +#define DDR3_1600J 11 +#define DDR3_1600K 12include/dt-bindings/memory/rk3368-dmc.h line 30
Quoted 10 lines
include/dt-bindings/memory/rk3368-dmc.h new file +10
-0+#define DDR3_1866J 13 +#define DDR3_1866K 14 +#define DDR3_1866L 15 +#define DDR3_1866M 16 +#define DDR3_2133K 17 +#define DDR3_2133L 18 +#define DDR3_2133M 19 +#define DDR3_2133N 20 + +#endif dpd;
arch/arm/include/asm/arch-rockchip/ddr_rk3368.h new file +108
-0+u32 trefi_mem_ddr3; +u32 reserved5[45 ]; +u32 dtuwactl; +u32 dturactl; +u32 dtucfg; +u32 dtuectl; +u32 dtuwd0; +u32 dtuwd1; +u32 dtuwd2; +u32 dtuwd3; +u32 dtuwdm; +u32 dturd0; +u32 dturd1; +u32 dturd2; +u32 dturd3; +u32 dtulfsrwd; +u32 dtulfsrrd; +u32 dtueaf; +u32 dfitctrldelay; +u32 dfiodtcfg; +u32 dfiodtcfg1; +u32 dfiodtrankmap; +u32 dfitphywrdata; +u32 dfitphywrlat; +u32 reserved7[2 ]; +u32 dfitrddataen; +u32 dfitphyrdlat; +u32 reserved8[2 ]; +u32 dfitphyupdtype0; +u32 dfitphyupdtype1; +u32 dfitphyupdtype2; +u32 dfitphyupdtype3; +u32 dfitctrlupdmin; +u32 dfitctrlupdmax; +u32 dfitctrlupddly; +u32 reserved9; +u32 dfiupdcfg; +u32 dfitrefmski; +u32 dfitctrlupdi; +u32 reserved10[4 ]; +u32 dfitrcfg0; +u32 dfitrstat0; +u32 dfitrwrlvlen; +u32 dfitrrdlvlen; +u32 dfitrrdlvlgateen; +u32 dfiststat0; +u32 dfistcfg0; +u32 dfistcfg1; +u32 reserved11; +u32 dfitdramclken; +u32 dfitdramclkdis; +u32 dfistcfg2; +u32 dfistparclr; +u32 dfistparlog; +u32 reserved12[3 ]; +u32 dfilpcfg0; +u32 reserved13[3 ]; +u32 dfitrwrlvlresp0; +u32 dfitrwrlvlresp1; +u32 dfitrwrlvlresp2; +u32 dfitrrdlvlresp0; +u32 dfitrrdlvlresp1; +u32 dfitrrdlvlresp2; +u32 dfitrwrlvldelay0; +u32 dfitrwrlvldelay1; +u32 dfitrwrlvldelay2; +u32 dfitrrdlvldelay0; +u32 dfitrrdlvldelay1; +u32 dfitrrdlvldelay2; +u32 dfitrrdlvlgatedelay0; +u32 dfitrrdlvlgatedelay1; +u32 dfitrrdlvlgatedelay2; +u32 dfitrcmd; +u32 reserved14[46 ]; +u32 ipvr; + u32 iptr; +}; +check_member (rk3368_ddr_pctl, iptr,0x03fc ); + +struct rk3368_ddrphy { +u32 reg[0x100 ]; +}; +check_member (rk3368_ddrphy, reg[0xff ],0x03fc ); + +struct rk3368_msch { +u32 coreid; +u32 revisionid; +u32 ddrconf; +u32 ddrtiming; +u32 ddrmode; +u32 readlatency; +u32 reserved1[8 ]; +u32 activate; +u32 devtodev; +}; +check_member (rk3368_msch, devtodev,0x003c ); + +/* GRF_SOC_CON0 */ +enum { +NOC_RSP_ERR_STALL =BIT (9 ), +MOBILE_DDR_SEL =BIT (4 ), +DDR0_16BIT_EN =BIT (3 ), +MSCH0_MAINDDR3_DDR3 =BIT (2 ), +MSCH0_MAINPARTIALPOP =BIT (1 ), +UPCTL_C_ACTIVE =BIT (0 ), +}; + +#endif arch/arm/include/asm/arch-rockchip/grf_rk3368.h +3
-0@@ -76,8 +76,11 @@ struct rk3368_grf {u32 soc_con15;u32 soc_con16;u32 soc_con17; +u32 reserved5[0x6e ]; +u32 ddrc0_con0; };check_member (rk3368_grf, soc_con17,0x444 ); +check_member (rk3368_grf, ddrc0_con0,0x600 );struct rk3368_pmu_grf {u32 gpio0a_iomux;arch/arm/mach-rockchip/rk3368/Makefile +0
-0arch/arm/mach-rockchip/rk3368/Makefile line 8
Quoted 5 lines
arch/arm/mach-rockchip/rk3368/Makefile +0
-1@@ -5,5 +5,4 @@ # obj-y += clk_rk3368.o obj-y += rk3368.o -obj-y += sdram_rk3368.o obj-y += syscon_rk3368.oThe current PX5 EVB and Sheep board(they have no spl now) depend on this
sdram_rk3368.c
to get the sdram capacity, and so is the geekbox board.
These boards will be broken when this driver removed.
We got the failed log like this on PX5 EVB:DRAM: DRAM init failed: -19
initcall sequence 000000002d=378208 failed at call 02023f0 (err=-19) ### ERROR ### Please RESET the board ###Quoted 1,194 lines
arch/arm/mach-rockchip/rk3368/sdram_rk3368.c deleted +0
-60@@ -1,60 +0,0 @@ -/* -* (C) Copyright 2016 Rockchip Electronics Co., Ltd. -* -* SPDX-License-Identifier: GPL-2.0 -*/ - -#include <common.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/sdram_common.h> - -DECLARE_GLOBAL_DATA_PTR ; -struct dram_info { -struct ram_info info; -struct rk3368_pmu_grf *pmugrf; -}; - -static int rk3368_dmc_probe (struct udevice *dev) -{ -struct dram_info *priv =dev_get_priv (dev); - - priv->pmugrf =syscon_get_first_range (ROCKCHIP_SYSCON_PMUGRF ); -debug ("%s: grf=%p\n" , __func__, priv->pmugrf); - priv->info.base =CONFIG_SYS_SDRAM_BASE ; - priv->info.size =rockchip_sdram_size ( - (phys_addr_t)&priv->pmugrf->os_reg[2 ]); - -return 0 ; -} - -static int rk3368_dmc_get_info (struct udevice *dev,struct ram_info *info) -{ -struct dram_info *priv =dev_get_priv (dev); - - *info = priv->info; - -return 0 ; -} - -static struct ram_ops rk3368_dmc_ops = { - .get_info = rk3368_dmc_get_info, -}; - - -static const struct udevice_id rk3368_dmc_ids[] = { - { .compatible ="rockchip,rk3368-dmc" }, - { } -}; - -U_BOOT_DRIVER (dmc_rk3368) = { - .name ="rockchip_rk3368_dmc" , - .id =UCLASS_RAM , - .of_match = rk3368_dmc_ids, - .ops = &rk3368_dmc_ops, - .probe = rk3368_dmc_probe, - .priv_auto_alloc_size =sizeof (struct dram_info ), -};doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt new file +67
-0@@ -0,0 +1,67 @@ +RK3368 dynamic memory controller driver +======================================= + +The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation +during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on +the following key configuration data: + (a) a target-frequency (i.e. operating point) for the memory operation + (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware + (c) a memory-schedule (i.e. mapping from physical addresses to the address + pins of the memory bus) + +Required properties +------------------- + +- compatible: "rockchip,rk3368-dmc" +- reg + protocol controller (PCTL) address and PHY controller (DDRPHY) address +- rockchip,ddr-speed-bin + the DDR3 device's speed-bin (as specified according to JESD-79) + DDR3_800D (5-5-5) + DDR3_800E (6-6-6) + DDR3_1066E (6-6-6) + DDR3_1066F (7-7-7) + DDR3_1066G (8-8-8) + DDR3_1333F (7-7-7) + DDR3_1333G (8-8-8) + DDR3_1333H (9-9-9) + DDR3_1333J (10-10-10) + DDR3_1600G (8-8-8) + DDR3_1600H (9-9-9) + DDR3_1600J (10-10-10) + DDR3_1600K (11-11-11) + DDR3_1866J (10-10-10) + DDR3_1866K (11-11-11) + DDR3_1866L (12-12-12) + DDR3_1866M (13-13-13) + DDR3_2133K (11-11-11) + DDR3_2133L (12-12-12) + DDR3_2133M (13-13-13) + DDR3_2133N (14-14-14) +- rockchip,ddr-frequency: + target DDR clock frequency in Hz (not all frequencies may be supported, + as there's some cooperation from the clock-driver required) +- rockchip,memory-schedule: + controls the decoding of physical addresses to DRAM addressing (i.e. how + the physical address maps onto the address pins/chip-select of the device) + DMC_MSCH_CBDR: column -> bank -> device -> row + DMC_MSCH_CBRD: column -> band -> row -> device + DMC_MSCH_CRBD: column -> row -> band -> device + +Example (for DDR3-1600K and 800MHz) +----------------------------------- + + #include <dt-bindings/memory/rk3368-dmc.h> + + dmc: dmc at ff610000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3368-dmc"; + reg = <0 0xff610000 0 0x400 + 0 0xff620000 0 0x400>; + }; + + &dmc { + rockchip,ddr-speed-bin = <DDR3_1600K>; + rockchip,ddr-frequency = <800000000>; + rockchip,memory-schedule = <DMC_MSCH_CBRD>; + };drivers/ram/Makefile +2
-0@@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o + +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/drivers/ram/rockchip/Makefile new file +7
-0@@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.odrivers/ram/rockchip/dmc-rk3368.c new file +990
-0@@ -0,0 +1,990 @@ +/* +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dt-bindings/memory/rk3368-dmc.h> +#include <dt-structs.h> +#include <ram.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3368.h> +#include <asm/arch/grf_rk3368.h> +#include <asm/arch/ddr_rk3368.h> +#include <asm/arch/sdram.h> +#include <asm/arch/sdram_common.h> + +DECLARE_GLOBAL_DATA_PTR ; + +struct dram_info { +struct ram_info info; +struct clk ddr_clk; +struct rk3368_cru *cru; +struct rk3368_grf *grf; +struct rk3368_ddr_pctl *pctl; +struct rk3368_ddrphy *phy; +struct rk3368_pmu_grf *pmugrf; +struct rk3368_msch *msch; +}; + +struct rk3368_sdram_params { +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +struct dtd_rockchip_rk3368_dmc of_plat; +#endif +struct rk3288_sdram_pctl_timing pctl_timing; +u32 trefi_mem_ddr3; +struct rk3288_sdram_channel chan; +struct regmap *map; +u32 ddr_freq; +u32 memory_schedule; +u32 ddr_speed_bin; +u32 tfaw_mult; +}; + +/* PTCL bits */ +enum { +/* PCTL_DFISTCFG0 */ +DFI_INIT_START =BIT (0 ), +DFI_DATA_BYTE_DISABLE_EN =BIT (2 ), + +/* PCTL_DFISTCFG1 */ +DFI_DRAM_CLK_SR_EN =BIT (0 ), +DFI_DRAM_CLK_DPD_EN =BIT (1 ), +ODT_LEN_BL8_W_SHIFT =16 , + +/* PCTL_DFISTCFG2 */ +DFI_PARITY_INTR_EN =BIT (0 ), +DFI_PARITY_EN =BIT (1 ), + +/* PCTL_DFILPCFG0 */ +TLP_RESP_TIME_SHIFT =16 , +LP_SR_EN =BIT (8 ), +LP_PD_EN =BIT (0 ), + +/* PCTL_DFIODTCFG */ +RANK0_ODT_WRITE_SEL =BIT (3 ), +RANK1_ODT_WRITE_SEL =BIT (11 ), + +/* PCTL_SCFG */ +HW_LOW_POWER_EN =BIT (0 ), + +/* PCTL_MCMD */ +START_CMD =BIT (31 ), +MCMD_RANK0 =BIT (20 ), +MCMD_RANK1 =BIT (21 ), +DESELECT_CMD =0 , +PREA_CMD , +REF_CMD , +MRS_CMD , +ZQCS_CMD , +ZQCL_CMD , +RSTL_CMD , +MRR_CMD =8 , +DPDE_CMD , + +/* PCTL_POWCTL */ +POWER_UP_START =BIT (0 ), + +/* PCTL_POWSTAT */ +POWER_UP_DONE =BIT (0 ), + +/* PCTL_SCTL */ +INIT_STATE =0 , +CFG_STATE , +GO_STATE , +SLEEP_STATE , +WAKEUP_STATE , + +/* PCTL_STAT */ +LP_TRIG_SHIFT =4 , +LP_TRIG_MASK =7 , +PCTL_STAT_MSK =7 , +INIT_MEM =0 , +CONFIG , +CONFIG_REQ , +ACCESS , +ACCESS_REQ , +LOW_POWER , +LOW_POWER_ENTRY_REQ , +LOW_POWER_EXIT_REQ , + +/* PCTL_MCFG */ +DDR2_DDR3_BL_8 =BIT (0 ), +DDR3_EN =BIT (5 ), +TFAW_TRRD_MULT4 = (0 <<18 ), +TFAW_TRRD_MULT5 = (1 <<18 ), +TFAW_TRRD_MULT6 = (2 <<18 ), +}; + +#define DDR3_MR0_WR (n) \ + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9)) +#define DDR3_MR0_CL (n) \ + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2)) +#define DDR3_MR0_BL8 \ + (0 << 0) +#define DDR3_MR0_DLL_RESET \ + (1 << 8) +#define DDR3_MR1_RTT120OHM \ + ((0 << 9) | (1 << 6) | (0 << 2)) +#define DDR3_MR2_TWL (n) \ + (((n - 5) & 0x7) << 3) + + +#ifdef CONFIG_TPL_BUILD + +static void ddr_set_noc_spr_err_stall (struct rk3368_grf *grf,bool enable) +{ +if (enable) +rk_setreg (&grf->ddrc0_con0,NOC_RSP_ERR_STALL ); +else +rk_clrreg (&grf->ddrc0_con0,NOC_RSP_ERR_STALL ); +} + +static void ddr_set_ddr3_mode (struct rk3368_grf *grf,bool ddr3_mode) +{ +if (ddr3_mode) +rk_setreg (&grf->ddrc0_con0,MSCH0_MAINDDR3_DDR3 ); +else +rk_clrreg (&grf->ddrc0_con0,MSCH0_MAINDDR3_DDR3 ); +} + +static void ddrphy_config (struct rk3368_ddrphy *phy, +u32 tcl,u32 tal,u32 tcwl) +{ +int i; + +/* Set to DDR3 mode */ +clrsetbits_le32 (&phy->reg[1 ],0x3 ,0x0 ); + +/* DDRPHY_REGB: CL, AL */ +clrsetbits_le32 (&phy->reg[0xb ],0xff , tcl <<4 | tal); +/* DDRPHY_REGC: CWL */ +clrsetbits_le32 (&phy->reg[0xc ],0x0f , tcwl); + +/* Update drive-strength */ +writel (0xcc , &phy->reg[0x11 ]); +writel (0xaa , &phy->reg[0x16 ]); +/* +* Update NRCOMP/PRCOMP for all 4 channels (for details of all +* affected registers refer to the documentation of DDRPHY_REG20 +* and DDRPHY_REG21 in the RK3368 TRM. +*/ +for (i =0 ; i <4 ; ++i) { +writel (0xcc , &phy->reg[0x20 + i *0x10 ]); +writel (0x44 , &phy->reg[0x21 + i *0x10 ]); + } + +/* Enable write-leveling calibration bypass */ +setbits_le32 (&phy->reg[2 ],BIT (3 )); +} + +static void copy_to_reg (u32 *dest,const u32 *src,u32 n) +{ +int i; + +for (i =0 ; i < n /sizeof (u32); i++) +writel (*src++, dest++); +} + +static void send_command (struct rk3368_ddr_pctl *pctl,u32 rank,u32 cmd) +{ +u32 mcmd =START_CMD | cmd | rank; + +debug ("%s: writing %x to MCMD\n" , __func__, mcmd); +writel (mcmd, &pctl->mcmd); +while (readl (&pctl->mcmd) &START_CMD ) +/* spin */ ; +} + +static void send_mrs (struct rk3368_ddr_pctl *pctl, +u32 rank,u32 mr_num,u32 mr_data) +{ +u32 mcmd =START_CMD |MRS_CMD | rank | (mr_num <<17 ) | (mr_data <<4 ); + +debug ("%s: writing %x to MCMD\n" , __func__, mcmd); +writel (mcmd, &pctl->mcmd); +while (readl (&pctl->mcmd) &START_CMD ) +/* spin */ ; +} + +static int memory_init (struct rk3368_ddr_pctl *pctl, +struct rk3368_sdram_params *params) +{ +u32 mr[4 ]; +const ulong timeout_ms =500 ; +ulong tmp; + +/* +* Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and +* wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register +* of PCTL. +*/ +writel (POWER_UP_START , &pctl->powctl); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: POWER_UP_START did not complete in %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while (!(readl (&pctl->powstat) &POWER_UP_DONE )); + +/* Configure MR0 through MR3 */ + mr[0 ] =DDR3_MR0_WR (params->pctl_timing.twr) | +DDR3_MR0_CL (params->pctl_timing.tcl) | +DDR3_MR0_DLL_RESET ; + mr[1 ] =DDR3_MR1_RTT120OHM ; + mr[2 ] =DDR3_MR2_TWL (params->pctl_timing.tcwl); + mr[3 ] =0 ; + +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.2 Initialization (DDR3 Initialization Sequence)" +*/ +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,DESELECT_CMD ); +udelay (1 ); +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,PREA_CMD ); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,2 , mr[2 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,3 , mr[3 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,1 , mr[1 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,0 , mr[0 ]); +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,ZQCL_CMD ); + +return 0 ; +} + +static void move_to_config_state (struct rk3368_ddr_pctl *pctl) +{ +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.1 State transition of PCTL (Moving to Config State)" +*/ +u32 state =readl (&pctl->stat) &PCTL_STAT_MSK ; + +switch (state) { +case LOW_POWER : +writel (WAKEUP_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=ACCESS ) +/* spin */ ; + +/* fall-through */ +case ACCESS : +case INIT_MEM : +writel (CFG_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=CONFIG ) +/* spin */ ; +break ; + +case CONFIG : +return ; + +default : +break ; + } +} + +static void move_to_access_state (struct rk3368_ddr_pctl *pctl) +{ +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.1 State transition of PCTL (Moving to Access State)" +*/ +u32 state =readl (&pctl->stat) &PCTL_STAT_MSK ; + +switch (state) { +case LOW_POWER : +if (((readl (&pctl->stat) >>LP_TRIG_SHIFT ) & +LP_TRIG_MASK ) ==1 ) +return ; + +writel (WAKEUP_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=ACCESS ) +/* spin */ ; + +/* fall-through */ +case INIT_MEM : +writel (CFG_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=CONFIG ) +/* spin */ ; + +/* fall-through */ +case CONFIG : +writel (GO_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) ==CONFIG ) +/* spin */ ; +break ; + +case ACCESS : +return ; + +default : +break ; + } +} + +static void ddrctl_reset (struct rk3368_cru *cru) +{ +const u32 ctl_reset =BIT (3 ) |BIT (2 ); +const u32 phy_reset =BIT (1 ) |BIT (0 ); + +rk_setreg (&cru->softrst_con[10 ], ctl_reset | phy_reset); +udelay (1 ); +rk_clrreg (&cru->softrst_con[10 ], ctl_reset | phy_reset); +} + +static void ddrphy_reset (struct rk3368_ddrphy *ddrphy) +{ +clrbits_le32 (&ddrphy->reg[0 ],BIT (3 ) |BIT (2 )); +udelay (1 ); +setbits_le32 (&ddrphy->reg[0 ],BIT (3 ) |BIT (2 )); +} + +static void ddrphy_config_delays (struct rk3368_ddrphy *ddrphy,u32 freq) +{ +u32 dqs_dll_delay; + +setbits_le32 (&ddrphy->reg[0x13 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x14 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x26 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x27 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x36 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x37 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x46 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x47 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x56 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x57 ],BIT (3 )); + +if (freq <=400000000 ) +setbits_le32 (&ddrphy->reg[0xa4 ],0x1f ); +else +clrbits_le32 (&ddrphy->reg[0xa4 ],0x1f ); + +if (freq <681000000 ) + dqs_dll_delay =3 ;/* 67.5 degree delay */ +else + dqs_dll_delay =2 ;/* 45 degree delay */ + +writel (dqs_dll_delay, &ddrphy->reg[0x28 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x38 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x48 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x58 ]); +} + +static int dfi_cfg (struct rk3368_ddr_pctl *pctl) +{ +const ulong timeout_ms =200 ; +ulong tmp; + +writel (DFI_DATA_BYTE_DISABLE_EN , &pctl->dfistcfg0); + +writel (DFI_DRAM_CLK_SR_EN |DFI_DRAM_CLK_DPD_EN , + &pctl->dfistcfg1); +writel (DFI_PARITY_INTR_EN |DFI_PARITY_EN , &pctl->dfistcfg2); +writel (7 <<TLP_RESP_TIME_SHIFT |LP_SR_EN |LP_PD_EN , + &pctl->dfilpcfg0); + +writel (1 , &pctl->dfitphyupdtype0); + +writel (0x1f , &pctl->dfitphyrdlat); +writel (0 , &pctl->dfitphywrdata); +writel (0 , &pctl->dfiupdcfg);/* phyupd and ctrlupd disabled */ + +setbits_le32 (&pctl->dfistcfg0,DFI_INIT_START ); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: DFI init did not complete within %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while ((readl (&pctl->dfiststat0) &1 ) ==0 ); + +return 0 ; +} + +static inline u32 ps_to_tCK (const u32 ps,const ulong freq) +{ +const ulong MHz =1000000 ; +return DIV_ROUND_UP (ps * freq,1000000 * MHz); +} + +static inline u32 ns_to_tCK (const u32 ns,const ulong freq) +{ +return ps_to_tCK (ns *1000 , freq); +} + +static inline u32 tCK_to_ps (const ulong tCK,const ulong freq) +{ +const ulong MHz =1000000 ; +return DIV_ROUND_UP (tCK *1000000 * MHz, freq); +} + +static int pctl_calc_timings (struct rk3368_sdram_params *params, +ulong freq) +{ +struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing; +const ulong MHz =1000000 ; +u32 tccd; +u32 tfaw_as_ps; + +if (params->ddr_speed_bin !=DDR3_1600K ) { +error ("%s: unimplemented DDR3 speed bin %d\n" , + __func__, params->ddr_speed_bin); +return -1 ; + } + +/* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */ + pctl_timing->togcnt1u =DIV_ROUND_UP (freq,2 * MHz); + pctl_timing->togcnt100n =DIV_ROUND_UP (freq /10 ,2 * MHz); + + pctl_timing->tinit =200 ;/* 200 usec */ + pctl_timing->trsth =500 ;/* 500 usec */ + pctl_timing->trefi =78 ;/* 7.8usec = 78 * 100ns */ + params->trefi_mem_ddr3 =ns_to_tCK (pctl_timing->trefi *100 , freq); + +if (freq <= (400 * MHz)) { + pctl_timing->tcl =6 ; + pctl_timing->tcwl =10 ; + }else if (freq <= (533 * MHz)) { + pctl_timing->tcl =8 ; + pctl_timing->tcwl =6 ; + }else if (freq <= (666 * MHz)) { + pctl_timing->tcl =10 ; + pctl_timing->tcwl =7 ; + }else { + pctl_timing->tcl =11 ; + pctl_timing->tcwl =8 ; + } + + pctl_timing->tmrd =4 ;/* 4 tCK (all speed bins) */ + pctl_timing->trfc =ns_to_tCK (350 , freq);/* tRFC: 350 (max) @ 8GBit */ + pctl_timing->trp =max (4u ,ps_to_tCK (13750 , freq)); +/* +* JESD-79: +* READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL +*/ + tccd =4 ; + pctl_timing->trtw = pctl_timing->tcl + tccd/2 +2 - pctl_timing->tcwl; + pctl_timing->tal =0 ; + pctl_timing->tras =ps_to_tCK (35000 , freq); + pctl_timing->trc =ps_to_tCK (48750 , freq); + pctl_timing->trcd =ps_to_tCK (13750 , freq); + pctl_timing->trrd =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->trtp =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->twr =ps_to_tCK (15000 , freq); +/* The DDR3 mode-register does only support even values for tWR > 8. */ +if (pctl_timing->twr >8 ) + pctl_timing->twr = (pctl_timing->twr +1 ) & ~1 ; + pctl_timing->twtr =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->texsr =512 ;/* tEXSR(max) is tDLLLK */ + pctl_timing->txp =max (3u ,ps_to_tCK (6000 , freq)); + pctl_timing->txpdll =max (10u ,ps_to_tCK (24000 , freq)); + pctl_timing->tzqcs =max (64u ,ps_to_tCK (80000 , freq)); + pctl_timing->tzqcsi =10000 ;/* as used by Rockchip */ + pctl_timing->tdqs =1 ;/* fixed for DDR3 */ + pctl_timing->tcksre =max (5u ,ps_to_tCK (10000 , freq)); + pctl_timing->tcksrx =max (5u ,ps_to_tCK (10000 , freq)); + pctl_timing->tcke =max (3u ,ps_to_tCK (5000 , freq)); + pctl_timing->tmod =max (12u ,ps_to_tCK (15000 , freq)); + pctl_timing->trstl =ns_to_tCK (100 , freq); + pctl_timing->tzqcl =max (256u ,ps_to_tCK (320000 , freq));/* tZQoper */ + pctl_timing->tmrr =0 ; + pctl_timing->tckesr = pctl_timing->tcke +1 ;/* JESD-79: tCKE + 1tCK */ + pctl_timing->tdpd =0 ;/* RK3368 TRM: "allowed values for DDR3: 0" */ + + +/* +* The controller can represent tFAW as 4x, 5x or 6x tRRD only. +* We want to use the smallest multiplier that satisfies the tFAW +* requirements of the given speed-bin. If necessary, we stretch out +* tRRD to allow us to operate on a 6x multiplier for tFAW. +*/ + tfaw_as_ps =40000 ;/* 40ns: tFAW for DDR3-1600K, 2KB page-size */ +if (tCK_to_ps (pctl_timing->trrd *6 , freq) < tfaw_as_ps) { +/* If tFAW is > 6 x tRRD, we need to stretch tRRD */ + pctl_timing->trrd =ps_to_tCK (DIV_ROUND_UP (40000 ,6 ), freq); + params->tfaw_mult =TFAW_TRRD_MULT6 ; + }else if (tCK_to_ps (pctl_timing->trrd *5 , freq) < tfaw_as_ps) { + params->tfaw_mult =TFAW_TRRD_MULT6 ; + }else if (tCK_to_ps (pctl_timing->trrd *4 , freq) < tfaw_as_ps) { + params->tfaw_mult =TFAW_TRRD_MULT5 ; + }else { + params->tfaw_mult =TFAW_TRRD_MULT4 ; + } + +return 0 ; +} + +static void pctl_cfg (struct rk3368_ddr_pctl *pctl, +struct rk3368_sdram_params *params, +struct rk3368_grf *grf) +{ +/* Configure PCTL timing registers */ + params->pctl_timing.trefi |=BIT (31 );/* see PCTL_TREFI */ +copy_to_reg (&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u, +sizeof (params->pctl_timing)); +writel (params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3); + +/* Set up ODT write selector and ODT write length */ +writel ((RANK0_ODT_WRITE_SEL |RANK1_ODT_WRITE_SEL ), &pctl->dfiodtcfg); +writel (7 <<ODT_LEN_BL8_W_SHIFT , &pctl->dfiodtcfg1); + +/* Set up the CL/CWL-dependent timings of DFI */ +writel ((params->pctl_timing.tcl -1 ) /2 -1 , &pctl->dfitrddataen); +writel ((params->pctl_timing.tcwl -1 ) /2 -1 , &pctl->dfitphywrlat); + +/* DDR3 */ +writel (params->tfaw_mult |DDR3_EN |DDR2_DDR3_BL_8 , &pctl->mcfg); +writel (0x001c0004 , &grf->ddrc0_con0); + +setbits_le32 (&pctl->scfg,HW_LOW_POWER_EN ); +} + +static int ddrphy_data_training (struct rk3368_ddr_pctl *pctl, +struct rk3368_ddrphy *ddrphy) +{ +const u32 trefi =readl (&pctl->trefi); +const ulong timeout_ms =500 ; +ulong tmp; + +/* disable auto-refresh */ +writel (0 |BIT (31 ), &pctl->trefi); + +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x20 ); +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x21 ); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: did not complete within %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while ((readl (&ddrphy->reg[0xff ]) &0xf ) !=0xf ); + +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,PREA_CMD ); +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x20 ); +/* resume auto-refresh */ +writel (trefi |BIT (31 ), &pctl->trefi); + +return 0 ; +} + +static int sdram_col_row_detect (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_sdram_params *params =dev_get_platdata (dev); +struct rk3368_ddr_pctl *pctl = priv->pctl; +struct rk3368_msch *msch = priv->msch; +const u32 test_pattern =0x5aa5f00f ; +int row, col; +uintptr_t addr; + +move_to_config_state (pctl); +writel (6 , &msch->ddrconf); +move_to_access_state (pctl); + +/* Detect col */ +for (col =11 ; col >=9 ; col--) { +writel (0 ,CONFIG_SYS_SDRAM_BASE ); + addr =CONFIG_SYS_SDRAM_BASE + + (1 << (col + params->chan.bw -1 )); +writel (test_pattern, addr); +if ((readl (addr) == test_pattern) && + (readl (CONFIG_SYS_SDRAM_BASE ) ==0 )) +break ; + } + +if (col ==8 ) { +error ("%s: col detect error\n" , __func__); +return -EINVAL ; + } + +move_to_config_state (pctl); +writel (15 , &msch->ddrconf); +move_to_access_state (pctl); + +/* Detect row*/ +for (row =16 ; row >=12 ; row--) { +writel (0 ,CONFIG_SYS_SDRAM_BASE ); + addr =CONFIG_SYS_SDRAM_BASE + (1 << (row +15 -1 )); +writel (test_pattern, addr); +if ((readl (addr) == test_pattern) && + (readl (CONFIG_SYS_SDRAM_BASE ) ==0 )) +break ; + } + +if (row ==11 ) { +error ("%s: row detect error\n" , __func__); +return -EINVAL ; + } + +/* Record results */ +debug ("%s: col %d, row %d\n" , __func__, col, row); + params->chan.col = col; + params->chan.cs0_row = row; + params->chan.cs1_row = row; + params->chan.row_3_4 =0 ; + +return 0 ; +} + +static int msch_niu_config (struct rk3368_msch *msch, +struct rk3368_sdram_params *params) +{ +int i; +const u8 cols = params->chan.col - ((params->chan.bw ==2 ) ?0 :1 ); +const u8 rows = params->chan.cs0_row; + +/* +* The DDR address-translation table always assumes a 32bit +* bus and the comparison below takes care of adjusting for +* a 16bit bus (i.e. one column-address is consumed). +*/ +const struct { +u8 rows; +u8 columns; +u8 type; + } ddrconf_table[] = { +/* +* C-B-R-D patterns are first. For these we require an +* exact match for the columns and rows (as there's +* one entry per possible configuration). +*/ + [0 ] = { .rows =13 , .columns =10 , .type =DMC_MSCH_CBRD }, + [1 ] = { .rows =14 , .columns =10 , .type =DMC_MSCH_CBRD }, + [2 ] = { .rows =15 , .columns =10 , .type =DMC_MSCH_CBRD }, + [3 ] = { .rows =16 , .columns =10 , .type =DMC_MSCH_CBRD }, + [4 ] = { .rows =14 , .columns =11 , .type =DMC_MSCH_CBRD }, + [5 ] = { .rows =15 , .columns =11 , .type =DMC_MSCH_CBRD }, + [6 ] = { .rows =16 , .columns =11 , .type =DMC_MSCH_CBRD }, + [7 ] = { .rows =13 , .columns =9 , .type =DMC_MSCH_CBRD }, + [8 ] = { .rows =14 , .columns =9 , .type =DMC_MSCH_CBRD }, + [9 ] = { .rows =15 , .columns =9 , .type =DMC_MSCH_CBRD }, + [10 ] = { .rows =16 , .columns =9 , .type =DMC_MSCH_CBRD }, +/* +* 11 through 13 are C-R-B-D patterns. These are +* matched for an exact number of columns and to +* ensure that the hardware uses at least as many rows +* as the pattern requires (i.e. we make sure that +* there's no gaps up until we hit the device/chip-select; +* however, these patterns can accept up to 16 rows, +* as the row-address continues right after the CS +* switching) +*/ + [11 ] = { .rows =15 , .columns =10 , .type =DMC_MSCH_CRBD }, + [12 ] = { .rows =14 , .columns =11 , .type =DMC_MSCH_CRBD }, + [13 ] = { .rows =13 , .columns =10 , .type =DMC_MSCH_CRBD }, +/* +* 14 and 15 are catch-all variants using a C-B-D-R +* scheme (i.e. alternating the chip-select every time +* C-B overflows) and stuffing the remaining C-bits +* into the top. Matching needs to make sure that the +* number of columns is either an exact match (i.e. we +* can use less the the maximum number of rows) -or- +* that the columns exceed what is given in this table +* and the rows are an exact match (in which case the +* remaining C-bits will be stuffed onto the top after +* the device/chip-select switches). +*/ + [14 ] = { .rows =16 , .columns =10 , .type =DMC_MSCH_CBDR }, + [15 ] = { .rows =16 , .columns =9 , .type =DMC_MSCH_CBDR }, + }; + +/* +* For C-B-R-D, we need an exact match (i.e. both for the number of +* columns and rows), while for C-B-D-R, only the the number of +* columns needs to match. +*/ +for (i =0 ; i <ARRAY_SIZE (ddrconf_table); i++) { +bool match = false; + +/* If this entry if for a different matcher, then skip it */ +if (ddrconf_table[i].type != params->memory_schedule) +continue ; + +/* +* Match according to the rules (exact/inexact/at-least) +* documented in the ddrconf_table above. +*/ +switch (params->memory_schedule) { +case DMC_MSCH_CBRD : + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows == rows); +break ; + +case DMC_MSCH_CRBD : + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows <= rows); +break ; + +case DMC_MSCH_CBDR : + match = (ddrconf_table[i].columns == cols) || + ((ddrconf_table[i].columns <= cols) && + (ddrconf_table[i].rows == rows)); +break ; + +default : +break ; + } + +if (match) { +debug ("%s: setting ddrconf 0x%x\n" , __func__, i); +writel (i, &msch->ddrconf); +return 0 ; + } + } + +error ("%s: ddrconf (NIU config) not found\n" , __func__); +return -EINVAL ; +} + +static void dram_all_config (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_pmu_grf *pmugrf = priv->pmugrf; +struct rk3368_sdram_params *params =dev_get_platdata (dev); +const struct rk3288_sdram_channel *info = ¶ms->chan; +u32 sys_reg =0 ; +const int chan =0 ; + + sys_reg |=DDR3 <<SYS_REG_DDRTYPE_SHIFT ; + sys_reg |=0 <<SYS_REG_NUM_CH_SHIFT ; + + sys_reg |= info->row_3_4 <<SYS_REG_ROW_3_4_SHIFT (chan); + sys_reg |=1 <<SYS_REG_CHINFO_SHIFT (chan); + sys_reg |= (info->rank -1 ) <<SYS_REG_RANK_SHIFT (chan); + sys_reg |= (info->col -9 ) <<SYS_REG_COL_SHIFT (chan); + sys_reg |= info->bk ==3 ?0 :1 <<SYS_REG_BK_SHIFT (chan); + sys_reg |= (info->cs0_row -13 ) <<SYS_REG_CS0_ROW_SHIFT (chan); + sys_reg |= (info->cs1_row -13 ) <<SYS_REG_CS1_ROW_SHIFT (chan); + sys_reg |= (2 >> info->bw) <<SYS_REG_BW_SHIFT (chan); + sys_reg |= (2 >> info->dbw) <<SYS_REG_DBW_SHIFT (chan); + +writel (sys_reg, &pmugrf->os_reg[2 ]); +} + +static int setup_sdram (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_sdram_params *params =dev_get_platdata (dev); + +struct rk3368_ddr_pctl *pctl = priv->pctl; +struct rk3368_ddrphy *ddrphy = priv->phy; +struct rk3368_cru *cru = priv->cru; +struct rk3368_grf *grf = priv->grf; +struct rk3368_msch *msch = priv->msch; + +int ret; + +/* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */ + ret =clk_set_rate (&priv->ddr_clk,2 * params->ddr_freq); +if (ret <0 ) { +debug ("%s: could not set DDR clock: %d\n" , __func__, ret); +return ret; + } + +/* Update the read-latency for the RK3368 */ +writel (0x32 , &msch->readlatency); + +/* Initialise the DDR PCTL and DDR PHY */ +ddrctl_reset (cru); +ddrphy_reset (ddrphy); +ddrphy_config_delays (ddrphy, params->ddr_freq); +dfi_cfg (pctl); +/* Configure relative system information of grf_ddrc0_con0 register */ +ddr_set_ddr3_mode (grf, true); +ddr_set_noc_spr_err_stall (grf, true); +/* Calculate timings */ +pctl_calc_timings (params, params->ddr_freq); +/* Initialise the device timings in protocol controller */ +pctl_cfg (pctl, params, grf); +/* Configure AL, CL ... information of PHY registers */ +ddrphy_config (ddrphy, + params->pctl_timing.tcl, + params->pctl_timing.tal, + params->pctl_timing.tcwl); + +/* Initialize DRAM and configure with mode-register values */ + ret =memory_init (pctl, params); +if (ret) + goto error; + +move_to_config_state (pctl); +/* Perform data-training */ +ddrphy_data_training (pctl, ddrphy); +move_to_access_state (pctl); + +/* TODO(prt): could detect rank in training... */ + params->chan.rank =2 ; +/* TODO(prt): bus width is not auto-detected (yet)... */ + params->chan.bw =2 ;/* 32bit wide bus */ + params->chan.dbw = params->chan.dbw;/* 32bit wide bus */ + +/* DDR3 is always 8 bank */ + params->chan.bk =3 ; +/* Detect col and row number */ + ret =sdram_col_row_detect (dev); +if (ret) + goto error; + +/* Configure NIU DDR configuration */ + ret =msch_niu_config (msch, params); +if (ret) + goto error; + +/* set up OS_REG to communicate w/ next stage and OS */ +dram_all_config (dev); + +return 0 ; + +error: +printf ("DRAM init failed!\n" ); +hang (); +} +#endif + +static int rk3368_dmc_ofdata_to_platdata (struct udevice *dev) +{ +int ret =0 ; + +#if !CONFIG_IS_ENABLED (OF_PLATDATA ) +struct rk3368_sdram_params *plat =dev_get_platdata (dev); + + ret =regmap_init_mem (dev, &plat->map); +if (ret) +return ret; +#endif + +return ret; +} + +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +static int conv_of_platdata (struct udevice *dev) +{ +struct rk3368_sdram_params *plat =dev_get_platdata (dev); +struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat; +int ret; + + plat->ddr_freq = of_plat->rockchip_ddr_frequency; + plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin; + plat->memory_schedule = of_plat->rockchip_memory_schedule; + + ret =regmap_init_mem_platdata (dev, of_plat->reg, +ARRAY_SIZE (of_plat->reg) /2 , + &plat->map); +if (ret) +return ret; + +return 0 ; +} +#endif + +static int rk3368_dmc_probe (struct udevice *dev) +{ +#ifdef CONFIG_TPL_BUILD +struct rk3368_sdram_params *plat =dev_get_platdata (dev); +struct rk3368_ddr_pctl *pctl; +struct rk3368_ddrphy *ddrphy; +struct rk3368_cru *cru; +struct rk3368_grf *grf; +struct rk3368_msch *msch; +int ret; +struct udevice *dev_clk; +#endif +struct dram_info *priv =dev_get_priv (dev); + +#if CONFIG_IS_ENABLED (OF_PLATDATA ) + ret =conv_of_platdata (dev); +if (ret) +return ret; +#endif + + priv->pmugrf =syscon_get_first_range (ROCKCHIP_SYSCON_PMUGRF ); +debug ("%s: pmugrf=%p\n" , __func__, priv->pmugrf); + +#ifdef CONFIG_TPL_BUILD + pctl =regmap_get_range (plat->map,0 ); + ddrphy =regmap_get_range (plat->map,1 ); + msch =syscon_get_first_range (ROCKCHIP_SYSCON_MSCH ); + grf =syscon_get_first_range (ROCKCHIP_SYSCON_GRF ); + + priv->pctl = pctl; + priv->phy = ddrphy; + priv->msch = msch; + priv->grf = grf; + + ret =rockchip_get_clk (&dev_clk); +if (ret) +return ret; + priv->ddr_clk.id =CLK_DDR ; + ret =clk_request (dev_clk, &priv->ddr_clk); +if (ret) +return ret; + + cru =rockchip_get_cru (); + priv->cru = cru; +if (IS_ERR (priv->cru)) +return PTR_ERR (priv->cru); + + ret =setup_sdram (dev); +if (ret) +return ret; +#endif + + priv->info.base =0 ; + priv->info.size = +rockchip_sdram_size ((phys_addr_t)&priv->pmugrf->os_reg[2 ]); + +/* +* we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff +* is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is +* inaccessible for some IP controller. +*/ + priv->info.size =min (priv->info.size, (size_t )0xfe000000 ); + +return 0 ; +} + +static int rk3368_dmc_get_info (struct udevice *dev,struct ram_info *info) +{ +struct dram_info *priv =dev_get_priv (dev); + + *info = priv->info; +return 0 ; +} + +static struct ram_ops rk3368_dmc_ops = { + .get_info = rk3368_dmc_get_info, +}; + + +static const struct udevice_id rk3368_dmc_ids[] = { + { .compatible ="rockchip,rk3368-dmc" }, + { } +}; + +U_BOOT_DRIVER (dmc_rk3368) = { + .name ="rockchip_rk3368_dmc" , + .id =UCLASS_RAM , + .of_match = rk3368_dmc_ids, + .ops = &rk3368_dmc_ops, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size =sizeof (struct dram_info ), + .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size =sizeof (struct dram_info ), + .platdata_auto_alloc_size =sizeof (struct rk3368_sdram_params ), +};include/dt-bindings/memory/rk3368-dmc.h new file +30
-0@@ -0,0 +1,30 @@ +#ifndef DT_BINDINGS_RK3368_DMC_H +#define DT_BINDINGS_RK3368_DMC_H + +#define DMC_MSCH_CBDR 0x0 +#define DMC_MSCH_CBRD 0x1 +#define DMC_MSCH_CRBD 0x2 + +#define DDR3_800D 0 +#define DDR3_800E 1 +#define DDR3_1066E 2 +#define DDR3_1066F 3 +#define DDR3_1066G 4 +#define DDR3_1333F 5 +#define DDR3_1333G 6 +#define DDR3_1333H 7 +#define DDR3_1333J 8 +#define DDR3_1600G 9 +#define DDR3_1600H 10 +#define DDR3_1600J 11 +#define DDR3_1600K 12 +#define DDR3_1866J 13 +#define DDR3_1866K 14 +#define DDR3_1866L 15 +#define DDR3_1866M 16 +#define DDR3_2133K 17 +#define DDR3_2133L 18 +#define DDR3_2133M 19 +#define DDR3_2133N 20 + +#endif
PATCH v3 51/66 rockchip: rk3368: dts: add DMC node in rk3368.dtsi
In reply to Philipp TomsichFor full SPL support, including DRAM initialisation, we need a few nodes from the DTS: this commit adds the DMC (DRAM controller) node, the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU as 'u-boot,dm-pre-reloc'. In addition to this, we also include the dt-binding for the DMC to allow DTS files including this DTSI to refer to the symbolic constants for the DDR3 bin and for the memory-schedule.
Note that the DMC contains both the memory regions for the (Designware) protocol controller as well as the DDR PHY.
Signed-off-by Philipp Tomsich <[email protected]>
---
Changes in v3: None
Changes in v2:
- removes a 'u-boot,dm-pre-reloc' from dmc-node in rk3368.dtsi
arch/arm/dts/rk3368.dtsi | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-)
arch/arm/dts/rk3368.dtsi +19 -6
@@ -46,6 +46,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/memory/rk3368-dmc.h> / { compatible = "rockchip,rk3368";
@@ -227,6 +228,22 @@ #clock-cells = <0>; }; + dmc: dmc at ff610000 { + compatible = "rockchip,rk3368-dmc", "syscon"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,msch = <&service_msch>; + reg = <0 0xff610000 0 0x400 + 0 0xff620000 0 0x400>; + }; + + service_msch: syscon at ffac0000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3368-msch", "syscon"; + reg = <0x0 0xffac0000 0x0 0x2000>; + status = "okay"; + }; + sdmmc: dwmmc at ff0c0000 { compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff0c0000 0x0 0x4000>;
@@ -546,12 +563,6 @@ status = "disabled"; }; - dmc: dmc at ff610000 { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3368-dmc", "syscon"; - reg = <0x0 0xff610000 0x0 0x1000>; - }; - i2c0: i2c at ff650000 { compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; reg = <0x0 0xff650000 0x0 0x1000>;
@@ -658,6 +669,7 @@ }; cru: clock-controller at ff760000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3368-cru"; reg = <0x0 0xff760000 0x0 0x1000>; rockchip,grf = <&grf>;
@@ -666,6 +678,7 @@ }; grf: syscon at ff770000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3368-grf", "syscon"; reg = <0x0 0xff770000 0x0 0x1000>; };
Signature · 1 line
2.1.4
PATCH v3 51/66 rockchip: rk3368: dts: add DMC node in rk3368.dtsi
Quoted 13 lines · Philipp Tomsich
For full SPL support, including DRAM initialisation, we need a few nodes from the DTS: this commit adds the DMC (DRAM controller) node, the
service_msch(memory scheduler) node and marks GRF, PMUGRF and CRU as 'u-boot,dm-pre-reloc'. In addition to this, we also include the dt-binding for the DMC to allow DTS files including this DTSI to refer to the symbolic constants for the DDR3 bin and for the memory-schedule.Note that the DMC contains both the memory regions for the (Designware) protocol controller as well as the DDR PHY.
Signed-off-by Philipp Tomsich <[email protected]>
Quoted 8 lines
---
Changes in v3: None
Changes in v2:
- removes a 'u-boot,dm-pre-reloc' from dmc-node inrk3368.dtsiarch/arm/dts/rk3368.dtsi | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-)
Reviewed-by Simon Glass <[email protected]>
PATCH v3 52/66 rockchip: rk3368: spl: enable SPL_FRAMEWORK in rk3368_common.h
In reply to Philipp TomsichTo build TPL and SPL stages for the RK3368, we will also need to enable the SPL_FRAMEWORK.
Signed-off-by Philipp Tomsich <[email protected]>
Version-changes: 2
- dropped duplicate definition (this in fact dropped one of the patches in this series) of CONFIG_SYS_SDRAM_BASE from rk3368_common.h
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
include/configs/rk3368_common.h | 1 + 1 file changed, 1 insertion(+)
include/configs/rk3368_common.h +1 -0
@@ -23,6 +23,7 @@#define COUNTER_FREQUENCY 24000000 +#define CONFIG_SPL_FRAMEWORK #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_TEXT_BASE 0x00200000
Signature · 1 line
2.1.4
PATCH v3 53/66 rockchip: rk3368: spl: add TPL support
In reply to Philipp TomsichThis adds the TPL support for the RK3368, including the u-boot-tpl.lds.
Signed-off-by Philipp Tomsich <[email protected]>
---
Changes in v3:
- removes the '#define DEBUG'
- uses the syscon API to access GRF and SGRF to avoid using hard-coded addresses
Changes in v2:
- copies the enum for the IOMUX config of the debug UART into the TPL support code, as the various constants are otherwise private to the pinctrl code (and we can't include pinctrl in the TPL stage due to size constraints/dependencies)
arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3368-board-tpl.c | 177 +++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds | 13 ++ 3 files changed, 191 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3368-board-tpl.c create mode 100644 arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds
arch/arm/mach-rockchip/Makefile +1 -0
@@ -12,6 +12,7 @@ obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o +obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
arch/arm/mach-rockchip/rk3368-board-tpl.c new file +177 -0
177 lines not on this page · raw message
arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds new file +13 -0
@@ -0,0 +1,13 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#undef CONFIG_SPL_TEXT_BASE +#define CONFIG_SPL_TEXT_BASE CONFIG_TPL_TEXT_BASE + +#undef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_MAX_SIZE CONFIG_TPL_MAX_SIZE + +#include "../../cpu/armv8/u-boot-spl.lds"
Signature · 1 line
2.1.4
PATCH v3 53/66 rockchip: rk3368: spl: add TPL support
Quoted 17 lines · Philipp Tomsich
This adds the TPL support for the RK3368, including the
u-boot-tpl.lds.Signed-off-by Philipp Tomsich <[email protected]>---
Changes in v3:
- removes the '#define DEBUG'
- uses the syscon API to access GRF and SGRF to avoid using hard-coded addressesChanges in v2:
- copies the enum for the IOMUX config of the debug UART into the TPL support code, as the various constants are otherwise private to the pinctrl code (and we can't include pinctrl in the TPL stage due to size constraints/dependencies)
Quoted 6 lines
arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3368-board-tpl.c | 177 +++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds | 13 ++ 3 files changed, 191 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3368-board-tpl.c create mode 100644 arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds
Reviewed-by Simon Glass <[email protected]>
We still have the timer address, but it looks like you are trying to drop that in the other series.
PATCH v3 54/66 rockchip: spl: make spl-boot-order code reusable (split from rk3399)
In reply to Philipp TomsichIn order to reuse the support for the u-boot,spl-boot-order property from the rk3399, we split it into a reusable module that can be included by the SPL code for any of our boards.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2:
- added in v2
arch/arm/mach-rockchip/Makefile | 2 +- arch/arm/mach-rockchip/rk3399-board-spl.c | 104 ---------------------------- arch/arm/mach-rockchip/spl-boot-order.c | 108 ++++++++++++++++++++++++++++++ 3 files changed, 109 insertions(+), 105 deletions(-) create mode 100644 arch/arm/mach-rockchip/spl-boot-order.c
arch/arm/mach-rockchip/Makefile +1 -1
@@ -19,7 +19,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o -obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
arch/arm/mach-rockchip/rk3399-board-spl.c +0 -104
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arch/arm/mach-rockchip/spl-boot-order.c new file +108 -0
108 lines not on this page · raw message
Signature · 1 line
2.1.4
PATCH v3 55/66 rockchip: rk3368: spl: add SPL support
In reply to Philipp TomsichAdds SPL support for the RK3368 (assuming that our TPL stage has initialised DRAM and set up the memory firewall).
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2:
- reuses the support for configuring the boot order using the u-boot,spl-boot-order property
- drops the initialisation of the debug_uart
- adds pinctrl-configuration for the preloader UART
arch/arm/mach-rockchip/Makefile | 2 +- arch/arm/mach-rockchip/rk3368-board-spl.c | 98 +++++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-rockchip/rk3368-board-spl.c
arch/arm/mach-rockchip/Makefile +1 -1
@@ -18,7 +18,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o -obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
arch/arm/mach-rockchip/rk3368-board-spl.c new file +98 -0
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Signature · 1 line
2.1.4
PATCH v3 56/66 rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368
In reply to Philipp TomsichWith SPL and TPL support for the RK3368 in place, mark SPL and TPL as supported from Kconfig for the RK3368. As this is primarily tested on the RK3368-uQ7, we'll leave it to board's individual defconfig to enable.
Also enable DEBUG_UART_BOARD_INIT for the RK3368, so we get output during the early boot-up, as we turn on TPL and SPL.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+)
arch/arm/mach-rockchip/Kconfig +7 -0
@@ -67,6 +67,13 @@ config ROCKCHIP_RK3328 config ROCKCHIP_RK3368 bool "Support Rockchip RK3368" select ARM64 + select SUPPORT_SPL + select SUPPORT_TPL + select SPL_SEPARATE_BSS + select SPL_SERIAL_SUPPORT + select TPL_SERIAL_SUPPORT + select ENABLE_ARM_SOC_BOOT0_HOOK + select DEBUG_UART_BOARD_INIT select SYS_NS16550 help The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
Signature · 1 line
2.1.4
PATCH v3 56/66 rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368
Hi Philipp:
2017-07-29 3:22 GMT+08:00 Philipp Tomsich <
[email protected]>:
Quoted 25 lines
With SPL and TPL support for the RK3368 in place, mark SPL and TPL as supported from
Kconfigfor the RK3368. As this is primarily tested on the RK3368-uQ7, we'll leave it to board's individual defconfig to enable.Also enable
DEBUG_UART_BOARD_INITfor the RK3368, so we get output during the early boot-up, as we turn on TPL and SPL.Signed-off-by Philipp Tomsich <[email protected]>Reviewed-by Simon Glass <[email protected]>---
Changes in v3: None
Changes in v2: Nonearch/arm/mach-rockchip/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+)arch/arm/mach-rockchip/ renamed from arch/arm/mach-rockchip/Kconfig +0
-0
Kconfig
index 8a89b51..8406e33 100644
arch/arm/mach-rockchip/Kconfig config ROCKCHIP_RK3328 · line 75
Quoted 9 lines
arch/arm/mach-rockchip/Kconfig +5
-0@@ -67,6 +67,13 @@ config ROCKCHIP_RK3328 config ROCKCHIP_RK3368 bool "Support Rockchip RK3368" select ARM64 + select SUPPORT_SPL + select SUPPORT_TPL + select SPL_SEPARATE_BSS + select SPL_SERIAL_SUPPORT + select TPL_SERIAL_SUPPORT
These should depends on TPL/SPL, or we will get compile warnings like
bellow on non-SPL/TPL boards(px5 evb):
(ROCKCHIP_RK3368 && ROCKCHIP_RK3399 && X86_RUN_64BIT) selectsSPL_SEPARATE_BSS which has unmet direct dependencies (SPL)
+ select ENABLE_ARM_SOC_BOOT0_HOOK
Quoted 13 lines
arch/arm/mach-rockchip/Kconfig +1
-0+ select DEBUG_UART_BOARD_INIT select SYS_NS16550 help The Rockchip RK3368 is a ARM-based SoC with a octa-core(organised
--
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PATCH v3 56/66 rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368
Looks like SPL_SEPARATE_BSS is special.
Guess, I’ll need to figure out how to best deal with that one (or fall back to defining it via defconfig until we can enable TPL/SPL for all RK3368 board). I wonder how an implies would behave here...
Quoted 55 lines · Andy Yan
Hi Philipp:
2017-07-29 3:22 GMT+08:00 Philipp Tomsich <philipp.tomsich at theobroma-systems.com <mailto:[email protected]>>:
With SPL and TPL support for the RK3368 in place, mark SPL and TPL as
supported fromKconfigfor the RK3368. As this is primarily tested on
the RK3368-uQ7, we'll leave it to board's individual defconfig to
enable.Also enable
DEBUG_UART_BOARD_INITfor the RK3368, so we get output during the early boot-up, as we turn on TPL and SPL.Signed-off-by Philipp Tomsich <philipp.tomsich at theobroma-systems.com <mailto:[email protected]>>Reviewed-by Simon Glass <sjg at chromium.org <mailto:[email protected]>>---
Changes in v3: None
Changes in v2: Nonearch/arm/mach-rockchip/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+)arch/arm/mach-rockchip/Kconfig +7
-1@@ -67,6 +67,13 @@ config ROCKCHIP_RK3328 config ROCKCHIP_RK3368 bool "Support Rockchip RK3368" select ARM64 + select SUPPORT_SPL + select SUPPORT_TPL + select SPL_SEPARATE_BSS + select SPL_SERIAL_SUPPORT + select TPL_SERIAL_SUPPORT These should depends on TPL/SPL, or we will get compile warnings like bellow on non-SPL/TPL boards(px5 evb): (ROCKCHIP_RK3368 && ROCKCHIP_RK3399 && X86_RUN_64BIT) selects SPL_SEPARATE_BSS which has unmet direct dependencies (SPL) + select ENABLE_ARM_SOC_BOOT0_HOOK + select DEBUG_UART_BOARD_INIT select SYS_NS16550 help The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised --2.1.4
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PATCH v3 57/66 rockchip: spi: enable support for the rk_spi driver for the RK3368
In reply to Philipp TomsichFor the RK3368, we can reuse the SPI driver (although we'll have to eventually investigate whether it can be merged with the designware_spi.c driver) also used for the RK3288 and RK3399. This adds the necessary compatible string to support the RK3368.
Note that the assumption that GPLL will be clocked at 594MHz is not true for the RK3368, but this will not lead to incorrect functioning (just to a lower-than-expected SPI operating frequency): this has been documented in the driver, so it doesn't cause any headaches when someone next needs to touch the clock code of this driver.
Signed-off-by Philipp Tomsich <[email protected]>
Version-changes: 2
- added in this version
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
drivers/spi/rk_spi.c | 9 +++++++++ 1 file changed, 9 insertions(+)
drivers/spi/rk_spi.c +9 -0
@@ -210,6 +210,14 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)static int rockchip_spi_calc_modclk (ulong max_freq) { +/* +* While this is not strictly correct for the RK3368, as the +* GPLL will be 576MHz, things will still work, as the +* clk_set_rate(...) implementation in our clock-driver will +* chose the next closest rate not exceeding what we request +* based on the output of this function. +*/ +unsigned div;const unsigned long gpll_hz =594000000UL ;
@@ -443,6 +451,7 @@ static const struct dm_spi_ops rockchip_spi_ops = {static const struct udevice_id rockchip_spi_ids[] = { { .compatible ="rockchip,rk3288-spi" }, + { .compatible ="rockchip,rk3368-spi" }, { .compatible ="rockchip,rk3399-spi" }, { } };
Signature · 1 line
2.1.4
PATCH v3 58/66 rockchip: board: lion-rk3368: add support for the RK3368-uQ7
In reply to Philipp TomsichThe RK3368-uQ7 (codenamed 'Lion') is a micro-Qseven (40mm x 70mm, MXM-230 edge connector compatible with the Qseven specification) form-factor system-on-module based on the octo-core Rockchip RK3368. It is designed, supported and manufactured by Theobroma Systems.
It provides the following features:
- 8x Cortex-A53 (in 2 clusters of 4 cores each)
- (on-module) up to 4GB of DDR3 memory
- (on-module) SPI-NOR flash
- (on-module) eMMC
- Gigabit Ethernet (with an on-module KSZ9031 PHY)
- USB
- HDMI
- MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group)
- various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...)
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3:
- (after rebase) update defconfig
- (after rebase and defconfig update) lion_rk3368.h: remove CONFIG_ENV_IS_NOWHERE
- moves remaining 'u-boot,dm-pre-reloc' to -u-boot.dtsi
- marks sgrf-node as pre-reloc
- defines SPL_LDSCRIPT and TPL_LDSCRIPT via defconfig
Changes in v2:
- marks pinctrl-node as 'u-boot,dm-pre-reloc' to ensure MMC2 (eMMC) works in the SPL stage
- makes uart0 as 'u-boot,dm-pre-reloc' to allow initialising the preloader console (instead of relying solely on the debug UART)
- adds support for SPI1 (and the on-module SPI flash)
- splits the a 'u-boot.dtsi' off the DTS file
- updates the defconfig for SPI and SPI flash support
arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3368-lion-u-boot.dtsi | 88 ++++++++++ arch/arm/dts/rk3368-lion.dts | 195 +++++++++++++++++++++ arch/arm/dts/rk3368.dtsi | 4 - arch/arm/mach-rockchip/rk3368/Kconfig | 21 +++ board/theobroma-systems/lion_rk3368/Kconfig | 15 ++ board/theobroma-systems/lion_rk3368/MAINTAINERS | 10 ++ board/theobroma-systems/lion_rk3368/Makefile | 7 + board/theobroma-systems/lion_rk3368/README | 60 +++++++ .../theobroma-systems/lion_rk3368/fit_spl_atf.its | 51 ++++++ board/theobroma-systems/lion_rk3368/lion_rk3368.c | 25 +++ configs/lion-rk3368_defconfig | 93 ++++++++++ include/configs/lion_rk3368.h | 18 ++ 13 files changed, 584 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/rk3368-lion-u-boot.dtsi create mode 100644 arch/arm/dts/rk3368-lion.dts create mode 100644 board/theobroma-systems/lion_rk3368/Kconfig create mode 100644 board/theobroma-systems/lion_rk3368/MAINTAINERS create mode 100644 board/theobroma-systems/lion_rk3368/Makefile create mode 100644 board/theobroma-systems/lion_rk3368/README create mode 100644 board/theobroma-systems/lion_rk3368/fit_spl_atf.its create mode 100644 board/theobroma-systems/lion_rk3368/lion_rk3368.c create mode 100644 configs/lion-rk3368_defconfig create mode 100644 include/configs/lion_rk3368.h
arch/arm/dts/Makefile +1 -0
@@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-mickey.dtb \ rk3288-veyron-minnie.dtb \ rk3328-evb.dtb \ + rk3368-lion.dtb \ rk3368-sheep.dtb \ rk3368-geekbox.dtb \ rk3368-px5-evb.dtb \
arch/arm/dts/rk3368-lion-u-boot.dtsi new file +88 -0
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arch/arm/dts/rk3368-lion.dts new file +195 -0
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arch/arm/dts/rk3368.dtsi +0 -4
@@ -238,7 +238,6 @@ }; service_msch: syscon at ffac0000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3368-msch", "syscon"; reg = <0x0 0xffac0000 0x0 0x2000>; status = "okay";
@@ -658,7 +657,6 @@ }; pmugrf: syscon at ff738000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3368-pmugrf", "syscon"; reg = <0x0 0xff738000 0x0 0x1000>; };
@@ -669,7 +667,6 @@ }; cru: clock-controller at ff760000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3368-cru"; reg = <0x0 0xff760000 0x0 0x1000>; rockchip,grf = <&grf>;
@@ -678,7 +675,6 @@ }; grf: syscon at ff770000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3368-grf", "syscon"; reg = <0x0 0xff770000 0x0 0x1000>; };
arch/arm/mach-rockchip/rk3368/Kconfig +21 -0
@@ -3,6 +3,26 @@ if ROCKCHIP_RK3368 choice prompt "RK3368 board" +config TARGET_LION_RK3368 + bool "Theobroma Systems RK3368-uQ7 (Lion) module" + help + The RK3368-uQ7 is a micro-Qseven form-factor (40mm x 70mm, + MXM-230 connector) system-on-module designed by Theobroma + Systems for industrial applications. + + It provides the following features: + - 8x Cortex-A53 (in 2 clusters of 4 cores each) + - (on-module) up to 4GB of DDR3 memory + - (on-module) SPI-NOR flash + - (on-module) eMMC + - Gigabit Ethernet (with an on-module KSZ9031 PHY) + - USB + - HDMI + - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group) + - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...) + - on-module STM32 providing CAN, RTC and fan-control + - (optional on-module) EAL4+-certified security module + config TARGET_SHEEP bool "Sheep board" help
@@ -25,6 +45,7 @@ endchoice config SYS_SOC default "rockchip" +source "board/theobroma-systems/lion_rk3368/Kconfig" source "board/rockchip/sheep_rk3368/Kconfig" source "board/geekbuying/geekbox/Kconfig" source "board/rockchip/evb_px5/Kconfig"
board/theobroma-systems/lion_rk3368/Kconfig new file +15 -0
@@ -0,0 +1,15 @@ +if TARGET_LION_RK3368 + +config SYS_BOARD + default "lion_rk3368" + +config SYS_VENDOR + default "theobroma-systems" + +config SYS_CONFIG_NAME + default "lion_rk3368" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif
board/theobroma-systems/lion_rk3368/MAINTAINERS new file +10 -0
@@ -0,0 +1,10 @@ +LION-RK3368 (RK3368-uQ7 system-on-module) +M: Philipp Tomsich <[email protected]> +M: Klaus Goger <[email protected]> +S: Maintained +F: board/theobroma-systems/lion_rk3368 +F: include/configs/lion_rk3368.h +F: arch/arm/dts/rk3368-lion.dts +F: configs/lion-rk3368_defconfig +W: https://www.theobroma-systems.com/rk3368-uq7/tech-specs +T: git git://git.theobroma-systems.com/lion-u-boot.git
board/theobroma-systems/lion_rk3368/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += lion_rk3368.o
board/theobroma-systems/lion_rk3368/README new file +60 -0
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board/theobroma-systems/lion_rk3368/fit_spl_atf.its new file +51 -0
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board/theobroma-systems/lion_rk3368/lion_rk3368.c new file +25 -0
@@ -0,0 +1,25 @@ +/* +* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0+ +*/ +#include <common.h> +#include <dm.h> +#include <ram.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk3368.h> +#include <asm/arch/timer.h> +#include <syscon.h> + +DECLARE_GLOBAL_DATA_PTR ; + +int mach_cpu_init (void ) +{ +return 0 ; +} + +int board_init (void ) +{ +return 0 ; +}
configs/lion-rk3368_defconfig new file +93 -0
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include/configs/lion_rk3368.h new file +18 -0
@@ -0,0 +1,18 @@ +/* +* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __CONFIGS_LION_RK3368_H +#define __CONFIGS_LION_RK3368_H + +#include <configs/rk3368_common.h> + +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define KERNEL_LOAD_ADDR 0x280000 +#define DTB_LOAD_ADDR 0x5600000 +#define INITRD_LOAD_ADDR 0x5bf0000 +#define CONFIG_ENV_SIZE 0x2000 + +#endif
Signature · 1 line
2.1.4
PATCH v3 59/66 spl: Kconfig: migrate $(SPL_TPL_)LDSCRIPT to Kconfig
In reply to Philipp TomsichNow that we have split up SPL_LDSCRIPT into a SPL and TPL variant and have started to use the TPL-variant for the RK3368, it's time to clean up behind ourselves: move both variants into Kconfig and remove them from the whitelist.
Signed-off-by Philipp Tomsich <[email protected]>
---
Changes in v3:
- moves SPL_LDSCRIPT and TPL_LDSCRIPT into Kconfig, as requested by by Tom; this gets rid of the whitelist-entry for SPL_LDSCRIPT (which qualifies as a preexisting condition) and of the newly created one for TPL_LDSCRIPT
Changes in v2: None
common/spl/Kconfig | 18 ++++++++++++++++++ scripts/Makefile.spl | 9 ++++++++- scripts/config_whitelist.txt | 2 -- 3 files changed, 26 insertions(+), 3 deletions(-)
common/spl/Kconfig +18 -0
@@ -18,6 +18,15 @@ config SPL if SPL +config SPL_LDSCRIPT + string "Linker script for the SPL stage" + depends on SPL + help + The SPL stage will usually require a different linker-script + (as it runs from a different memory region) than the regular + U-Boot stage. Set this to the path of the linker-script to + be used for SPL. + config SPL_BOARD_INIT bool "Call board-specific initialization in SPL" help
@@ -707,6 +716,15 @@ config TPL if TPL +config TPL_LDSCRIPT + string "Linker script for the TPL stage" + depends on TPL + help + The TPL stage will usually require a different linker-script + (as it runs from a different memory region) than the regular + U-Boot stage. Set this to the path of the linker-script to + be used for TPL. + config TPL_BOOTROM_SUPPORT bool "Support returning to the BOOTROM (from TPL)" help
scripts/Makefile.spl +8 -1
@@ -103,9 +103,16 @@ u-boot-spl-platdata := $(obj)/dts/dt-platdata.o endif # Linker Script -ifdef CONFIG_$(SPL_TPL_)LDSCRIPT +# First test whether there's a linker-script for the specific stage defined... +ifneq ($(CONFIG_$(SPL_TPL_)LDSCRIPT),) # need to strip off double quotes LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_$(SPL_TPL_)LDSCRIPT:"%"=%)) +else +# ...then fall back to the generic SPL linker-script +ifneq ($(CONFIG_SPL_LDSCRIPT),) +# need to strip off double quotes +LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_SPL_LDSCRIPT:"%"=%)) +endif endif ifeq ($(wildcard $(LDSCRIPT)),)
scripts/config_whitelist.txt +0 -2
@@ -2252,7 +2252,6 @@ CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER CONFIG_SPL_INIT_MINIMAL CONFIG_SPL_JR0_LIODN_NS CONFIG_SPL_JR0_LIODN_S -CONFIG_SPL_LDSCRIPT CONFIG_SPL_LOAD_FIT_ADDRESS CONFIG_SPL_MAX_FOOTPRINT CONFIG_SPL_MAX_PEB_SIZE
@@ -4981,7 +4980,6 @@ CONFIG_TI_KEYSTONE_SERDES CONFIG_TI_KSNAV CONFIG_TI_SPI_MMAP CONFIG_TMU_TIMER -CONFIG_TPL_LDSCRIPT CONFIG_TPL_MAX_SIZE CONFIG_TPL_PAD_TO CONFIG_TPL_STACK
Signature · 1 line
2.1.4
PATCH v3 59/66 spl: Kconfig: migrate $(SPL_TPL_)LDSCRIPT to Kconfig
Quoted 15 lines · Philipp Tomsich
Now that we have split up
SPL_LDSCRIPTinto a SPL and TPL variant and have started to use the TPL-variant for the RK3368, it's time to clean up behind ourselves: move both variants intoKconfigand remove them from the whitelist.Signed-off-by Philipp Tomsich <[email protected]>---
Changes in v3:
- movesSPL_LDSCRIPTandTPL_LDSCRIPTintoKconfig, as requested by by Tom; this gets rid of the whitelist-entry forSPL_LDSCRIPT(which qualifies as a preexisting condition) and of the newly created one forTPL_LDSCRIPT
Quoted 6 lines
Changes in v2: None
common/spl/Kconfig | 18 ++++++++++++++++++ scripts/Makefile.spl | 9 ++++++++- scripts/config_whitelist.txt | 2 -- 3 files changed, 26 insertions(+), 3 deletions(-)
Reviewed-by Simon Glass <[email protected]>
PATCH v3 60/66 spl: moveconfig: migrate CONFIG_SPL_LDSCRIPT
In reply to Philipp TomsichWith SPL_LDSCRIPT defined via Kconfig, we can run moveconfig... this will touch every configuration that uses SPL, even if there was an implicit resolution of the SPL_LDSCRIPT: now everything is explicit.
Signed-off-by Philipp Tomsich <[email protected]>
---
Changes in v3:
- moveconfig.py CONFIG_SPL_LDSCRIPT
(Note: I really don't know whether this is what we want, as it's making the SPL_LDSCRIPT resolution explicit for every board... then again, I understood Tom's comment that moving things into Kconfig should be the priority...)
Changes in v2: None
configs/A10-OLinuXino-Lime_defconfig | 1 + configs/A10s-OLinuXino-M_defconfig | 1 + configs/A13-OLinuXinoM_defconfig | 1 + configs/A13-OLinuXino_defconfig | 1 + configs/A20-OLinuXino-Lime2_defconfig | 1 + configs/A20-OLinuXino-Lime_defconfig | 1 + configs/A20-OLinuXino_MICRO_defconfig | 1 + configs/A20-Olimex-SOM-EVB_defconfig | 1 + configs/A33-OLinuXino_defconfig | 1 + configs/Ainol_AW1_defconfig | 1 + configs/Ampe_A76_defconfig | 1 + configs/Auxtek-T003_defconfig | 1 + configs/Auxtek-T004_defconfig | 1 + configs/Bananapi_M2_Ultra_defconfig | 1 + configs/Bananapi_defconfig | 1 + configs/Bananapro_defconfig | 1 + configs/CHIP_defconfig | 1 + configs/CHIP_pro_defconfig | 1 + configs/CSQ_CS908_defconfig | 1 + configs/Chuwi_V7_CW0825_defconfig | 1 + configs/Colombus_defconfig | 1 + configs/Cubieboard2_defconfig | 1 + configs/Cubieboard4_defconfig | 1 + configs/Cubieboard_defconfig | 1 + configs/Cubietruck_defconfig | 1 + configs/Cubietruck_plus_defconfig | 1 + configs/Empire_electronix_d709_defconfig | 1 + configs/Empire_electronix_m712_defconfig | 1 + configs/Hummingbird_A31_defconfig | 1 + configs/Hyundai_A7HD_defconfig | 1 + configs/Itead_Ibox_A20_defconfig | 1 + configs/Lamobo_R1_defconfig | 1 + configs/Linksprite_pcDuino3_Nano_defconfig | 1 + configs/Linksprite_pcDuino3_defconfig | 1 + configs/Linksprite_pcDuino_defconfig | 1 + configs/MK808C_defconfig | 1 + configs/MSI_Primo73_defconfig | 1 + configs/MSI_Primo81_defconfig | 1 + configs/Marsboard_A10_defconfig | 1 + configs/Mele_A1000G_quad_defconfig | 1 + configs/Mele_A1000_defconfig | 1 + configs/Mele_I7_defconfig | 1 + configs/Mele_M3_defconfig | 1 + configs/Mele_M5_defconfig | 1 + configs/Mele_M9_defconfig | 1 + configs/Merrii_A80_Optimus_defconfig | 1 + configs/Mini-X_defconfig | 1 + configs/Nintendo_NES_Classic_Edition_defconfig | 1 + configs/Orangepi_defconfig | 1 + configs/Orangepi_mini_defconfig | 1 + configs/Sinlinx_SinA31s_defconfig | 1 + configs/Sinlinx_SinA33_defconfig | 1 + configs/Sinovoip_BPI_M2_Plus_defconfig | 1 + configs/Sinovoip_BPI_M2_defconfig | 1 + configs/Sinovoip_BPI_M3_defconfig | 1 + configs/Sunchip_CX-A99_defconfig | 1 + configs/UTOO_P66_defconfig | 1 + configs/Wexler_TAB7200_defconfig | 1 + configs/Wits_Pro_A20_DKT_defconfig | 1 + configs/Wobo_i5_defconfig | 1 + configs/Yones_Toptech_BD1078_defconfig | 1 + configs/Yones_Toptech_BS1078_V2_defconfig | 1 + configs/am335x_baltos_defconfig | 1 + configs/am335x_boneblack_defconfig | 1 + configs/am335x_boneblack_vboot_defconfig | 1 + configs/am335x_evm_defconfig | 1 + configs/am335x_evm_nor_defconfig | 1 + configs/am335x_evm_spiboot_defconfig | 1 + configs/am335x_evm_usbspl_defconfig | 1 + configs/am335x_hs_evm_defconfig | 1 + configs/am335x_igep003x_defconfig | 1 + configs/am335x_shc_defconfig | 1 + configs/am335x_shc_ict_defconfig | 1 + configs/am335x_shc_netboot_defconfig | 1 + configs/am335x_shc_prompt_defconfig | 1 + configs/am335x_shc_sdboot_defconfig | 1 + configs/am335x_shc_sdboot_prompt_defconfig | 1 + configs/am335x_sl50_defconfig | 1 + configs/am3517_crane_defconfig | 1 + configs/am3517_evm_defconfig | 1 + configs/am43xx_evm_defconfig | 1 + configs/am43xx_evm_ethboot_defconfig | 1 + configs/am43xx_evm_usbhost_boot_defconfig | 1 + configs/am43xx_hs_evm_defconfig | 1 + configs/am57xx_evm_defconfig | 1 + configs/am57xx_evm_nodt_defconfig | 1 + configs/am57xx_hs_evm_defconfig | 1 + configs/apalis_imx6_defconfig | 1 + configs/apf27_defconfig | 1 + configs/apx4devkit_defconfig | 1 + configs/arndale_defconfig | 1 + configs/ba10_tv_box_defconfig | 1 + configs/bg0900_defconfig | 1 + configs/birdland_bav335a_defconfig | 1 + configs/birdland_bav335b_defconfig | 1 + configs/brppt1_mmc_defconfig | 1 + configs/brppt1_nand_defconfig | 1 + configs/brppt1_spi_defconfig | 1 + configs/brxre1_defconfig | 1 + configs/cairo_defconfig | 1 + configs/cgtqmx6eval_defconfig | 1 + configs/chiliboard_defconfig | 1 + configs/chromebook_link64_defconfig | 5 +++-- configs/cl-som-am57x_defconfig | 1 + configs/cm_fx6_defconfig | 1 + configs/cm_t335_defconfig | 1 + configs/cm_t35_defconfig | 1 + configs/cm_t43_defconfig | 1 + configs/cm_t54_defconfig | 3 ++- configs/colibri_imx6_defconfig | 1 + configs/colorfly_e708_q1_defconfig | 1 + configs/controlcenterdc_defconfig | 2 +- configs/da850_am18xxevm_defconfig | 1 + configs/da850evm_defconfig | 1 + configs/db-88f6820-gp_defconfig | 2 +- configs/devkit8000_defconfig | 1 + configs/difrnce_dit4350_defconfig | 1 + configs/dra7xx_evm_defconfig | 3 ++- configs/dra7xx_hs_evm_defconfig | 3 ++- configs/draco_defconfig | 1 + configs/dserve_dsrv9703c_defconfig | 1 + configs/duovero_defconfig | 1 + configs/eco5pk_defconfig | 1 + configs/edminiv2_defconfig | 1 + configs/etamin_defconfig | 1 + configs/evb-rk3036_defconfig | 2 +- configs/evb-rk3229_defconfig | 1 - configs/firefly-rk3288_defconfig | 5 +---- configs/ga10h_v1_1_defconfig | 1 + configs/gt90h_v4_defconfig | 1 + configs/gwventana_emmc_defconfig | 1 + configs/gwventana_gw5904_defconfig | 1 + configs/gwventana_nand_defconfig | 1 + configs/h8_homlet_v2_defconfig | 1 + configs/i12-tvbox_defconfig | 1 + configs/iNet_3F_defconfig | 1 + configs/iNet_3W_defconfig | 1 + configs/iNet_86VS_defconfig | 1 + configs/iNet_D978_rev2_defconfig | 1 + configs/icnova-a20-swac_defconfig | 1 + configs/igep0020_defconfig | 1 + configs/igep0030_defconfig | 1 + configs/igep0032_defconfig | 1 + configs/imx6qdl_icore_mmc_defconfig | 1 + configs/imx6qdl_icore_nand_defconfig | 1 + configs/imx6qdl_icore_rqs_defconfig | 1 + configs/imx6ul_geam_mmc_defconfig | 1 + configs/imx6ul_geam_nand_defconfig | 1 + configs/imx6ul_isiot_emmc_defconfig | 1 + configs/imx6ul_isiot_mmc_defconfig | 1 + configs/imx6ul_isiot_nand_defconfig | 1 + configs/inet1_defconfig | 1 + configs/inet86dz_defconfig | 1 + configs/inet97fv2_defconfig | 1 + configs/inet98v_rev2_defconfig | 1 + configs/inet9f_rev03_defconfig | 1 + configs/inet_q972_defconfig | 1 + configs/ipam390_defconfig | 1 + configs/jesurun_q5_defconfig | 1 + configs/kc1_defconfig | 1 + configs/kylin-rk3036_defconfig | 2 +- configs/liteboard_defconfig | 1 + configs/ls1021aiot_sdcard_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021aqds_sdcard_qspi_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig | 1 + configs/ls1043aqds_nand_defconfig | 1 + configs/ls1043aqds_sdcard_ifc_defconfig | 1 + configs/ls1043aqds_sdcard_qspi_defconfig | 1 + configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_nand_defconfig | 1 + configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_sdcard_defconfig | 1 + configs/ls1046aqds_nand_defconfig | 1 + configs/ls1046aqds_sdcard_ifc_defconfig | 1 + configs/ls1046aqds_sdcard_qspi_defconfig | 1 + configs/ls1046ardb_emmc_defconfig | 1 + configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_sdcard_defconfig | 1 + configs/ls2080aqds_nand_defconfig | 1 + configs/ls2080aqds_sdcard_defconfig | 1 + configs/ls2080ardb_nand_defconfig | 1 + configs/m28evk_defconfig | 1 + configs/ma5d4evk_defconfig | 1 + configs/mccmon6_nor_defconfig | 1 + configs/mccmon6_sd_defconfig | 1 + configs/mcx_defconfig | 1 + configs/microblaze-generic_defconfig | 1 + configs/mixtile_loftq_defconfig | 1 + configs/mk802_a10s_defconfig | 1 + configs/mk802_defconfig | 1 + configs/mk802ii_defconfig | 1 + configs/mt_ventoux_defconfig | 1 + configs/mx23_olinuxino_defconfig | 1 + configs/mx23evk_defconfig | 1 + configs/mx28evk_auart_console_defconfig | 1 + configs/mx28evk_defconfig | 1 + configs/mx28evk_nand_defconfig | 1 + configs/mx28evk_spi_defconfig | 1 + configs/mx31pdk_defconfig | 1 + configs/mx6cuboxi_defconfig | 1 + configs/mx6sabreauto_defconfig | 1 + configs/mx6sabresd_defconfig | 1 + configs/mx6slevk_spl_defconfig | 1 + configs/mx6sxsabresd_spl_defconfig | 1 + configs/mx6ul_14x14_evk_defconfig | 1 + configs/mx6ul_9x9_evk_defconfig | 1 + configs/nanopi_m1_defconfig | 1 + configs/nanopi_m1_plus_defconfig | 1 + configs/nanopi_neo_air_defconfig | 1 + configs/nanopi_neo_defconfig | 1 + configs/novena_defconfig | 1 + configs/omap3_beagle_defconfig | 1 + configs/omap3_evm_defconfig | 1 + configs/omap3_ha_defconfig | 1 + configs/omap3_logic_defconfig | 1 + configs/omap3_overo_defconfig | 1 + configs/omap4_panda_defconfig | 1 + configs/omap4_sdp4430_defconfig | 1 + configs/omap5_uevm_defconfig | 3 ++- configs/omapl138_lcdk_defconfig | 1 + configs/opos6uldev_defconfig | 1 + configs/orangepi_2_defconfig | 1 + configs/orangepi_lite_defconfig | 1 + configs/orangepi_one_defconfig | 1 + configs/orangepi_pc_defconfig | 1 + configs/orangepi_pc_plus_defconfig | 1 + configs/orangepi_plus2e_defconfig | 1 + configs/orangepi_plus_defconfig | 1 + configs/orangepi_zero_defconfig | 1 + configs/origen_defconfig | 1 + configs/ot1200_spl_defconfig | 1 + configs/parrot_r16_defconfig | 1 + configs/pcm051_rev1_defconfig | 1 + configs/pcm051_rev3_defconfig | 1 + configs/pcm058_defconfig | 1 + configs/peach-pi_defconfig | 1 + configs/peach-pit_defconfig | 1 + configs/pengwyn_defconfig | 1 + configs/pepper_defconfig | 1 + configs/picosam9g45_defconfig | 1 + configs/platinum_picon_defconfig | 1 + configs/platinum_titanium_defconfig | 1 + configs/polaroid_mid2407pxe03_defconfig | 1 + configs/polaroid_mid2809pxe04_defconfig | 1 + configs/pov_protab2_ips9_defconfig | 1 + configs/puma-rk3399_defconfig | 8 ++++---- configs/pxm2_defconfig | 1 + configs/q8_a13_tablet_defconfig | 1 + configs/q8_a23_tablet_800x480_defconfig | 1 + configs/q8_a33_tablet_1024x600_defconfig | 1 + configs/q8_a33_tablet_800x480_defconfig | 1 + configs/qemu-x86_64_defconfig | 1 + configs/r7-tv-dongle_defconfig | 1 + configs/rastaban_defconfig | 1 + configs/rut_defconfig | 1 + configs/sama5d2_xplained_mmc_defconfig | 1 + configs/sama5d3_xplained_mmc_defconfig | 1 + configs/sama5d3xek_mmc_defconfig | 1 + configs/sama5d4_xplained_mmc_defconfig | 1 + configs/sama5d4ek_mmc_defconfig | 1 + configs/sansa_fuze_plus_defconfig | 1 + configs/sc_sps_1_defconfig | 1 + configs/smartweb_defconfig | 1 + configs/smdk5250_defconfig | 1 + configs/smdk5420_defconfig | 1 + configs/smdkv310_defconfig | 1 + configs/sniper_defconfig | 1 + configs/snow_defconfig | 1 + configs/spring_defconfig | 1 + configs/sun8i_a23_evb_defconfig | 1 + configs/sunxi_Gemei_G9_defconfig | 1 + configs/tao3530_defconfig | 1 + configs/thuban_defconfig | 1 + configs/ti814x_evm_defconfig | 1 + configs/ti816x_evm_defconfig | 1 + configs/topic_miami_defconfig | 1 + configs/topic_miamilite_defconfig | 1 + configs/topic_miamiplus_defconfig | 1 + configs/tricorder_defconfig | 1 + configs/tricorder_flash_defconfig | 1 + configs/ts4600_defconfig | 1 + configs/twister_defconfig | 1 + configs/udoo_defconfig | 1 + configs/udoo_neo_defconfig | 1 + configs/wandboard_defconfig | 1 + configs/woodburn_sd_defconfig | 1 + configs/x600_defconfig | 1 + configs/xfi3_defconfig | 1 + configs/xpress_spl_defconfig | 1 + configs/zc5202_defconfig | 1 + configs/zc5601_defconfig | 1 + configs/zynq_microzed_defconfig | 1 + configs/zynq_picozed_defconfig | 1 + configs/zynq_zc702_defconfig | 1 + configs/zynq_zc706_defconfig | 1 + configs/zynq_zc770_xm010_defconfig | 1 + configs/zynq_zc770_xm011_defconfig | 1 + configs/zynq_zc770_xm012_defconfig | 1 + configs/zynq_zc770_xm013_defconfig | 1 + configs/zynq_zed_defconfig | 1 + configs/zynq_zybo_defconfig | 1 + include/configs/am335x_evm.h | 2 -- include/configs/am335x_igep003x.h | 1 - include/configs/am335x_shc.h | 2 -- include/configs/am335x_sl50.h | 2 -- include/configs/am3517_crane.h | 1 - include/configs/am3517_evm.h | 1 - include/configs/am43xx_evm.h | 2 -- include/configs/apf27.h | 1 - include/configs/at91sam9m10g45ek.h | 1 - include/configs/at91sam9n12ek.h | 1 - include/configs/at91sam9x5ek.h | 1 - include/configs/baltos.h | 2 -- include/configs/bav335x.h | 2 -- include/configs/bur_am335x_common.h | 1 - include/configs/chiliboard.h | 2 -- include/configs/cm_t335.h | 1 - include/configs/cm_t35.h | 1 - include/configs/cm_t43.h | 2 -- include/configs/da850evm.h | 1 - include/configs/edminiv2.h | 1 - include/configs/exynos5-common.h | 1 - include/configs/imx6_spl.h | 1 - include/configs/ipam390.h | 1 - include/configs/kc1.h | 2 -- include/configs/ls1021aiot.h | 1 - include/configs/ls1021aqds.h | 2 -- include/configs/ls1021atwr.h | 1 - include/configs/ls1043a_common.h | 2 -- include/configs/ls1046a_common.h | 2 -- include/configs/ls2080a_common.h | 1 - include/configs/ma5d4evk.h | 1 - include/configs/mcx.h | 1 - include/configs/microblaze-generic.h | 2 -- include/configs/mx31pdk.h | 1 - include/configs/mxs.h | 1 - include/configs/omap3_evm.h | 1 - include/configs/omapl138_lcdk.h | 1 - include/configs/origen.h | 1 - include/configs/pcm051.h | 2 -- include/configs/pengwyn.h | 2 -- include/configs/pepper.h | 1 - include/configs/picosam9g45.h | 1 - include/configs/rk3368_common.h | 2 -- include/configs/sama5d2_xplained.h | 1 - include/configs/sama5d3_xplained.h | 1 - include/configs/sama5d3xek.h | 1 - include/configs/sama5d4_xplained.h | 1 - include/configs/sama5d4ek.h | 1 - include/configs/siemens-am33x-common.h | 2 -- include/configs/smartweb.h | 1 - include/configs/smdkv310.h | 1 - include/configs/sniper.h | 2 -- include/configs/sunxi-common.h | 4 ---- include/configs/tam3517-common.h | 1 - include/configs/tao3530.h | 1 - include/configs/ti814x_evm.h | 1 - include/configs/ti816x_evm.h | 2 -- include/configs/ti_omap3_common.h | 1 - include/configs/ti_omap4_common.h | 1 - include/configs/ti_omap5_common.h | 1 - include/configs/tricorder.h | 1 - include/configs/woodburn_sd.h | 1 - include/configs/x600.h | 1 - include/configs/zynq-common.h | 2 -- 369 files changed, 313 insertions(+), 106 deletions(-)
configs/A10-OLinuXino-Lime_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/A10s-OLinuXino-M_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_USB1_VBUS_PIN="PB10" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/A13-OLinuXinoM_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/A13-OLinuXino_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/A20-OLinuXino-Lime2_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/A20-OLinuXino-Lime_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/A20-OLinuXino_MICRO_defconfig +1 -0
@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/A20-Olimex-SOM-EVB_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/A33-OLinuXino_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-olinuxino" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/Ainol_AW1_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Ampe_A76_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Auxtek-T003_defconfig +1 -0
@@ -8,6 +8,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t003" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Auxtek-T004_defconfig +1 -0
@@ -6,6 +6,7 @@ CONFIG_USB1_VBUS_PIN="PG13" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Bananapi_M2_Ultra_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Bananapi_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Bananapro_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/CHIP_defconfig +1 -0
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip" # CONFIG_ENV_IS_IN_MMC is not set CONFIG_ENV_IS_NOWHERE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_DFU=y
configs/CHIP_pro_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_ENV_IS_IN_UBI=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot-env" CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_LOADB is not set
configs/CSQ_CS908_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_USB2_VBUS_PIN="" CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/Chuwi_V7_CW0825_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Colombus_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/Cubieboard2_defconfig +1 -0
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Cubieboard4_defconfig +1 -0
@@ -12,6 +12,7 @@ CONFIG_USB3_VBUS_PIN="PH15" CONFIG_AXP_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-cubieboard4" CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/Cubieboard_defconfig +1 -0
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Cubietruck_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Cubietruck_plus_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/Empire_electronix_d709_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-d709" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Empire_electronix_m712_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-m712" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Hummingbird_A31_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25" CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/Hyundai_A7HD_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Itead_Ibox_A20_defconfig +1 -0
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-itead-ibox" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Lamobo_R1_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Linksprite_pcDuino3_Nano_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3-nano" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Linksprite_pcDuino3_defconfig +1 -0
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Linksprite_pcDuino_defconfig +1 -0
@@ -6,6 +6,7 @@ CONFIG_USB2_VBUS_PIN="" CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/MK808C_defconfig +1 -0
@@ -5,6 +5,7 @@ CONFIG_DRAM_CLK=384 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/MSI_Primo73_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/MSI_Primo81_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-primo81" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/Marsboard_A10_defconfig +1 -0
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/Mele_A1000G_quad_defconfig +1 -0
@@ -8,6 +8,7 @@ CONFIG_USB2_VBUS_PIN="" CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/Mele_A1000_defconfig +1 -0
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Mele_I7_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_USB2_VBUS_PIN="" CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/Mele_M3_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Mele_M5_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Mele_M9_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_USB2_VBUS_PIN="" CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/Merrii_A80_Optimus_defconfig +1 -0
@@ -12,6 +12,7 @@ CONFIG_USB3_VBUS_PIN="PH5" CONFIG_AXP_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus" CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/Mini-X_defconfig +1 -0
@@ -6,6 +6,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Nintendo_NES_Classic_Edition_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-nintendo-nes-classic-edition" # CONFIG_ENV_IS_IN_MMC is not set CONFIG_ENV_IS_NOWHERE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/Orangepi_defconfig +1 -0
@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Orangepi_mini_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Sinlinx_SinA31s_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_USB2_VBUS_PIN="" CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sina31s" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/Sinlinx_SinA33_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_DFU=y
configs/Sinovoip_BPI_M2_Plus_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/Sinovoip_BPI_M2_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_USB2_VBUS_PIN="" CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/Sinovoip_BPI_M3_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-sinovoip-bpi-m3" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/Sunchip_CX-A99_defconfig +1 -0
@@ -12,6 +12,7 @@ CONFIG_USB3_VBUS_PIN="PL8" CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-cx-a99" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/UTOO_P66_defconfig +1 -0
@@ -20,6 +20,7 @@ CONFIG_VIDEO_LCD_TL059WV5C0=y CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Wexler_TAB7200_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Wits_Pro_A20_DKT_defconfig +1 -0
@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wits-pro-a20-dkt" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Wobo_i5_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_USB1_VBUS_PIN="PG12" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-wobo-i5" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Yones_Toptech_BD1078_defconfig +1 -0
@@ -19,6 +19,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/Yones_Toptech_BS1078_V2_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-yones-toptech-bs1078-v2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/am335x_baltos_defconfig +1 -0
@@ -20,6 +20,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y
configs/am335x_boneblack_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_MUSB_NEW_SUPPORT=y CONFIG_SPL_OS_BOOT=y
configs/am335x_boneblack_vboot_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_MUSB_NEW_SUPPORT=y CONFIG_SPL_OS_BOOT=y
configs/am335x_evm_defconfig +1 -0
@@ -12,6 +12,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_MUSB_NEW_SUPPORT=y
configs/am335x_evm_nor_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_MUSB_NEW_SUPPORT=y
configs/am335x_evm_spiboot_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_MUSB_NEW_SUPPORT=y CONFIG_FASTBOOT=y
configs/am335x_evm_usbspl_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_MUSB_NEW_SUPPORT=y CONFIG_SPL_NET_SUPPORT=y
configs/am335x_hs_evm_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_SPL_MTD_SUPPORT=y
configs/am335x_igep003x_defconfig +1 -0
@@ -19,6 +19,7 @@ CONFIG_ENV_IS_IN_UBI=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y
configs/am335x_shc_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y
configs/am335x_shc_ict_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y
configs/am335x_shc_netboot_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_EXT_SUPPORT=y
configs/am335x_shc_prompt_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y
configs/am335x_shc_sdboot_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y
configs/am335x_shc_sdboot_prompt_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y
configs/am335x_sl50_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_EXT_SUPPORT=y
configs/am3517_crane_defconfig +1 -0
@@ -6,6 +6,7 @@ CONFIG_TARGET_AM3517_CRANE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AM3517_CRANE # "
configs/am3517_evm_defconfig +1 -0
@@ -8,6 +8,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=10 CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_SPL_MTD_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/am43xx_evm_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_ENV_IS_IN_FAT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_OS_BOOT=y
configs/am43xx_evm_ethboot_defconfig +1 -0
@@ -6,6 +6,7 @@ CONFIG_ENV_IS_IN_FAT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SPL_SYS_MALLOC_SIMPLE is not set CONFIG_SPL_ETH_SUPPORT=y CONFIG_SPL_MTD_SUPPORT=y
configs/am43xx_evm_usbhost_boot_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_ENV_IS_IN_FAT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_OS_BOOT=y
configs/am43xx_hs_evm_defconfig +1 -0
@@ -19,6 +19,7 @@ CONFIG_ENV_IS_IN_FAT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_ETH_SUPPORT=y CONFIG_SPL_MTD_SUPPORT=y
configs/am57xx_evm_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y
configs/am57xx_evm_nodt_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y
configs/am57xx_hs_evm_defconfig +1 -0
@@ -23,6 +23,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y
configs/apalis_imx6_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/apf27_defconfig +1 -0
@@ -8,6 +8,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=5 CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="BIOS> " # CONFIG_CMD_IMLS is not set
configs/apx4devkit_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/arndale_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds" CONFIG_SYS_PROMPT="ARNDALE # " # CONFIG_CMD_IMLS is not set CONFIG_CMD_MMC=y
configs/ba10_tv_box_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/bg0900_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set
configs/birdland_bav335a_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MUSB_NEW_SUPPORT=y
configs/birdland_bav335b_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MUSB_NEW_SUPPORT=y
configs/brppt1_mmc_defconfig +1 -0
@@ -21,6 +21,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y
configs/brppt1_nand_defconfig +1 -0
@@ -21,6 +21,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y
configs/brppt1_spi_defconfig +1 -0
@@ -24,6 +24,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y
configs/brxre1_defconfig +1 -0
@@ -19,6 +19,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y
configs/cairo_defconfig +1 -0
@@ -6,6 +6,7 @@ CONFIG_BOOTDELAY=-2 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y
configs/cgtqmx6eval_defconfig +1 -0
@@ -20,6 +20,7 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y # CONFIG_SYS_STDIO_DEREGISTER is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/chiliboard_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_BOOTDELAY=1 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y
configs/chromebook_link64_defconfig +3 -2
@@ -58,6 +58,8 @@ CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y CONFIG_BLK=y CONFIG_CPU=y CONFIG_DM_I2C=y
@@ -70,14 +72,13 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_NS16550=y CONFIG_ICH_SPI=y CONFIG_TIMER=y +CONFIG_SPL_TIMER=y CONFIG_TPM_TIS_LPC=y CONFIG_USB=y CONFIG_DM_USB=y
configs/cl-som-am57x_defconfig +1 -0
@@ -6,6 +6,7 @@ CONFIG_TARGET_CL_SOM_AM57X=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# "
configs/cm_fx6_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_BOOTDELAY=3 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80 CONFIG_SPL_I2C_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/cm_t335_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MTD_SUPPORT=y
configs/cm_t35_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="CM-T3x # "
configs/cm_t43_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480 CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y
configs/cm_t54_defconfig +2 -1
@@ -10,6 +10,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_SATA_SUPPORT=y CONFIG_HUSH_PARSER=y
@@ -39,8 +40,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_MMC_OMAP_HS=y CONFIG_SCSI=y +CONFIG_MMC_OMAP_HS=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y
configs/colibri_imx6_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/colorfly_e708_q1_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-colorfly-e708-q1" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/controlcenterdc_defconfig +1 -1
@@ -35,6 +35,7 @@ CONFIG_CMD_EXT4=y CONFIG_EFI_PARTITION=y CONFIG_OF_BOARD_FIXUP=y CONFIG_SPL_OF_TRANSLATE=y +CONFIG_SCSI=y CONFIG_DM_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y
@@ -45,7 +46,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_MV=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SCSI=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART_SHIFT=2
configs/da850_am18xxevm_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="board/$(BOARDDIR)/u-boot-spl-da850evm.lds" CONFIG_SPL_BOARD_INIT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set
configs/da850evm_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="board/$(BOARDDIR)/u-boot-spl-da850evm.lds" CONFIG_SPL_BOARD_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > "
configs/db-88f6820-gp_defconfig +1 -1
@@ -38,6 +38,7 @@ CONFIG_EFI_PARTITION=y # CONFIG_PARTITION_UUIDS is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_SPL_OF_TRANSLATE=y +CONFIG_SCSI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y
@@ -45,7 +46,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PCI=y -CONFIG_SCSI=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART_SHIFT=2
configs/devkit8000_defconfig +1 -0
@@ -5,6 +5,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMI is not set
configs/difrnce_dit4350_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-difrnce-dit4350" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/dra7xx_evm_defconfig +2 -1
@@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y
@@ -45,6 +46,7 @@ CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y +CONFIG_DM_SCSI=y CONFIG_DWC_AHCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y
@@ -68,7 +70,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_PALMAS=y CONFIG_DM_REGULATOR_LP873X=y -CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y
configs/dra7xx_hs_evm_defconfig +2 -1
@@ -23,6 +23,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y
@@ -48,6 +49,7 @@ CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y +CONFIG_DM_SCSI=y CONFIG_DWC_AHCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y
@@ -71,7 +73,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_PALMAS=y CONFIG_DM_REGULATOR_LP873X=y -CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y
configs/draco_defconfig +1 -0
@@ -22,6 +22,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/dserve_dsrv9703c_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-dserve-dsrv9703c" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/duovero_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SPL_I2C_SUPPORT is not set CONFIG_SYS_PROMPT="duovero # " # CONFIG_CMD_IMLS is not set
configs/eco5pk_defconfig +1 -0
@@ -5,6 +5,7 @@ CONFIG_TARGET_ECO5PK=y CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ECO5-PK # "
configs/edminiv2_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="$(CPUDIR)/orion5x/u-boot-spl.lds" CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/etamin_defconfig +1 -0
@@ -22,6 +22,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/evb-rk3036_defconfig +1 -1
@@ -7,8 +7,8 @@ CONFIG_ROCKCHIP_RK3036=y CONFIG_TARGET_EVB_RK3036=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" -CONFIG_SPL_SYS_MALLOC_F_LEN=0x0 CONFIG_DEBUG_UART=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x0 CONFIG_ENV_IS_NOWHERE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y
configs/evb-rk3229_defconfig +0 -1
@@ -4,7 +4,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_ROCKCHIP_RK322X=y -CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y CONFIG_TARGET_EVB_RK3229=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
configs/firefly-rk3288_defconfig +1 -4
@@ -41,6 +41,7 @@ CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_DM_KEYBOARD=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MMC_DW=y
@@ -76,7 +77,3 @@ CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y -CONFIG_USB_KEYBOARD=y -CONFIG_DM_KEYBOARD=y -CONFIG_SYS_USB_EVENT_POLL=y -CONFIG_SYS_STDIO_DEREGISTER=y
configs/ga10h_v1_1_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ga10h-v1.1" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/gt90h_v4_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-gt90h-v4" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/gwventana_emmc_defconfig +1 -0
@@ -22,6 +22,7 @@ CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_DMA_SUPPORT=y
configs/gwventana_gw5904_defconfig +1 -0
@@ -22,6 +22,7 @@ CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_DMA_SUPPORT=y
configs/gwventana_nand_defconfig +1 -0
@@ -23,6 +23,7 @@ CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_DMA_SUPPORT=y
configs/h8_homlet_v2_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-allwinner-h8homlet-v2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/i12-tvbox_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/iNet_3F_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/iNet_3W_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/iNet_86VS_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/iNet_D978_rev2_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-inet-d978-rev2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/icnova-a20-swac_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-swac" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_UNZIP=y
configs/igep0020_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_ONENAND_SUPPORT=y
configs/igep0030_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_ONENAND_SUPPORT=y
configs/igep0032_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_ONENAND_SUPPORT=y
configs/imx6qdl_icore_mmc_defconfig +1 -0
@@ -18,6 +18,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_ENV_IS_IN_MMC=y CONFIG_BOOTDELAY=3 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl> "
configs/imx6qdl_icore_nand_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=3 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_DMA_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl> "
configs/imx6qdl_icore_rqs_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_ENV_IS_IN_MMC=y CONFIG_BOOTDELAY=3 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl-rqs> "
configs/imx6ul_geam_mmc_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_ENV_IS_IN_MMC=y CONFIG_BOOTDELAY=3 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="geam6ul> "
configs/imx6ul_geam_nand_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=3 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_DMA_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="geam6ul> "
configs/imx6ul_isiot_emmc_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_ENV_IS_IN_MMC=y CONFIG_BOOTDELAY=3 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="isiotmx6ul> "
configs/imx6ul_isiot_mmc_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_ENV_IS_IN_MMC=y CONFIG_BOOTDELAY=3 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="isiotmx6ul> "
configs/imx6ul_isiot_nand_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=3 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_DMA_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="isiotmx6ul> "
configs/inet1_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet1" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/inet86dz_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-inet86dz" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/inet97fv2_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet97fv2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/inet98v_rev2_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-98v-rev2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/inet9f_rev03_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet9f-rev03" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/inet_q972_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-inet-q972" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/ipam390_defconfig +1 -0
@@ -12,6 +12,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="board/$(BOARDDIR)/u-boot-spl-ipam390.lds" CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y
configs/jesurun_q5_defconfig +1 -0
@@ -8,6 +8,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/kc1_defconfig +1 -0
@@ -6,6 +6,7 @@ CONFIG_TARGET_KC1=y CONFIG_ENV_IS_NOWHERE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2
configs/kylin-rk3036_defconfig +1 -1
@@ -7,8 +7,8 @@ CONFIG_ROCKCHIP_RK3036=y CONFIG_TARGET_KYLIN_RK3036=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" -CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x0 +CONFIG_ENV_IS_IN_MMC=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y # CONFIG_CMD_IMLS is not set
configs/liteboard_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_BOOTDELAY=1 CONFIG_DEFAULT_FDT_FILE="imx6ul-liteboard.dtb" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set
configs/ls1021aiot_sdcard_defconfig +1 -0
@@ -5,6 +5,7 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" CONFIG_ENV_IS_IN_MMC=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_CMD_GPT=y
configs/ls1021aqds_nand_defconfig +1 -0
@@ -20,6 +20,7 @@ CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y
configs/ls1021aqds_sdcard_ifc_defconfig +1 -0
@@ -18,6 +18,7 @@ CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y
configs/ls1021aqds_sdcard_qspi_defconfig +1 -0
@@ -18,6 +18,7 @@ CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +1 -0
@@ -19,6 +19,7 @@ CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_CRYPTO_SUPPORT=y
configs/ls1021atwr_sdcard_ifc_defconfig +1 -0
@@ -19,6 +19,7 @@ CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y
configs/ls1021atwr_sdcard_qspi_defconfig +1 -0
@@ -19,6 +19,7 @@ CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y
configs/ls1043aqds_nand_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_NAND_BOOT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y
configs/ls1043aqds_sdcard_ifc_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_SD_BOOT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y
configs/ls1043aqds_sdcard_qspi_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_SD_BOOT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y
configs/ls1043ardb_nand_SECURE_BOOT_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_CRYPTO_SUPPORT=y
configs/ls1043ardb_nand_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_NAND_BOOT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y
configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_SPL_CRYPTO_SUPPORT=y
configs/ls1043ardb_sdcard_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_SD_BOOT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y
configs/ls1046aqds_nand_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_NAND_BOOT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
configs/ls1046aqds_sdcard_ifc_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_SD_BOOT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
configs/ls1046aqds_sdcard_qspi_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_SD_BOOT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
configs/ls1046ardb_emmc_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_SD_BOOT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_SPL_CRYPTO_SUPPORT=y
configs/ls1046ardb_sdcard_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_SD_BOOT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
configs/ls2080aqds_nand_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_NAND_BOOT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
configs/ls2080aqds_sdcard_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_SD_BOOT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_ENV_SUPPORT=y
configs/ls2080ardb_nand_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_NAND_BOOT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
configs/m28evk_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y
configs/ma5d4evk_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-at91/armv7/u-boot-spl.lds" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set
configs/mccmon6_nor_defconfig +1 -0
@@ -8,6 +8,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg,MX6QDL" CONFIG_ENV_IS_IN_FLASH=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y
configs/mccmon6_sd_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg,MX6QDL" CONFIG_ENV_IS_IN_FLASH=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y
configs/mcx_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="mcx # "
configs/microblaze-generic_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=-1 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/microblaze/cpu/u-boot-spl.lds" CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y
configs/mixtile_loftq_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_USB2_VBUS_PIN="" CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/mk802_a10s_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_USB1_VBUS_PIN="PB10" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/mk802_defconfig +1 -0
@@ -5,6 +5,7 @@ CONFIG_USB2_VBUS_PIN="PH12" CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/mk802ii_defconfig +1 -0
@@ -4,6 +4,7 @@ CONFIG_MACH_SUN4I=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/mt_ventoux_defconfig +1 -0
@@ -8,6 +8,7 @@ CONFIG_BOOTDELAY=10 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="mt_ventoux => "
configs/mx23_olinuxino_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/mx23evk_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set
configs/mx28evk_auart_console_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set
configs/mx28evk_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set
configs/mx28evk_nand_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set
configs/mx28evk_spi_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set
configs/mx31pdk_defconfig +1 -0
@@ -8,6 +8,7 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=1 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds" CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_SPI=y
configs/mx6cuboxi_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_ENV_IS_IN_MMC=y # CONFIG_SYS_STDIO_DEREGISTER is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set
configs/mx6sabreauto_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/mx6sabresd_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y
configs/mx6slevk_spl_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/mx6sxsabresd_spl_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/mx6ul_14x14_evk_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/mx6ul_9x9_evk_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/nanopi_m1_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_DRAM_ODT_EN=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/nanopi_m1_plus_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/nanopi_neo_air_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo-air" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/nanopi_neo_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/novena_defconfig +1 -0
@@ -19,6 +19,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set
configs/omap3_beagle_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_OS_BOOT=y # CONFIG_CMD_IMLS is not set
configs/omap3_evm_defconfig +1 -0
@@ -5,6 +5,7 @@ CONFIG_TARGET_OMAP3_EVM=y CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=3 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="OMAP3_EVM # "
configs/omap3_ha_defconfig +1 -0
@@ -6,6 +6,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA" CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=3 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMI is not set
configs/omap3_logic_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_MTD_SUPPORT=y
configs/omap3_overo_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_MTD_SUPPORT=y
configs/omap4_panda_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SPL_EXT_SUPPORT is not set # CONFIG_SPL_I2C_SUPPORT is not set CONFIG_SPL_OS_BOOT=y
configs/omap4_sdp4430_defconfig +1 -0
@@ -12,6 +12,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SPL_I2C_SUPPORT is not set # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y
configs/omap5_uevm_defconfig +2 -1
@@ -9,6 +9,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y
@@ -33,10 +34,10 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ISO_PARTITION=y +CONFIG_SCSI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_MMC_OMAP_HS=y -CONFIG_SCSI=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y
configs/omapl138_lcdk_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="board/$(BOARDDIR)/u-boot-spl-da850evm.lds" CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5 CONFIG_HUSH_PARSER=y
configs/opos6uldev_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_DEFAULT_FDT_FILE="imx6ul-opos6uldev.dtb" CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/orangepi_2_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_USB1_VBUS_PIN="PG13" CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/orangepi_lite_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_DRAM_ODT_EN=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-lite" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/orangepi_one_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_DRAM_ODT_EN=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/orangepi_pc_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_DRAM_ODT_EN=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/orangepi_pc_plus_defconfig +1 -0
@@ -8,6 +8,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc-plus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/orangepi_plus2e_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus2e" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/orangepi_plus_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_SATAPWR="PG11" CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/orangepi_zero_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/origen_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ORIGEN # " CONFIG_CMD_BOOTZ=y
configs/ot1200_spl_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y
configs/parrot_r16_defconfig +1 -0
@@ -12,6 +12,7 @@ CONFIG_AXP_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-parrot" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/pcm051_rev1_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ETH_SUPPORT=y CONFIG_SPL_EXT_SUPPORT=y
configs/pcm051_rev3_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ETH_SUPPORT=y CONFIG_SPL_EXT_SUPPORT=y
configs/pcm058_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y
configs/peach-pi_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_FIT_BEST_MATCH=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SILENT_CONSOLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds" CONFIG_SYS_PROMPT="Peach-Pi # " # CONFIG_CMD_IMLS is not set CONFIG_CMD_MMC=y
configs/peach-pit_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_FIT_BEST_MATCH=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SILENT_CONSOLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds" CONFIG_SYS_PROMPT="Peach-Pit # " # CONFIG_CMD_IMLS is not set CONFIG_CMD_MMC=y
configs/pengwyn_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ETH_SUPPORT=y CONFIG_SPL_EXT_SUPPORT=y
configs/pepper_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y
configs/picosam9g45_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set
configs/platinum_picon_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y
configs/platinum_titanium_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y
configs/polaroid_mid2407pxe03_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2407pxe03" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/polaroid_mid2809pxe04_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2809pxe04" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/pov_protab2_ips9_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pov-protab2-ips9" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/puma-rk3399_defconfig +4 -4
@@ -84,13 +84,13 @@ CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_STORAGE=y -CONFIG_DM_VIDEO=y -CONFIG_DISPLAY=y -CONFIG_VIDEO_ROCKCHIP=y -CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Theobroma Systems" CONFIG_G_DNL_VENDOR_NUM=0x2294 CONFIG_G_DNL_PRODUCT_NUM=0x3399 +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_ERRNO_STR=y
configs/pxm2_defconfig +1 -0
@@ -25,6 +25,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/q8_a13_tablet_defconfig +1 -0
@@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-q8-tablet" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/q8_a23_tablet_800x480_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-q8-tablet" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/q8_a33_tablet_1024x600_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/q8_a33_tablet_800x480_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/qemu-x86_64_defconfig +1 -0
@@ -71,6 +71,7 @@ CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_SYS_NS16550=y CONFIG_TIMER=y +CONFIG_SPL_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y
configs/r7-tv-dongle_defconfig +1 -0
@@ -6,6 +6,7 @@ CONFIG_USB1_VBUS_PIN="PG13" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/rastaban_defconfig +1 -0
@@ -22,6 +22,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/rut_defconfig +1 -0
@@ -26,6 +26,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/sama5d2_xplained_mmc_defconfig +1 -0
@@ -18,6 +18,7 @@ CONFIG_ENV_IS_IN_FAT=y CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-at91/armv7/u-boot-spl.lds" CONFIG_SPL_SEPARATE_BSS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y
configs/sama5d3_xplained_mmc_defconfig +1 -0
@@ -18,6 +18,7 @@ CONFIG_ENV_IS_IN_FAT=y CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-at91/armv7/u-boot-spl.lds" CONFIG_SPL_SEPARATE_BSS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y
configs/sama5d3xek_mmc_defconfig +1 -0
@@ -20,6 +20,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-at91/armv7/u-boot-spl.lds" CONFIG_SPL_SEPARATE_BSS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y
configs/sama5d4_xplained_mmc_defconfig +1 -0
@@ -18,6 +18,7 @@ CONFIG_ENV_IS_IN_FAT=y CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-at91/armv7/u-boot-spl.lds" CONFIG_SPL_SEPARATE_BSS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y
configs/sama5d4ek_mmc_defconfig +1 -0
@@ -20,6 +20,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-at91/armv7/u-boot-spl.lds" CONFIG_SPL_SEPARATE_BSS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y
configs/sansa_fuze_plus_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y
configs/sc_sps_1_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/smartweb_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_AUTOBOOT_KEYED=y
configs/smdk5250_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds" CONFIG_SYS_PROMPT="SMDK5250 # " # CONFIG_CMD_IMLS is not set CONFIG_CMD_MMC=y
configs/smdk5420_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds" CONFIG_SYS_PROMPT="SMDK5420 # " # CONFIG_CMD_IMLS is not set CONFIG_CMD_MMC=y
configs/smdkv310_defconfig +1 -0
@@ -4,6 +4,7 @@ CONFIG_ARCH_EXYNOS4=y CONFIG_IDENT_STRING=" for SMDKC210/V310" CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310" CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SMDKV310 # " CONFIG_CMD_BOOTZ=y
configs/sniper_defconfig +1 -0
@@ -6,6 +6,7 @@ CONFIG_TARGET_SNIPER=y CONFIG_ENV_IS_NOWHERE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2
configs/snow_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_FIT_BEST_MATCH=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SILENT_CONSOLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds" CONFIG_SYS_PROMPT="snow # " # CONFIG_CMD_IMLS is not set CONFIG_CMD_MMC=y
configs/spring_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_FIT_BEST_MATCH=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SILENT_CONSOLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds" CONFIG_SYS_PROMPT="spring # " # CONFIG_CMD_IMLS is not set CONFIG_CMD_MMC=y
configs/sun8i_a23_evb_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_USB1_VBUS_PIN="PH7" CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-evb" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set
configs/sunxi_Gemei_G9_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/tao3530_defconfig +1 -0
@@ -5,6 +5,7 @@ CONFIG_TARGET_TAO3530=y CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=3 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="TAO-3530 # "
configs/thuban_defconfig +1 -0
@@ -22,6 +22,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/ti814x_evm_defconfig +1 -0
@@ -16,6 +16,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_YMODEM_SUPPORT=y
configs/ti816x_evm_defconfig +1 -0
@@ -20,6 +20,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_STACK_R=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
configs/topic_miami_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_BOOTDELAY=0 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="zynq-uboot> " # CONFIG_CMD_IMLS is not set
configs/topic_miamilite_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_BOOTDELAY=0 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="zynq-uboot> " # CONFIG_CMD_IMLS is not set
configs/topic_miamiplus_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_BOOTDELAY=0 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="zynq-uboot> " # CONFIG_CMD_IMLS is not set
configs/tricorder_defconfig +1 -0
@@ -5,6 +5,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=0 CONFIG_SILENT_CONSOLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="OMAP3 Tricorder # " # CONFIG_CMD_IMI is not set
configs/tricorder_flash_defconfig +1 -0
@@ -6,6 +6,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_BOOTDELAY=0 CONFIG_SILENT_CONSOLE=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set
configs/ts4600_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set
configs/twister_defconfig +1 -0
@@ -5,6 +5,7 @@ CONFIG_TARGET_TWISTER=y CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y
configs/udoo_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/udoo_neo_defconfig +1 -0
@@ -13,6 +13,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_EXT_SUPPORT=y # CONFIG_CMD_IMLS is not set
configs/wandboard_defconfig +1 -0
@@ -18,6 +18,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set
configs/woodburn_sd_defconfig +1 -0
@@ -11,6 +11,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm1136/u-boot-spl.lds" CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
configs/x600_defconfig +1 -0
@@ -12,6 +12,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds" CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="X600> "
configs/xfi3_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
configs/xpress_spl_defconfig +1 -0
@@ -14,6 +14,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_HUSH_PARSER=y
configs/zc5202_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_BOOTDELAY=3 CONFIG_DEFAULT_FDT_FILE="imx6q-zc5202.dtb" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_MMC=y
configs/zc5601_defconfig +1 -0
@@ -17,6 +17,7 @@ CONFIG_BOOTDELAY=3 CONFIG_DEFAULT_FDT_FILE="imx6q-zc5601.dtb" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds" CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_MMC=y
configs/zynq_microzed_defconfig +1 -0
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_ENV_IS_IN_SPI_FLASH=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds" CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> "
configs/zynq_picozed_defconfig +1 -0
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed" CONFIG_ENV_IS_NOWHERE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds" CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> "
configs/zynq_zc702_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_ENV_IS_IN_SPI_FLASH=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds" CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> "
configs/zynq_zc706_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_ENV_IS_IN_SPI_FLASH=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds" CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> "
configs/zynq_zc770_xm010_defconfig +1 -0
@@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010" CONFIG_ENV_IS_IN_SPI_FLASH=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds" CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> "
configs/zynq_zc770_xm011_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011" CONFIG_ENV_IS_NOWHERE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds" CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> "
configs/zynq_zc770_xm012_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012" CONFIG_ENV_IS_IN_FLASH=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds" CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> "
configs/zynq_zc770_xm013_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013" CONFIG_ENV_IS_NOWHERE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds" CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> "
configs/zynq_zed_defconfig +1 -0
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_ENV_IS_IN_SPI_FLASH=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds" CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> "
configs/zynq_zybo_defconfig +1 -0
@@ -10,6 +10,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_ENV_IS_IN_SPI_FLASH=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds" CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> "
include/configs/am335x_evm.h +0 -2
@@ -191,8 +191,6 @@#define CONFIG_SYS_BOOTCOUNT_BE /* USB gadget RNDIS */ - -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"#endif #ifdef CONFIG_NAND
include/configs/am335x_igep003x.h +0 -1
@@ -125,7 +125,6 @@#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(SPL),-(UBI)"/* SPL */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"/* UBI configuration */ #define CONFIG_SPL_UBI 1
include/configs/am335x_shc.h +0 -2
@@ -247,8 +247,6 @@/* SPL */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" -#ifndef CONFIG_SPL_USBETH_SUPPORT #define CONFIG_FASTBOOT_FLASH_MMC_DEV 1#endif
include/configs/am335x_sl50.h +0 -2
@@ -78,8 +78,6 @@#define CONFIG_BOOTCOUNT_AM33XX #define CONFIG_SYS_BOOTCOUNT_BE -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" -#ifndef CONFIG_SPL_USBETH_SUPPORT #define CONFIG_FASTBOOT_FLASH_MMC_DEV 1#endif
include/configs/am3517_crane.h +0 -1
@@ -262,7 +262,6 @@#define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"/* NAND boot config */ #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
include/configs/am3517_evm.h +0 -1
@@ -309,6 +309,5 @@#define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"#endif /* __CONFIG_H */
include/configs/am43xx_evm.h +0 -2
@@ -75,8 +75,6 @@#define FAT_ENV_DEVICE_AND_PART "0:1"#define FAT_ENV_FILE "uboot.env" -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" -/* SPL USB Support */ #if defined(CONFIG_SPL_USB_HOST_SUPPORT ) || !defined(CONFIG_SPL_BUILD )
include/configs/apf27.h +0 -1
@@ -27,7 +27,6 @@* SPL */ #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"#define CONFIG_SPL_MAX_SIZE 2048#define CONFIG_SPL_TEXT_BASE 0xA0000000
include/configs/at91sam9m10g45ek.h +0 -1
@@ -150,7 +150,6 @@#define CONFIG_SYS_SPL_MALLOC_START 0x70080000#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 -#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
include/configs/at91sam9n12ek.h +0 -1
@@ -200,7 +200,6 @@#define CONFIG_SYS_MCKR_CSS 0x1302#ifdef CONFIG_SYS_USE_MMC -#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
include/configs/at91sam9x5ek.h +0 -1
@@ -190,7 +190,6 @@#define CONFIG_SYS_MCKR_CSS 0x1302#ifdef CONFIG_SYS_USE_MMC -#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
include/configs/baltos.h +0 -2
@@ -243,8 +243,6 @@/* General network SPL, both CPSW and USB gadget RNDIS */ #define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"*/ -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" -#ifdef CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC #define CONFIG_NAND_OMAP_GPMC_PREFETCH
include/configs/bav335x.h +0 -2
@@ -344,8 +344,6 @@ DEFAULT_LINUX_BOOT_ENV \#define CONFIG_SYS_BOOTCOUNT_BE /* USB gadget RNDIS */ - -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"#endif #ifdef CONFIG_NAND
include/configs/bur_am335x_common.h +0 -1
@@ -104,6 +104,5 @@#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN/* General parts of the framework, required. */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"#endif /* ! __BUR_AM335X_COMMON_H__ */
include/configs/chiliboard.h +0 -2
@@ -129,8 +129,6 @@#define CONFIG_BOOTCOUNT_AM33XX #define CONFIG_SYS_BOOTCOUNT_BE -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" -/* NAND: device related configs */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
include/configs/cm_t335.h +0 -1
@@ -99,7 +99,6 @@#define CONFIG_SYS_I2C_EEPROM_BUS 0/* SPL */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"/* Network. */ #define CONFIG_PHY_GIGE
include/configs/cm_t35.h +0 -1
@@ -264,7 +264,6 @@#define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_OMAP3_ID_NAND -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"/* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE
include/configs/cm_t43.h +0 -2
@@ -101,8 +101,6 @@#define CONFIG_ENV_OFFSET (768 * 1024)#define CONFIG_ENV_SPI_MAX_HZ 48000000 -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" -#define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ "fdtaddr=0x81200000\0" \
include/configs/da850evm.h +0 -1
@@ -298,7 +298,6 @@ CONFIG_SYS_MALLOC_LEN)#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN#define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"#define CONFIG_SPL_STACK 0x8001ff00#define CONFIG_SPL_TEXT_BASE 0x80000000#define CONFIG_SPL_MAX_FOOTPRINT 32768
include/configs/edminiv2.h +0 -1
@@ -24,7 +24,6 @@#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff#define CONFIG_SYS_SPL_MALLOC_START 0x00040000#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds"#define CONFIG_SYS_UBOOT_BASE 0xfff90000#define CONFIG_SYS_UBOOT_START 0x00800000#define CONFIG_SYS_TEXT_BASE 0x00800000
include/configs/exynos5-common.h +0 -1
@@ -49,7 +49,6 @@#define CONFIG_SUPPORT_EMMC_BOOT /* specific .lds file */ -#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"/* Boot Argument Buffer Size */ /* memtest works on */
include/configs/imx6_spl.h +0 -1
@@ -24,7 +24,6 @@* and some padding thus 'our' max size is really 0x00908000 - 0x00918000 * or 64KB */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"#define CONFIG_SPL_TEXT_BASE 0x00908000#define CONFIG_SPL_MAX_SIZE 0x10000#define CONFIG_SPL_STACK 0x0091FFB8
include/configs/ipam390.h +0 -1
@@ -269,7 +269,6 @@#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ CONFIG_SYS_MALLOC_LEN)#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-ipam390.lds"#define CONFIG_SPL_STACK 0x8001ff00#define CONFIG_SPL_TEXT_BASE 0x80000000#define CONFIG_SPL_MAX_SIZE 0x20000
include/configs/kc1.h +0 -2
@@ -89,8 +89,6 @@#define CONFIG_SYS_SPL_MALLOC_START 0x80208000#define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024) -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" -/* * Console */
include/configs/ls1021aiot.h +0 -1
@@ -77,7 +77,6 @@#define CONFIG_SYS_FSL_PBL_RCW \ board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"#define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_ENV_SUPPORT
include/configs/ls1021aqds.h +0 -2
@@ -52,7 +52,6 @@ unsigned long get_board_ddr_clk(void); board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg#endif #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"#define CONFIG_SPL_TEXT_BASE 0x10000000#define CONFIG_SPL_MAX_SIZE 0x1a000
@@ -75,7 +74,6 @@ unsigned long get_board_ddr_clk(void);#ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"#define CONFIG_SPL_TEXT_BASE 0x10000000#define CONFIG_SPL_MAX_SIZE 0x1a000
include/configs/ls1021atwr.h +0 -1
@@ -96,7 +96,6 @@ board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg#endif #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"#ifdef CONFIG_SECURE_BOOT /*
include/configs/ls1043a_common.h +0 -2
@@ -66,7 +66,6 @@/* SD boot SPL */ #ifdef CONFIG_SD_BOOT #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"#define CONFIG_SPL_TEXT_BASE 0x10000000
@@ -98,7 +97,6 @@#ifdef CONFIG_NAND_BOOT #define CONFIG_SPL_PBL_PAD #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"#define CONFIG_SPL_TEXT_BASE 0x10000000#define CONFIG_SPL_MAX_SIZE 0x1a000
include/configs/ls1046a_common.h +0 -2
@@ -64,7 +64,6 @@/* SD boot SPL */ #ifdef CONFIG_SD_BOOT #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"#define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT
@@ -104,7 +103,6 @@#ifdef CONFIG_NAND_BOOT #define CONFIG_SPL_PBL_PAD #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"#define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT
include/configs/ls2080a_common.h +0 -1
@@ -233,7 +233,6 @@ unsigned long long get_qixis_addr(void);#define CONFIG_SPL_BSS_START_ADDR 0x80100000#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"#define CONFIG_SPL_MAX_SIZE 0x16000#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
include/configs/ma5d4evk.h +0 -1
@@ -215,7 +215,6 @@#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000#define CONFIG_SYS_USE_MMC -#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds#define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
include/configs/mcx.h +0 -1
@@ -288,7 +288,6 @@#define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"#define CONFIG_SPL_TEXT_BASE 0x40200000/*CONFIG_SYS_SRAM_START*/ #define CONFIG_SPL_MAX_SIZE (54 * 1024)/* 8 KB for stack */
include/configs/microblaze-generic.h +0 -2
@@ -258,8 +258,6 @@#define CONFIG_CMD_SPL #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds" -#ifdef CONFIG_SYS_FLASH_BASE # define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE#endif
include/configs/mx31pdk.h +0 -1
@@ -26,7 +26,6 @@#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"#define CONFIG_SPL_MAX_SIZE 2048#define CONFIG_SPL_TEXT_BASE 0x87dc0000
include/configs/mxs.h +0 -1
@@ -46,7 +46,6 @@/* SPL */ #define CONFIG_SPL_NO_CPU_SUPPORT_CODE #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"/* Memory sizes */ #define CONFIG_SYS_MALLOC_LEN 0x00400000/* 4 MB for malloc */
include/configs/omap3_evm.h +0 -1
@@ -314,7 +314,6 @@#define CONFIG_SPL_BSS_MAX_SIZE 0x80000/* 512 KB */ #define CONFIG_SPL_OMAP3_ID_NAND -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"/* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
include/configs/omapl138_lcdk.h +0 -1
@@ -313,7 +313,6 @@#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ CONFIG_SYS_MALLOC_LEN)#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"#define CONFIG_SPL_STACK 0x8001ff00#define CONFIG_SPL_TEXT_BASE 0x80000000#define CONFIG_SPL_MAX_FOOTPRINT 32768
include/configs/origen.h +0 -1
@@ -95,7 +95,6 @@#define BL1_SIZE (16 << 10)/*16 K reserved for BL1*/ #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) -#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)#define CONFIG_SYS_INIT_SP_ADDR 0x02040000
include/configs/pcm051.h +0 -2
@@ -117,8 +117,6 @@/* CPU */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" -#ifdef CONFIG_SPI_BOOT #define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
include/configs/pengwyn.h +0 -2
@@ -199,6 +199,4 @@/* CPSW support */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" -#endif /* ! __CONFIG_PENGWYN_H */
include/configs/pepper.h +0 -1
@@ -85,6 +85,5 @@#define CONFIG_PHY_RESET_DELAY 1000/* SPL */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"#endif /* __CONFIG_PEPPER_H */
include/configs/picosam9g45.h +0 -1
@@ -152,7 +152,6 @@#define CONFIG_SYS_SPL_MALLOC_START 0x20080000#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 -#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
include/configs/rk3368_common.h +0 -2
@@ -35,8 +35,6 @@#define CONFIG_SPL_BSS_START_ADDR 0x400000#define CONFIG_SPL_BSS_MAX_SIZE 0x20000 -#define CONFIG_TPL_LDSCRIPT \ - "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"#define CONFIG_TPL_TEXT_BASE 0xff8c1000#define CONFIG_TPL_MAX_SIZE 0x7000#define CONFIG_TPL_STACK 0xff8cffff
include/configs/sama5d2_xplained.h +0 -1
@@ -82,7 +82,6 @@#define CONFIG_SYS_MONITOR_LEN (512 << 10)#ifdef CONFIG_SYS_USE_MMC -#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
include/configs/sama5d3_xplained.h +0 -1
@@ -90,7 +90,6 @@#define CONFIG_SYS_MONITOR_LEN (512 << 10)#ifdef CONFIG_SYS_USE_MMC -#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
include/configs/sama5d3xek.h +0 -1
@@ -123,7 +123,6 @@#define CONFIG_SYS_MONITOR_LEN (512 << 10)#ifdef CONFIG_SYS_USE_MMC -#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
include/configs/sama5d4_xplained.h +0 -1
@@ -78,7 +78,6 @@#define CONFIG_SYS_MONITOR_LEN (512 << 10)#ifdef CONFIG_SYS_USE_MMC -#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
include/configs/sama5d4ek.h +0 -1
@@ -76,7 +76,6 @@#define CONFIG_SYS_MONITOR_LEN (512 << 10)#ifdef CONFIG_SYS_USE_MMC -#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
include/configs/siemens-am33x-common.h +0 -2
@@ -121,8 +121,6 @@#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" -#define CONFIG_SPL_NAND_AM33XX_BCH #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS
include/configs/smartweb.h +0 -1
@@ -231,7 +231,6 @@#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ CONFIG_SPL_BSS_MAX_SIZE)#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)#define CONFIG_SYS_USE_NANDFLASH 1
include/configs/smdkv310.h +0 -1
@@ -79,7 +79,6 @@#define BL1_SIZE (16 << 10)/*16 K reserved for BL1*/ #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) -#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)#define CONFIG_SYS_INIT_SP_ADDR 0x02040000
include/configs/sniper.h +0 -2
@@ -86,8 +86,6 @@#define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024)#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
include/configs/sunxi-common.h +0 -4
@@ -202,10 +202,6 @@#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK -#ifndef CONFIG_ARM64 -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" -#endif -#define CONFIG_SPL_PAD_TO 32768/* decimal for 'dd' */
include/configs/tam3517-common.h +0 -1
@@ -176,7 +176,6 @@#define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"#define CONFIG_SPL_TEXT_BASE 0x40200000/*CONFIG_SYS_SRAM_START*/ #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
include/configs/tao3530.h +0 -1
@@ -246,7 +246,6 @@#define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_OMAP3_ID_NAND -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"/* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE
include/configs/ti814x_evm.h +0 -1
@@ -149,7 +149,6 @@#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"/* * 1MB into the SDRAM to allow for SPL's bss@the beginning of SDRAM
include/configs/ti816x_evm.h +0 -2
@@ -118,8 +118,6 @@#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" -#define CONFIG_SYS_TEXT_BASE 0x80800000#define CONFIG_DRIVER_TI_EMAC
include/configs/ti_omap3_common.h +0 -1
@@ -60,7 +60,6 @@/* SPL */ #define CONFIG_SPL_TEXT_BASE 0x40200800 -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ (64 << 20))
include/configs/ti_omap4_common.h +0 -1
@@ -139,7 +139,6 @@* So moving TEXT_BASE down to non-HS limit. */ #define CONFIG_SPL_TEXT_BASE 0x40300000 -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ (128 << 20))
include/configs/ti_omap5_common.h +0 -1
@@ -100,7 +100,6 @@#define CONFIG_SPL_TEXT_BASE 0x40300000#endif -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ (128 << 20))
include/configs/tricorder.h +0 -1
@@ -264,7 +264,6 @@#define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
include/configs/woodburn_sd.h +0 -1
@@ -21,7 +21,6 @@* SPL */ #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm1136/u-boot-spl.lds"#define CONFIG_SPL_TEXT_BASE 0x10002300#define CONFIG_SPL_MAX_SIZE (64 * 1024)/* 8 KB for stack */
include/configs/x600.h +0 -1
@@ -246,7 +246,6 @@#define CONFIG_SPL_TEXT_BASE 0xd2800b00#define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00)#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"#define CONFIG_SPL_FRAMEWORK
include/configs/zynq-common.h +0 -2
@@ -275,8 +275,6 @@#define CONFIG_CMD_SPL #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-zynq/u-boot-spl.lds" -/* MMC support */ #ifdef CONFIG_MMC_SDHCI_ZYNQ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
Signature · 1 line
2.1.4
PATCH v3 60/66 spl: moveconfig: migrate CONFIG_SPL_LDSCRIPT
Quoted 18 lines · On Fri, 28 Jul 2017 21:22:32 +0200 Philipp Tomsich…
With
SPL_LDSCRIPTdefined viaKconfig, we can run moveconfig... this will touch every configuration that uses SPL, even if there was an implicit resolution of theSPL_LDSCRIPT: now everything is explicit.Signed-off-by Philipp Tomsich <[email protected]>---
Changes in v3:
-moveconfig.pyCONFIG_SPL_LDSCRIPT
(Note: I really don't know whether this is what we want, as it's making theSPL_LDSCRIPTresolution explicit for every board... then again, I understood Tom's comment that moving things intoKconfigshould be the priority...)Changes in v2: None
configs/A10-OLinuXino-Lime_defconfig | 1 +
[...]
configs/A10-OLinuXino-Lime_defconfig CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime" · line 14
Quoted 12 lines
include/configs/zynq-common.h | 2 -- 369 files changed, 313 insertions(+), 106 deletions(-)configs/A10-OLinuXino-Lime_defconfig +1
-0@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
Why do we want to clutter board-specific config files with this information?
If this is migrated to Kconfig, then we probably want to have reasonable SoC-specific defaults there and leave defconfigs alone.
Quoted 3 lines
configs/A10-OLinuXino-Lime_defconfig +0
-0CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set
Signature · 2 lines
Best regards, Siarhei Siamashka
PATCH v3 60/66 spl: moveconfig: migrate CONFIG_SPL_LDSCRIPT
Quoted 30 lines · Siarhei Siamashka
Quoted 18 lines · On Fri, 28 Jul 2017 21:22:32 +0200 Philipp Tomsich…
With
SPL_LDSCRIPTdefined viaKconfig, we can run moveconfig... this will touch every configuration that uses SPL, even if there was an implicit resolution of theSPL_LDSCRIPT: now everything is explicit.Signed-off-by Philipp Tomsich <[email protected]>---
Changes in v3:
-moveconfig.pyCONFIG_SPL_LDSCRIPT
(Note: I really don't know whether this is what we want, as it's making theSPL_LDSCRIPTresolution explicit for every board... then again, I understood Tom's comment that moving things intoKconfigshould be the priority...)Changes in v2: None
configs/A10-OLinuXino-Lime_defconfig | 1 +
[...]
Quoted 3 lines
include/configs/zynq-common.h| 2 --369 files changed, 313 insertions(+), 106 deletions(-)
Quoted 12 lines
Quoted 9 lines
configs/A10-OLinuXino-Lime_defconfig +0
-0@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
CONFIG_AHCI=y
#CONFIG_SYS_MALLOC_CLEAR_ON_INITis not setCONFIG_SPL=y+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"Why do we want to clutter board-specific config files with this information?
I do agree that this is not the preferable way of doing things and that this should be propagated back up through Kconfig. One possibility might be to add ‘default “…” if “…”’ entries either to the central Kconfig for SPL or to have these in the various machine-subdirectories.
Let’s see if some consensus emerges from this...
My plan was to skip this specific patch on the merge (which is the reason I kept the moveconfig-run as a separate commit), but keep it here as a point-of-reference.
Quoted 11 lines
If this is migrated to
Kconfig, then we probably want to have reasonable SoC-specific defaults there and leave defconfigs alone.Quoted 3 lines
CONFIG_SPL_I2C_SUPPORT=y
#CONFIG_CMD_IMLSis not set
#CONFIG_CMD_FLASHis not setSignature · 2 lines
Best regards, Siarhei Siamashka
PATCH v3 60/66 spl: moveconfig: migrate CONFIG_SPL_LDSCRIPT
Quoted 43 lines · Dr. Philipp Tomsich
Quoted 30 lines · Siarhei Siamashka
Quoted 18 lines · On Fri, 28 Jul 2017 21:22:32 +0200 Philipp Tomsich…
With
SPL_LDSCRIPTdefined viaKconfig, we can run moveconfig... this will touch every configuration that uses SPL, even if there was an implicit resolution of theSPL_LDSCRIPT: now everything is explicit.Signed-off-by Philipp Tomsich <[email protected]>---
Changes in v3:
-moveconfig.pyCONFIG_SPL_LDSCRIPT
(Note: I really don't know whether this is what we want, as it's making theSPL_LDSCRIPTresolution explicit for every board... then again, I understood Tom's comment that moving things intoKconfigshould be the priority...)Changes in v2: None
configs/A10-OLinuXino-Lime_defconfig | 1 +
[...]
Quoted 3 lines
include/configs/zynq-common.h| 2 --369 files changed, 313 insertions(+), 106 deletions(-)Quoted 12 lines
Quoted 9 lines
configs/A10-OLinuXino-Lime_defconfig +0
-0@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
CONFIG_AHCI=y
#CONFIG_SYS_MALLOC_CLEAR_ON_INITis not setCONFIG_SPL=y+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"Why do we want to clutter board-specific config files with this information?
Quoted 8 lines
I do agree that this is not the preferable way of doing things and that this should be propagated back up through
Kconfig. One possibility might be to add ‘default “…” if “…”’ entries either to the centralKconfigfor SPL or to have these in the various machine-subdirectories.Let’s see if some consensus emerges from this...
My vote would be to have the Target selection or Platform selection imply the respective linker script, so you can keep any exceptions in the defconfig files, but the majority of them not get overly cluttered.
adam
Quoted 20 lines
My plan was to skip this specific patch on the merge (which is the reason I kept the moveconfig-run as a separate commit), but keep it here as a point-of-reference.
Quoted 11 lines
If this is migrated to
Kconfig, then we probably want to have reasonable SoC-specific defaults there and leave defconfigs alone.Quoted 3 lines
CONFIG_SPL_I2C_SUPPORT=y
#CONFIG_CMD_IMLSis not set
#CONFIG_CMD_FLASHis not set--
Best regards,
Siarhei Siamashka_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
https://lists.denx.de/listinfo/u-boot
PATCH v3 61/66 spl: support TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE via Kconfig
In reply to Philipp TomsichLet's clean up behind ourselves and move the (newly defined) TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE into Kconfig. Given that 0x0 might be considered to be valid values for TPL_TEXT_BASE and TPL_STACK, we need to introduce helper config options ("TPL_NEEDS_SEPARATE_...") to indicate that these symbols are used (and not inherited from their SPL variants) for any given target-platform.
Signed-off-by Philipp Tomsich <[email protected]>
---
Changes in v3:
- moves TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE to Kconfig
Changes in v2: None
common/spl/Kconfig | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)
common/spl/Kconfig +39 -0
@@ -725,6 +725,45 @@ config TPL_LDSCRIPT U-Boot stage. Set this to the path of the linker-script to be used for TPL. + May be left empty to trigger the Makefile infrastructure to + fall back to the linker-script used for the SPL stage. + +config TPL_NEEDS_SEPARATE_TEXT_BASE + bool "TPL needs a separate text-base" + default n + depends on TPL + help + Enable, if the TPL stage should not inherit its text-base + from the SPL stage. When enabled, a base address for the + .text sections of the TPL stage has to be set below. + +config TPL_NEEDS_SEPARATE_STACK + bool "TPL needs a separate initial stack-pointer" + default n + depends on TPL + help + Enable, if the TPL stage should not inherit its initial + stack-pointer from the settings for the SPL stage. + +config TPL_TEXT_BASE + hex "Base address for the .text section of the TPL stage" + depends on TPL_NEEDS_SEPARATE_TEXT_BASE + help + The base address for the .text section of the TPL stage. + +config TPL_MAX_SIZE + int "Maximum size (in bytes) for the TPL stage" + depends on TPL + help + The maximum size (in bytes) of the TPL stage. + +config TPL_STACK + hex "Address of the initial stack-pointer for the TPL stage" + depends on TPL_NEEDS_SEPARATE_STACK + help + The address of the initial stack-pointer for the TPL stage. + Usually this will be the (aligned) top-of-stack. + config TPL_BOOTROM_SUPPORT bool "Support returning to the BOOTROM (from TPL)" help
Signature · 1 line
2.1.4
PATCH v3 61/66 spl: support TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE via Kconfig
Quoted 12 lines · Philipp Tomsich
Let's clean up behind ourselves and move the (newly defined)
TPL_STACK,TPL_MAX_SIZEandTPL_TEXT_BASEintoKconfig. Given that0x0might be considered to be valid values forTPL_TEXT_BASEandTPL_STACK, we need to introduce helper config options ("TPL_NEEDS_SEPARATE_...") to indicate that these symbols are used (and not inherited from their SPL variants) for any given target-platform.Signed-off-by Philipp Tomsich <[email protected]>---
Quoted 7 lines
Changes in v3:
- movesTPL_STACK,TPL_MAX_SIZEandTPL_TEXT_BASEtoKconfigChanges in v2: None
common/spl/Kconfig | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)
Reviewed-by Simon Glass <[email protected]>
PATCH v3 62/66 armv8: TPL_STACK will always be defined, so test CONFIG_TPL_NEEDS_SEPARATE_STACK
In reply to Philipp TomsichNow that TPL_STACK has been moved off the whitelist (ok, I'm lying:
the 'moving off the whitelist' part comes in once moveconfig runs... which will be a few commits down the line) and added to Kconfig, we need to test CONFIG_TPL_NEEDS_SEPARATE_STACK to see whether the value from TPL_STACK should be used or whether we try to inherit whatever SPL uses.
Signed-off-by Philipp Tomsich <[email protected]>
---
Changes in v3:
- changes the test to CONFIG_TPL_NEEDS_SEPARATE_STACK, as TPL_STACK will be a hex-value now (and this always be defined)
Changes in v2: None
arch/arm/lib/crt0_64.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/lib/crt0_64.S +1 -1
@@ -69,7 +69,7 @@ ENTRY(_main) /* * Set up initial C runtime environment and call board_init_f(0). */ -#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_STACK) +#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK) ldr x0, =(CONFIG_TPL_STACK) #elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) ldr x0, =(CONFIG_SPL_STACK)
Signature · 1 line
2.1.4
PATCH v3 62/66 armv8: TPL_STACK will always be defined, so test CONFIG_TPL_NEEDS_SEPARATE_STACK
Quoted 11 lines · Philipp Tomsich
Now that
TPL_STACKhas been moved off the whitelist (ok, I'm lying:
the 'moving off the whitelist' part comes in once moveconfig runs... which will be a few commits down the line) and added toKconfig, we need to testCONFIG_TPL_NEEDS_SEPARATE_STACKto see whether the value fromTPL_STACKshould be used or whether we try to inherit whatever SPL uses.Signed-off-by Philipp Tomsich <[email protected]>---
Quoted 8 lines
Changes in v3:
- changes the test toCONFIG_TPL_NEEDS_SEPARATE_STACK, asTPL_STACKwill be a hex-value now (and this always be defined)Changes in v2: None
arch/arm/lib/crt0_64.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by Simon Glass <[email protected]>
PATCH v3 63/66 rockchip: rk3368: mark TPL as not inheriting its stack, text-base and size from SPL
In reply to Philipp TomsichThe RK3368 needs to have a different base-address and stack-pointer for its TPL stage. Now that we want to do this via Kconfig, we need to tick the appropriate 'TPL_NEEDS_...' boxes.
Signed-off-by Philipp Tomsich <[email protected]>
---
Changes in v3:
- changes Kconfig, so RK3368 will notify the SPL configuration of its need to have the TPL text-base, stack-pointer and max-size configured
Changes in v2: None
arch/arm/mach-rockchip/Kconfig | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/mach-rockchip/Kconfig +2 -0
@@ -69,6 +69,8 @@ config ROCKCHIP_RK3368 select ARM64 select SUPPORT_SPL select SUPPORT_TPL + select TPL_NEEDS_SEPARATE_TEXT_BASE + select TPL_NEEDS_SEPARATE_STACK select SPL_SEPARATE_BSS select SPL_SERIAL_SUPPORT select TPL_SERIAL_SUPPORT
Signature · 1 line
2.1.4
PATCH v3 63/66 rockchip: rk3368: mark TPL as not inheriting its stack, text-base and size from SPL
Quoted 13 lines · Philipp Tomsich
The RK3368 needs to have a different base-address and stack-pointer for its TPL stage. Now that we want to do this via
Kconfig, we need to tick the appropriate 'TPL_NEEDS_...' boxes.Signed-off-by Philipp Tomsich <[email protected]>---
Changes in v3:
- changesKconfig, so RK3368 will notify the SPL configuration of its need to have the TPL text-base, stack-pointer and max-size configured
Quoted 4 lines
Changes in v2: None
arch/arm/mach-rockchip/Kconfig | 2 ++ 1 file changed, 2 insertions(+)
Reviewed-by Simon Glass <[email protected]>
PATCH v3 64/66 moveconfig: migrate TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE
In reply to Philipp TomsichWe can finally drop TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE off the whitelist (this time it's really happening!) and migrate the setting (only used on the RK3368-uQ7 so far) into defconfig.
One major caveat: other RK3368 boards that move to use SPL/TPL will also need to set these values in their defconfig.
Signed-off-by Philipp Tomsich <[email protected]>
---
Changes in v3:
- runs moveconfig.py TPL_STACK TPL_TEXT_BASE TPL_MAX_SIZE
Changes in v2: None
configs/lion-rk3368_defconfig | 3 +++ include/configs/rk3368_common.h | 4 ---- scripts/config_whitelist.txt | 3 --- 3 files changed, 3 insertions(+), 7 deletions(-)
configs/lion-rk3368_defconfig +3 -0
@@ -33,6 +33,9 @@ CONFIG_SPL_ATF_SUPPORT=y CONFIG_SPL_ATF_TEXT_BASE=0x10000 CONFIG_TPL=y CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds" +CONFIG_TPL_TEXT_BASE=0xff8c1000 +CONFIG_TPL_MAX_SIZE=28672 +CONFIG_TPL_STACK=0xff8cffff CONFIG_TPL_BOOTROM_SUPPORT=y CONFIG_TPL_DRIVERS_MISC_SUPPORT=y CONFIG_FASTBOOT=y
include/configs/rk3368_common.h +0 -4
@@ -35,10 +35,6 @@#define CONFIG_SPL_BSS_START_ADDR 0x400000#define CONFIG_SPL_BSS_MAX_SIZE 0x20000 -#define CONFIG_TPL_TEXT_BASE 0xff8c1000 -#define CONFIG_TPL_MAX_SIZE 0x7000 -#define CONFIG_TPL_STACK 0xff8cffff -#define CONFIG_BOUNCE_BUFFER #ifndef CONFIG_SPL_BUILD
scripts/config_whitelist.txt +0 -3
@@ -4980,10 +4980,7 @@ CONFIG_TI_KEYSTONE_SERDES CONFIG_TI_KSNAV CONFIG_TI_SPI_MMAP CONFIG_TMU_TIMER -CONFIG_TPL_MAX_SIZE CONFIG_TPL_PAD_TO -CONFIG_TPL_STACK -CONFIG_TPL_TEXT_BASE CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_TPS6586X_POWER CONFIG_TQM834X
Signature · 1 line
2.1.4
PATCH v3 64/66 moveconfig: migrate TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE
Quoted 14 lines · Philipp Tomsich
We can finally drop
TPL_STACK,TPL_TEXT_BASEandTPL_MAX_SIZEoff the whitelist (this time it's really happening!) and migrate the setting (only used on the RK3368-uQ7 so far) into defconfig.One major caveat: other RK3368 boards that move to use SPL/TPL will also need to set these values in their defconfig.
Signed-off-by Philipp Tomsich <[email protected]>---
Changes in v3:
- runsmoveconfig.pyTPL_STACKTPL_TEXT_BASETPL_MAX_SIZE
Quoted 6 lines
Changes in v2: None
configs/lion-rk3368_defconfig | 3 +++ include/configs/rk3368_common.h | 4 ---- scripts/config_whitelist.txt | 3 --- 3 files changed, 3 insertions(+), 7 deletions(-)
Reviewed-by Simon Glass <[email protected]>
PATCH v3 65/66 rockchip: board: puma-rk3399: fix warnings in puma_rk3399/fit_spl_atf.its
In reply to Philipp TomsichThe ITS file generated warnings due to @<num> designations in the naming
which cause DTC to complain as follows:
Warning (unit_address_vs_reg): Node /images/uboot at 1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /images/atf at 1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /images/pmu at 1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /images/fdt at 1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /configurations/conf at 1 has a unit name, but no reg property
This removes the @<num> part from the names, as we only have a single image for each payload aspect (and only a single configuration) anyway.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
board/theobroma-systems/puma_rk3399/fit_spl_atf.its | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)
board/theobroma-systems/puma_rk3399/fit_spl_atf.its +9 -9
@@ -13,7 +13,7 @@ #address-cells = <1>; images { - uboot at 1 { + uboot { description = "U-Boot (64-bit)"; data = /incbin/("../../../u-boot-nodtb.bin"); type = "standalone";
@@ -21,7 +21,7 @@ compression = "none"; load = <0x00200000>; }; - atf at 1 { + atf { description = "ARM Trusted Firmware"; data = /incbin/("../../../bl31.bin"); type = "firmware";
@@ -30,14 +30,14 @@ load = <0x00001000>; entry = <0x00001000>; }; - pmu at 1 { + pmu { description = "Cortex-M0 firmware"; data = /incbin/("../../../rk3399m0.bin"); type = "pmu-firmware"; compression = "none"; load = <0xff8c0000>; }; - fdt at 1 { + fdt { description = "RK3399-Q7 (Puma) flat device-tree"; data = /incbin/("../../../u-boot.dtb"); type = "flat_dt";
@@ -46,12 +46,12 @@ }; configurations { - default = "conf at 1"; - conf at 1 { + default = "conf"; + conf { description = "Theobroma Systems RK3399-Q7 (Puma) SoM"; - firmware = "uboot at 1"; - loadables = "atf at 1"; - fdt = "fdt at 1"; + firmware = "uboot"; + loadables = "atf"; + fdt = "fdt"; }; }; };
Signature · 1 line
2.1.4
PATCH v3 65/66 rockchip: board: puma-rk3399: fix warnings in puma_rk3399/fit_spl_atf.its
Hi Philipp,
rk3399 atf has 3 parts, sram.data, sram.text, pmu_fw for m0, and
now the ATF project output
with all 3 section in one bl31.elf, I use to abstract them into 3 separate bin file and package them
with fit.
Could you share some more detail about how you use the ATF in
puma-rk3399? You only have
two section in its description. How many steps do you need for rk3399 to get uboot, atf and the image
can be flash to eMMC?
Thanks,
- Kever
Quoted 79 lines · Philipp Tomsich
The ITS file generated warnings due to @<num> designations in the naming
which cause DTC to complain as follows:
Warning (unit_address_vs_reg): Node /images/uboot at 1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /images/atf at 1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /images/pmu at 1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /images/fdt at 1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /configurations/conf at 1 has a unit name, but no reg propertyThis removes the @<num> part from the names, as we only have a single image for each payload aspect (and only a single configuration) anyway.
Signed-off-by Philipp Tomsich <[email protected]>Reviewed-by Simon Glass <[email protected]>---
Changes in v3: None
Changes in v2: Noneboard/theobroma-systems/puma_rk3399/fit_spl_atf.its | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)board/theobroma-systems/puma_rk3399/fit_spl_atf.its +9
-9@@ -13,7 +13,7 @@ #address-cells = <1>; images { - uboot at 1 { + uboot { description = "U-Boot (64-bit)"; data = /incbin/("../../../u-boot-nodtb.bin"); type = "standalone";@@ -21,7 +21,7 @@ compression = "none"; load = <0x00200000>; }; - atf at 1 { + atf { description = "ARM Trusted Firmware"; data = /incbin/("../../../bl31.bin"); type = "firmware";@@ -30,14 +30,14 @@ load = <0x00001000>; entry = <0x00001000>; }; - pmu at 1 { + pmu { description = "Cortex-M0 firmware"; data = /incbin/("../../../rk3399m0.bin"); type = "pmu-firmware"; compression = "none"; load = <0xff8c0000>; }; - fdt at 1 { + fdt { description = "RK3399-Q7 (Puma) flat device-tree"; data = /incbin/("../../../u-boot.dtb"); type = "flat_dt";@@ -46,12 +46,12 @@ }; configurations { - default = "conf at 1"; - conf at 1 { + default = "conf"; + conf { description = "Theobroma Systems RK3399-Q7 (Puma) SoM"; - firmware = "uboot at 1"; - loadables = "atf at 1"; - fdt = "fdt at 1"; + firmware = "uboot"; + loadables = "atf"; + fdt = "fdt"; }; }; };
PATCH v3 65/66 rockchip: board: puma-rk3399: fix warnings in puma_rk3399/fit_spl_atf.its
Kever,
We use a fork of the ATF repository and have the M3 firmware completely factored out and have changed parts of the SRAM setup. In other words: there will be two separate .bin files created that need to be loaded to two separate locations. Please refer to our board’s README for the steps to get it set up and booted.
Note that there will be a structural update to our ATF in the next couple of weeks that is expected to change things around quite a bit.
Regards,
Philipp.
Quoted 98 lines · Kever Yang
Hi Philipp,
rk3399 atf has 3 parts, sram.data, sram.text,
pmu_fwfor m0, and now the ATF project outputwith all 3 section in one bl31.elf, I use to abstract them into 3 separate bin file and package them
with fit.
Could you share some more detail about how you use the ATF in puma-rk3399? You only have
two section in its description. How many steps do you need for rk3399 to get uboot, atf and the image
can be flash to eMMC?
Thanks,
- KeverQuoted 77 lines · Philipp Tomsich
The ITS file generated warnings due to @<num> designations in the naming
which cause DTC to complain as follows:
Warning (unit_address_vs_reg): Node /images/uboot at 1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /images/atf at 1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /images/pmu at 1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /images/fdt at 1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /configurations/conf at 1 has a unit name, but no reg propertyThis removes the @<num> part from the names, as we only have a single image for each payload aspect (and only a single configuration) anyway.
Signed-off-by Philipp Tomsich <[email protected]>Reviewed-by Simon Glass <[email protected]>---
Changes in v3: None
Changes in v2: Noneboard/theobroma-systems/puma_rk3399/fit_spl_atf.its | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)board/theobroma-systems/puma_rk3399/fit_spl_atf.its +9
-9@@ -13,7 +13,7 @@ #address-cells = <1>; images { - uboot at 1 { + uboot { description = "U-Boot (64-bit)"; data = /incbin/("../../../u-boot-nodtb.bin"); type = "standalone";@@ -21,7 +21,7 @@ compression = "none"; load = <0x00200000>; }; - atf at 1 { + atf { description = "ARM Trusted Firmware"; data = /incbin/("../../../bl31.bin"); type = "firmware";@@ -30,14 +30,14 @@ load = <0x00001000>; entry = <0x00001000>; }; - pmu at 1 { + pmu { description = "Cortex-M0 firmware"; data = /incbin/("../../../rk3399m0.bin"); type = "pmu-firmware"; compression = "none"; load = <0xff8c0000>; }; - fdt at 1 { + fdt { description = "RK3399-Q7 (Puma) flat device-tree"; data = /incbin/("../../../u-boot.dtb"); type = "flat_dt";@@ -46,12 +46,12 @@ }; configurations { - default = "conf at 1"; - conf at 1 { + default = "conf"; + conf { description = "Theobroma Systems RK3399-Q7 (Puma) SoM"; - firmware = "uboot at 1"; - loadables = "atf at 1"; - fdt = "fdt at 1"; + firmware = "uboot"; + loadables = "atf"; + fdt = "fdt"; }; }; };
PATCH v3 66/66 rockchip: board: puma_rk3399: rename ATF firmware
In reply to Philipp TomsichFrom: Klaus Goger <[email protected]>
prefix the bl31 firmware needed to build uboot.itb so it can coexist in the build area with ATFs from other boards (i.e. lion_rk3368)
Signed-off-by Klaus Goger <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Signed-off-by Philipp Tomsich <[email protected]>
---
Changes in v3: None
Changes in v2: None
board/theobroma-systems/puma_rk3399/README | 2 +- board/theobroma-systems/puma_rk3399/fit_spl_atf.its | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
board/theobroma-systems/puma_rk3399/README +1 -1
@@ -37,7 +37,7 @@ Compile the ATF > cd arm-trusted-firmware > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31 - > cp build/rk3399/release/bl31.bin ../u-boot + > cp build/rk3399/release/bl31.bin ../u-boot/bl31-rk3399.bin Compile the M0 firmware =======================
board/theobroma-systems/puma_rk3399/fit_spl_atf.its +1 -1
@@ -23,7 +23,7 @@ }; atf { description = "ARM Trusted Firmware"; - data = /incbin/("../../../bl31.bin"); + data = /incbin/("../../../bl31-rk3399.bin"); type = "firmware"; arch = "arm64"; compression = "none";
Signature · 1 line
2.1.4