Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7
Subsystems (16)
v3 cover Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7
Here's the (hopefully final) updated series to enable the RK3368 which addresses the concerns regarding the prefixing of GRF bit-definitions with a RK3368-prefix: while I had intended to temporarily pull the GMAC support to get around the underlying issue, moving the bit-definitions into the pinctrl-driver's implementation turned out to rather straightforward (and there's little use in having these definitions visible outside of the pinctrl driver anyway).
Thanks to everyone, who took the time to comment/discuss the initial version.
This series (still) has a lot going on, but I didn't want to split it to allow everyone to understand the motivation between some of the changes to the SPL/TPL framework. The short summary of this is "enablement for DRAM init on the RK3368 with everything else that's necessary to do it using OF_PLATDATA in TPL".
Enabling the RK3368 created a few more challenges that I'd expected:
- I needed different stack locations, text addresses and sizes for TPL and SPL
- the TPL stage was to use OF_PLATDATA and SPL was to use full OF_CONTROL
- with the RK3368 TPL stage, there was a need to extend the back-to-bootrom support for Rockchip to AArch64
- I wanted to start folding some of the Rockchip specific SPL support (i.e. back-to-bootrom) back into the general SPL framework to allow using it as a general boot method
So I ended up separating quite a bit of features between SPL and TPL while keeping things transparent to the few other boards using TPL (at least I hope that things are transparent, as we didn't have any of those in our lab to test on)...
Tested with: RK3368-uQ7, Debian 9, Linux 4.13-rc1.
Just one final remark: the DMC driver for the RK3368 currently covers the configuration we use on the RK3368-uQ7 (i.e. 32bit wide, 2 ranks) and is stress-tested (including 8-way SPEC runs) at all 3 supported speeds. I've built a bit of infrastructure (e.g. the way the memory-schedule is determined) that I hope will be a useful starting-point in unifying the drivers for the various closely related DRAM controllers (e.g. for the RK3288) for Rockchip devices in the future.
Changes in v3:
- (new patch) added fix-up of SPL/TPL confusion in help text
- change to use function-sections (instead of disabling at the Makefile-level for TPL builds) per Tom's suggestion
- commit message now correctly refers to TPL
- adds SGRF syscon support with OF_PLATDATA (to allow access to the SGRF address range from TPL)
- correctly states the location of the driver in the commit message
- removes the '#define DEBUG'
- uses the syscon API to access GRF and SGRF to avoid using hard-coded addresses
- (after rebase) update defconfig
- (after rebase and defconfig update) lion_rk3368.h: remove CONFIG_ENV_IS_NOWHERE
- moves remaining 'u-boot,dm-pre-reloc' to -u-boot.dtsi
- marks sgrf-node as pre-reloc
- defines SPL_LDSCRIPT and TPL_LDSCRIPT via defconfig
- moves SPL_LDSCRIPT and TPL_LDSCRIPT into Kconfig, as requested by by Tom; this gets rid of the whitelist-entry for SPL_LDSCRIPT (which qualifies as a preexisting condition) and of the newly created one for TPL_LDSCRIPT
- moveconfig.py CONFIG_SPL_LDSCRIPT
(Note: I really don't know whether this is what we want, as it's making the SPL_LDSCRIPT resolution explicit for every board... then again, I understood Tom's comment that moving things into Kconfig should be the priority...)
- moves TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE to Kconfig
- changes the test to CONFIG_TPL_NEEDS_SEPARATE_STACK, as TPL_STACK will be a hex-value now (and this always be defined)
- changes Kconfig, so RK3368 will notify the SPL configuration of its need to have the TPL text-base, stack-pointer and max-size configured
- runs moveconfig.py TPL_STACK TPL_TEXT_BASE TPL_MAX_SIZE
Changes in v2:
- dropped the RK3368_ prefix for the GRF constants
- removed the RK3368-prefix on bit-definitions for GMAC pinctrl
- removed the RK3368 prefix on the SD/MMC pin definitions
- moved bit-definitions pertinent to pinctrl (i.e. the various IOMUX definitions) to the rk3368 pinctrl driver implementation
- added SPI clock setup
- moves the bit-definitions (for GRF registers) specific to the GMAC into the GMAC driver: these include interface speed selection and configuring the RGMII output mode
- removes a 'u-boot,dm-pre-reloc' from dmc-node in rk3368.dtsi
- copies the enum for the IOMUX config of the debug UART into the TPL support code, as the various constants are otherwise private to the pinctrl code (and we can't include pinctrl in the TPL stage due to size constraints/dependencies)
- added in v2
- reuses the support for configuring the boot order using the u-boot,spl-boot-order property
- drops the initialisation of the debug_uart
- adds pinctrl-configuration for the preloader UART
- marks pinctrl-node as 'u-boot,dm-pre-reloc' to ensure MMC2 (eMMC) works in the SPL stage
- makes uart0 as 'u-boot,dm-pre-reloc' to allow initialising the preloader console (instead of relying solely on the debug UART)
- adds support for SPI1 (and the on-module SPI flash)
- splits the a 'u-boot.dtsi' off the DTS file
- updates the defconfig for SPI and SPI flash support
Klaus Goger (1):
rockchip: board: puma_rk3399: rename ATF firmware
Philipp Tomsich (65):
spl: add a 'return to bootrom' boot method
spl: configure 'return to bootrom' separately for SPL and TPL
rockchip: back-to-bootrom: add 'back-to-bootrom' support for AArch64
rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL
rockchip: back-to-bootrom: simplify the #ifdef-check for LIBGENERIC in
TPL/SPL
spl: adapts SYS_MALLOC_F_LEN for TPL
spl: dm: Kconfig: fix help text for SPL/TPL confusion
spl: dm: Kconfig: use more specific prereqs for SPL_REGMAP and
SPL_SYSCON
spl: dm: Kconfig: split REGMAP/SYSCON support for TPL from SPL
spl: dm: Kconfig: SPL_RAM depends on SPL_DM
spl: dm: Kconfig: introduce TPL_RAM (in analogy to SPL_RAM)
spl: dm: Kconfig: SPL_CLK depends on SPL_DM
spl: dm: Kconfig: split CLK support for SPL and TPL
spl: dm: Kconfig: split OF_CONTROL and OF_PLATDATA between SPL and TPL
spl: dm: use CONFIG_IS_ENABLED to test for the DM option
armv8: move low-level assembly functions into function-sections
armv8: spl: Support separate stack for TPL
spl: allow a separate TEXT_BASE, LDSCRIPT and MAX_SIZE for TPL
spl: Kconfig: split SYS_MALLOC_SIMPLE for TPL and SPL
lib: spl: differentiate between TPL and SPL for
libfdt/of_control/of_platdata
spl: consistently use $(SPL_TPL_) to select features for SPL and TPL
builds
spl: add TPL_DRIVER_MISC_SUPPORT option
drivers: spl: consistently use the $(SPL_TPL_) macro
rockchip: Makefile: allow selective inclusion of sdram_common.o from
TPL/SPL/U-Boot
rockchip: rk3368: improve Kconfig text for the RK3368
rockchip: rk3368: mkimage: add support for the RK3368
rockchip: rk3368: pmugrf: add definitions for os_reg[0..3]
rockchip: rk3368: spl: define COUNTER_FREQUENCY to 24MHz
rockchip: rk3368: spl: add memory layout for TPL and SPL
rockchip: rk3368: syscon: MSCH/PMUGRF/GRF support for OF_PLATDATA
rockchip: rk3368: syscon: SGRF support for OF_PLATDATA
rockchip: rk3368: grf: use shifted-constants
rockchip: rk3368: dts: add sgrf node
rockchip: pinctrl: rk3368: add GMAC (RGMII only) support
rockchip: pinctrl: rk3368: add support for configuring the MMC pins
rockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl
driver
rockchip: pinctrl: rk3368: add SPI support
rockchip: clk: rk3368: implement bandwidth adjust for PLLs
rockchip: clk: rk3368: support OF_PLATDATA for the RK3368 clk driver
rockchip: clk: rk3368: do not change CPLL/GPLL before returning to
BROM
rockchip: clk: rk3368: implement DPLL (DRAM PLL) support
rockchip: clk: rk3368: define DMA1_SRST_REQ and DMA2_SRST_REQ
rockchip: clk: rk3368: implement MMC/SD clock reparenting
rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL)
rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock
rockchip: clk: rk3368: mark 'priv' __maybe_unused in
rk3368_clk_set_rate()
rockchip: clk: rk3368: add support for configuring the SPI clocks
net: gmac_rockchip: Add support for the RK3368 GMAC
rockchip: Makefile: streamline SPL/TPL configuration
rockchip: rk3368: add DRAM controller driver with DRAM initialisation
rockchip: rk3368: dts: add DMC node in rk3368.dtsi
rockchip: rk3368: spl: enable SPL_FRAMEWORK in rk3368_common.h
rockchip: rk3368: spl: add TPL support
rockchip: spl: make spl-boot-order code reusable (split from rk3399)
rockchip: rk3368: spl: add SPL support
rockchip: rk3368: spl: mark SPL and TPL as supported for
ROCKCHIP_RK3368
rockchip: spi: enable support for the rk_spi driver for the RK3368
rockchip: board: lion-rk3368: add support for the RK3368-uQ7
spl: Kconfig: migrate $(SPL_TPL_)LDSCRIPT to Kconfig
spl: moveconfig: migrate CONFIG_SPL_LDSCRIPT
spl: support TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE via Kconfig
armv8: TPL_STACK will always be defined, so test
CONFIG_TPL_NEEDS_SEPARATE_STACK
rockchip: rk3368: mark TPL as not inheriting its stack, text-base and
size from SPL
moveconfig: migrate TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE
rockchip: board: puma-rk3399: fix warnings in
puma_rk3399/fit_spl_atf.itsKconfig | 12 +- Makefile | 2 +- arch/arm/cpu/armv8/Makefile | 2 +- arch/arm/cpu/armv8/cache.S | 22 + arch/arm/cpu/armv8/tlb.S | 4 +- arch/arm/cpu/armv8/transition.S | 6 + arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3368-lion-u-boot.dtsi | 88 ++ arch/arm/dts/rk3368-lion.dts | 195 ++++ arch/arm/dts/rk3368.dtsi | 28 +- arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 15 +- arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++ arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 326 +------ arch/arm/include/asm/spl.h | 1 + arch/arm/lib/crt0_64.S | 4 +- arch/arm/mach-rockchip/Kconfig | 39 +- arch/arm/mach-rockchip/Makefile | 51 +- arch/arm/mach-rockchip/bootrom.c | 4 +- arch/arm/mach-rockchip/rk3188-board-spl.c | 5 +- arch/arm/mach-rockchip/rk3188-board.c | 2 +- arch/arm/mach-rockchip/rk3288-board-spl.c | 4 +- arch/arm/mach-rockchip/rk3288-board.c | 4 +- arch/arm/mach-rockchip/rk3368-board-spl.c | 98 ++ arch/arm/mach-rockchip/rk3368-board-tpl.c | 177 ++++ arch/arm/mach-rockchip/rk3368/Kconfig | 21 + arch/arm/mach-rockchip/rk3368/Makefile | 1 - arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 -- arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 44 + arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds | 13 + arch/arm/mach-rockchip/rk3399-board-spl.c | 106 +-- arch/arm/mach-rockchip/save_boot_param.S | 37 + arch/arm/mach-rockchip/spl-boot-order.c | 108 +++ board/theobroma-systems/lion_rk3368/Kconfig | 15 + board/theobroma-systems/lion_rk3368/MAINTAINERS | 10 + board/theobroma-systems/lion_rk3368/Makefile | 7 + board/theobroma-systems/lion_rk3368/README | 60 ++ .../theobroma-systems/lion_rk3368/fit_spl_atf.its | 51 ++ board/theobroma-systems/lion_rk3368/lion_rk3368.c | 25 + board/theobroma-systems/puma_rk3399/README | 2 +- .../theobroma-systems/puma_rk3399/fit_spl_atf.its | 20 +- common/Makefile | 8 +- common/spl/Kconfig | 106 ++- common/spl/Makefile | 35 +- common/spl/spl.c | 7 +- common/spl/spl_bootrom.c | 27 + configs/A10-OLinuXino-Lime_defconfig | 1 + configs/A10s-OLinuXino-M_defconfig | 1 + configs/A13-OLinuXinoM_defconfig | 1 + configs/A13-OLinuXino_defconfig | 1 + configs/A20-OLinuXino-Lime2_defconfig | 1 + configs/A20-OLinuXino-Lime_defconfig | 1 + configs/A20-OLinuXino_MICRO_defconfig | 1 + configs/A20-Olimex-SOM-EVB_defconfig | 1 + configs/A33-OLinuXino_defconfig | 1 + configs/Ainol_AW1_defconfig | 1 + configs/Ampe_A76_defconfig | 1 + configs/Auxtek-T003_defconfig | 1 + configs/Auxtek-T004_defconfig | 1 + configs/Bananapi_M2_Ultra_defconfig | 1 + configs/Bananapi_defconfig | 1 + configs/Bananapro_defconfig | 1 + configs/CHIP_defconfig | 1 + configs/CHIP_pro_defconfig | 1 + configs/CSQ_CS908_defconfig | 1 + configs/Chuwi_V7_CW0825_defconfig | 1 + configs/Colombus_defconfig | 1 + configs/Cubieboard2_defconfig | 1 + configs/Cubieboard4_defconfig | 1 + configs/Cubieboard_defconfig | 1 + configs/Cubietruck_defconfig | 1 + configs/Cubietruck_plus_defconfig | 1 + configs/Empire_electronix_d709_defconfig | 1 + configs/Empire_electronix_m712_defconfig | 1 + configs/Hummingbird_A31_defconfig | 1 + configs/Hyundai_A7HD_defconfig | 1 + configs/Itead_Ibox_A20_defconfig | 1 + configs/Lamobo_R1_defconfig | 1 + configs/Linksprite_pcDuino3_Nano_defconfig | 1 + configs/Linksprite_pcDuino3_defconfig | 1 + configs/Linksprite_pcDuino_defconfig | 1 + configs/MK808C_defconfig | 1 + configs/MSI_Primo73_defconfig | 1 + configs/MSI_Primo81_defconfig | 1 + configs/Marsboard_A10_defconfig | 1 + configs/Mele_A1000G_quad_defconfig | 1 + configs/Mele_A1000_defconfig | 1 + configs/Mele_I7_defconfig | 1 + configs/Mele_M3_defconfig | 1 + configs/Mele_M5_defconfig | 1 + configs/Mele_M9_defconfig | 1 + configs/Merrii_A80_Optimus_defconfig | 1 + configs/Mini-X_defconfig | 1 + configs/Nintendo_NES_Classic_Edition_defconfig | 1 + configs/Orangepi_defconfig | 1 + configs/Orangepi_mini_defconfig | 1 + configs/Sinlinx_SinA31s_defconfig | 1 + configs/Sinlinx_SinA33_defconfig | 1 + configs/Sinovoip_BPI_M2_Plus_defconfig | 1 + configs/Sinovoip_BPI_M2_defconfig | 1 + configs/Sinovoip_BPI_M3_defconfig | 1 + configs/Sunchip_CX-A99_defconfig | 1 + configs/UTOO_P66_defconfig | 1 + configs/Wexler_TAB7200_defconfig | 1 + configs/Wits_Pro_A20_DKT_defconfig | 1 + configs/Wobo_i5_defconfig | 1 + configs/Yones_Toptech_BD1078_defconfig | 1 + configs/Yones_Toptech_BS1078_V2_defconfig | 1 + configs/am335x_baltos_defconfig | 1 + configs/am335x_boneblack_defconfig | 1 + configs/am335x_boneblack_vboot_defconfig | 1 + configs/am335x_evm_defconfig | 1 + configs/am335x_evm_nor_defconfig | 1 + configs/am335x_evm_spiboot_defconfig | 1 + configs/am335x_evm_usbspl_defconfig | 1 + configs/am335x_hs_evm_defconfig | 1 + configs/am335x_igep003x_defconfig | 1 + configs/am335x_shc_defconfig | 1 + configs/am335x_shc_ict_defconfig | 1 + configs/am335x_shc_netboot_defconfig | 1 + configs/am335x_shc_prompt_defconfig | 1 + configs/am335x_shc_sdboot_defconfig | 1 + configs/am335x_shc_sdboot_prompt_defconfig | 1 + configs/am335x_sl50_defconfig | 1 + configs/am3517_crane_defconfig | 1 + configs/am3517_evm_defconfig | 1 + configs/am43xx_evm_defconfig | 1 + configs/am43xx_evm_ethboot_defconfig | 1 + configs/am43xx_evm_usbhost_boot_defconfig | 1 + configs/am43xx_hs_evm_defconfig | 1 + configs/am57xx_evm_defconfig | 1 + configs/am57xx_evm_nodt_defconfig | 1 + configs/am57xx_hs_evm_defconfig | 1 + configs/apalis_imx6_defconfig | 1 + configs/apf27_defconfig | 1 + configs/apx4devkit_defconfig | 1 + configs/arndale_defconfig | 1 + configs/ba10_tv_box_defconfig | 1 + configs/bg0900_defconfig | 1 + configs/birdland_bav335a_defconfig | 1 + configs/birdland_bav335b_defconfig | 1 + configs/brppt1_mmc_defconfig | 1 + configs/brppt1_nand_defconfig | 1 + configs/brppt1_spi_defconfig | 1 + configs/brxre1_defconfig | 1 + configs/cairo_defconfig | 1 + configs/cgtqmx6eval_defconfig | 1 + configs/chiliboard_defconfig | 1 + configs/chromebook_link64_defconfig | 5 +- configs/cl-som-am57x_defconfig | 1 + configs/cm_fx6_defconfig | 1 + configs/cm_t335_defconfig | 1 + configs/cm_t35_defconfig | 1 + configs/cm_t43_defconfig | 1 + configs/cm_t54_defconfig | 3 +- configs/colibri_imx6_defconfig | 1 + configs/colorfly_e708_q1_defconfig | 1 + configs/controlcenterdc_defconfig | 2 +- configs/da850_am18xxevm_defconfig | 1 + configs/da850evm_defconfig | 1 + configs/db-88f6820-gp_defconfig | 2 +- configs/devkit8000_defconfig | 1 + configs/difrnce_dit4350_defconfig | 1 + configs/dra7xx_evm_defconfig | 3 +- configs/dra7xx_hs_evm_defconfig | 3 +- configs/draco_defconfig | 1 + configs/dserve_dsrv9703c_defconfig | 1 + configs/duovero_defconfig | 1 + configs/eco5pk_defconfig | 1 + configs/edminiv2_defconfig | 1 + configs/etamin_defconfig | 1 + configs/evb-rk3036_defconfig | 2 +- configs/evb-rk3229_defconfig | 1 - configs/evb-rk3288_defconfig | 2 +- configs/fennec-rk3288_defconfig | 2 +- configs/firefly-rk3288_defconfig | 7 +- configs/ga10h_v1_1_defconfig | 1 + configs/gt90h_v4_defconfig | 1 + configs/gwventana_emmc_defconfig | 1 + configs/gwventana_gw5904_defconfig | 1 + configs/gwventana_nand_defconfig | 1 + configs/h8_homlet_v2_defconfig | 1 + configs/i12-tvbox_defconfig | 1 + configs/iNet_3F_defconfig | 1 + configs/iNet_3W_defconfig | 1 + configs/iNet_86VS_defconfig | 1 + configs/iNet_D978_rev2_defconfig | 1 + configs/icnova-a20-swac_defconfig | 1 + configs/igep0020_defconfig | 1 + configs/igep0030_defconfig | 1 + configs/igep0032_defconfig | 1 + configs/imx6qdl_icore_mmc_defconfig | 1 + configs/imx6qdl_icore_nand_defconfig | 1 + configs/imx6qdl_icore_rqs_defconfig | 1 + configs/imx6ul_geam_mmc_defconfig | 1 + configs/imx6ul_geam_nand_defconfig | 1 + configs/imx6ul_isiot_emmc_defconfig | 1 + configs/imx6ul_isiot_mmc_defconfig | 1 + configs/imx6ul_isiot_nand_defconfig | 1 + configs/inet1_defconfig | 1 + configs/inet86dz_defconfig | 1 + configs/inet97fv2_defconfig | 1 + configs/inet98v_rev2_defconfig | 1 + configs/inet9f_rev03_defconfig | 1 + configs/inet_q972_defconfig | 1 + configs/ipam390_defconfig | 1 + configs/jesurun_q5_defconfig | 1 + configs/kc1_defconfig | 1 + configs/kylin-rk3036_defconfig | 2 +- configs/lion-rk3368_defconfig | 96 ++ configs/liteboard_defconfig | 1 + configs/ls1021aiot_sdcard_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021aqds_sdcard_qspi_defconfig | 1 + .../ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig | 1 + configs/ls1043aqds_nand_defconfig | 1 + configs/ls1043aqds_sdcard_ifc_defconfig | 1 + configs/ls1043aqds_sdcard_qspi_defconfig | 1 + configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_nand_defconfig | 1 + configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_sdcard_defconfig | 1 + configs/ls1046aqds_nand_defconfig | 1 + configs/ls1046aqds_sdcard_ifc_defconfig | 1 + configs/ls1046aqds_sdcard_qspi_defconfig | 1 + configs/ls1046ardb_emmc_defconfig | 1 + configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_sdcard_defconfig | 1 + configs/ls2080aqds_nand_defconfig | 1 + configs/ls2080aqds_sdcard_defconfig | 1 + configs/ls2080ardb_nand_defconfig | 1 + configs/m28evk_defconfig | 1 + configs/ma5d4evk_defconfig | 1 + configs/mccmon6_nor_defconfig | 1 + configs/mccmon6_sd_defconfig | 1 + configs/mcx_defconfig | 1 + configs/microblaze-generic_defconfig | 1 + configs/miqi-rk3288_defconfig | 2 +- configs/mixtile_loftq_defconfig | 1 + configs/mk802_a10s_defconfig | 1 + configs/mk802_defconfig | 1 + configs/mk802ii_defconfig | 1 + configs/mt_ventoux_defconfig | 1 + configs/mx23_olinuxino_defconfig | 1 + configs/mx23evk_defconfig | 1 + configs/mx28evk_auart_console_defconfig | 1 + configs/mx28evk_defconfig | 1 + configs/mx28evk_nand_defconfig | 1 + configs/mx28evk_spi_defconfig | 1 + configs/mx31pdk_defconfig | 1 + configs/mx6cuboxi_defconfig | 1 + configs/mx6sabreauto_defconfig | 1 + configs/mx6sabresd_defconfig | 1 + configs/mx6slevk_spl_defconfig | 1 + configs/mx6sxsabresd_spl_defconfig | 1 + configs/mx6ul_14x14_evk_defconfig | 1 + configs/mx6ul_9x9_evk_defconfig | 1 + configs/nanopi_m1_defconfig | 1 + configs/nanopi_m1_plus_defconfig | 1 + configs/nanopi_neo_air_defconfig | 1 + configs/nanopi_neo_defconfig | 1 + configs/novena_defconfig | 1 + configs/omap3_beagle_defconfig | 1 + configs/omap3_evm_defconfig | 1 + configs/omap3_ha_defconfig | 1 + configs/omap3_logic_defconfig | 1 + configs/omap3_overo_defconfig | 1 + configs/omap4_panda_defconfig | 1 + configs/omap4_sdp4430_defconfig | 1 + configs/omap5_uevm_defconfig | 3 +- configs/omapl138_lcdk_defconfig | 1 + configs/opos6uldev_defconfig | 1 + configs/orangepi_2_defconfig | 1 + configs/orangepi_lite_defconfig | 1 + configs/orangepi_one_defconfig | 1 + configs/orangepi_pc_defconfig | 1 + configs/orangepi_pc_plus_defconfig | 1 + configs/orangepi_plus2e_defconfig | 1 + configs/orangepi_plus_defconfig | 1 + configs/orangepi_zero_defconfig | 1 + configs/origen_defconfig | 1 + configs/ot1200_spl_defconfig | 1 + configs/parrot_r16_defconfig | 1 + configs/pcm051_rev1_defconfig | 1 + configs/pcm051_rev3_defconfig | 1 + configs/pcm058_defconfig | 1 + configs/peach-pi_defconfig | 1 + configs/peach-pit_defconfig | 1 + configs/pengwyn_defconfig | 1 + configs/pepper_defconfig | 1 + configs/picosam9g45_defconfig | 1 + configs/platinum_picon_defconfig | 1 + configs/platinum_titanium_defconfig | 1 + configs/polaroid_mid2407pxe03_defconfig | 1 + configs/polaroid_mid2809pxe04_defconfig | 1 + configs/popmetal-rk3288_defconfig | 2 +- configs/pov_protab2_ips9_defconfig | 1 + configs/puma-rk3399_defconfig | 8 +- configs/pxm2_defconfig | 1 + configs/q8_a13_tablet_defconfig | 1 + configs/q8_a23_tablet_800x480_defconfig | 1 + configs/q8_a33_tablet_1024x600_defconfig | 1 + configs/q8_a33_tablet_800x480_defconfig | 1 + configs/qemu-x86_64_defconfig | 1 + configs/r7-tv-dongle_defconfig | 1 + configs/rastaban_defconfig | 1 + configs/rock2_defconfig | 2 +- configs/rock_defconfig | 2 +- configs/rut_defconfig | 1 + configs/sama5d2_xplained_mmc_defconfig | 1 + configs/sama5d3_xplained_mmc_defconfig | 1 + configs/sama5d3xek_mmc_defconfig | 1 + configs/sama5d4_xplained_mmc_defconfig | 1 + configs/sama5d4ek_mmc_defconfig | 1 + configs/sansa_fuze_plus_defconfig | 1 + configs/sc_sps_1_defconfig | 1 + configs/smartweb_defconfig | 1 + configs/smdk5250_defconfig | 1 + configs/smdk5420_defconfig | 1 + configs/smdkv310_defconfig | 1 + configs/sniper_defconfig | 1 + configs/snow_defconfig | 1 + configs/spring_defconfig | 1 + configs/sun8i_a23_evb_defconfig | 1 + configs/sunxi_Gemei_G9_defconfig | 1 + configs/tao3530_defconfig | 1 + configs/thuban_defconfig | 1 + configs/ti814x_evm_defconfig | 1 + configs/ti816x_evm_defconfig | 1 + configs/tinker-rk3288_defconfig | 2 +- configs/topic_miami_defconfig | 1 + configs/topic_miamilite_defconfig | 1 + configs/topic_miamiplus_defconfig | 1 + configs/tricorder_defconfig | 1 + configs/tricorder_flash_defconfig | 1 + configs/ts4600_defconfig | 1 + configs/twister_defconfig | 1 + configs/udoo_defconfig | 1 + configs/udoo_neo_defconfig | 1 + configs/wandboard_defconfig | 1 + configs/woodburn_sd_defconfig | 1 + configs/x600_defconfig | 1 + configs/xfi3_defconfig | 1 + configs/xpress_spl_defconfig | 1 + configs/zc5202_defconfig | 1 + configs/zc5601_defconfig | 1 + configs/zynq_microzed_defconfig | 1 + configs/zynq_picozed_defconfig | 1 + configs/zynq_zc702_defconfig | 1 + configs/zynq_zc706_defconfig | 1 + configs/zynq_zc770_xm010_defconfig | 1 + configs/zynq_zc770_xm011_defconfig | 1 + configs/zynq_zc770_xm012_defconfig | 1 + configs/zynq_zc770_xm013_defconfig | 1 + configs/zynq_zed_defconfig | 1 + configs/zynq_zybo_defconfig | 1 + doc/README.rockchip | 2 +- .../clock/rockchip,rk3368-dmc.txt | 67 ++ drivers/Makefile | 36 +- drivers/clk/Kconfig | 12 +- drivers/clk/Makefile | 2 +- drivers/clk/rockchip/clk_rk3368.c | 302 ++++++- drivers/core/Kconfig | 23 +- drivers/core/Makefile | 4 +- drivers/net/gmac_rockchip.c | 78 ++ drivers/pinctrl/rockchip/pinctrl_rk3368.c | 508 ++++++++++- drivers/ram/Kconfig | 11 +- drivers/ram/Makefile | 2 + drivers/ram/rockchip/Makefile | 7 + drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++ drivers/spi/rk_spi.c | 9 + dts/Kconfig | 29 + include/configs/am335x_evm.h | 2 - include/configs/am335x_igep003x.h | 1 - include/configs/am335x_shc.h | 2 - include/configs/am335x_sl50.h | 2 - include/configs/am3517_crane.h | 1 - include/configs/am3517_evm.h | 1 - include/configs/am43xx_evm.h | 2 - include/configs/apf27.h | 1 - include/configs/at91sam9m10g45ek.h | 1 - include/configs/at91sam9n12ek.h | 1 - include/configs/at91sam9x5ek.h | 1 - include/configs/baltos.h | 2 - include/configs/bav335x.h | 2 - include/configs/bur_am335x_common.h | 1 - include/configs/chiliboard.h | 2 - include/configs/cm_t335.h | 1 - include/configs/cm_t35.h | 1 - include/configs/cm_t43.h | 2 - include/configs/da850evm.h | 1 - include/configs/edminiv2.h | 1 - include/configs/exynos5-common.h | 1 - include/configs/imx6_spl.h | 1 - include/configs/ipam390.h | 1 - include/configs/kc1.h | 2 - include/configs/lion_rk3368.h | 18 + include/configs/ls1021aiot.h | 1 - include/configs/ls1021aqds.h | 2 - include/configs/ls1021atwr.h | 1 - include/configs/ls1043a_common.h | 2 - include/configs/ls1046a_common.h | 2 - include/configs/ls2080a_common.h | 1 - include/configs/ma5d4evk.h | 1 - include/configs/mcx.h | 1 - include/configs/microblaze-generic.h | 2 - include/configs/mx31pdk.h | 1 - include/configs/mxs.h | 1 - include/configs/omap3_evm.h | 1 - include/configs/omapl138_lcdk.h | 1 - include/configs/origen.h | 1 - include/configs/pcm051.h | 2 - include/configs/pengwyn.h | 2 - include/configs/pepper.h | 1 - include/configs/picosam9g45.h | 1 - include/configs/rk3188_common.h | 2 +- include/configs/rk3288_common.h | 2 +- include/configs/rk3368_common.h | 8 + include/configs/rock.h | 2 +- include/configs/rockchip-common.h | 2 +- include/configs/sama5d2_xplained.h | 1 - include/configs/sama5d3_xplained.h | 1 - include/configs/sama5d3xek.h | 1 - include/configs/sama5d4_xplained.h | 1 - include/configs/sama5d4ek.h | 1 - include/configs/siemens-am33x-common.h | 2 - include/configs/smartweb.h | 1 - include/configs/smdkv310.h | 1 - include/configs/sniper.h | 2 - include/configs/sunxi-common.h | 4 - include/configs/tam3517-common.h | 1 - include/configs/tao3530.h | 1 - include/configs/ti814x_evm.h | 1 - include/configs/ti816x_evm.h | 2 - include/configs/ti_omap3_common.h | 1 - include/configs/ti_omap4_common.h | 1 - include/configs/ti_omap5_common.h | 1 - include/configs/tricorder.h | 1 - include/configs/woodburn_sd.h | 1 - include/configs/x600.h | 1 - include/configs/zynq-common.h | 2 - include/dt-bindings/memory/rk3368-dmc.h | 30 + include/linux/kconfig.h | 13 + include/spl.h | 10 + lib/Makefile | 10 +- scripts/Makefile.spl | 19 +- scripts/config_whitelist.txt | 2 - tools/rkcommon.c | 1 + 450 files changed, 3999 insertions(+), 771 deletions(-) create mode 100644 arch/arm/dts/rk3368-lion-u-boot.dtsi create mode 100644 arch/arm/dts/rk3368-lion.dts create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h create mode 100644 arch/arm/mach-rockchip/rk3368-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3368-board-tpl.c delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c create mode 100644 arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds create mode 100644 arch/arm/mach-rockchip/spl-boot-order.c create mode 100644 board/theobroma-systems/lion_rk3368/Kconfig create mode 100644 board/theobroma-systems/lion_rk3368/MAINTAINERS create mode 100644 board/theobroma-systems/lion_rk3368/Makefile create mode 100644 board/theobroma-systems/lion_rk3368/README create mode 100644 board/theobroma-systems/lion_rk3368/fit_spl_atf.its create mode 100644 board/theobroma-systems/lion_rk3368/lion_rk3368.c create mode 100644 common/spl/spl_bootrom.c create mode 100644 configs/lion-rk3368_defconfig create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt create mode 100644 drivers/ram/rockchip/Makefile create mode 100644 drivers/ram/rockchip/dmc-rk3368.c create mode 100644 include/configs/lion_rk3368.h create mode 100644 include/dt-bindings/memory/rk3368-dmc.h
Signature · 1 line
2.1.4
PATCH v3 1/66 spl: add a 'return to bootrom' boot method
Some devices (e.g. the RK3368) have only limited SRAM, but provide support for loading the next boot stage after our SPL performs basic setup (e.g. DRAM).
For target systems like these, we add a boot device BOOTROM that will invoke a board-specific hook to return to the bootrom (if supported).
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Tom Rini <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/spl.h | 1 + common/spl/Kconfig | 11 +++++++++++ common/spl/Makefile | 1 + common/spl/spl_bootrom.c | 27 +++++++++++++++++++++++++++ include/spl.h | 10 ++++++++++ 5 files changed, 50 insertions(+) create mode 100644 common/spl/spl_bootrom.c
arch/arm/include/asm/spl.h +1 -0
@@ -30,6 +30,7 @@ enum {BOOT_DEVICE_BOARD ,BOOT_DEVICE_DFU ,BOOT_DEVICE_XIP , +BOOT_DEVICE_BOOTROM ,BOOT_DEVICE_NONE };#endif
common/spl/Kconfig +11 -0
@@ -25,6 +25,17 @@ config SPL_BOARD_INIT spl_board_init() from board_init_r(). This function should be provided by the board. +config SPL_BOOTROM_SUPPORT + bool "Support returning to the BOOTROM" + help + Some platforms (e.g. the Rockchip RK3368) provide support in their + ROM for loading the next boot-stage after performing basic setup + from the SPL stage. + + Enable this option, to return to the BOOTROM through the + BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the + boot device list, if not implemented for a given board) + config SPL_RAW_IMAGE_SUPPORT bool "Support SPL loading and booting of RAW images" default n if (ARCH_MX6 && (SPL_MMC_SUPPORT || SPL_SATA_SUPPORT))
common/spl/Makefile +1 -0
@@ -10,6 +10,7 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_FRAMEWORK) += spl.o +obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_bootrom.o obj-$(CONFIG_SPL_LOAD_FIT) += spl_fit.o obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o obj-$(CONFIG_SPL_XIP_SUPPORT) += spl_xip.o
common/spl/spl_bootrom.c new file +27 -0
@@ -0,0 +1,27 @@ +/* +* Copyright (C) 2017 Theobroma Systems Design und Consulting GmH +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <spl.h> + +__weak void board_return_to_bootrom (void ) +{ +} + +static int spl_return_to_bootrom (struct spl_image_info *spl_image, +struct spl_boot_device *bootdev) +{ +/* +* If the board implements a way to return to its ROM (with +* the expectation that the next stage of will be booted by +* the ROM), it will implement board_return_to_bootrom() and +* should not return from it. +*/ +board_return_to_bootrom (); +return false; +} + +SPL_LOAD_IMAGE_METHOD ("BOOTROM" ,0 ,BOOT_DEVICE_BOOTROM , spl_return_to_bootrom);
include/spl.h +10 -0
@@ -278,4 +278,14 @@ int spl_mmc_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev);void bl31_entry (void ); + +/** +* board_return_to_bootrom - allow for boards to continue with the boot ROM +* +* If a board (e.g. the Rockchip RK3368 boards) provide some +* supporting functionality for SPL in their boot ROM and the SPL +* stage wants to return to the ROM code to continue booting, boards +* can implement 'board_return_to_bootrom'. +*/ +void board_return_to_bootrom (void );#endif
Signature · 1 line
2.1.4
PATCH v3 2/66 spl: configure 'return to bootrom' separately for SPL and TPL
In reply to Philipp TomsichOn the RK3368, we want our TPL to use the 'return to bootrom' boot method (to have the bootrom load up the SPL stage) and then continue with different boot methods (MMC, SPI, etc.) from SPL.
This adds the config option needed to control the availabily of the 'return to bootrom' boot-method separately for the TPL stage.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
Changes in v3: None
Changes in v2: None
common/spl/Kconfig | 11 +++++++++++ 1 file changed, 11 insertions(+)
common/spl/Kconfig +11 -0
@@ -698,6 +698,17 @@ config TPL if TPL +config TPL_BOOTROM_SUPPORT + bool "Support returning to the BOOTROM (from TPL)" + help + Some platforms (e.g. the Rockchip RK3368) provide support in their + ROM for loading the next boot-stage after performing basic setup + from the TPL stage. + + Enable this option, to return to the BOOTROM through the + BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the + boot device list, if not implemented for a given board) + config TPL_ENV_SUPPORT bool "Support an environment" help
Signature · 1 line
2.1.4
PATCH v3 3/66 rockchip: back-to-bootrom: add 'back-to-bootrom' support for AArch64
In reply to Philipp TomsichThe back-to-bootrom support for Rockchip is equivalent to an (assembly) implementation of setjmp/longjmp (i.e. it saves the stack-pointer, link-register and callee-saved registers). Up until now, this had only been implemented for AArch32 (i.e. ARMv7 or older), which puts the new ARMv8 devices (which boot in AArch64 mode) at a slight disadvantage.
To allow use of the 'back-to-bootrom' feature on new devices (e.g. the RK3368), this commit adds an implementation for AArch64.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/save_boot_param.S | 37 ++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+)
arch/arm/mach-rockchip/save_boot_param.S +37 -0
@@ -1,11 +1,47 @@ /* * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH * * SPDX-License-Identifier: GPL-2.0+ */ #include <linux/linkage.h> +#if defined(CONFIG_ARM64) +.globl SAVE_SP_ADDR +SAVE_SP_ADDR: + .quad 0 + +ENTRY(save_boot_params) + sub sp, sp, #0x100 + stp x29, x30, [sp, #0x50] + stp x27, x28, [sp, #0x40] + stp x25, x26, [sp, #0x30] + stp x23, x24, [sp, #0x20] + stp x21, x22, [sp, #0x10] + stp x19, x20, [sp, #0] + ldr x8, =SAVE_SP_ADDR + mov x9, sp + str x9, [x8] + b save_boot_params_ret /* back to my caller */ +ENDPROC(save_boot_params) + +.globl _back_to_bootrom_s +ENTRY(_back_to_bootrom_s) + ldr x0, =SAVE_SP_ADDR + ldr x0, [x0] + mov sp, x0 + ldp x29, x30, [sp, #0x50] + ldp x27, x28, [sp, #0x40] + ldp x25, x26, [sp, #0x30] + ldp x23, x24, [sp, #0x20] + ldp x21, x22, [sp, #0x10] + ldp x19, x20, [sp] + add sp, sp, #0x100 + mov x0, xzr + ret +ENDPROC(_back_to_bootrom_s) +#else .globl SAVE_SP_ADDR SAVE_SP_ADDR: .word 0
@@ -30,3 +66,4 @@ ENTRY(_back_to_bootrom_s) mov r0, #0 pop {r1-r12, pc} ENDPROC(_back_to_bootrom_s) +#endif
Signature · 1 line
2.1.4
PATCH v3 4/66 rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL
In reply to Philipp TomsichThe back-to-bootrom option is rather unfortunately named
CONFIG_ROCKCHIP_SPL_BACK_TO_BOOTROM
instead of
CONFIG_SPL_ROCKCHIP_BACK_TO_BOOTROM
To make is selectable through CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BOOTROM), we need to rename it. At the same time, we introduce a TPL_ variant of the option to give us finer-grained control over when it should be used.
This change is motivated by our RK3368 boot process, which returns to the boot ROM only from the TPL stage, but not from the SPL stage.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/Kconfig | 15 +++++++++++++-- arch/arm/mach-rockchip/rk3188-board-spl.c | 5 ++--- arch/arm/mach-rockchip/rk3188-board.c | 2 +- arch/arm/mach-rockchip/rk3288-board-spl.c | 4 ++-- arch/arm/mach-rockchip/rk3288-board.c | 4 ++-- arch/arm/mach-rockchip/rk3399-board-spl.c | 4 ++-- configs/evb-rk3288_defconfig | 2 +- configs/fennec-rk3288_defconfig | 2 +- configs/firefly-rk3288_defconfig | 2 +- configs/miqi-rk3288_defconfig | 2 +- configs/popmetal-rk3288_defconfig | 2 +- configs/rock2_defconfig | 2 +- configs/rock_defconfig | 2 +- configs/tinker-rk3288_defconfig | 2 +- doc/README.rockchip | 2 +- include/configs/rk3188_common.h | 2 +- include/configs/rk3288_common.h | 2 +- include/configs/rock.h | 2 +- include/configs/rockchip-common.h | 2 +- 19 files changed, 35 insertions(+), 25 deletions(-)
arch/arm/mach-rockchip/Kconfig +13 -2
@@ -101,10 +101,21 @@ config ROCKCHIP_RV1108 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 and a DSP. -config ROCKCHIP_SPL_BACK_TO_BROM +config SPL_ROCKCHIP_BACK_TO_BROM bool "SPL returns to bootrom" default y if ROCKCHIP_RK3036 select ROCKCHIP_BROM_HELPER + depends on SPL + help + Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, + SPL will return to the boot rom, which will then load the U-Boot + binary to keep going on. + +config TPL_ROCKCHIP_BACK_TO_BROM + bool "TPL returns to bootrom" + default y if ROCKCHIP_RK3368 + select ROCKCHIP_BROM_HELPER + depends on TPL help Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, SPL will return to the boot rom, which will then load the U-Boot
@@ -122,7 +133,7 @@ config ROCKCHIP_BROM_HELPER bool config SPL_MMC_SUPPORT - default y if !ROCKCHIP_SPL_BACK_TO_BROM + default y if !SPL_ROCKCHIP_BACK_TO_BROM source "arch/arm/mach-rockchip/rk3036/Kconfig" source "arch/arm/mach-rockchip/rk3188/Kconfig"
arch/arm/mach-rockchip/rk3188-board-spl.c +2 -3
@@ -167,8 +167,7 @@ void board_init_f(ulong dummy) }setup_arm_clock (); - -#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM ) && !defined(CONFIG_SPL_BOARD_INIT ) +#if CONFIG_IS_ENABLED (ROCKCHIP_BACK_TO_BROM ) && !defined(CONFIG_SPL_BOARD_INIT )back_to_bootrom ();#endif }
@@ -229,7 +228,7 @@ void spl_board_init(void) }preloader_console_init (); -#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#if CONFIG_IS_ENABLED (ROCKCHIP_BACK_TO_BROM )back_to_bootrom ();#endif return ;
arch/arm/mach-rockchip/rk3188-board.c +1 -1
@@ -39,7 +39,7 @@ int board_late_init(void)int board_init (void ) { -#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM ) +#if CONFIG_IS_ENABLED (ROCKCHIP_BACK_TO_BROM )struct udevice *pinctrl;int ret;
arch/arm/mach-rockchip/rk3288-board-spl.c +2 -2
@@ -249,7 +249,7 @@ void board_init_f(ulong dummy)debug ("DRAM init failed: %d\n" , ret);return ; } -#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM ) && !defined(CONFIG_SPL_BOARD_INIT ) +#if CONFIG_IS_ENABLED (ROCKCHIP_BACK_TO_BROM ) && !defined(CONFIG_SPL_BOARD_INIT )back_to_bootrom ();#endif }
@@ -316,7 +316,7 @@ void spl_board_init(void) }preloader_console_init (); -#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#if CONFIG_IS_ENABLED (ROCKCHIP_BACK_TO_BROM )back_to_bootrom ();#endif return ;
arch/arm/mach-rockchip/rk3288-board.c +2 -2
@@ -78,7 +78,7 @@ int board_late_init(void)return rk_board_late_init (); } -#ifndef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#if CONFIG_IS_ENABLED (ROCKCHIP_BACK_TO_BROM )static int veyron_init (void ) {struct udevice *dev;
@@ -115,7 +115,7 @@ static int veyron_init(void)int board_init (void ) { -#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#if CONFIG_IS_ENABLED (ROCKCHIP_BACK_TO_BROM )struct udevice *pinctrl;int ret;
arch/arm/mach-rockchip/rk3399-board-spl.c +2 -2
@@ -28,7 +28,7 @@DECLARE_GLOBAL_DATA_PTR ; -#if defined(CONFIG_SPL_BUILD ) && defined(CONFIG_SPL_OF_CONTROL ) +#if CONFIG_IS_ENABLED (OF_CONTROL )static int spl_node_to_boot_device (int node) {struct udevice *parent;
@@ -263,7 +263,7 @@ void spl_board_init(void) }preloader_console_init (); -#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#if CONFIG_IS_ENABLED (ROCKCHIP_BACK_TO_BROM )back_to_bootrom ();#endif
configs/evb-rk3288_defconfig +1 -1
@@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y -CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_EVB_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb"
configs/fennec-rk3288_defconfig +1 -1
@@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y -CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_FENNEC_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-fennec"
configs/firefly-rk3288_defconfig +1 -1
@@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y -CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_FIREFLY_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
configs/miqi-rk3288_defconfig +1 -1
@@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y -CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_MIQI_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-miqi"
configs/popmetal-rk3288_defconfig +1 -1
@@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y -CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_POPMETAL_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-popmetal"
configs/rock2_defconfig +1 -1
@@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y -CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_ROCK2=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock2-square"
configs/rock_defconfig +1 -1
@@ -4,7 +4,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3188=y -CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_ROCK=y CONFIG_SPL_STACK_R_ADDR=0x60080000 CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
configs/tinker-rk3288_defconfig +1 -1
@@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y -CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_TINKER_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker"
doc/README.rockchip +1 -1
@@ -130,7 +130,7 @@ load a second-level bootloader(ie. U-BOOT) as soon as it returns to bootrom. Therefore RK3288 has another loading sequence like RK3036. The option of U-Boot is controlled with this setting in U-Boot: - #define CONFIG_ROCKCHIP_SPL_BACK_TO_BROM + #define CONFIG_SPL_ROCKCHIP_BACK_TO_BROM You can create the image via the following operations:
include/configs/rk3188_common.h +1 -1
@@ -26,7 +26,7 @@#define CONFIG_SYS_NS16550_MEM32 -#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ #define CONFIG_SYS_TEXT_BASE 0x60000000#else
include/configs/rk3288_common.h +1 -1
@@ -24,7 +24,7 @@#define CONFIG_SPL_FRAMEWORK #define CONFIG_SYS_NS16550_MEM32 -#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM /* Bootrom will load u-boot binary to 0x0 once return from SPL */ #define CONFIG_SYS_TEXT_BASE 0x00000000#else
include/configs/rock.h +1 -1
@@ -12,7 +12,7 @@#define CONFIG_SYS_MMC_ENV_DEV 0 -#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM /* SPL @ 32k for 34k * u-boot directly after @ 68k for 400k or so * ENV @ 992k
include/configs/rockchip-common.h +1 -1
@@ -47,7 +47,7 @@#endif #if !defined(CONFIG_ENV_OFFSET ) -#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM /* SPL @ 32k for 34k * u-boot directly after @ 68k for 400k or so * ENV @ 992k
Signature · 1 line
2.1.4
PATCH v3 5/66 rockchip: back-to-bootrom: simplify the #ifdef-check for LIBGENERIC in TPL/SPL
In reply to Philipp TomsichWith the finer-grained control over LIBGENERIC_SUPPORT for TPL/SPL (i.e. with the newly introduced distinction between TPL_LIBGENERIC_SUPPORT and SPL_LIBGENERIC_SUPPORT), we can simplify the #ifdef-check to simply use CONFIG_IS_ENABELD.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/bootrom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/mach-rockchip/bootrom.c +2 -2
@@ -9,8 +9,8 @@void back_to_bootrom (void ) { -#if defined(CONFIG_SPL_LIBCOMMON_SUPPORT ) && !defined(CONFIG_TPL_BUILD ) -puts ("Returning to boot ROM..." ); +#if CONFIG_IS_ENABLED (LIBGENERIC_SUPPORT ) +printf ("Returning to boot ROM...\n" );#endif _back_to_bootrom_s (); }
Signature · 1 line
2.1.4
PATCH v3 5/66 rockchip: back-to-bootrom: simplify the #ifdef-check for LIBGENERIC in TPL/SPL
Hi Philipp:
2017-07-29 3:21 GMT+08:00 Philipp Tomsich <
[email protected]>:
Quoted 23 lines
With the finer-grained control over
LIBGENERIC_SUPPORTfor TPL/SPL (i.e. with the newly introduced distinction betweenTPL_LIBGENERIC_SUPPORTandSPL_LIBGENERIC_SUPPORT), we can simplify the #ifdef-check to simply useCONFIG_IS_ENABELD.Signed-off-by Philipp Tomsich <[email protected]>Reviewed-by Simon Glass <[email protected]>Reviewed-by Tom Rini <[email protected]>---
Changes in v3: None
Changes in v2: Nonearch/arm/mach-rockchip/bootrom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)arch/arm/mach-rockchip/ renamed from arch/arm/mach-rockchip/bootrom.c +0
-0
bootrom.c
index 4ca9962..4d38ed6 100644
arch/arm/mach-rockchip/bootrom.c line 14
Quoted 8 lines
arch/arm/mach-rockchip/bootrom.c +2
-2@@ -9,8 +9,8 @@void back_to_bootrom (void ) { -#if defined(CONFIG_SPL_LIBCOMMON_SUPPORT ) && !defined(CONFIG_TPL_BUILD ) -puts ("Returning to boot ROM..." ); +#if CONFIG_IS_ENABLED (LIBGENERIC_SUPPORT ) +printf ("Returning to boot ROM...\n" );
We need to use puts here, or the code size will increase too much for sram limited platform, like RK3036
Quoted 11 lines
arch/arm/mach-rockchip/bootrom.c +0
-0#endif _back_to_bootrom_s ();}
--
2.1.4_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
https://lists.denx.de/listinfo/u-boot
PATCH v3 6/66 spl: adapts SYS_MALLOC_F_LEN for TPL
In reply to Philipp TomsichThe (upstream) changes to break up SYS_MALLOC_F_LEN for the full U-Boot and the SPL stage, break TPL (if simple malloc is enabled in TPL).
This adds support for a TPL-variant of SYS_MALLOC_F_LEN:
- adds TPL_SYS_MALLOC_F_LEN
- rewrites a test for CONFIG_SPL_SYS_MALLOC_F_LEN to access CONFIG_VAL(SYS_MALLOC_F_LEN)
Signed-off-by Philipp Tomsich <[email protected]>
Version-changes: 3
- (new patch) adds changes to SYS_MALLOC_F_LEN for TPL to fix breakage from rebasing to u-boot-rockchip/master
---
Changes in v3: None
Changes in v2: None
Kconfig | 12 +++++++++++- common/spl/spl.c | 2 +- 2 files changed, 12 insertions(+), 2 deletions(-)
Kconfig +11 -1
@@ -96,7 +96,17 @@ config SYS_MALLOC_F_LEN initial serial device and any others that are needed. config SPL_SYS_MALLOC_F_LEN - hex "Size of malloc() pool in spl before relocation" + hex "Size of malloc() pool in SPL before relocation" + depends on SYS_MALLOC_F + default SYS_MALLOC_F_LEN + help + Before relocation, memory is very limited on many platforms. Still, + we can provide a small malloc() pool if needed. Driver model in + particular needs this to operate, so that it can allocate the + initial serial device and any others that are needed. + +config TPL_SYS_MALLOC_F_LEN + hex "Size of malloc() pool in TPL before relocation" depends on SYS_MALLOC_F default SYS_MALLOC_F_LEN help
common/spl/spl.c +1 -1
@@ -487,7 +487,7 @@ ulong spl_relocate_stack_gd(void)gd_t *new_gd;ulong ptr =CONFIG_SPL_STACK_R_ADDR ; -#if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE ) &&CONFIG_SPL_SYS_MALLOC_F_LEN +#if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE ) &&CONFIG_VAL (SYS_MALLOC_F_LEN )if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN ) { ptr -=CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN ; gd->malloc_base = ptr;
Signature · 1 line
2.1.4
PATCH v3 6/66 spl: adapts SYS_MALLOC_F_LEN for TPL
Quoted 15 lines · Philipp Tomsich
The (upstream) changes to break up
SYS_MALLOC_F_LENfor the full U-Boot and the SPL stage, break TPL (if simple malloc is enabled in TPL).This adds support for a TPL-variant of
SYS_MALLOC_F_LEN:
- addsTPL_SYS_MALLOC_F_LEN
- rewrites a test forCONFIG_SPL_SYS_MALLOC_F_LENto accessCONFIG_VAL(SYS_MALLOC_F_LEN)Signed-off-by Philipp Tomsich <[email protected]>Version-changes: 3
- (new patch) adds changes toSYS_MALLOC_F_LENfor TPL to fix breakage from rebasing to u-boot-rockchip/master
Quoted 8 lines
---
Changes in v3: None
Changes in v2: NoneKconfig | 12 +++++++++++- common/spl/spl.c | 2 +- 2 files changed, 12 insertions(+), 2 deletions(-)
Reviewed-by Simon Glass <[email protected]>
PATCH v3 7/66 spl: dm: Kconfig: fix help text for SPL/TPL confusion
In reply to Philipp TomsichTPL_NAND_SUPPORT, TPL_SERIAL_SUPPORT, TPL_SPI_FLASH_SUPPORT and TPL_SPI_SUPPORT refer to SPL in their help text. This fixes up the description to correctly reference TPL.
Signed-off-by Philipp Tomsich <[email protected]>
---
Changes in v3:
- (new patch) added fix-up of SPL/TPL confusion in help text
Changes in v2: None
common/spl/Kconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
common/spl/Kconfig +5 -5
@@ -717,7 +717,7 @@ config TPL_ENV_SUPPORT config TPL_I2C_SUPPORT bool "Support I2C" help - Enable support for the I2C bus in SPL. See SPL_I2C_SUPPORT for + Enable support for the I2C bus in TPL. See SPL_I2C_SUPPORT for details. config TPL_LIBCOMMON_SUPPORT
@@ -747,24 +747,24 @@ config TPL_MMC_SUPPORT config TPL_NAND_SUPPORT bool "Support NAND flash" help - Enable support for NAND in SPL. See SPL_NAND_SUPPORT for details. + Enable support for NAND in TPL. See SPL_NAND_SUPPORT for details. config TPL_SERIAL_SUPPORT bool "Support serial" help - Enable support for serial in SPL. See SPL_SERIAL_SUPPORT for + Enable support for serial in TPL. See SPL_SERIAL_SUPPORT for details. config TPL_SPI_FLASH_SUPPORT bool "Support SPI flash drivers" help - Enable support for using SPI flash in SPL. See SPL_SPI_FLASH_SUPPORT + Enable support for using SPI flash in TPL. See SPL_SPI_FLASH_SUPPORT for details. config TPL_SPI_SUPPORT bool "Support SPI drivers" help - Enable support for using SPI in SPL. See SPL_SPI_SUPPORT for + Enable support for using SPI in TPL. See SPL_SPI_SUPPORT for details. endif # TPL
Signature · 1 line
2.1.4
PATCH v3 7/66 spl: dm: Kconfig: fix help text for SPL/TPL confusion
Quoted 8 lines · Philipp Tomsich
TPL_NAND_SUPPORT,TPL_SERIAL_SUPPORT,TPL_SPI_FLASH_SUPPORTandTPL_SPI_SUPPORTrefer to SPL in their help text. This fixes up the description to correctly reference TPL.Signed-off-by Philipp Tomsich <[email protected]>---
Quoted 7 lines
Changes in v3:
- (new patch) added fix-up of SPL/TPL confusion in help textChanges in v2: None
common/spl/Kconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
Reviewed-by Simon Glass <[email protected]>
PATCH v3 8/66 spl: dm: Kconfig: use more specific prereqs for SPL_REGMAP and SPL_SYSCON
In reply to Philipp TomsichSPL_REGMAP and SPL_SYSCON were marked as depending on DM, when a stricter dependency of SPL_DM was possible. This commit makes the prereq more specific.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
Changes in v3: None
Changes in v2: None
drivers/core/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/core/Kconfig +2 -2
@@ -97,7 +97,7 @@ config REGMAP config SPL_REGMAP bool "Support register maps in SPL" - depends on DM + depends on SPL_DM help Hardware peripherals tend to have one or more sets of registers which can be accessed to control the hardware. A register map
@@ -116,7 +116,7 @@ config SYSCON config SPL_SYSCON bool "Support system controllers in SPL" - depends on REGMAP + depends on SPL_REGMAP help Many SoCs have a number of system controllers which are dealt with as a group by a single driver. Some common functionality is provided
Signature · 1 line
2.1.4
PATCH v3 9/66 spl: dm: Kconfig: split REGMAP/SYSCON support for TPL from SPL
In reply to Philipp TomsichThis change introduces TPL variants of the REGMAP and SYSCON config options (i.e. TPL_REGMAP and TPL_SYSCON in analogy to SPL_REGMAP and SPL_SYSCON) in preparation of a finer-grained feature selection for building feature-rich TPL variants.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
Changes in v3: None
Changes in v2: None
drivers/core/Kconfig | 19 +++++++++++++++++++ drivers/core/Makefile | 4 ++-- 2 files changed, 21 insertions(+), 2 deletions(-)
drivers/core/Kconfig +19 -0
@@ -105,6 +105,16 @@ config SPL_REGMAP support any bus type (I2C, SPI) but so far this only supports direct memory access. +config TPL_REGMAP + bool "Support register maps in TPL" + depends on TPL_DM + help + Hardware peripherals tend to have one or more sets of registers + which can be accessed to control the hardware. A register map + models this with a simple read/write interface. It can in principle + support any bus type (I2C, SPI) but so far this only supports + direct memory access. + config SYSCON bool "Support system controllers" depends on REGMAP
@@ -123,6 +133,15 @@ config SPL_SYSCON by this uclass, including accessing registers via regmap and assigning a unique number to each. +config TPL_SYSCON + bool "Support system controllers in TPL" + depends on TPL_REGMAP + help + Many SoCs have a number of system controllers which are dealt with + as a group by a single driver. Some common functionality is provided + by this uclass, including accessing registers via regmap and + assigning a unique number to each. + config DEVRES bool "Managed device resources" depends on DM
drivers/core/Makefile +2 -2
@@ -9,8 +9,8 @@ obj-$(CONFIG_DEVRES) += devres.o obj-$(CONFIG_$(SPL_)DM_DEVICE_REMOVE) += device-remove.o obj-$(CONFIG_$(SPL_)SIMPLE_BUS) += simple-bus.o obj-$(CONFIG_DM) += dump.o -obj-$(CONFIG_$(SPL_)REGMAP) += regmap.o -obj-$(CONFIG_$(SPL_)SYSCON) += syscon-uclass.o +obj-$(CONFIG_$(SPL_TPL_)REGMAP) += regmap.o +obj-$(CONFIG_$(SPL_TPL_)SYSCON) += syscon-uclass.o obj-$(CONFIG_OF_LIVE) += of_access.o of_addr.o ifndef CONFIG_DM_DEV_READ_INLINE obj-$(CONFIG_OF_CONTROL) += read.o
Signature · 1 line
2.1.4
PATCH v3 10/66 spl: dm: Kconfig: SPL_RAM depends on SPL_DM
In reply to Philipp TomsichThis commit models the dependency from SPL_RAM to SPL_DM in Kconfig.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
Changes in v3: None
Changes in v2: None
drivers/ram/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/ram/Kconfig +1 -1
@@ -10,7 +10,7 @@ config RAM config SPL_RAM bool "Enable RAM support in SPL" - depends on RAM + depends on RAM && SPL_DM help The RAM subsystem adds a small amount of overhead to the image. If this is acceptable and you have a need to use RAM drivers in
Signature · 1 line
2.1.4
PATCH v3 11/66 spl: dm: Kconfig: introduce TPL_RAM (in analogy to SPL_RAM)
In reply to Philipp TomsichTo allow finer grained selection of features for TPL, we introduce TPL_RAM (in analogy to SPL_RAM).
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
Changes in v3: None
Changes in v2: None
drivers/ram/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+)
drivers/ram/Kconfig +9 -0
@@ -17,6 +17,15 @@ config SPL_RAM SPL, enable this option. It might provide a cleaner interface to setting up RAM (e.g. SDRAM / DDR) within SPL. +config TPL_RAM + bool "Enable RAM support in SPL" + depends on RAM && TPL_DM + help + The RAM subsystem adds a small amount of overhead to the image. + If this is acceptable and you have a need to use RAM drivers in + TPL, enable this option. It might provide a cleaner interface to + setting up RAM (e.g. SDRAM / DDR) within TPL. + config STM32_SDRAM bool "Enable STM32 SDRAM support" depends on RAM
Signature · 1 line
2.1.4
PATCH v3 12/66 spl: dm: Kconfig: SPL_CLK depends on SPL_DM
In reply to Philipp TomsichSPL_CLK should also depend on SPL_DM (and not just on CLK). Add the additional dependency.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
Changes in v3: None
Changes in v2: None
drivers/clk/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/Kconfig +1 -1
@@ -12,7 +12,7 @@ config CLK config SPL_CLK bool "Enable clock support in SPL" - depends on CLK + depends on CLK && SPL_DM help The clock subsystem adds a small amount of overhead to the image. If this is acceptable and you have a need to use clock drivers in
Signature · 1 line
2.1.4
PATCH v3 13/66 spl: dm: Kconfig: split CLK support for SPL and TPL
In reply to Philipp TomsichIntroduce TPL_CLK to allow finer-grained selection of TPL features for feature-rich (i.e. DM-based) TPL stages.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
Changes in v3: None
Changes in v2: None
drivers/clk/Kconfig | 10 ++++++++++ drivers/clk/Makefile | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-)
drivers/clk/Kconfig +10 -0
@@ -20,6 +20,16 @@ config SPL_CLK setting up clocks within SPL, and allows the same drivers to be used as U-Boot proper. +config TPL_CLK + bool "Enable clock support in TPL" + depends on CLK && TPL_DM + help + The clock subsystem adds a small amount of overhead to the image. + If this is acceptable and you have a need to use clock drivers in + SPL, enable this option. It might provide a cleaner interface to + setting up clocks within TPL, and allows the same drivers to be + used as U-Boot proper. + config CLK_BCM6345 bool "Clock controller driver for BCM6345" depends on CLK && ARCH_BMIPS
drivers/clk/Makefile +1 -1
@@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_CLK) += clk-uclass.o clk_fixed_rate.o +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_SANDBOX) += clk_sandbox.o obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
Signature · 1 line
2.1.4
PATCH v3 14/66 spl: dm: Kconfig: split OF_CONTROL and OF_PLATDATA between SPL and TPL
In reply to Philipp TomsichFor the RK3368, we want to use OF_PLATDATA in TPL, but full OF_CONTROL in SPL: this requires the introduction of a new family of configuration options to decouple SPL_OF_CONTROL and SPL_OF_PLATDATA from TPL.
Consequently, Makefile.spl needs to be adjusted to test for these configuration items through the $(SPL_TPL_) macro instead of hard-coding the SPL variant.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
Changes in v3: None
Changes in v2: None
Makefile | 2 +- dts/Kconfig | 29 +++++++++++++++++++++++++++++ scripts/Makefile.spl | 4 ++-- 3 files changed, 32 insertions(+), 3 deletions(-)
Makefile +1 -1
@@ -1398,7 +1398,7 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE spl/u-boot-spl.bin: spl/u-boot-spl @: spl/u-boot-spl: tools prepare \ - $(if $(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) + $(if $(CONFIG_OF_SEPARATE)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),dts/dt.dtb) $(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.spl all spl/sunxi-spl.bin: spl/u-boot-spl
dts/Kconfig +29 -0
@@ -32,6 +32,14 @@ config SPL_OF_CONTROL which is not enough to support device tree. Enable this option to allow such boards to be supported by U-Boot SPL. +config TPL_OF_CONTROL + bool "Enable run-time configuration via Device Tree in TPL" + depends on TPL && OF_CONTROL + help + Some boards use device tree in U-Boot but only have 4KB of SRAM + which is not enough to support device tree. Enable this option to + allow such boards to be supported by U-Boot TPL. + config OF_LIVE bool "Enable use of a live tree" depends on OF_CONTROL
@@ -136,4 +144,25 @@ config SPL_OF_PLATDATA declarations for each node. See README.platdata for more information. +config TPL_OF_PLATDATA + bool "Generate platform data for use in TPL" + depends on TPL_OF_CONTROL + help + For very constrained SPL environments the overhead of decoding + device tree nodes and converting their contents into platform data + is too large. This overhead includes libfdt code as well as the + device tree contents itself. The latter is fairly compact, but the + former can add 3KB or more to a Thumb 2 Image. + + This option enables generation of platform data from the device + tree as C code. This code creates devices using U_BOOT_DEVICE() + declarations. The benefit is that it allows driver code to access + the platform data directly in C structures, avoidin the libfdt + overhead. + + This option works by generating C structure declarations for each + compatible string, then adding platform data and U_BOOT_DEVICE + declarations for each node. See README.platdata for more + information. + endmenu
scripts/Makefile.spl +2 -2
@@ -98,7 +98,7 @@ endif u-boot-spl-init := $(head-y) u-boot-spl-main := $(libs-y) -ifdef CONFIG_SPL_OF_PLATDATA +ifdef CONFIG_$(SPL_TPL_)OF_PLATDATA u-boot-spl-platdata := $(obj)/dts/dt-platdata.o endif
@@ -202,7 +202,7 @@ cmd_cat = cat $(filter-out $(PHONY), $^) > $@ quiet_cmd_copy = COPY $@ cmd_copy = cp $< $@ -ifeq ($(CONFIG_SPL_OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),yy) +ifeq ($(CONFIG_$(SPL_TPL_)OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy) $(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin \ $(if $(CONFIG_SPL_SEPARATE_BSS),,$(obj)/$(SPL_BIN)-pad.bin) \ $(obj)/$(SPL_BIN).dtb FORCE
Signature · 1 line
2.1.4
PATCH v3 15/66 spl: dm: use CONFIG_IS_ENABLED to test for the DM option
In reply to Philipp TomsichEven though there's now a TPL_DM configuration option, the spl logic still checks for SPL_DM and thus does not pick up the proper config option.
This introduces the use of CONFIG_IS_ENABLED(DM) in spl.c to always pick up the desired configuration option instead of having a hard-coded check for the SPL variant.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
Changes in v3: None
Changes in v2: None
common/spl/spl.c | 5 +++-- include/linux/kconfig.h | 13 +++++++++++++ 2 files changed, 16 insertions(+), 2 deletions(-)
common/spl/spl.c +3 -2
@@ -6,6 +6,7 @@* * SPDX-License-Identifier: GPL-2.0+ */ +#include <common.h> #include <dm.h> #include <spl.h>
@@ -243,7 +244,7 @@ static int spl_common_init(bool setup_malloc)return ret; } } -if (IS_ENABLED (CONFIG_SPL_DM )) { +if (CONFIG_IS_ENABLED (DM )) {bootstage_start (BOOTSTATE_ID_ACCUM_DM_SPL ,"dm_spl" );/* With CONFIG_SPL_OF_PLATDATA, bring in all devices */ ret =dm_init_and_scan (!CONFIG_IS_ENABLED (OF_PLATDATA ));
@@ -425,7 +426,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) gd->malloc_ptr / 1024);#endif -if (IS_ENABLED (CONFIG_SPL_ATF_SUPPORT )) { +if (CONFIG_IS_ENABLED (ATF_SUPPORT )) {debug ("loaded - jumping to U-Boot via ATF BL31.\n" );bl31_entry (); }
include/linux/kconfig.h +13 -0
@@ -51,12 +51,25 @@#define _IS_SPL 1#endif +#ifdef CONFIG_TPL_BUILD +#define _IS_TPL 1 +#endif + +#if defined(CONFIG_TPL_BUILD ) +#define config_val (cfg) _config_val(_IS_TPL, cfg) +#define _config_val (x, cfg) __config_val(x, cfg) +#define __config_val (x, cfg) ___config_val(__ARG_PLACEHOLDER_##x, cfg) +#define ___config_val (arg1_or_junk, cfg) \ + ____config_val(arg1_or_junk CONFIG_TPL_##cfg, CONFIG_##cfg) +#define ____config_val (__ignored, val, ...) val +#else #define config_val (cfg) _config_val(_IS_SPL, cfg)#define _config_val (x, cfg) __config_val(x, cfg)#define __config_val (x, cfg) ___config_val(__ARG_PLACEHOLDER_##x, cfg)#define ___config_val (arg1_or_junk, cfg) \ ____config_val(arg1_or_junk CONFIG_SPL_##cfg, CONFIG_##cfg)#define ____config_val (__ignored, val, ...) val +#endif /* * CONFIG_VAL(FOO) evaluates to the value of
Signature · 1 line
2.1.4
PATCH v3 16/66 armv8: move low-level assembly functions into function-sections
In reply to Philipp TomsichTPL builds today don't need to call into firmware or set up the MMU (if this changes, it should be controlled through a config option whether to include this or not), but include the needed support code for this anyway. By moving these unused low-level functions into seperate function-sections, the linker can garbage-collect the unused sections.
Note that (if DM support is enabled), there will be a call to the cache-flushing code from alloc_priv(...) in drivers/core/device.c. This then add 52 bytes of binary size (an increase from 20589 to 20641 bytes) compared to completely removing this code.
Even for a feature-rich TPL (including DM support as for the RK3368), this equates to a size difference of significantly more than 10% in TPL binary size.
Signed-off-by Philipp Tomsich <[email protected]>
---
Changes in v3:
- change to use function-sections (instead of disabling at the Makefile-level for TPL builds) per Tom's suggestion
Changes in v2: None
arch/arm/cpu/armv8/Makefile | 2 +- arch/arm/cpu/armv8/cache.S | 22 ++++++++++++++++++++++ arch/arm/cpu/armv8/tlb.S | 4 +++- arch/arm/cpu/armv8/transition.S | 6 ++++++ 4 files changed, 32 insertions(+), 2 deletions(-)
arch/arm/cpu/armv8/Makefile +1 -1
@@ -10,11 +10,11 @@ extra-y := start.o obj-y += cpu.o obj-y += generic_timer.o obj-y += cache_v8.o -obj-y += exceptions.o obj-y += cache.o obj-y += tlb.o obj-y += transition.o obj-y += fwcall.o +obj-y += exceptions.o obj-y += cpu-dt.o obj-$(CONFIG_ARM_SMCCC) += smccc-call.o
arch/arm/cpu/armv8/cache.S +22 -0
@@ -22,6 +22,7 @@ * x1: 0 clean & invalidate, 1 invalidate only * x2~x9: clobbered */ +.pushsection .text.__asm_dcache_level, "ax" ENTRY(__asm_dcache_level) lsl x12, x0, #1 msr csselr_el1, x12 /* select cache level */
@@ -58,6 +59,7 @@ loop_way: ret ENDPROC(__asm_dcache_level) +.popsection /* * void __asm_flush_dcache_all(int invalidate_only)
@@ -66,6 +68,7 @@ ENDPROC(__asm_dcache_level) * * flush or invalidate all data cache by SET/WAY. */ +.pushsection .text.__asm_dcache_all, "ax" ENTRY(__asm_dcache_all) mov x1, x0 dsb sy
@@ -102,16 +105,21 @@ skip: finished: ret ENDPROC(__asm_dcache_all) +.popsection +.pushsection .text.__asm_flush_dcache_all, "ax" ENTRY(__asm_flush_dcache_all) mov x0, #0 b __asm_dcache_all ENDPROC(__asm_flush_dcache_all) +.popsection +.pushsection .text.__asm_invalidate_dcache_all, "ax" ENTRY(__asm_invalidate_dcache_all) mov x0, #0x1 b __asm_dcache_all ENDPROC(__asm_invalidate_dcache_all) +.popsection /* * void __asm_flush_dcache_range(start, end)
@@ -121,6 +129,7 @@ ENDPROC(__asm_invalidate_dcache_all) * x0: start address * x1: end address */ +.pushsection .text.__asm_flush_dcache_range, "ax" ENTRY(__asm_flush_dcache_range) mrs x3, ctr_el0 lsr x3, x3, #16
@@ -138,6 +147,7 @@ ENTRY(__asm_flush_dcache_range) dsb sy ret ENDPROC(__asm_flush_dcache_range) +.popsection /* * void __asm_invalidate_dcache_range(start, end) *
@@ -146,6 +156,7 @@ ENDPROC(__asm_flush_dcache_range) * x0: start address * x1: end address */ +.pushsection .text.__asm_invalidate_dcache_range, "ax" ENTRY(__asm_invalidate_dcache_range) mrs x3, ctr_el0 ubfm x3, x3, #16, #19
@@ -162,41 +173,51 @@ ENTRY(__asm_invalidate_dcache_range) dsb sy ret ENDPROC(__asm_invalidate_dcache_range) +.popsection /* * void __asm_invalidate_icache_all(void) * * invalidate all tlb entries. */ +.pushsection .text.__asm_invalidate_icache_all, "ax" ENTRY(__asm_invalidate_icache_all) ic ialluis isb sy ret ENDPROC(__asm_invalidate_icache_all) +.popsection +.pushsection .text.__asm_invalidate_l3_dcache, "ax" ENTRY(__asm_invalidate_l3_dcache) mov x0, #0 /* return status as success */ ret ENDPROC(__asm_invalidate_l3_dcache) .weak __asm_invalidate_l3_dcache +.popsection +.pushsection .text.__asm_flush_l3_dcache, "ax" ENTRY(__asm_flush_l3_dcache) mov x0, #0 /* return status as success */ ret ENDPROC(__asm_flush_l3_dcache) .weak __asm_flush_l3_dcache +.popsection +.pushsection .text.__asm_invalidate_l3_icache, "ax" ENTRY(__asm_invalidate_l3_icache) mov x0, #0 /* return status as success */ ret ENDPROC(__asm_invalidate_l3_icache) .weak __asm_invalidate_l3_icache +.popsection /* * void __asm_switch_ttbr(ulong new_ttbr) * * Safely switches to a new page table. */ +.pushsection .text.__asm_switch_ttbr, "ax" ENTRY(__asm_switch_ttbr) /* x2 = SCTLR (alive throghout the function) */ switch_el x4, 3f, 2f, 1f
@@ -244,3 +265,4 @@ ENTRY(__asm_switch_ttbr) ret x3 ENDPROC(__asm_switch_ttbr) +.popsection
arch/arm/cpu/armv8/tlb.S +3 -1
@@ -14,7 +14,8 @@ * void __asm_invalidate_tlb_all(void) * * invalidate all tlb entries. - */ +*/ +.pushsection .text.__asm_invalidate_tlb_all, "ax" ENTRY(__asm_invalidate_tlb_all) switch_el x9, 3f, 2f, 1f 3: tlbi alle3
@@ -31,3 +32,4 @@ ENTRY(__asm_invalidate_tlb_all) 0: ret ENDPROC(__asm_invalidate_tlb_all) +.popsection
arch/arm/cpu/armv8/transition.S +6 -0
@@ -10,6 +10,7 @@ #include <linux/linkage.h> #include <asm/macro.h> +.pushsection .text.armv8_switch_to_el2, "ax" ENTRY(armv8_switch_to_el2) switch_el x6, 1f, 0f, 0f 0:
@@ -30,7 +31,9 @@ ENTRY(armv8_switch_to_el2) br x4 1: armv8_switch_to_el2_m x4, x5, x6 ENDPROC(armv8_switch_to_el2) +.popsection +.pushsection .text.armv8_switch_to_el1, "ax" ENTRY(armv8_switch_to_el1) switch_el x6, 0f, 1f, 0f 0:
@@ -40,7 +43,10 @@ ENTRY(armv8_switch_to_el1) br x4 1: armv8_switch_to_el1_m x4, x5, x6 ENDPROC(armv8_switch_to_el1) +.popsection +.pushsection .text.armv8_el2_to_aarch32, "ax" WEAK(armv8_el2_to_aarch32) ret ENDPROC(armv8_el2_to_aarch32) +.popsection
Signature · 1 line
2.1.4
PATCH v3 16/66 armv8: move low-level assembly functions into function-sections
Quoted 24 lines · Philipp Tomsich
TPL builds today don't need to call into firmware or set up the MMU (if this changes, it should be controlled through a config option whether to include this or not), but include the needed support code for this anyway. By moving these unused low-level functions into seperate function-sections, the linker can garbage-collect the unused sections.
Note that (if DM support is enabled), there will be a call to the cache-flushing code from
alloc_priv(...)indrivers/core/device.c. This then add 52 bytes of binary size (an increase from 20589 to 20641 bytes) compared to completely removing this code.Even for a feature-rich TPL (including DM support as for the RK3368), this equates to a size difference of significantly more than 10% in TPL binary size.
Signed-off-by Philipp Tomsich <[email protected]>---
Changes in v3:
- change to use function-sections (instead of disabling at the Makefile-level for TPL builds) per Tom's suggestion
Quoted 8 lines
Changes in v2: None
arch/arm/cpu/armv8/Makefile | 2 +- arch/arm/cpu/armv8/cache.S | 22 ++++++++++++++++++++++ arch/arm/cpu/armv8/tlb.S | 4 +++- arch/arm/cpu/armv8/transition.S | 6 ++++++ 4 files changed, 32 insertions(+), 2 deletions(-)
Reviewed-by Simon Glass <[email protected]>
Quoted 5 lines
arch/arm/cpu/armv8/Makefile +0
-0
arch/arm/cpu/armv8/Makefile extra-y := start.o · line 17
Quoted 9 lines
arch/arm/cpu/armv8/Makefile +1
-1@@ -10,11 +10,11 @@ extra-y := start.o obj-y += cpu.o obj-y += generic_timer.o obj-y += cache_v8.o -obj-y += exceptions.o obj-y += cache.o obj-y += tlb.o obj-y += transition.o obj-y += fwcall.o +obj-y += exceptions.o
But what is happened here?
Quoted 2 lines
arch/arm/cpu/armv8/Makefile +0
-0obj-y += cpu-dt.o obj-$(CONFIG_ARM_SMCCC) += smccc-call.o
PATCH v3 17/66 armv8: spl: Support separate stack for TPL
In reply to Philipp TomsichTo allow a TPL and SPL to run from different addresses/memories, we need to split setup of the TPL and SPL stacks. To do so, we introduce CONFIG_TPL_STACK (not listed in Kconfig) which can be used to override the initial stack pointer for TPL.
To provide backward compatibility for existing boards, this is added as an optional configuration item and the normal search order (i.e. SPL_STACK, then SYS_STACK) apply if not defined.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
Changes in v3: None
Changes in v2: None
arch/arm/lib/crt0_64.S | 4 +++- scripts/config_whitelist.txt | 1 + 2 files changed, 4 insertions(+), 1 deletion(-)
arch/arm/lib/crt0_64.S +3 -1
@@ -69,7 +69,9 @@ ENTRY(_main) /* * Set up initial C runtime environment and call board_init_f(0). */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_STACK) + ldr x0, =(CONFIG_TPL_STACK) +#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) ldr x0, =(CONFIG_SPL_STACK) #else ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
scripts/config_whitelist.txt +1 -0
@@ -4983,6 +4983,7 @@ CONFIG_TI_SPI_MMAP CONFIG_TMU_TIMER CONFIG_TPL_DRIVERS_MISC_SUPPORT CONFIG_TPL_PAD_TO +CONFIG_TPL_STACK CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_TPS6586X_POWER CONFIG_TQM834X
Signature · 1 line
2.1.4
PATCH v3 18/66 spl: allow a separate TEXT_BASE, LDSCRIPT and MAX_SIZE for TPL
In reply to Philipp TomsichFor the bringup of the RK3368, we need to support TPL and SPL running from different addresses... which requires both stages to use a distinct TEXT_BASE.
This commit adds support for having a separate LDSCRIPT for TPL (which is expected to make use of the TPL_MAX_SIZE define) and for having a the option of defining TPL_TEXT_BASE and having the TPL stage linked against this address.
Note that the handling of the TEXT_BASE is designed to not interfere with the previous assumption that SPL_TEXT_BASE should be used for TPL as well, unless TPL_TEXT_BASE is defined. For this reason, the test in Makefile.spl uses the following (seemingly redundant checks):
1. looks for $(SPL_TPL_)TEXT_BASE
2. looks for SPL_TEXT_BASE (even when building in TPL)
Signed-off-by Philipp Tomsich <[email protected]>
---
Changes in v3: None
Changes in v2: None
scripts/Makefile.spl | 10 ++++++++-- scripts/config_whitelist.txt | 3 +++ 2 files changed, 11 insertions(+), 2 deletions(-)
scripts/Makefile.spl +8 -2
@@ -103,9 +103,9 @@ u-boot-spl-platdata := $(obj)/dts/dt-platdata.o endif # Linker Script -ifdef CONFIG_SPL_LDSCRIPT +ifdef CONFIG_$(SPL_TPL_)LDSCRIPT # need to strip off double quotes -LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_SPL_LDSCRIPT:"%"=%)) +LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_$(SPL_TPL_)LDSCRIPT:"%"=%)) endif ifeq ($(wildcard $(LDSCRIPT)),)
@@ -293,9 +293,15 @@ LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL) # Avoid 'Not enough room for program headers' error on binutils 2.28 onwards. LDFLAGS_$(SPL_BIN) += $(call ld-option, --no-dynamic-linker) +# First try the best-match (i.e. SPL_TEXT_BASE for SPL, TPL_TEXT_BASE for TPL) +ifneq ($(CONFIG_$(SPL_TPL_)TEXT_BASE),) +LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_$(SPL_TPL_)TEXT_BASE) +else +# And then fall back to just testing for SPL_TEXT_BASE, even if in TPL mode ifneq ($(CONFIG_SPL_TEXT_BASE),) LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE) endif +endif MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE
scripts/config_whitelist.txt +3 -0
@@ -4982,8 +4982,11 @@ CONFIG_TI_KSNAV CONFIG_TI_SPI_MMAP CONFIG_TMU_TIMER CONFIG_TPL_DRIVERS_MISC_SUPPORT +CONFIG_TPL_LDSCRIPT +CONFIG_TPL_MAX_SIZE CONFIG_TPL_PAD_TO CONFIG_TPL_STACK +CONFIG_TPL_TEXT_BASE CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_TPS6586X_POWER CONFIG_TQM834X
Signature · 1 line
2.1.4
PATCH v3 18/66 spl: allow a separate TEXT_BASE, LDSCRIPT and MAX_SIZE for TPL
Quoted 17 lines · Philipp Tomsich
For the bringup of the RK3368, we need to support TPL and SPL running from different addresses... which requires both stages to use a distinct
TEXT_BASE.This commit adds support for having a separate LDSCRIPT for TPL (which is expected to make use of the
TPL_MAX_SIZEdefine) and for having a the option of definingTPL_TEXT_BASEand having the TPL stage linked against this address.Note that the handling of the
TEXT_BASEis designed to not interfere with the previous assumption thatSPL_TEXT_BASEshould be used for TPL as well, unlessTPL_TEXT_BASEis defined. For this reason, the test in Makefile.spl uses the following (seemingly redundant checks):
1. looks for $(SPL_TPL_)TEXT_BASE
2. looks forSPL_TEXT_BASE(even when building in TPL)Signed-off-by Philipp Tomsich <[email protected]>
Quoted 8 lines
---
Changes in v3: None
Changes in v2: Nonescripts/Makefile.spl | 10 ++++++++-- scripts/config_whitelist.txt | 3 +++ 2 files changed, 11 insertions(+), 2 deletions(-)
Reviewed-by Simon Glass <[email protected]>
PATCH v3 19/66 spl: Kconfig: split SYS_MALLOC_SIMPLE for TPL and SPL
In reply to Philipp TomsichAs include/malloc.h already checks for SYS_MALLOC_SIMPLE using the CONFIG_IS_ENABLED macro, we need to move to having separate entries as we switch to fully separate configuration for SPL and TPL.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
Changes in v3: None
Changes in v2: None
common/spl/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+)
common/spl/Kconfig +9 -0
@@ -62,6 +62,15 @@ config SPL_SYS_MALLOC_SIMPLE this will make the SPL binary smaller at the cost of more heap usage as the *_simple malloc functions do not re-use free-ed mem. +config TPL_SYS_MALLOC_SIMPLE + bool + prompt "Only use malloc_simple functions in the TPL" + help + Say Y here to only use the *_simple malloc functions from + malloc_simple.c, rather then using the versions from dlmalloc.c; + this will make the TPL binary smaller at the cost of more heap + usage as the *_simple malloc functions do not re-use free-ed mem. + config SPL_STACK_R bool "Enable SDRAM location for SPL stack" help
Signature · 1 line
2.1.4
PATCH v3 20/66 lib: spl: differentiate between TPL and SPL for libfdt/of_control/of_platdata
In reply to Philipp TomsichThis splits the compilation of code modules for TPL and SPL for OF_CONTROL (and related) features between TPL and SPL. The typical use-case of this is a TPL stage that uses OF_PLATDATA at TPL and provides full OF_CONTROL at SPL (e.g. on the RK3368).
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
Changes in v3: None
Changes in v2: None
lib/Makefile | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
lib/Makefile +5 -5
@@ -49,11 +49,11 @@ obj-$(CONFIG_RSA) += rsa/ obj-$(CONFIG_SHA1) += sha1.o obj-$(CONFIG_SHA256) += sha256.o -obj-$(CONFIG_SPL_SAVEENV) += qsort.o -obj-$(CONFIG_$(SPL_)OF_LIBFDT) += libfdt/ -ifneq ($(CONFIG_SPL_BUILD)$(CONFIG_SPL_OF_PLATDATA),yy) -obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec_common.o -obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec.o +obj-$(CONFIG_$(SPL_TPL_)SAVEENV) += qsort.o +obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/ +ifneq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy) +obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec_common.o +obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec.o endif ifdef CONFIG_SPL_BUILD
Signature · 1 line
2.1.4
PATCH v3 21/66 spl: consistently use $(SPL_TPL_) to select features for SPL and TPL builds
In reply to Philipp TomsichTo allow for a finer-grained control of features for TPL and SPL builds all modules/boot-methods/etc. need to be consistently selected based on the $(SPL_TPL_) macros.
This allows splitting the associated config-options in Kconfig: we don't split the Kconfig options here and now, as this should happen on an as-needed basis, whenever someone needs a feature/boot-method/etc. in their TPL.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
Changes in v3: None
Changes in v2: None
common/Makefile | 8 ++++---- common/spl/Makefile | 36 ++++++++++++++++++------------------ 2 files changed, 22 insertions(+), 22 deletions(-)
common/Makefile +4 -4
@@ -53,7 +53,7 @@ obj-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o obj-$(CONFIG_CMD_BEDBUG) += bedbug.o -obj-$(CONFIG_$(SPL_)OF_LIBFDT) += fdt_support.o +obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o obj-$(CONFIG_MII) += miiphyutil.o obj-$(CONFIG_CMD_MII) += miiphyutil.o
@@ -146,10 +146,10 @@ endif endif obj-y += image.o obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o -obj-$(CONFIG_$(SPL_)OF_LIBFDT) += image-fdt.o -obj-$(CONFIG_$(SPL_)FIT) += image-fit.o +obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o +obj-$(CONFIG_$(SPL_TPL_)FIT) += image-fit.o obj-$(CONFIG_FIT_EMBED) += boot_fit.o common_fit.o -obj-$(CONFIG_$(SPL_)FIT_SIGNATURE) += image-sig.o +obj-$(CONFIG_$(SPL_TPL_)FIT_SIGNATURE) += image-sig.o obj-$(CONFIG_IO_TRACE) += iotrace.o obj-y += memsize.o obj-y += stdio.o
common/spl/Makefile +18 -18
@@ -10,24 +10,24 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_FRAMEWORK) += spl.o -obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_bootrom.o -obj-$(CONFIG_SPL_LOAD_FIT) += spl_fit.o -obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o -obj-$(CONFIG_SPL_XIP_SUPPORT) += spl_xip.o -obj-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o +obj-$(CONFIG_$(SPL_TPL_)BOOTROM_SUPPORT) += spl_bootrom.o +obj-$(CONFIG_$(SPL_TPL_)LOAD_FIT) += spl_fit.o +obj-$(CONFIG_$(SPL_TPL_)SPL_NOR_SUPPORT) += spl_nor.o +obj-$(CONFIG_$(SPL_TPL_)SPL_XIP_SUPPORT) += spl_xip.o +obj-$(CONFIG_$(SPL_TPL_)SPL_YMODEM_SUPPORT) += spl_ymodem.o ifndef CONFIG_SPL_UBI -obj-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o -obj-$(CONFIG_SPL_ONENAND_SUPPORT) += spl_onenand.o +obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += spl_nand.o +obj-$(CONFIG_$(SPL_TPL_)ONENAND_SUPPORT) += spl_onenand.o endif -obj-$(CONFIG_SPL_UBI) += spl_ubi.o -obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o -obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o -obj-$(CONFIG_SPL_ATF_SUPPORT) += spl_atf.o -obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o -obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o -obj-$(CONFIG_SPL_EXT_SUPPORT) += spl_ext.o -obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o -obj-$(CONFIG_SPL_DFU_SUPPORT) += spl_dfu.o -obj-$(CONFIG_SPL_SPI_LOAD) += spl_spi.o -obj-$(CONFIG_SPL_RAM_SUPPORT) += spl_ram.o +obj-$(CONFIG_$(SPL_TPL_)UBI) += spl_ubi.o +obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o +obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o +obj-$(CONFIG_$(SPL_TPL_)ATF_SUPPORT) += spl_atf.o +obj-$(CONFIG_$(SPL_TPL_)USB_SUPPORT) += spl_usb.o +obj-$(CONFIG_$(SPL_TPL_)FAT_SUPPORT) += spl_fat.o +obj-$(CONFIG_$(SPL_TPL_)EXT_SUPPORT) += spl_ext.o +obj-$(CONFIG_$(SPL_TPL_)SATA_SUPPORT) += spl_sata.o +obj-$(CONFIG_$(SPL_TPL_)DFU_SUPPORT) += spl_dfu.o +obj-$(CONFIG_$(SPL_TPL_)SPI_LOAD) += spl_spi.o +obj-$(CONFIG_$(SPL_TPL_)RAM_SUPPORT) += spl_ram.o endif
Signature · 1 line
2.1.4
PATCH v3 22/66 spl: add TPL_DRIVER_MISC_SUPPORT option
In reply to Philipp TomsichThis adds the TPL_DRIVER_MISC_SUPPORT option to allow activation of DRIVER_MISC_SUPPORT for devices that need it in the TPL stage.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Reviewed-by Tom Rini <[email protected]>
Version-changes: 3
- removes TPL_MISC_DRIVERS_SUPPORT from the whitelist
---
Changes in v3: None
Changes in v2: None
common/spl/Kconfig | 8 ++++++++ scripts/config_whitelist.txt | 1 - 2 files changed, 8 insertions(+), 1 deletion(-)
common/spl/Kconfig +8 -0
@@ -718,6 +718,14 @@ config TPL_BOOTROM_SUPPORT BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the boot device list, if not implemented for a given board) +config TPL_DRIVERS_MISC_SUPPORT + bool "Support misc drivers in TPL" + help + Enable miscellaneous drivers in TPL. These drivers perform various + tasks that don't fall nicely into other categories, Enable this + option to build the drivers in drivers/misc as part of an TPL + build, for those that support building in TPL (not all drivers do). + config TPL_ENV_SUPPORT bool "Support an environment" help
scripts/config_whitelist.txt +0 -1
@@ -4981,7 +4981,6 @@ CONFIG_TI_KEYSTONE_SERDES CONFIG_TI_KSNAV CONFIG_TI_SPI_MMAP CONFIG_TMU_TIMER -CONFIG_TPL_DRIVERS_MISC_SUPPORT CONFIG_TPL_LDSCRIPT CONFIG_TPL_MAX_SIZE CONFIG_TPL_PAD_TO
Signature · 1 line
2.1.4
PATCH v3 23/66 drivers: spl: consistently use the $(SPL_TPL_) macro
In reply to Philipp TomsichTo simplify drivers/Makefile a bit when using TPL/SPL, we consistently use the $(SPL_TPL_) macro to test for drivers that have separate configuration symbols for the full U-boot, SPL and TPL stages. Instead of explicitly repeating them in two separate if-guarded sections of the Makefile, we can now simply list these options once.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Reviewed-by Tom Rini <[email protected]>
---
Changes in v3: None
Changes in v2: None
drivers/Makefile | 36 ++++++++++++++++-------------------- 1 file changed, 16 insertions(+), 20 deletions(-)
drivers/Makefile +16 -20
@@ -2,33 +2,34 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_$(SPL_TPL_)DM) += core/ -obj-$(CONFIG_$(SPL_)CLK) += clk/ -obj-$(CONFIG_$(SPL_)LED) += led/ -obj-$(CONFIG_$(SPL_)PHY) += phy/ -obj-$(CONFIG_$(SPL_)PINCTRL) += pinctrl/ -obj-$(CONFIG_$(SPL_)RAM) += ram/ +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/ +obj-$(CONFIG_$(SPL_TPL_)DM) += core/ +obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/ +obj-$(CONFIG_$(SPL_TPL_)I2C_SUPPORT) += i2c/ +obj-$(CONFIG_$(SPL_TPL_)LED) += led/ +obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += mmc/ +obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += mtd/nand/ +obj-$(CONFIG_$(SPL_TPL_)PHY) += phy/ +obj-$(CONFIG_$(SPL_TPL_)PINCTRL) += pinctrl/ +obj-$(CONFIG_$(SPL_TPL_)RAM) += ram/ +obj-$(CONFIG_$(SPL_TPL_)SERIAL_SUPPORT) += serial/ +obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPORT) += mtd/spi/ +obj-$(CONFIG_$(SPL_TPL_)SPI_SUPPORT) += spi/ +ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/ obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/ -obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/ obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/ -obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc/ obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/ obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/ -obj-$(CONFIG_SPL_SERIAL_SUPPORT) += serial/ -obj-$(CONFIG_SPL_SPI_SUPPORT) += spi/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/ -obj-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/ obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd/ -obj-$(CONFIG_SPL_NAND_SUPPORT) += mtd/nand/ obj-$(CONFIG_SPL_ONENAND_SUPPORT) += mtd/onenand/ -obj-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += mtd/spi/ obj-$(CONFIG_SPL_UBI) += mtd/ubispl/ obj-$(CONFIG_SPL_DMA_SUPPORT) += dma/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/
@@ -48,18 +49,13 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/ obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/ obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/ obj-$(CONFIG_SPL_MMC_SUPPORT) += block/ + +endif endif ifdef CONFIG_TPL_BUILD -obj-$(CONFIG_TPL_I2C_SUPPORT) += i2c/ -obj-$(CONFIG_TPL_DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/ -obj-$(CONFIG_TPL_MMC_SUPPORT) += mmc/ obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ -obj-$(CONFIG_TPL_NAND_SUPPORT) += mtd/nand/ -obj-$(CONFIG_TPL_SERIAL_SUPPORT) += serial/ -obj-$(CONFIG_TPL_SPI_FLASH_SUPPORT) += mtd/spi/ -obj-$(CONFIG_TPL_SPI_SUPPORT) += spi/ endif
Signature · 1 line
2.1.4
PATCH v3 24/66 rockchip: Makefile: allow selective inclusion of sdram_common.o from TPL/SPL/U-Boot
In reply to Philipp TomsichThe utility functions in sdram_common.c will be useful both for some SPL implementations (and if unused, the linked will discard these anyway) and for the full U-Boot stage.
This changes selects sdram_common.o through the $(SPL_TPL_) macro to allow better control of its inclusion through the CONFIG_ROM, CONFIG_SPL_RAM or CONFIG_TPL_RAM options.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/Makefile | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)
arch/arm/mach-rockchip/Makefile +1 -3
@@ -5,6 +5,7 @@ # obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o +obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o ifdef CONFIG_TPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
@@ -21,9 +22,6 @@ obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o -ifdef CONFIG_RAM -obj-y += sdram_common.o -endif endif ifndef CONFIG_ARM64 obj-y += rk_timer.o
Signature · 1 line
2.1.4
PATCH v3 25/66 rockchip: rk3368: improve Kconfig text for the RK3368
In reply to Philipp TomsichThe RK3368 option in Kconfig referred to the RK3328 (copy-and-paste) and had a few typos and unnecessarily used UTF-8 characters. While fixing this, I also reformatted and further clarified the text (e.g. made the grouping into a a big and little cluster of 4 cores each explicit).
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/Kconfig | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-)
arch/arm/mach-rockchip/Kconfig +9 -6
@@ -69,12 +69,15 @@ config ROCKCHIP_RK3368 select ARM64 select SYS_NS16550 help - The Rockchip RK3328 is a ARM-based SoC with a octa-core Cortex-A53. - including NEON and GPU, 512KB L2 cache for big cluster and 256 KB - L2 cache for little cluser, PowerVR G6110 based graphics, one video - output processor supporting LVDS、HDMI、eDP, several DDR3 options - and video codec support. Peripherals include Gigabit Ethernet, - USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. + The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised + into a big and little cluster with 4 cores each) Cortex-A53 including + AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache + (for the little cluster), PowerVR G6110 based graphics, one video + output processor supporting LVDS/HDMI/eDP, several DDR3 options and + video codec support. + + On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, + I2S, UARTs, SPI, I2C and PWMs. config ROCKCHIP_RK3399 bool "Support Rockchip RK3399"
Signature · 1 line
2.1.4
PATCH v3 26/66 rockchip: rk3368: mkimage: add support for the RK3368
In reply to Philipp TomsichThis commit adds support for RK3368 SoC in mkimage.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
tools/rkcommon.c | 1 + 1 file changed, 1 insertion(+)
tools/rkcommon.c +1 -0
@@ -77,6 +77,7 @@ static struct spl_info spl_infos[] = { { "rk322x", "RK32", 0x8000 - 0x1000, false, false }, { "rk3288", "RK32", 0x8000, false, false }, { "rk3328", "RK32", 0x8000 - 0x1000, false, false }, + { "rk3368", "RK33", 0x8000 - 0x1000, false, true }, { "rk3399", "RK33", 0x30000 - 0x2000, false, true }, { "rv1108", "RK11", 0x1800, false, false}, };
Signature · 1 line
2.1.4
PATCH v3 27/66 rockchip: rk3368: pmugrf: add definitions for os_reg[0..3]
In reply to Philipp TomsichOn the RK3368 we use a TPL-stage similar to Rockchip's DDR init (i.e. it initialises DRAM, leaves some info for the next stage and returns to the BootROM). To allow compatibility with Rockchip's DDR init code, we use the same register os_reg2 in pmugrf for passing this info (i.e. DRAM size and configuration) between stages.
This change adds the definitions for os_reg[0] through os_reg[3] to the pmugrf structure for the RK3368.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/grf_rk3368.h +3 -2
@@ -92,10 +92,11 @@ struct rk3368_pmu_grf {u32 gpio0d_drv;u32 gpio0l_sr;u32 gpio0h_sr; -u32 reserved[(0x200 -0x34 ) /4 -1 ]; +u32 reserved[0x72 ];u32 os_reg[4 ]; }; -check_member (rk3368_pmu_grf, os_reg[3 ],0x20c ); +check_member (rk3368_pmu_grf, gpio0h_sr,0x34 ); +check_member (rk3368_pmu_grf, os_reg[0 ],0x200 );/*GRF_GPIO0C_IOMUX*/ enum {
Signature · 1 line
2.1.4
PATCH v3 28/66 rockchip: rk3368: spl: define COUNTER_FREQUENCY to 24MHz
In reply to Philipp TomsichThe BootROM of the RK3368 Boot ROM does not initialise cntfrq_el0. This change defines COUNTER_FREQUENCY, which is used by the AArch64 init code in arch/arm/cpu/armv8/start.S to set up cntfrq_el0.
If the counter-frequency is not correctly set up, the calculation of delays using the ARMv8 generic timer can not work correctly.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
include/configs/rk3368_common.h | 2 ++ 1 file changed, 2 insertions(+)
include/configs/rk3368_common.h +2 -0
@@ -21,6 +21,8 @@#define CONFIG_SYS_CBSIZE 1024#define CONFIG_SKIP_LOWLEVEL_INIT +#define COUNTER_FREQUENCY 24000000 +#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_TEXT_BASE 0x00200000
Signature · 1 line
2.1.4
PATCH v3 29/66 rockchip: rk3368: spl: add memory layout for TPL and SPL
In reply to Philipp TomsichFor the RK3368, we use a multi-stage boot-process consisting of the following:
1. TPL: initalises DRAM, returns to boot-ROM (which then loads the next stage and transfers control to it)
2. SPL: a full-features SPL stage including OF_CONTROL and FIT image loading, which fetches the ATF, DTB and full U-Boot and then transfers control to the ATF (using the BL31 parameter block to indicate the location of BL33/U-Boot)
3. ATF: sets up the secure world and exits to BL33 (i.e. a full U-Boot) in the normal world
4. full U-Boot
TPL/SPL and the full U-Boot are built from this tree and need to run from distinct text addresses and with distinct initial stack pointer addresses.
This commit sets up the configuration to run:
- TPL from the SRAM at 0xff8c0000 (note that the first 0x1000 are reserved for use by the boot-ROM and contain the SP when the TPL is entered)
- SPL from DRAM at 0x0
- U-Boot from DRAM at 0x200000
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
include/configs/rk3368_common.h | 11 +++++++++++ 1 file changed, 11 insertions(+)
include/configs/rk3368_common.h +11 -0
@@ -29,6 +29,17 @@#define CONFIG_SYS_INIT_SP_ADDR 0x00300000#define CONFIG_SYS_LOAD_ADDR 0x00280000 +#define CONFIG_SPL_TEXT_BASE 0x00000000 +#define CONFIG_SPL_MAX_SIZE 0x40000 +#define CONFIG_SPL_BSS_START_ADDR 0x400000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x20000 + +#define CONFIG_TPL_LDSCRIPT \ + "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds" +#define CONFIG_TPL_TEXT_BASE 0xff8c1000 +#define CONFIG_TPL_MAX_SIZE 0x7000 +#define CONFIG_TPL_STACK 0xff8cffff +#define CONFIG_BOUNCE_BUFFER #ifndef CONFIG_SPL_BUILD
Signature · 1 line
2.1.4
PATCH v3 30/66 rockchip: rk3368: syscon: MSCH/PMUGRF/GRF support for OF_PLATDATA
In reply to Philipp TomsichThe RK3368 has both a limited TPL size (just 0x7000 bytes) and the added challenge of booting in AArch64, which increases the code size for TPL (particularily when using the LP64 programming model). For this reason we expect the RK3368 to always use OF_PLATDATA for its TPL stage.
This change adds support for the MSCH, PMUGRF and GRF register regions in syscon, which are necessary for initialising the RK3368's DRAM controller.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3:
- commit message now correctly refers to TPL
Changes in v2: None
arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 35 +++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)
arch/arm/mach-rockchip/rk3368/syscon_rk3368.c +35 -0
@@ -1,6 +1,8 @@/* * (C) Copyright 2017 Rockchip Electronics Co., Ltd * Author: Andy Yan <[email protected]> +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* * SPDX-License-Identifier: GPL-2.0+ */
@@ -14,6 +16,8 @@ static const struct udevice_id rk3368_syscon_ids[] = { .data = ROCKCHIP_SYSCON_GRF }, { .compatible = "rockchip,rk3368-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF }, + { .compatible = "rockchip,rk3368-msch", + .data = ROCKCHIP_SYSCON_MSCH }, { } };
@@ -22,3 +26,34 @@ U_BOOT_DRIVER(syscon_rk3368) = { .id = UCLASS_SYSCON, .of_match = rk3368_syscon_ids, }; + +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +static int rk3368_syscon_bind_of_platdata (struct udevice *dev) +{ + dev->driver_data = dev->driver->of_match->data; +debug ("syscon: %s %d\n" , dev->name, (uint )dev->driver_data); + +return 0 ; +} + +U_BOOT_DRIVER (rockchip_rk3368_grf) = { + .name ="rockchip_rk3368_grf" , + .id =UCLASS_SYSCON , + .of_match = rk3368_syscon_ids, + .bind = rk3368_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER (rockchip_rk3368_pmugrf) = { + .name ="rockchip_rk3368_pmugrf" , + .id =UCLASS_SYSCON , + .of_match = rk3368_syscon_ids +1 , + .bind = rk3368_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER (rockchip_rk3368_msch) = { + .name ="rockchip_rk3368_msch" , + .id =UCLASS_SYSCON , + .of_match = rk3368_syscon_ids +2 , + .bind = rk3368_syscon_bind_of_platdata, +}; +#endif
Signature · 1 line
2.1.4
PATCH v3 31/66 rockchip: rk3368: syscon: SGRF support for OF_PLATDATA
In reply to Philipp TomsichIn TPL we will need to configure security in the SGRF of the RK3368. This change adds support for the SGRF as a syscon device, so we can retrieve its address range through the syscon API in TPL (and can avoid having to hard-code the address).
Signed-off-by Philipp Tomsich <[email protected]>
---
Changes in v3:
- adds SGRF syscon support with OF_PLATDATA (to allow access to the SGRF address range from TPL)
Changes in v2: None
arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/arm/mach-rockchip/rk3368/syscon_rk3368.c +9 -0
@@ -18,6 +18,8 @@ static const struct udevice_id rk3368_syscon_ids[] = { .data = ROCKCHIP_SYSCON_PMUGRF }, { .compatible = "rockchip,rk3368-msch", .data = ROCKCHIP_SYSCON_MSCH }, + { .compatible = "rockchip,rk3368-sgrf", + .data = ROCKCHIP_SYSCON_SGRF }, { } };
@@ -56,4 +58,11 @@ U_BOOT_DRIVER(rockchip_rk3368_msch) = { .of_match = rk3368_syscon_ids + 2, .bind = rk3368_syscon_bind_of_platdata, }; + +U_BOOT_DRIVER (rockchip_rk3368_sgrf) = { + .name ="rockchip_rk3368_sgrf" , + .id =UCLASS_SYSCON , + .of_match = rk3368_syscon_ids +3 , + .bind = rk3368_syscon_bind_of_platdata, +};#endif
Signature · 1 line
2.1.4
PATCH v3 31/66 rockchip: rk3368: syscon: SGRF support for OF_PLATDATA
Quoted 9 lines · Philipp Tomsich
In TPL we will need to configure security in the SGRF of the RK3368. This change adds support for the SGRF as a syscon device, so we can retrieve its address range through the syscon API in TPL (and can avoid having to hard-code the address).
Signed-off-by Philipp Tomsich <[email protected]>---
Quoted 8 lines
Changes in v3:
- adds SGRF syscon support withOF_PLATDATA(to allow access to the SGRF address range from TPL)Changes in v2: None
arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 9 +++++++++ 1 file changed, 9 insertions(+)
Reviewed-by Simon Glass <[email protected]>
PATCH v3 32/66 rockchip: rk3368: grf: use shifted-constants
In reply to Philipp TomsichThe RK3368 GRF header was still defines with a shifted-mask but with non-shifted function selectors for the IOMUX defines. As the RK3368 support is still fresh enough to allow a quick change, we do this now before having more code use this.
Signed-off-by Philipp Tomsich <[email protected]>
---
Changes in v3: None
Changes in v2:
- dropped the RK3368_ prefix for the GRF constants
arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 441 ++++++++++++------------ drivers/pinctrl/rockchip/pinctrl_rk3368.c | 9 +- 2 files changed, 226 insertions(+), 224 deletions(-)
arch/arm/include/asm/arch-rockchip/grf_rk3368.h +223 -218
@@ -1,4 +1,6 @@ -/* (C) Copyright 2016 Rockchip Electronics Co., Ltd +/* +* (C) Copyright 2016 Rockchip Electronics Co., Ltd +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH * * SPDX-License-Identifier: GPL-2.0+ */
@@ -100,315 +102,318 @@ check_member(rk3368_pmu_grf, os_reg[0], 0x200);/*GRF_GPIO0C_IOMUX*/ enum { -GPIO0C7_SHIFT =14 , -GPIO0C7_MASK =3 <<GPIO0C7_SHIFT , -GPIO0C7_GPIO =0 , -GPIO0C7_LCDC_D19 , -GPIO0C7_TRACE_D9 , -GPIO0C7_UART1_RTSN , - -GPIO0C6_SHIFT =12 , -GPIO0C6_MASK =3 <<GPIO0C6_SHIFT , +GPIO0C7_MASK =GENMASK (15 ,14 ), +GPIO0C7_GPIO =0 , +GPIO0C7_LCDC_D19 = (1 <<14 ), +GPIO0C7_TRACE_D9 = (2 <<14 ), +GPIO0C7_UART1_RTSN = (3 <<14 ), + +GPIO0C6_MASK =GENMASK (13 ,12 ),GPIO0C6_GPIO =0 , -GPIO0C6_LCDC_D18 , -GPIO0C6_TRACE_D8 , -GPIO0C6_UART1_CTSN , +GPIO0C6_LCDC_D18 = (1 <<12 ), +GPIO0C6_TRACE_D8 = (2 <<12 ), +GPIO0C6_UART1_CTSN = (3 <<12 ), -GPIO0C5_SHIFT =10 , -GPIO0C5_MASK =3 <<GPIO0C5_SHIFT , +GPIO0C5_MASK =GENMASK (11 ,10 ),GPIO0C5_GPIO =0 , -GPIO0C5_LCDC_D17 , -GPIO0C5_TRACE_D7 , -GPIO0C5_UART1_SOUT , +GPIO0C5_LCDC_D17 = (1 <<10 ), +GPIO0C5_TRACE_D7 = (2 <<10 ), +GPIO0C5_UART1_SOUT = (3 <<10 ), -GPIO0C4_SHIFT =8 , -GPIO0C4_MASK =3 <<GPIO0C4_SHIFT , +GPIO0C4_MASK =GENMASK (9 ,8 ),GPIO0C4_GPIO =0 , -GPIO0C4_LCDC_D16 , -GPIO0C4_TRACE_D6 , -GPIO0C4_UART1_SIN , +GPIO0C4_LCDC_D16 = (1 <<8 ), +GPIO0C4_TRACE_D6 = (2 <<8 ), +GPIO0C4_UART1_SIN = (3 <<8 ), -GPIO0C3_SHIFT =6 , -GPIO0C3_MASK =3 <<GPIO0C3_SHIFT , +GPIO0C3_MASK =GENMASK (7 ,6 ),GPIO0C3_GPIO =0 , -GPIO0C3_LCDC_D15 , -GPIO0C3_TRACE_D5 , -GPIO0C3_MCU_JTAG_TDO , +GPIO0C3_LCDC_D15 = (1 <<6 ), +GPIO0C3_TRACE_D5 = (2 <<6 ), +GPIO0C3_MCU_JTAG_TDO = (3 <<6 ), -GPIO0C2_SHIFT =4 , -GPIO0C2_MASK =3 <<GPIO0C2_SHIFT , +GPIO0C2_MASK =GENMASK (5 ,4 ),GPIO0C2_GPIO =0 , -GPIO0C2_LCDC_D14 , -GPIO0C2_TRACE_D4 , -GPIO0C2_MCU_JTAG_TDI , +GPIO0C2_LCDC_D14 = (1 <<4 ), +GPIO0C2_TRACE_D4 = (2 <<4 ), +GPIO0C2_MCU_JTAG_TDI = (3 <<4 ), -GPIO0C1_SHIFT =2 , -GPIO0C1_MASK =3 <<GPIO0C1_SHIFT , +GPIO0C1_MASK =GENMASK (3 ,2 ),GPIO0C1_GPIO =0 , -GPIO0C1_LCDC_D13 , -GPIO0C1_TRACE_D3 , -GPIO0C1_MCU_JTAG_TRTSN , +GPIO0C1_LCDC_D13 = (1 <<2 ), +GPIO0C1_TRACE_D3 = (2 <<2 ), +GPIO0C1_MCU_JTAG_TRTSN = (3 <<2 ), -GPIO0C0_SHIFT =0 , -GPIO0C0_MASK =3 <<GPIO0C0_SHIFT , +GPIO0C0_MASK =GENMASK (1 ,0 ),GPIO0C0_GPIO =0 , -GPIO0C0_LCDC_D12 , -GPIO0C0_TRACE_D2 , -GPIO0C0_MCU_JTAG_TDO , +GPIO0C0_LCDC_D12 = (1 <<0 ), +GPIO0C0_TRACE_D2 = (2 <<0 ), +GPIO0C0_MCU_JTAG_TDO = (3 <<0 ), };/*GRF_GPIO0D_IOMUX*/ enum { -GPIO0D7_SHIFT =14 , -GPIO0D7_MASK =3 <<GPIO0D7_SHIFT , +GPIO0D7_MASK =GENMASK (15 ,14 ),GPIO0D7_GPIO =0 , -GPIO0D7_LCDC_DCLK , -GPIO0D7_TRACE_CTL , -GPIO0D7_PMU_DEBUG5 , +GPIO0D7_LCDC_DCLK = (1 <<14 ), +GPIO0D7_TRACE_CTL = (2 <<14 ), +GPIO0D7_PMU_DEBUG5 = (3 <<14 ), -GPIO0D6_SHIFT =12 , -GPIO0D6_MASK =3 <<GPIO0D6_SHIFT , +GPIO0D6_MASK =GENMASK (13 ,12 ),GPIO0D6_GPIO =0 , -GPIO0D6_LCDC_DEN , -GPIO0D6_TRACE_CLK , -GPIO0D6_PMU_DEBUG4 , +GPIO0D6_LCDC_DEN = (1 <<12 ), +GPIO0D6_TRACE_CLK = (2 <<12 ), +GPIO0D6_PMU_DEBUG4 = (3 <<12 ), -GPIO0D5_SHIFT =10 , -GPIO0D5_MASK =3 <<GPIO0D5_SHIFT , +GPIO0D5_MASK =GENMASK (11 ,10 ),GPIO0D5_GPIO =0 , -GPIO0D5_LCDC_VSYNC , -GPIO0D5_TRACE_D15 , -GPIO0D5_PMU_DEBUG3 , +GPIO0D5_LCDC_VSYNC = (1 <<10 ), +GPIO0D5_TRACE_D15 = (2 <<10 ), +GPIO0D5_PMU_DEBUG3 = (3 <<10 ), -GPIO0D4_SHIFT =8 , -GPIO0D4_MASK =3 <<GPIO0D4_SHIFT , +GPIO0D4_MASK =GENMASK (9 ,8 ),GPIO0D4_GPIO =0 , -GPIO0D4_LCDC_HSYNC , -GPIO0D4_TRACE_D14 , -GPIO0D4_PMU_DEBUG2 , +GPIO0D4_LCDC_HSYNC = (1 <<8 ), +GPIO0D4_TRACE_D14 = (2 <<8 ), +GPIO0D4_PMU_DEBUG2 = (3 <<8 ), -GPIO0D3_SHIFT =6 , -GPIO0D3_MASK =3 <<GPIO0D3_SHIFT , +GPIO0D3_MASK =GENMASK (7 ,6 ),GPIO0D3_GPIO =0 , -GPIO0D3_LCDC_D23 , -GPIO0D3_TRACE_D13 , -GPIO0D3_UART4_SIN , +GPIO0D3_LCDC_D23 = (1 <<6 ), +GPIO0D3_TRACE_D13 = (2 <<6 ), +GPIO0D3_UART4_SIN = (3 <<6 ), -GPIO0D2_SHIFT =4 , -GPIO0D2_MASK =3 <<GPIO0D2_SHIFT , +GPIO0D2_MASK =GENMASK (5 ,4 ),GPIO0D2_GPIO =0 , -GPIO0D2_LCDC_D22 , -GPIO0D2_TRACE_D12 , -GPIO0D2_UART4_SOUT , +GPIO0D2_LCDC_D22 = (1 <<4 ), +GPIO0D2_TRACE_D12 = (2 <<4 ), +GPIO0D2_UART4_SOUT = (3 <<4 ), -GPIO0D1_SHIFT =2 , -GPIO0D1_MASK =3 <<GPIO0D1_SHIFT , +GPIO0D1_MASK =GENMASK (3 ,2 ),GPIO0D1_GPIO =0 , -GPIO0D1_LCDC_D21 , -GPIO0D1_TRACE_D11 , -GPIO0D1_UART4_RTSN , +GPIO0D1_LCDC_D21 = (1 <<2 ), +GPIO0D1_TRACE_D11 = (2 <<2 ), +GPIO0D1_UART4_RTSN = (3 <<2 ), -GPIO0D0_SHIFT =0 , -GPIO0D0_MASK =3 <<GPIO0D0_SHIFT , +GPIO0D0_MASK =GENMASK (1 ,0 ),GPIO0D0_GPIO =0 , -GPIO0D0_LCDC_D20 , -GPIO0D0_TRACE_D10 , -GPIO0D0_UART4_CTSN , +GPIO0D0_LCDC_D20 = (1 <<0 ), +GPIO0D0_TRACE_D10 = (2 <<0 ), +GPIO0D0_UART4_CTSN = (3 <<0 ), };/*GRF_GPIO2A_IOMUX*/ enum { -GPIO2A7_SHIFT =14 , -GPIO2A7_MASK =3 <<GPIO2A7_SHIFT , +GPIO2A7_MASK =GENMASK (15 ,14 ),GPIO2A7_GPIO =0 , -GPIO2A7_SDMMC0_D2 , -GPIO2A7_JTAG_TCK , +GPIO2A7_SDMMC0_D2 = (1 <<14 ), +GPIO2A7_JTAG_TCK = (2 <<14 ), -GPIO2A6_SHIFT =12 , -GPIO2A6_MASK =3 <<GPIO2A6_SHIFT , +GPIO2A6_MASK =GENMASK (13 ,12 ),GPIO2A6_GPIO =0 , -GPIO2A6_SDMMC0_D1 , -GPIO2A6_UART2_SIN , +GPIO2A6_SDMMC0_D1 = (1 <<12 ), +GPIO2A6_UART2_SIN = (2 <<12 ), -GPIO2A5_SHIFT =10 , -GPIO2A5_MASK =3 <<GPIO2A5_SHIFT , +GPIO2A5_MASK =GENMASK (11 ,10 ),GPIO2A5_GPIO =0 , -GPIO2A5_SDMMC0_D0 , -GPIO2A5_UART2_SOUT , +GPIO2A5_SDMMC0_D0 = (1 <<10 ), +GPIO2A5_UART2_SOUT = (2 <<10 ), -GPIO2A4_SHIFT =8 , -GPIO2A4_MASK =3 <<GPIO2A4_SHIFT , -GPIO2A4_GPIO =0 , -GPIO2A4_FLASH_DQS , -GPIO2A4_EMMC_CLKO , +GPIO2A4_MASK =GENMASK (9 ,8 ), +GPIO2A4_GPIO =0 , +GPIO2A4_FLASH_DQS = (1 <<8 ), +GPIO2A4_EMMC_CLKOUT = (2 <<8 ), -GPIO2A3_SHIFT =6 , -GPIO2A3_MASK =3 <<GPIO2A3_SHIFT , +GPIO2A3_MASK =GENMASK (7 ,6 ),GPIO2A3_GPIO =0 , -GPIO2A3_FLASH_CSN3 , -GPIO2A3_EMMC_RSTNO , +GPIO2A3_FLASH_CSN3 = (1 <<6 ), +GPIO2A3_EMMC_RSTNOUT = (2 <<6 ), -GPIO2A2_SHIFT =4 , -GPIO2A2_MASK =3 <<GPIO2A2_SHIFT , -GPIO2A2_GPIO =0 , -GPIO2A2_FLASH_CSN2 , +GPIO2A2_MASK =GENMASK (5 ,4 ), +GPIO2A2_GPIO =0 , +GPIO2A2_FLASH_CSN2 = (1 <<4 ), -GPIO2A1_SHIFT =2 , -GPIO2A1_MASK =3 <<GPIO2A1_SHIFT , +GPIO2A1_MASK =GENMASK (3 ,2 ),GPIO2A1_GPIO =0 , -GPIO2A1_FLASH_CSN1 , +GPIO2A1_FLASH_CSN1 = (1 <<2 ), -GPIO2A0_SHIFT =0 , -GPIO2A0_MASK =3 <<GPIO2A0_SHIFT , +GPIO2A0_MASK =GENMASK (1 ,0 ),GPIO2A0_GPIO =0 , -GPIO2A0_FLASH_CSN0 , +GPIO2A0_FLASH_CSN0 = (1 <<0 ), };/*GRF_GPIO2D_IOMUX*/ enum { -GPIO2D7_SHIFT =14 , -GPIO2D7_MASK =3 <<GPIO2D7_SHIFT , +GPIO2D7_MASK =GENMASK (15 ,14 ),GPIO2D7_GPIO =0 , -GPIO2D7_SDIO0_D3 , +GPIO2D7_SDIO0_D3 = (1 <<14 ), -GPIO2D6_SHIFT =12 , -GPIO2D6_MASK =3 <<GPIO2D6_SHIFT , +GPIO2D6_MASK =GENMASK (13 ,12 ),GPIO2D6_GPIO =0 , -GPIO2D6_SDIO0_D2 , +GPIO2D6_SDIO0_D2 = (1 <<12 ), -GPIO2D5_SHIFT =10 , -GPIO2D5_MASK =3 <<GPIO2D5_SHIFT , +GPIO2D5_MASK =GENMASK (11 ,10 ),GPIO2D5_GPIO =0 , -GPIO2D5_SDIO0_D1 , +GPIO2D5_SDIO0_D1 = (1 <<10 ), -GPIO2D4_SHIFT =8 , -GPIO2D4_MASK =3 <<GPIO2D4_SHIFT , +GPIO2D4_MASK =GENMASK (9 ,8 ),GPIO2D4_GPIO =0 , -GPIO2D4_SDIO0_D0 , +GPIO2D4_SDIO0_D0 = (1 <<8 ), -GPIO2D3_SHIFT =6 , -GPIO2D3_MASK =3 <<GPIO2D3_SHIFT , +GPIO2D3_MASK =GENMASK (7 ,6 ),GPIO2D3_GPIO =0 , -GPIO2D3_UART0_RTS0 , +GPIO2D3_UART0_RTS0 = (1 <<6 ), -GPIO2D2_SHIFT =4 , -GPIO2D2_MASK =3 <<GPIO2D2_SHIFT , +GPIO2D2_MASK =GENMASK (5 ,4 ),GPIO2D2_GPIO =0 , -GPIO2D2_UART0_CTS0 , +GPIO2D2_UART0_CTS0 = (1 <<4 ), -GPIO2D1_SHIFT =2 , -GPIO2D1_MASK =3 <<GPIO2D1_SHIFT , +GPIO2D1_MASK =GENMASK (3 ,2 ),GPIO2D1_GPIO =0 , -GPIO2D1_UART0_SOUT , +GPIO2D1_UART0_SOUT = (1 <<2 ), -GPIO2D0_SHIFT =0 , -GPIO2D0_MASK =3 <<GPIO2D0_SHIFT , +GPIO2D0_MASK =GENMASK (1 ,0 ),GPIO2D0_GPIO =0 , -GPIO2D0_UART0_SIN , +GPIO2D0_UART0_SIN = (1 <<0 ), +}; + +/* GRF_GPIO1C_IOMUX */ +enum { +GPIO1C7_MASK =GENMASK (15 ,14 ), +GPIO1C7_GPIO =0 , +GPIO1C7_EMMC_DATA5 = (2 <<14 ), + +GPIO1C6_MASK =GENMASK (13 ,12 ), +GPIO1C6_GPIO =0 , +GPIO1C6_EMMC_DATA4 = (2 <<12 ), + +GPIO1C5_MASK =GENMASK (11 ,10 ), +GPIO1C5_GPIO =0 , +GPIO1C5_EMMC_DATA3 = (2 <<10 ), + +GPIO1C4_MASK =GENMASK (9 ,8 ), +GPIO1C4_GPIO =0 , +GPIO1C4_EMMC_DATA2 = (2 <<8 ), + +GPIO1C3_MASK =GENMASK (7 ,6 ), +GPIO1C3_GPIO =0 , +GPIO1C3_EMMC_DATA1 = (2 <<6 ), + +GPIO1C2_MASK =GENMASK (5 ,4 ), +GPIO1C2_GPIO =0 , +GPIO1C2_EMMC_DATA0 = (2 <<4 ), +}; + +/* GRF_GPIO1D_IOMUX*/ +enum { +GPIO1D3_MASK =GENMASK (7 ,6 ), +GPIO1D3_GPIO =0 , +GPIO1D3_EMMC_PWREN = (2 <<6 ), + +GPIO1D2_MASK =GENMASK (5 ,4 ), +GPIO1D2_GPIO =0 , +GPIO1D2_EMMC_CMD = (2 <<4 ), + +GPIO1D1_MASK =GENMASK (3 ,2 ), +GPIO1D1_GPIO =0 , +GPIO1D1_EMMC_DATA7 = (2 <<2 ), + +GPIO1D0_MASK =GENMASK (1 ,0 ), +GPIO1D0_GPIO =0 , +GPIO1D0_EMMC_DATA6 = (2 <<0 ), +}; + + +/*GRF_GPIO3B_IOMUX*/ +enum { +GPIO3B7_MASK =GENMASK (15 ,14 ), +GPIO3B7_GPIO =0 , +GPIO3B7_MAC_RXD0 = (1 <<14 ), + +GPIO3B6_MASK =GENMASK (13 ,12 ), +GPIO3B6_GPIO =0 , +GPIO3B6_MAC_TXD3 = (1 <<12 ), + +GPIO3B5_MASK =GENMASK (11 ,10 ), +GPIO3B5_GPIO =0 , +GPIO3B5_MAC_TXEN = (1 <<10 ), + +GPIO3B4_MASK =GENMASK (9 ,8 ), +GPIO3B4_GPIO =0 , +GPIO3B4_MAC_COL = (1 <<8 ), + +GPIO3B3_MASK =GENMASK (7 ,6 ), +GPIO3B3_GPIO =0 , +GPIO3B3_MAC_CRS = (1 <<6 ), + +GPIO3B2_MASK =GENMASK (5 ,4 ), +GPIO3B2_GPIO =0 , +GPIO3B2_MAC_TXD2 = (1 <<4 ), + +GPIO3B1_MASK =GENMASK (3 ,2 ), +GPIO3B1_GPIO =0 , +GPIO3B1_MAC_TXD1 = (1 <<2 ), + +GPIO3B0_MASK =GENMASK (1 ,0 ), +GPIO3B0_GPIO =0 , +GPIO3B0_MAC_TXD0 = (1 <<0 ), +GPIO3B0_PWM0 = (2 <<0 ), };/*GRF_GPIO3C_IOMUX*/ enum { -GPIO3C7_SHIFT =14 , -GPIO3C7_MASK =3 <<GPIO3C7_SHIFT , -GPIO3C7_GPIO =0 , -GPIO3C7_EDPHDMI_CECINOUT , -GPIO3C7_ISP_FLASHTRIGIN , - -GPIO3C6_SHIFT =12 , -GPIO3C6_MASK =3 <<GPIO3C6_SHIFT , +GPIO3C6_MASK =GENMASK (13 ,12 ),GPIO3C6_GPIO =0 , -GPIO3C6_MAC_CLK , -GPIO3C6_ISP_SHUTTERTRIG , +GPIO3C6_MAC_CLK = (1 <<12 ), -GPIO3C5_SHIFT =10 , -GPIO3C5_MASK =3 <<GPIO3C5_SHIFT , +GPIO3C5_MASK =GENMASK (11 ,10 ),GPIO3C5_GPIO =0 , -GPIO3C5_MAC_RXER , -GPIO3C5_ISP_PRELIGHTTRIG , +GPIO3C5_MAC_RXEN = (1 <<10 ), -GPIO3C4_SHIFT =8 , -GPIO3C4_MASK =3 <<GPIO3C4_SHIFT , +GPIO3C4_MASK =GENMASK (9 ,8 ),GPIO3C4_GPIO =0 , -GPIO3C4_MAC_RXDV , -GPIO3C4_ISP_FLASHTRIGOUT , +GPIO3C4_MAC_RXDV = (1 <<8 ), -GPIO3C3_SHIFT =6 , -GPIO3C3_MASK =3 <<GPIO3C3_SHIFT , +GPIO3C3_MASK =GENMASK (7 ,6 ),GPIO3C3_GPIO =0 , -GPIO3C3_MAC_RXDV , -GPIO3C3_EMMC_RSTNO , +GPIO3C3_MAC_MDC = (1 <<6 ), -GPIO3C2_SHIFT =4 , -GPIO3C2_MASK =3 <<GPIO3C2_SHIFT , -GPIO3C2_MAC_MDC =0 , -GPIO3C2_ISP_SHUTTEREN , +GPIO3C2_MASK =GENMASK (5 ,4 ), +GPIO3C2_GPIO =0 , +GPIO3C2_MAC_RXD3 = (1 <<4 ), -GPIO3C1_SHIFT =2 , -GPIO3C1_MASK =3 <<GPIO3C1_SHIFT , +GPIO3C1_MASK =GENMASK (3 ,2 ),GPIO3C1_GPIO =0 , -GPIO3C1_MAC_RXD2 , -GPIO3C1_UART3_RTSN , +GPIO3C1_MAC_RXD2 = (1 <<2 ), -GPIO3C0_SHIFT =0 , -GPIO3C0_MASK =3 <<GPIO3C0_SHIFT , +GPIO3C0_MASK =GENMASK (1 ,0 ),GPIO3C0_GPIO =0 , -GPIO3C0_MAC_RXD1 , -GPIO3C0_UART3_CTSN , -GPIO3C0_GPS_RFCLK , +GPIO3C0_MAC_RXD1 = (1 <<0 ), };/*GRF_GPIO3D_IOMUX*/ enum { -GPIO3D7_SHIFT =14 , -GPIO3D7_MASK =3 <<GPIO3D7_SHIFT , -GPIO3D7_GPIO =0 , -GPIO3D7_SC_VCC18V , -GPIO3D7_I2C2_SDA , -GPIO3D7_GPUJTAG_TCK , - -GPIO3D6_SHIFT =12 , -GPIO3D6_MASK =3 <<GPIO3D6_SHIFT , -GPIO3D6_GPIO =0 , -GPIO3D6_IR_TX , -GPIO3D6_UART3_SOUT , -GPIO3D6_PWM3 , - -GPIO3D5_SHIFT =10 , -GPIO3D5_MASK =3 <<GPIO3D5_SHIFT , -GPIO3D5_GPIO =0 , -GPIO3D5_IR_RX , -GPIO3D5_UART3_SIN , - -GPIO3D4_SHIFT =8 , -GPIO3D4_MASK =3 <<GPIO3D4_SHIFT , +GPIO3D4_MASK =GENMASK (9 ,8 ),GPIO3D4_GPIO =0 , -GPIO3D4_MAC_TXCLKOUT , -GPIO3D4_SPI1_CSN1 , - -GPIO3D3_SHIFT =6 , -GPIO3D3_MASK =3 <<GPIO3D3_SHIFT , -GPIO3D3_GPIO =0 , -GPIO3D3_HDMII2C_SCL , -GPIO3D3_I2C5_SCL , - -GPIO3D2_SHIFT =4 , -GPIO3D2_MASK =3 <<GPIO3D2_SHIFT , -GPIO3D2_GPIO =0 , -GPIO3D2_HDMII2C_SDA , -GPIO3D2_I2C5_SDA , - -GPIO3D1_SHIFT =2 , -GPIO3D1_MASK =3 <<GPIO3D1_SHIFT , +GPIO3D4_MAC_TXCLK = (1 <<8 ), + +GPIO3D1_MASK =GENMASK (3 ,2 ),GPIO3D1_GPIO =0 , -GPIO3D1_MAC_RXCLKIN , -GPIO3D1_I2C4_SCL , +GPIO3D1_MAC_RXCLK = (1 <<2 ), -GPIO3D0_SHIFT =0 , -GPIO3D0_MASK =3 <<GPIO3D0_SHIFT , +GPIO3D0_MASK =GENMASK (1 ,0 ),GPIO3D0_GPIO =0 , -GPIO3D0_MAC_MDIO , -GPIO3D0_I2C4_SDA , +GPIO3D0_MAC_MDIO = (1 <<0 ), +}; + +/* GRF_SOC_CON0 */ +enum { +NOC_RSP_ERR_STALL =BIT (9 ), +MOBILE_DDR_SEL =BIT (4 ), +DDR0_16BIT_EN =BIT (3 ), +MSCH0_MAINDDR3_DDR3 =BIT (2 ), +MSCH0_MAINPARTIALPOP =BIT (1 ), +UPCTL_C_ACTIVE =BIT (0 ), };/*GRF_SOC_CON11/12/13*/
drivers/pinctrl/rockchip/pinctrl_rk3368.c +3 -6
@@ -31,8 +31,7 @@ static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,case PERIPH_ID_UART2 :rk_clrsetreg (&grf->gpio2a_iomux,GPIO2A6_MASK |GPIO2A5_MASK , -GPIO2A6_UART2_SIN <<GPIO2A6_SHIFT | -GPIO2A5_UART2_SOUT <<GPIO2A5_SHIFT ); +GPIO2A6_UART2_SIN |GPIO2A5_UART2_SOUT );break ;case PERIPH_ID_UART0 :break ;
@@ -44,10 +43,8 @@ static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,rk_clrsetreg (&pmugrf->gpio0d_iomux,GPIO0D0_MASK |GPIO0D1_MASK |GPIO0D2_MASK |GPIO0D3_MASK , -GPIO0D0_GPIO <<GPIO0D0_SHIFT | -GPIO0D1_GPIO <<GPIO0D1_SHIFT | -GPIO0D2_UART4_SOUT <<GPIO0D2_SHIFT | -GPIO0D3_UART4_SIN <<GPIO0D3_SHIFT ); +GPIO0D0_GPIO |GPIO0D1_GPIO | +GPIO0D2_UART4_SOUT |GPIO0D3_UART4_SIN );break ;default :debug ("uart id = %d iomux error!\n" , uart_id);
Signature · 1 line
2.1.4
PATCH v3 33/66 rockchip: rk3368: dts: add sgrf node
In reply to Philipp TomsichWe will to drop device security temporarily (until the ATF initialises it fully) from the TPL/SPL stage: this requires access to some registers in the SGRF.
This adds the sgrf node to the rk3368.dtsi, so we can then bind a syscon device onto it and access its memory ranges.
Signed-off-by Philipp Tomsich <[email protected]>
---
Changes in v3: None
Changes in v2: None
arch/arm/dts/rk3368.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
arch/arm/dts/rk3368.dtsi +5 -0
@@ -652,6 +652,11 @@ reg = <0x0 0xff738000 0x0 0x1000>; }; + sgrf: syscon at ff740000 { + compatible = "rockchip,rk3368-sgrf", "syscon"; + reg = <0x0 0xff740000 0x0 0x1000>; + }; + cru: clock-controller at ff760000 { compatible = "rockchip,rk3368-cru"; reg = <0x0 0xff760000 0x0 0x1000>;
Signature · 1 line
2.1.4
PATCH v3 33/66 rockchip: rk3368: dts: add sgrf node
Quoted 7 lines · Philipp Tomsich
We will to drop device security temporarily (until the ATF initialises it fully) from the TPL/SPL stage: this requires access to some registers in the SGRF.
This adds the sgrf node to the
rk3368.dtsi, so we can then bind a syscon device onto it and access its memory ranges.
Quoted 8 lines
Signed-off-by Philipp Tomsich <[email protected]>---
Changes in v3: None
Changes in v2: Nonearch/arm/dts/rk3368.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
Reviewed-by Simon Glass <[email protected]>
PATCH v3 34/66 rockchip: pinctrl: rk3368: add GMAC (RGMII only) support
In reply to Philipp TomsichTo add GMAC (Gigabit Ethernet) support (limited to RGMII only at this point), we need support for additional pin-configuration. This commit adds the pinctrl support for GMAC in RGMII mode:
* adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
* configures the RGMII pins
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2:
- removed the RK3368-prefix on bit-definitions for GMAC pinctrl
drivers/pinctrl/rockchip/pinctrl_rk3368.c | 36 +++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)
drivers/pinctrl/rockchip/pinctrl_rk3368.c +36 -0
@@ -52,6 +52,33 @@ static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv, } } +#if CONFIG_IS_ENABLED (GMAC_ROCKCHIP ) +static void pinctrl_rk3368_gmac_config (struct rk3368_grf *grf,int gmac_id) +{ +rk_clrsetreg (&grf->gpio3b_iomux, +GPIO3B0_MASK |GPIO3B1_MASK | +GPIO3B2_MASK |GPIO3B5_MASK | +GPIO3B6_MASK |GPIO3B7_MASK , +GPIO3B0_MAC_TXD0 |GPIO3B1_MAC_TXD1 | +GPIO3B2_MAC_TXD2 |GPIO3B5_MAC_TXEN | +GPIO3B6_MAC_TXD3 |GPIO3B7_MAC_RXD0 ); +rk_clrsetreg (&grf->gpio3c_iomux, +GPIO3C0_MASK |GPIO3C1_MASK | +GPIO3C2_MASK |GPIO3C3_MASK | +GPIO3C4_MASK |GPIO3C5_MASK | +GPIO3C6_MASK , +GPIO3C0_MAC_RXD1 |GPIO3C1_MAC_RXD2 | +GPIO3C2_MAC_RXD3 |GPIO3C3_MAC_MDC | +GPIO3C4_MAC_RXDV |GPIO3C5_MAC_RXEN | +GPIO3C6_MAC_CLK ); +rk_clrsetreg (&grf->gpio3d_iomux, +GPIO3D0_MASK |GPIO3D1_MASK | +GPIO3D4_MASK , +GPIO3D0_MAC_MDIO |GPIO3D1_MAC_RXCLK | +GPIO3D4_MAC_TXCLK ); +} +#endif +static int rk3368_pinctrl_request (struct udevice *dev,int func,int flags) {struct rk3368_pinctrl_priv *priv =dev_get_priv (dev);
@@ -65,6 +92,11 @@ static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)case PERIPH_ID_UART4 :pinctrl_rk3368_uart_config (priv, func);break ; +#if CONFIG_IS_ENABLED (GMAC_ROCKCHIP ) +case PERIPH_ID_GMAC : +pinctrl_rk3368_gmac_config (priv->grf, func); +break ; +#endif default :return -EINVAL ; }
@@ -94,6 +126,10 @@ static int rk3368_pinctrl_get_periph_id(struct udevice *dev,return PERIPH_ID_UART1 ;case 55 :return PERIPH_ID_UART0 ; +#if CONFIG_IS_ENABLED (GMAC_ROCKCHIP ) +case 27 : +return PERIPH_ID_GMAC ; +#endif }return -ENOENT ;
Signature · 1 line
2.1.4
PATCH v3 35/66 rockchip: pinctrl: rk3368: add support for configuring the MMC pins
In reply to Philipp TomsichThe RK3368 has two SD/MMC controllers that can be used from U-Boot both during SPL and for booting an OS from the full bootloader stage. While both are configured to (mostly) sensible settings from the BROM, additional configuration for the MMC controller is needed to configure it to 8bit mode.
This adds pinctrl support for the MMC controller.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2:
- removed the RK3368 prefix on the SD/MMC pin definitions
drivers/pinctrl/rockchip/pinctrl_rk3368.c | 48 +++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+)
drivers/pinctrl/rockchip/pinctrl_rk3368.c +48 -0
@@ -79,6 +79,46 @@ static void pinctrl_rk3368_gmac_config(struct rk3368_grf *grf, int gmac_id) }#endif +static void pinctrl_rk3368_sdmmc_config (struct rk3368_grf *grf,int mmc_id) +{ +switch (mmc_id) { +case PERIPH_ID_EMMC : +debug ("mmc id = %d setting registers!\n" , mmc_id); +rk_clrsetreg (&grf->gpio1c_iomux, +GPIO1C2_MASK |GPIO1C3_MASK | +GPIO1C4_MASK |GPIO1C5_MASK | +GPIO1C6_MASK |GPIO1C7_MASK , +GPIO1C2_EMMC_DATA0 | +GPIO1C3_EMMC_DATA1 | +GPIO1C4_EMMC_DATA2 | +GPIO1C5_EMMC_DATA3 | +GPIO1C6_EMMC_DATA4 | +GPIO1C7_EMMC_DATA5 ); +rk_clrsetreg (&grf->gpio1d_iomux, +GPIO1D0_MASK |GPIO1D1_MASK | +GPIO1D2_MASK |GPIO1D3_MASK , +GPIO1D0_EMMC_DATA6 | +GPIO1D1_EMMC_DATA7 | +GPIO1D2_EMMC_CMD | +GPIO1D3_EMMC_PWREN ); +rk_clrsetreg (&grf->gpio2a_iomux, +GPIO2A3_MASK |GPIO2A4_MASK , +GPIO2A3_EMMC_RSTNOUT | +GPIO2A4_EMMC_CLKOUT ); +break ; +case PERIPH_ID_SDCARD : +/* +* We assume that the BROM has already set this up +* correctly for us and that there's nothing to do +* here. +*/ +break ; +default : +debug ("mmc id = %d iomux error!\n" , mmc_id); +break ; + } +} +static int rk3368_pinctrl_request (struct udevice *dev,int func,int flags) {struct rk3368_pinctrl_priv *priv =dev_get_priv (dev);
@@ -92,6 +132,10 @@ static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)case PERIPH_ID_UART4 :pinctrl_rk3368_uart_config (priv, func);break ; +case PERIPH_ID_EMMC : +case PERIPH_ID_SDCARD : +pinctrl_rk3368_sdmmc_config (priv->grf, func); +break ;#if CONFIG_IS_ENABLED (GMAC_ROCKCHIP )case PERIPH_ID_GMAC :pinctrl_rk3368_gmac_config (priv->grf, func);
@@ -126,6 +170,10 @@ static int rk3368_pinctrl_get_periph_id(struct udevice *dev,return PERIPH_ID_UART1 ;case 55 :return PERIPH_ID_UART0 ; +case 35 : +return PERIPH_ID_EMMC ; +case 32 : +return PERIPH_ID_SDCARD ;#if CONFIG_IS_ENABLED (GMAC_ROCKCHIP )case 27 :return PERIPH_ID_GMAC ;
Signature · 1 line
2.1.4
PATCH v3 36/66 rockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl driver
In reply to Philipp TomsichThere is no real reason to keep the bit-definitions for the IOMUX in the grf header file (which defines the register layout of the GRF block):
these should only be used by our pinctrl driver (with the possible exception of early debug-init code in TPL/SPL).
This moves the relevant definitions from the grf_rk3368.h header into the pinctrl driver pinctrl_rk3368.c.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2:
- moved bit-definitions pertinent to pinctrl (i.e. the various IOMUX definitions) to the rk3368 pinctrl driver implementation
arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 316 ----------------------- drivers/pinctrl/rockchip/pinctrl_rk3368.c | 325 ++++++++++++++++++++++++ 2 files changed, 325 insertions(+), 316 deletions(-)
arch/arm/include/asm/arch-rockchip/grf_rk3368.h +0 -316
@@ -100,322 +100,6 @@ struct rk3368_pmu_grf {check_member (rk3368_pmu_grf, gpio0h_sr,0x34 );check_member (rk3368_pmu_grf, os_reg[0 ],0x200 ); -/*GRF_GPIO0C_IOMUX*/ -enum { -GPIO0C7_MASK =GENMASK (15 ,14 ), -GPIO0C7_GPIO =0 , -GPIO0C7_LCDC_D19 = (1 <<14 ), -GPIO0C7_TRACE_D9 = (2 <<14 ), -GPIO0C7_UART1_RTSN = (3 <<14 ), - -GPIO0C6_MASK =GENMASK (13 ,12 ), -GPIO0C6_GPIO =0 , -GPIO0C6_LCDC_D18 = (1 <<12 ), -GPIO0C6_TRACE_D8 = (2 <<12 ), -GPIO0C6_UART1_CTSN = (3 <<12 ), - -GPIO0C5_MASK =GENMASK (11 ,10 ), -GPIO0C5_GPIO =0 , -GPIO0C5_LCDC_D17 = (1 <<10 ), -GPIO0C5_TRACE_D7 = (2 <<10 ), -GPIO0C5_UART1_SOUT = (3 <<10 ), - -GPIO0C4_MASK =GENMASK (9 ,8 ), -GPIO0C4_GPIO =0 , -GPIO0C4_LCDC_D16 = (1 <<8 ), -GPIO0C4_TRACE_D6 = (2 <<8 ), -GPIO0C4_UART1_SIN = (3 <<8 ), - -GPIO0C3_MASK =GENMASK (7 ,6 ), -GPIO0C3_GPIO =0 , -GPIO0C3_LCDC_D15 = (1 <<6 ), -GPIO0C3_TRACE_D5 = (2 <<6 ), -GPIO0C3_MCU_JTAG_TDO = (3 <<6 ), - -GPIO0C2_MASK =GENMASK (5 ,4 ), -GPIO0C2_GPIO =0 , -GPIO0C2_LCDC_D14 = (1 <<4 ), -GPIO0C2_TRACE_D4 = (2 <<4 ), -GPIO0C2_MCU_JTAG_TDI = (3 <<4 ), - -GPIO0C1_MASK =GENMASK (3 ,2 ), -GPIO0C1_GPIO =0 , -GPIO0C1_LCDC_D13 = (1 <<2 ), -GPIO0C1_TRACE_D3 = (2 <<2 ), -GPIO0C1_MCU_JTAG_TRTSN = (3 <<2 ), - -GPIO0C0_MASK =GENMASK (1 ,0 ), -GPIO0C0_GPIO =0 , -GPIO0C0_LCDC_D12 = (1 <<0 ), -GPIO0C0_TRACE_D2 = (2 <<0 ), -GPIO0C0_MCU_JTAG_TDO = (3 <<0 ), -}; - -/*GRF_GPIO0D_IOMUX*/ -enum { -GPIO0D7_MASK =GENMASK (15 ,14 ), -GPIO0D7_GPIO =0 , -GPIO0D7_LCDC_DCLK = (1 <<14 ), -GPIO0D7_TRACE_CTL = (2 <<14 ), -GPIO0D7_PMU_DEBUG5 = (3 <<14 ), - -GPIO0D6_MASK =GENMASK (13 ,12 ), -GPIO0D6_GPIO =0 , -GPIO0D6_LCDC_DEN = (1 <<12 ), -GPIO0D6_TRACE_CLK = (2 <<12 ), -GPIO0D6_PMU_DEBUG4 = (3 <<12 ), - -GPIO0D5_MASK =GENMASK (11 ,10 ), -GPIO0D5_GPIO =0 , -GPIO0D5_LCDC_VSYNC = (1 <<10 ), -GPIO0D5_TRACE_D15 = (2 <<10 ), -GPIO0D5_PMU_DEBUG3 = (3 <<10 ), - -GPIO0D4_MASK =GENMASK (9 ,8 ), -GPIO0D4_GPIO =0 , -GPIO0D4_LCDC_HSYNC = (1 <<8 ), -GPIO0D4_TRACE_D14 = (2 <<8 ), -GPIO0D4_PMU_DEBUG2 = (3 <<8 ), - -GPIO0D3_MASK =GENMASK (7 ,6 ), -GPIO0D3_GPIO =0 , -GPIO0D3_LCDC_D23 = (1 <<6 ), -GPIO0D3_TRACE_D13 = (2 <<6 ), -GPIO0D3_UART4_SIN = (3 <<6 ), - -GPIO0D2_MASK =GENMASK (5 ,4 ), -GPIO0D2_GPIO =0 , -GPIO0D2_LCDC_D22 = (1 <<4 ), -GPIO0D2_TRACE_D12 = (2 <<4 ), -GPIO0D2_UART4_SOUT = (3 <<4 ), - -GPIO0D1_MASK =GENMASK (3 ,2 ), -GPIO0D1_GPIO =0 , -GPIO0D1_LCDC_D21 = (1 <<2 ), -GPIO0D1_TRACE_D11 = (2 <<2 ), -GPIO0D1_UART4_RTSN = (3 <<2 ), - -GPIO0D0_MASK =GENMASK (1 ,0 ), -GPIO0D0_GPIO =0 , -GPIO0D0_LCDC_D20 = (1 <<0 ), -GPIO0D0_TRACE_D10 = (2 <<0 ), -GPIO0D0_UART4_CTSN = (3 <<0 ), -}; - -/*GRF_GPIO2A_IOMUX*/ -enum { -GPIO2A7_MASK =GENMASK (15 ,14 ), -GPIO2A7_GPIO =0 , -GPIO2A7_SDMMC0_D2 = (1 <<14 ), -GPIO2A7_JTAG_TCK = (2 <<14 ), - -GPIO2A6_MASK =GENMASK (13 ,12 ), -GPIO2A6_GPIO =0 , -GPIO2A6_SDMMC0_D1 = (1 <<12 ), -GPIO2A6_UART2_SIN = (2 <<12 ), - -GPIO2A5_MASK =GENMASK (11 ,10 ), -GPIO2A5_GPIO =0 , -GPIO2A5_SDMMC0_D0 = (1 <<10 ), -GPIO2A5_UART2_SOUT = (2 <<10 ), - -GPIO2A4_MASK =GENMASK (9 ,8 ), -GPIO2A4_GPIO =0 , -GPIO2A4_FLASH_DQS = (1 <<8 ), -GPIO2A4_EMMC_CLKOUT = (2 <<8 ), - -GPIO2A3_MASK =GENMASK (7 ,6 ), -GPIO2A3_GPIO =0 , -GPIO2A3_FLASH_CSN3 = (1 <<6 ), -GPIO2A3_EMMC_RSTNOUT = (2 <<6 ), - -GPIO2A2_MASK =GENMASK (5 ,4 ), -GPIO2A2_GPIO =0 , -GPIO2A2_FLASH_CSN2 = (1 <<4 ), - -GPIO2A1_MASK =GENMASK (3 ,2 ), -GPIO2A1_GPIO =0 , -GPIO2A1_FLASH_CSN1 = (1 <<2 ), - -GPIO2A0_MASK =GENMASK (1 ,0 ), -GPIO2A0_GPIO =0 , -GPIO2A0_FLASH_CSN0 = (1 <<0 ), -}; - -/*GRF_GPIO2D_IOMUX*/ -enum { -GPIO2D7_MASK =GENMASK (15 ,14 ), -GPIO2D7_GPIO =0 , -GPIO2D7_SDIO0_D3 = (1 <<14 ), - -GPIO2D6_MASK =GENMASK (13 ,12 ), -GPIO2D6_GPIO =0 , -GPIO2D6_SDIO0_D2 = (1 <<12 ), - -GPIO2D5_MASK =GENMASK (11 ,10 ), -GPIO2D5_GPIO =0 , -GPIO2D5_SDIO0_D1 = (1 <<10 ), - -GPIO2D4_MASK =GENMASK (9 ,8 ), -GPIO2D4_GPIO =0 , -GPIO2D4_SDIO0_D0 = (1 <<8 ), - -GPIO2D3_MASK =GENMASK (7 ,6 ), -GPIO2D3_GPIO =0 , -GPIO2D3_UART0_RTS0 = (1 <<6 ), - -GPIO2D2_MASK =GENMASK (5 ,4 ), -GPIO2D2_GPIO =0 , -GPIO2D2_UART0_CTS0 = (1 <<4 ), - -GPIO2D1_MASK =GENMASK (3 ,2 ), -GPIO2D1_GPIO =0 , -GPIO2D1_UART0_SOUT = (1 <<2 ), - -GPIO2D0_MASK =GENMASK (1 ,0 ), -GPIO2D0_GPIO =0 , -GPIO2D0_UART0_SIN = (1 <<0 ), -}; - -/* GRF_GPIO1C_IOMUX */ -enum { -GPIO1C7_MASK =GENMASK (15 ,14 ), -GPIO1C7_GPIO =0 , -GPIO1C7_EMMC_DATA5 = (2 <<14 ), - -GPIO1C6_MASK =GENMASK (13 ,12 ), -GPIO1C6_GPIO =0 , -GPIO1C6_EMMC_DATA4 = (2 <<12 ), - -GPIO1C5_MASK =GENMASK (11 ,10 ), -GPIO1C5_GPIO =0 , -GPIO1C5_EMMC_DATA3 = (2 <<10 ), - -GPIO1C4_MASK =GENMASK (9 ,8 ), -GPIO1C4_GPIO =0 , -GPIO1C4_EMMC_DATA2 = (2 <<8 ), - -GPIO1C3_MASK =GENMASK (7 ,6 ), -GPIO1C3_GPIO =0 , -GPIO1C3_EMMC_DATA1 = (2 <<6 ), - -GPIO1C2_MASK =GENMASK (5 ,4 ), -GPIO1C2_GPIO =0 , -GPIO1C2_EMMC_DATA0 = (2 <<4 ), -}; - -/* GRF_GPIO1D_IOMUX*/ -enum { -GPIO1D3_MASK =GENMASK (7 ,6 ), -GPIO1D3_GPIO =0 , -GPIO1D3_EMMC_PWREN = (2 <<6 ), - -GPIO1D2_MASK =GENMASK (5 ,4 ), -GPIO1D2_GPIO =0 , -GPIO1D2_EMMC_CMD = (2 <<4 ), - -GPIO1D1_MASK =GENMASK (3 ,2 ), -GPIO1D1_GPIO =0 , -GPIO1D1_EMMC_DATA7 = (2 <<2 ), - -GPIO1D0_MASK =GENMASK (1 ,0 ), -GPIO1D0_GPIO =0 , -GPIO1D0_EMMC_DATA6 = (2 <<0 ), -}; - - -/*GRF_GPIO3B_IOMUX*/ -enum { -GPIO3B7_MASK =GENMASK (15 ,14 ), -GPIO3B7_GPIO =0 , -GPIO3B7_MAC_RXD0 = (1 <<14 ), - -GPIO3B6_MASK =GENMASK (13 ,12 ), -GPIO3B6_GPIO =0 , -GPIO3B6_MAC_TXD3 = (1 <<12 ), - -GPIO3B5_MASK =GENMASK (11 ,10 ), -GPIO3B5_GPIO =0 , -GPIO3B5_MAC_TXEN = (1 <<10 ), - -GPIO3B4_MASK =GENMASK (9 ,8 ), -GPIO3B4_GPIO =0 , -GPIO3B4_MAC_COL = (1 <<8 ), - -GPIO3B3_MASK =GENMASK (7 ,6 ), -GPIO3B3_GPIO =0 , -GPIO3B3_MAC_CRS = (1 <<6 ), - -GPIO3B2_MASK =GENMASK (5 ,4 ), -GPIO3B2_GPIO =0 , -GPIO3B2_MAC_TXD2 = (1 <<4 ), - -GPIO3B1_MASK =GENMASK (3 ,2 ), -GPIO3B1_GPIO =0 , -GPIO3B1_MAC_TXD1 = (1 <<2 ), - -GPIO3B0_MASK =GENMASK (1 ,0 ), -GPIO3B0_GPIO =0 , -GPIO3B0_MAC_TXD0 = (1 <<0 ), -GPIO3B0_PWM0 = (2 <<0 ), -}; - -/*GRF_GPIO3C_IOMUX*/ -enum { -GPIO3C6_MASK =GENMASK (13 ,12 ), -GPIO3C6_GPIO =0 , -GPIO3C6_MAC_CLK = (1 <<12 ), - -GPIO3C5_MASK =GENMASK (11 ,10 ), -GPIO3C5_GPIO =0 , -GPIO3C5_MAC_RXEN = (1 <<10 ), - -GPIO3C4_MASK =GENMASK (9 ,8 ), -GPIO3C4_GPIO =0 , -GPIO3C4_MAC_RXDV = (1 <<8 ), - -GPIO3C3_MASK =GENMASK (7 ,6 ), -GPIO3C3_GPIO =0 , -GPIO3C3_MAC_MDC = (1 <<6 ), - -GPIO3C2_MASK =GENMASK (5 ,4 ), -GPIO3C2_GPIO =0 , -GPIO3C2_MAC_RXD3 = (1 <<4 ), - -GPIO3C1_MASK =GENMASK (3 ,2 ), -GPIO3C1_GPIO =0 , -GPIO3C1_MAC_RXD2 = (1 <<2 ), - -GPIO3C0_MASK =GENMASK (1 ,0 ), -GPIO3C0_GPIO =0 , -GPIO3C0_MAC_RXD1 = (1 <<0 ), -}; - -/*GRF_GPIO3D_IOMUX*/ -enum { -GPIO3D4_MASK =GENMASK (9 ,8 ), -GPIO3D4_GPIO =0 , -GPIO3D4_MAC_TXCLK = (1 <<8 ), - -GPIO3D1_MASK =GENMASK (3 ,2 ), -GPIO3D1_GPIO =0 , -GPIO3D1_MAC_RXCLK = (1 <<2 ), - -GPIO3D0_MASK =GENMASK (1 ,0 ), -GPIO3D0_GPIO =0 , -GPIO3D0_MAC_MDIO = (1 <<0 ), -}; - -/* GRF_SOC_CON0 */ -enum { -NOC_RSP_ERR_STALL =BIT (9 ), -MOBILE_DDR_SEL =BIT (4 ), -DDR0_16BIT_EN =BIT (3 ), -MSCH0_MAINDDR3_DDR3 =BIT (2 ), -MSCH0_MAINPARTIALPOP =BIT (1 ), -UPCTL_C_ACTIVE =BIT (0 ), -}; -/*GRF_SOC_CON11/12/13*/ enum {MCU_SRAM_BASE_BIT27_BIT12_SHIFT =0 ,
drivers/pinctrl/rockchip/pinctrl_rk3368.c +325 -0
331 lines not on this page · raw message
Signature · 1 line
2.1.4
PATCH v3 37/66 rockchip: pinctrl: rk3368: add SPI support
In reply to Philipp TomsichTo implement pinctrl support for the RK3368, we need to add the bit-definitions to configure the IOMUX and tie these into the pinctrl framework. This also adds the mapping from the IRQ# back onto the periheral id for the SPI devices.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
drivers/pinctrl/rockchip/pinctrl_rk3368.c | 90 +++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+)
drivers/pinctrl/rockchip/pinctrl_rk3368.c +90 -0
@@ -1,8 +1,11 @@/* * (C) Copyright 2017 Rockchip Electronics Co., Ltd * Author: Andy Yan <[email protected]> +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* * SPDX-License-Identifier: GPL-2.0+ */ +#include <common.h> #include <dm.h> #include <errno.h>
@@ -16,6 +19,25 @@DECLARE_GLOBAL_DATA_PTR ; +/* PMUGRF_GPIO0B_IOMUX */ +enum { +GPIO0B5_MASK =GENMASK (11 ,10 ), +GPIO0B5_GPIO =0 , +GPIO0B5_SPI2_CSN0 = (2 <<10 ), + +GPIO0B4_MASK =GENMASK (9 ,8 ), +GPIO0B4_GPIO =0 , +GPIO0B4_SPI2_CLK = (2 <<8 ), + +GPIO0B3_MASK =GENMASK (7 ,6 ), +GPIO0B3_GPIO =0 , +GPIO0B3_SPI2_TXD = (2 <<6 ), + +GPIO0B2_MASK =GENMASK (5 ,4 ), +GPIO0B2_GPIO =0 , +GPIO0B2_SPI2_RXD = (2 <<4 ), +}; +/*GRF_GPIO0C_IOMUX*/ enum {GPIO0C7_MASK =GENMASK (15 ,14 ),
@@ -209,10 +231,12 @@ enum {GPIO1C7_MASK =GENMASK (15 ,14 ),GPIO1C7_GPIO =0 ,GPIO1C7_EMMC_DATA5 = (2 <<14 ), +GPIO1C7_SPI0_TXD = (3 <<14 ),GPIO1C6_MASK =GENMASK (13 ,12 ),GPIO1C6_GPIO =0 ,GPIO1C6_EMMC_DATA4 = (2 <<12 ), +GPIO1C6_SPI0_RXD = (3 <<12 ),GPIO1C5_MASK =GENMASK (11 ,10 ), GPIO1C5_GPIO = 0,
@@ -241,6 +265,10 @@ enum {/* GRF_GPIO1D_IOMUX*/ enum { +GPIO1D5_MASK =GENMASK (11 ,10 ), +GPIO1D5_GPIO =0 , +GPIO1D5_SPI0_CLK = (2 <<10 ), +GPIO1D3_MASK =GENMASK (7 ,6 ),GPIO1D3_GPIO =0 ,GPIO1D3_EMMC_PWREN = (2 <<6 ),
@@ -252,10 +280,12 @@ enum {GPIO1D1_MASK =GENMASK (3 ,2 ),GPIO1D1_GPIO =0 ,GPIO1D1_EMMC_DATA7 = (2 <<2 ), +GPIO1D1_SPI0_CSN1 = (3 <<2 ),GPIO1D0_MASK =GENMASK (1 ,0 ),GPIO1D0_GPIO =0 ,GPIO1D0_EMMC_DATA6 = (2 <<0 ), + GPIO1D0_SPI0_CSN0 = (3 << 0), };
@@ -331,6 +361,7 @@ enum {GPIO3D4_MASK =GENMASK (9 ,8 ),GPIO3D4_GPIO =0 ,GPIO3D4_MAC_TXCLK = (1 <<8 ), +GPIO3D4_SPI1_CNS1 = (2 <<8 ),GPIO3D1_MASK =GENMASK (3 ,2 ), GPIO3D1_GPIO = 0,
@@ -377,6 +408,54 @@ static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv, } } +static void pinctrl_rk3368_spi_config (struct rk3368_pinctrl_priv *priv, +int spi_id) +{ +struct rk3368_grf *grf = priv->grf; +struct rk3368_pmu_grf *pmugrf = priv->pmugrf; + +switch (spi_id) { +case PERIPH_ID_SPI0 : +/* +* eMMC can only be connected with 4 bits, when SPI0 is used. +* This is all-or-nothing, so we assume that if someone asks us +* to configure SPI0, that their eMMC interface is unused or +* configured appropriately. +*/ +rk_clrsetreg (&grf->gpio1d_iomux, +GPIO1D0_MASK |GPIO1D1_MASK | +GPIO1D5_MASK , +GPIO1D0_SPI0_CSN0 |GPIO1D1_SPI0_CSN1 | +GPIO1D5_SPI0_CLK ); +rk_clrsetreg (&grf->gpio1c_iomux, +GPIO1C6_MASK |GPIO1C7_MASK , +GPIO1C6_SPI0_RXD |GPIO1C7_SPI0_TXD ); +break ; +case PERIPH_ID_SPI1 : +/* +* We don't implement support for configuring SPI1_CSN#1, as it +* will conflicts with the GMAC (MAC TX clk-out). +*/ +rk_clrsetreg (&grf->gpio1b_iomux, +GPIO1B6_MASK |GPIO1B7_MASK , +GPIO1B6_SPI1_CLK |GPIO1B7_SPI1_CSN0 ); +rk_clrsetreg (&grf->gpio1c_iomux, +GPIO1C0_MASK |GPIO1C1_MASK , +GPIO1C0_SPI1_TXD |GPIO1C1_SPI1_RXD ); +break ; +case PERIPH_ID_SPI2 : +rk_clrsetreg (&pmugrf->gpio0b_iomux, +GPIO0B2_MASK |GPIO0B3_MASK | +GPIO0B4_MASK |GPIO0B5_MASK , +GPIO0B2_SPI2_RXD |GPIO0B3_SPI2_TXD | +GPIO0B4_SPI2_CLK |GPIO0B5_SPI2_CSN0 ); +break ; +default : +debug ("%s: spi id = %d iomux error!\n" , __func__, spi_id); +break ; + } +} +#if CONFIG_IS_ENABLED (GMAC_ROCKCHIP )static void pinctrl_rk3368_gmac_config (struct rk3368_grf *grf,int gmac_id) {
@@ -457,6 +536,11 @@ static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)case PERIPH_ID_UART4 :pinctrl_rk3368_uart_config (priv, func);break ; +case PERIPH_ID_SPI0 : +case PERIPH_ID_SPI1 : +case PERIPH_ID_SPI2 : +pinctrl_rk3368_spi_config (priv, func); +break ;case PERIPH_ID_EMMC :case PERIPH_ID_SDCARD :pinctrl_rk3368_sdmmc_config (priv->grf, func);
@@ -495,6 +579,12 @@ static int rk3368_pinctrl_get_periph_id(struct udevice *dev,return PERIPH_ID_UART1 ;case 55 :return PERIPH_ID_UART0 ; +case 44 : +return PERIPH_ID_SPI0 ; +case 45 : +return PERIPH_ID_SPI1 ; +case 41 : +return PERIPH_ID_SPI2 ;case 35 :return PERIPH_ID_EMMC ;case 32 :
Signature · 1 line
2.1.4
PATCH v3 38/66 rockchip: clk: rk3368: implement bandwidth adjust for PLLs
In reply to Philipp TomsichThe RK3368 TRM recommends to configure the bandwith adjustment (CON2) for PLLs to NF/2. This implements this for all reconfigurations of PLLs and removes the 'has_bwadj' flag (as the RK3368 always has the bandwidth-adjustment feature according to its manual).
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk_rk3368.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-)
drivers/clk/rockchip/clk_rk3368.c +12 -5
@@ -1,6 +1,7 @@/* * (C) Copyright 2017 Rockchip Electronics Co., Ltd * Author: Andy Yan <[email protected]> +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH * SPDX-License-Identifier: GPL-2.0 */
@@ -74,7 +75,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru, }static int rkclk_set_pll (struct rk3368_cru *cru,enum rk3368_pll_id pll_id, -const struct pll_div *div,bool has_bwadj) +const struct pll_div *div) {struct rk3368_pll *pll = &cru->pll[pll_id];/* All PLLs have same VCO and output frequency range restrictions*/
@@ -92,6 +93,12 @@ static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, ((div->nr -1 ) <<PLL_NR_SHIFT ) | ((div->no - 1) << PLL_OD_SHIFT));writel ((div->nf -1 ) <<PLL_NF_SHIFT , &pll->con1); +/* +* BWADJ should be set to NF / 2 to ensure the nominal bandwidth. +* Compare the RK3368 TRM, section "3.6.4 PLL Bandwidth Adjustment". +*/ +clrsetbits_le32 (&pll->con2,PLL_BWADJ_MASK , (div->nf >>1 ) -1 ); +udelay (10 );/* return from reset */
@@ -111,10 +118,10 @@ static void rkclk_init(struct rk3368_cru *cru) {u32 apllb, aplll, dpll, cpll, gpll; -rkclk_set_pll (cru,APLLB , &apll_b_init_cfg, false); -rkclk_set_pll (cru,APLLL , &apll_l_init_cfg, false); -rkclk_set_pll (cru,GPLL , &gpll_init_cfg, false); -rkclk_set_pll (cru,CPLL , &cpll_init_cfg, false); +rkclk_set_pll (cru,APLLB , &apll_b_init_cfg); +rkclk_set_pll (cru,APLLL , &apll_l_init_cfg); +rkclk_set_pll (cru,GPLL , &gpll_init_cfg); +rkclk_set_pll (cru,CPLL , &cpll_init_cfg); apllb =rkclk_pll_get_rate (cru,APLLB ); aplll =rkclk_pll_get_rate (cru,APLLL );
Signature · 1 line
2.1.4
PATCH v3 39/66 rockchip: clk: rk3368: support OF_PLATDATA for the RK3368 clk driver
In reply to Philipp TomsichWith the RK3368's limited TPL size, we'll want to use OF_PLATFDATA for the SPL stage. This implements support for OF_PLATDATA in the clock driver for the RK3368.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk_rk3368.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
drivers/clk/rockchip/clk_rk3368.c +17 -0
@@ -8,7 +8,9 @@#include <common.h> #include <clk-uclass.h> #include <dm.h> +#include <dt-structs.h> #include <errno.h> +#include <mapmem.h> #include <syscon.h> #include <asm/arch/clock.h> #include <asm/arch/cru_rk3368.h>
@@ -19,6 +21,12 @@DECLARE_GLOBAL_DATA_PTR ; +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +struct rk3368_clk_plat { +struct dtd_rockchip_rk3368_cru dtd; +}; +#endif +struct pll_div {u32 nr;u32 nf;
@@ -254,7 +262,11 @@ static struct clk_ops rk3368_clk_ops = {static int rk3368_clk_probe (struct udevice *dev) {struct rk3368_clk_priv *priv =dev_get_priv (dev); +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +struct rk3368_clk_plat *plat =dev_get_platdata (dev); + priv->cru =map_sysmem (plat->dtd.reg[1 ], plat->dtd.reg[3 ]); +#endif rkclk_init (priv->cru);return 0 ;
@@ -262,9 +274,11 @@ static int rk3368_clk_probe(struct udevice *dev)static int rk3368_clk_ofdata_to_platdata (struct udevice *dev) { +#if !CONFIG_IS_ENABLED (OF_PLATDATA )struct rk3368_clk_priv *priv =dev_get_priv (dev); priv->cru = (struct rk3368_cru *)devfdt_get_addr (dev); +#endif return 0 ; }
@@ -291,6 +305,9 @@ U_BOOT_DRIVER(rockchip_rk3368_cru) = { .id = UCLASS_CLK, .of_match = rk3368_clk_ids, .priv_auto_alloc_size = sizeof(struct rk3368_clk_priv), +#if CONFIG_IS_ENABLED(OF_PLATDATA) + .platdata_auto_alloc_size = sizeof(struct rk3368_clk_plat), +#endif .ofdata_to_platdata = rk3368_clk_ofdata_to_platdata, .ops = &rk3368_clk_ops, .bind = rk3368_clk_bind,
Signature · 1 line
2.1.4
PATCH v3 40/66 rockchip: clk: rk3368: do not change CPLL/GPLL before returning to BROM
In reply to Philipp TomsichThe RK3368 has a somewhat temperamental BootROM (which I learned the hard way) when it comes to reconfiguring the CPLL and GPLL (in fact, experiments show that changing the GPLL broke things for me, while changing the CPLL seems to be more benign). These should not be modified by the SPL stage, if we intend to return to the BootROM for chain booting the next stage.
This commit changes the clock initialisation to not change CPLL/GPLL before returning to the BootROM (i.e. in TPL). As it's safe to change these settings if we no longer intend to return to U-Boot, we'll run the full PLL setup a little later (i.e. in SPL).
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk_rk3368.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)
drivers/clk/rockchip/clk_rk3368.c +17 -1
@@ -50,10 +50,14 @@ struct pll_div { (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \ "divisors on line " __stringify(__LINE__)); +#if IS_ENABLED (CONFIG_SPL_BUILD ) ||IS_ENABLED (CONFIG_TPL_BUILD )static const struct pll_div apll_l_init_cfg =PLL_DIVISORS (APLL_L_HZ ,12 ,2 );static const struct pll_div apll_b_init_cfg =PLL_DIVISORS (APLL_B_HZ ,1 ,2 ); +#if !defined(CONFIG_TPL_BUILD )static const struct pll_div gpll_init_cfg =PLL_DIVISORS (GPLL_HZ ,1 ,2 );static const struct pll_div cpll_init_cfg =PLL_DIVISORS (CPLL_HZ ,1 ,6 ); +#endif +#endif /* Get pll rate by id */ static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
@@ -82,6 +86,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru, } } +#if IS_ENABLED (CONFIG_SPL_BUILD ) ||IS_ENABLED (CONFIG_TPL_BUILD )static int rkclk_set_pll (struct rk3368_cru *cru,enum rk3368_pll_id pll_id,const struct pll_div *div) {
@@ -121,15 +126,23 @@ static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,return 0 ; } +#endif +#if IS_ENABLED (CONFIG_SPL_BUILD ) ||IS_ENABLED (CONFIG_TPL_BUILD )static void rkclk_init (struct rk3368_cru *cru) {u32 apllb, aplll, dpll, cpll, gpll;rkclk_set_pll (cru,APLLB , &apll_b_init_cfg);rkclk_set_pll (cru,APLLL , &apll_l_init_cfg); +#if !defined(CONFIG_TPL_BUILD ) +/* +* If we plan to return to the boot ROM, we can't increase the +* GPLL rate from the SPL stage. +*/ rkclk_set_pll (cru,GPLL , &gpll_init_cfg);rkclk_set_pll (cru,CPLL , &cpll_init_cfg); +#endif apllb =rkclk_pll_get_rate (cru,APLLB ); aplll =rkclk_pll_get_rate (cru,APLLL );
@@ -140,6 +153,7 @@ static void rkclk_init(struct rk3368_cru *cru)debug ("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n" , __func__, apllb, aplll, dpll, cpll, gpll); } +#endif static ulong rk3368_mmc_get_clk (struct rk3368_cru *cru,uint clk_id) {
@@ -261,13 +275,15 @@ static struct clk_ops rk3368_clk_ops = {static int rk3368_clk_probe (struct udevice *dev) { -struct rk3368_clk_priv *priv =dev_get_priv (dev); +struct rk3368_clk_priv __maybe_unused *priv =dev_get_priv (dev);#if CONFIG_IS_ENABLED (OF_PLATDATA )struct rk3368_clk_plat *plat =dev_get_platdata (dev); priv->cru =map_sysmem (plat->dtd.reg[1 ], plat->dtd.reg[3 ]);#endif +#if IS_ENABLED (CONFIG_SPL_BUILD ) ||IS_ENABLED (CONFIG_TPL_BUILD )rkclk_init (priv->cru); +#endif return 0 ; }
Signature · 1 line
2.1.4
PATCH v3 41/66 rockchip: clk: rk3368: implement DPLL (DRAM PLL) support
In reply to Philipp TomsichTo implement a TPL stage (incl. its DRAM controller setup) for the RK3368, we'll want to configure the DPLL (DRAM PLL).
This commit implements setting the DPLL (CLK_DDR) and provides PLL configuration details for the common DRAM operating speeds found on RK3368 boards.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk_rk3368.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)
drivers/clk/rockchip/clk_rk3368.c +35 -0
@@ -250,6 +250,37 @@ static ulong rk3368_clk_get_rate(struct clk *clk)return rate; } +static ulong rk3368_ddr_set_clk (struct rk3368_cru *cru,ulong set_rate) +{ +const struct pll_div *dpll_cfg =NULL ; +const ulong MHz =1000000 ; + +/* Fout = ((Fin /NR) * NF )/ NO */ +static const struct pll_div dpll_1200 = +PLL_DIVISORS (1200 * MHz,1 ,1 ); +static const struct pll_div dpll_1332 = +PLL_DIVISORS (1332 * MHz,2 ,1 ); +static const struct pll_div dpll_1600 = +PLL_DIVISORS (1600 * MHz,3 ,2 ); + +switch (set_rate) { +case 1200 *MHz: + dpll_cfg = &dpll_1200; +break ; +case 1332 *MHz: + dpll_cfg = &dpll_1332; +break ; +case 1600 *MHz: + dpll_cfg = &dpll_1600; +break ; +default : +error ("Unsupported SDRAM frequency!,%ld\n" , set_rate); + } +rkclk_set_pll (cru,DPLL , dpll_cfg); + +return set_rate; +} +static ulong rk3368_clk_set_rate (struct clk *clk,ulong rate) {struct rk3368_clk_priv *priv =dev_get_priv (clk->dev);
@@ -257,6 +288,10 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)debug ("%s id:%ld rate:%ld\n" , __func__, clk->id, rate);switch (clk->id) { +case CLK_DDR : + ret =rk3368_ddr_set_clk (priv->cru, rate); +break ; +case SCLK_SDMMC :case SCLK_EMMC : ret =rk3368_mmc_set_clk (priv->cru, clk->id, rate);
Signature · 1 line
2.1.4
PATCH v3 42/66 rockchip: clk: rk3368: define DMA1_SRST_REQ and DMA2_SRST_REQ
In reply to Philipp TomsichOn he RK3368, we need to temporarily disable security on the DMA engines during TPL and SPL to allow the MMC host to DMA into DRAM. To do so, we need to reset the two DMA engines, which in turn requires the DMA1_SRST_REQ and DMA2_SRST_REQ constants to refer to the appropriate bits in the CRU.
As the ATF correctly initialises security (and only leaves EL3 after doing so), this can not pose a security issue.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm/include/asm/arch-rockchip/cru_rk3368.h +4 -0
@@ -102,6 +102,10 @@ enum {/* SOFTRST1_CON */ MCU_PO_SRST_MASK =BIT (13 ),MCU_SYS_SRST_MASK =BIT (12 ), +DMA1_SRST_REQ =BIT (2 ), + +/* SOFTRST4_CON */ +DMA2_SRST_REQ =BIT (0 ),/* GLB_RST_CON */ PMU_GLB_SRST_CTRL_SHIFT = 2,
Signature · 1 line
2.1.4
PATCH v3 43/66 rockchip: clk: rk3368: implement MMC/SD clock reparenting
In reply to Philipp TomsichThe original clock support for MMC/SD cards on the RK3368 suffered from a tendency to select a divider less-or-equal to the the one giving the requested clock-rate: this can lead to higher-than-expected (or rather: higher than supported) clock rates for the MMC/SD communiction.
This change rewrites the MMC/SD clock generation to:
* always generate a clock less-than-or-equal to the requested clock
* support reparenting among the CPLL, GPLL and OSC24M parents to generate the highest clock that does not exceed the requested rate
In addition to this, the Linux DTS uses HCLK_MMC/HCLK_SDMMC instead of SCLK_MMC/SCLK_SDMMC: to match this (and to ensure that clock setup always works), we adjust the driver appropriately.
This includes the changes from:
- rockchip: clk: rk3368: convert MMC_PLL_SEL_* definitions to shifted-value form
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 8 +- drivers/clk/rockchip/clk_rk3368.c | 119 ++++++++++++++++++------ 2 files changed, 95 insertions(+), 32 deletions(-)
arch/arm/include/asm/arch-rockchip/cru_rk3368.h +4 -4
@@ -92,10 +92,10 @@ enum {/* CLKSEL51_CON */ MMC_PLL_SEL_SHIFT =8 ,MMC_PLL_SEL_MASK =GENMASK (9 ,8 ), -MMC_PLL_SEL_CPLL =0 , -MMC_PLL_SEL_GPLL , -MMC_PLL_SEL_USBPHY_480M , -MMC_PLL_SEL_24M , +MMC_PLL_SEL_CPLL = (0 <<MMC_PLL_SEL_SHIFT ), +MMC_PLL_SEL_GPLL = (1 <<MMC_PLL_SEL_SHIFT ), +MMC_PLL_SEL_USBPHY_480M = (2 <<MMC_PLL_SEL_SHIFT ), +MMC_PLL_SEL_24M = (3 <<MMC_PLL_SEL_SHIFT ),MMC_CLK_DIV_SHIFT =0 , MMC_CLK_DIV_MASK = GENMASK(6, 0),
drivers/clk/rockchip/clk_rk3368.c +91 -28
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Signature · 1 line
2.1.4
PATCH v3 44/66 rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL)
In reply to Philipp TomsichAs part of the DRAM initialisation process (running as part of the TPL stage) on the RK3368, we need to set up the DRAM PLL.
This implements support for configuring the PLL to for 1200, 1332 or 1600 MHz (i.e. for DDR3-1200, DDR3-1333, DDR3-1600 operating modes).
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk_rk3368.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-)
drivers/clk/rockchip/clk_rk3368.c +7 -6
@@ -308,18 +308,16 @@ static ulong rk3368_clk_get_rate(struct clk *clk)return rate; } +#if IS_ENABLED (CONFIG_TPL_BUILD )static ulong rk3368_ddr_set_clk (struct rk3368_cru *cru,ulong set_rate) {const struct pll_div *dpll_cfg =NULL ;const ulong MHz =1000000 ;/* Fout = ((Fin /NR) * NF )/ NO */ -static const struct pll_div dpll_1200 = -PLL_DIVISORS (1200 * MHz,1 ,1 ); -static const struct pll_div dpll_1332 = -PLL_DIVISORS (1332 * MHz,2 ,1 ); -static const struct pll_div dpll_1600 = -PLL_DIVISORS (1600 * MHz,3 ,2 ); +static const struct pll_div dpll_1200 =PLL_DIVISORS (1200 * MHz,1 ,1 ); +static const struct pll_div dpll_1332 =PLL_DIVISORS (1332 * MHz,2 ,1 ); +static const struct pll_div dpll_1600 =PLL_DIVISORS (1600 * MHz,3 ,2 );switch (set_rate) {case 1200 *MHz:
@@ -338,6 +336,7 @@ static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate) return set_rate; } +#endif static ulong rk3368_clk_set_rate (struct clk *clk,ulong rate) {
@@ -346,9 +345,11 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)debug ("%s id:%ld rate:%ld\n" , __func__, clk->id, rate);switch (clk->id) { +#if IS_ENABLED (CONFIG_TPL_BUILD )case CLK_DDR : ret =rk3368_ddr_set_clk (priv->cru, rate);break ; +#endif #if !IS_ENABLED (CONFIG_SPL_BUILD ) ||CONFIG_IS_ENABLED (MMC_SUPPORT )case HCLK_SDMMC :case HCLK_EMMC :
Signature · 1 line
2.1.4
PATCH v3 45/66 rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock
In reply to Philipp TomsichTo enable the GMAC on the RK3368, we need to set up the clocking appropriately to generate a tx_clk for the MAC.
This adds an implementation that implements the use of the <&ext_gmac> clock (i.e. an external 125MHz clock for RGMII provided by the PHY). This is the clock setup used by the boards currently supported by U-Boot (i.e. Geekbox, Sheep and RK3368-uQ7).
This includes the change from commit
- rockchip: clk: rk3368: define GMAC_MUX_SEL_EXTCLK
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 3 +++ drivers/clk/rockchip/clk_rk3368.c | 19 +++++++++++++++++-- 2 files changed, 20 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/cru_rk3368.h +3 -0
@@ -89,6 +89,9 @@ enum {MCU_CLK_DIV_SHIFT =0 ,MCU_CLK_DIV_MASK =GENMASK (4 ,0 ), +/* CLKSEL43_CON */ +GMAC_MUX_SEL_EXTCLK =BIT (8 ), +/* CLKSEL51_CON */ MMC_PLL_SEL_SHIFT =8 , MMC_PLL_SEL_MASK = GENMASK(9, 8),
drivers/clk/rockchip/clk_rk3368.c +17 -2
@@ -338,6 +338,19 @@ static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate) }#endif +#if CONFIG_IS_ENABLED (GMAC_ROCKCHIP ) +static ulong rk3368_gmac_set_clk (struct rk3368_cru *cru, +ulong clk_id,ulong set_rate) +{ +/* +* This models the 'assigned-clock-parents = <&ext_gmac>' from +* the DTS and switches to the 'ext_gmac' clock parent. +*/ +rk_setreg (&cru->clksel_con[43 ],GMAC_MUX_SEL_EXTCLK ); +return set_rate; +} +#endif +static ulong rk3368_clk_set_rate (struct clk *clk,ulong rate) {struct rk3368_clk_priv *priv =dev_get_priv (clk->dev);
@@ -356,10 +369,12 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) ret =rk3368_mmc_set_clk (clk, rate);break ;#endif +#if CONFIG_IS_ENABLED (GMAC_ROCKCHIP )case SCLK_MAC : -/* nothing to do, as this is an external clock */ - ret = rate; +/* select the external clock */ + ret =rk3368_gmac_set_clk (priv->cru, clk->id, rate);break ; +#endif default :return -ENOENT ; }
Signature · 1 line
2.1.4
PATCH v3 46/66 rockchip: clk: rk3368: mark 'priv' __maybe_unused in rk3368_clk_set_rate()
In reply to Philipp TomsichWith the clock support in rk3368_clk_set_rate() conditionalized on various feature definitions, 'priv' can remain unused (e.g. in the SPL build when only MMC is enabled).
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk_rk3368.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/rockchip/clk_rk3368.c +1 -1
@@ -353,7 +353,7 @@ static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru,static ulong rk3368_clk_set_rate (struct clk *clk,ulong rate) { -struct rk3368_clk_priv *priv =dev_get_priv (clk->dev); +__maybe_unused struct rk3368_clk_priv *priv =dev_get_priv (clk->dev);ulong ret =0 ;debug ("%s id:%ld rate:%ld\n" , __func__, clk->id, rate);
Signature · 1 line
2.1.4
PATCH v3 47/66 rockchip: clk: rk3368: add support for configuring the SPI clocks
In reply to Philipp TomsichAs SPI support may be useful in the boot-flow, this adds support for configuring the SPI controller's clocks in the RK3368 clock driver.
Reviewed-by Simon Glass <[email protected]>
Signed-off-by Philipp Tomsich <[email protected]>
---
Changes in v3: None
Changes in v2:
- added SPI clock setup
drivers/clk/rockchip/clk_rk3368.c | 132 ++++++++++++++++++++++++++++++-------- 1 file changed, 106 insertions(+), 26 deletions(-)
drivers/clk/rockchip/clk_rk3368.c +106 -26
@@ -282,32 +282,6 @@ static ulong rk3368_mmc_set_clk(struct clk *clk, ulong rate) }#endif -static ulong rk3368_clk_get_rate (struct clk *clk) -{ -struct rk3368_clk_priv *priv =dev_get_priv (clk->dev); -ulong rate =0 ; - -debug ("%s: id %ld\n" , __func__, clk->id); -switch (clk->id) { -case PLL_CPLL : - rate =rkclk_pll_get_rate (priv->cru,CPLL ); -break ; -case PLL_GPLL : - rate =rkclk_pll_get_rate (priv->cru,GPLL ); -break ; -#if !IS_ENABLED (CONFIG_SPL_BUILD ) ||CONFIG_IS_ENABLED (MMC_SUPPORT ) -case HCLK_SDMMC : -case HCLK_EMMC : - rate =rk3368_mmc_get_clk (priv->cru, clk->id); -break ; -#endif -default : -return -ENOENT ; - } - -return rate; -} -#if IS_ENABLED (CONFIG_TPL_BUILD )static ulong rk3368_ddr_set_clk (struct rk3368_cru *cru,ulong set_rate) {
@@ -351,6 +325,109 @@ static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru, }#endif +/* +* RK3368 SPI clocks have a common divider-width (7 bits) and a single bit +* to select either CPLL or GPLL as the clock-parent. The location within +* the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable. +*/ + +struct spi_clkreg { +uint8_t reg;/* CLKSEL_CON[reg] register in CRU */ +uint8_t div_shift; +uint8_t sel_shift; +}; + +/* +* The entries are numbered relative to their offset from SCLK_SPI0. +*/ +static const struct spi_clkreg spi_clkregs[] = { + [0 ] = { .reg =45 , .div_shift =0 , .sel_shift =7 , }, + [1 ] = { .reg =45 , .div_shift =8 , .sel_shift =15 , }, + [2 ] = { .reg =46 , .div_shift =8 , .sel_shift =15 , }, +}; + +static inline u32 extract_bits (u32 val,unsigned width,unsigned shift) +{ +return (val >> shift) & ((1 << width) -1 ); +} + +static ulong rk3368_spi_get_clk (struct rk3368_cru *cru,ulong clk_id) +{ +const struct spi_clkreg *spiclk =NULL ; +u32 div, val; + +switch (clk_id) { + case SCLK_SPI0 ... SCLK_SPI2: + spiclk = &spi_clkregs[clk_id -SCLK_SPI0 ]; +break ; + +default : +error ("%s: SPI clk-id %ld not supported\n" , __func__, clk_id); +return -EINVAL ; + } + + val =readl (&cru->clksel_con[spiclk->reg]); + div =extract_bits (val,7 , spiclk->div_shift); + +debug ("%s: div 0x%x\n" , __func__, div); +return DIV_TO_RATE (GPLL_HZ , div); +} + +static ulong rk3368_spi_set_clk (struct rk3368_cru *cru,ulong clk_id,uint hz) +{ +const struct spi_clkreg *spiclk =NULL ; +int src_clk_div; + + src_clk_div =RATE_TO_DIV (GPLL_HZ , hz); +assert (src_clk_div <127 ); + +switch (clk_id) { + case SCLK_SPI0 ... SCLK_SPI2: + spiclk = &spi_clkregs[clk_id -SCLK_SPI0 ]; +break ; + +default : +error ("%s: SPI clk-id %ld not supported\n" , __func__, clk_id); +return -EINVAL ; + } + +rk_clrsetreg (&cru->clksel_con[spiclk->reg], + ((0x7f << spiclk->div_shift) | (0x1 << spiclk->sel_shift)), + ((src_clk_div << spiclk->div_shift) | + (1 /* TODO */ << spiclk->sel_shift))); + +return rk3368_spi_get_clk (cru, clk_id); +} + +static ulong rk3368_clk_get_rate (struct clk *clk) +{ +struct rk3368_clk_priv *priv =dev_get_priv (clk->dev); +ulong rate =0 ; + +debug ("%s: id %ld\n" , __func__, clk->id); +switch (clk->id) { +case PLL_CPLL : + rate =rkclk_pll_get_rate (priv->cru,CPLL ); +break ; +case PLL_GPLL : + rate =rkclk_pll_get_rate (priv->cru,GPLL ); +break ; + case SCLK_SPI0 ... SCLK_SPI2: + rate =rk3368_spi_get_clk (priv->cru, clk->id); +break ; +#if !IS_ENABLED (CONFIG_SPL_BUILD ) ||CONFIG_IS_ENABLED (MMC_SUPPORT ) +case HCLK_SDMMC : +case HCLK_EMMC : + rate =rk3368_mmc_get_clk (priv->cru, clk->id); +break ; +#endif +default : +return -ENOENT ; + } + +return rate; +} +static ulong rk3368_clk_set_rate (struct clk *clk,ulong rate) {__maybe_unused struct rk3368_clk_priv *priv =dev_get_priv (clk->dev);
@@ -358,6 +435,9 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)debug ("%s id:%ld rate:%ld\n" , __func__, clk->id, rate);switch (clk->id) { + case SCLK_SPI0 ... SCLK_SPI2: + ret =rk3368_spi_set_clk (priv->cru, clk->id, rate); +break ;#if IS_ENABLED (CONFIG_TPL_BUILD )case CLK_DDR : ret =rk3368_ddr_set_clk (priv->cru, rate);
Signature · 1 line
2.1.4
PATCH v3 48/66 net: gmac_rockchip: Add support for the RK3368 GMAC
In reply to Philipp TomsichThe GMAC in the RK3368 once again is identical to the incarnation in the RK3288 and the RK3399, except for where some of the configuration and control registers are located in the GRF.
This adds the RK3368-specific logic necessary to reuse this driver.
Signed-off-by Philipp Tomsich <[email protected]>
Acked-by Joe Hershberger <[email protected]>
---
Changes in v3: None
Changes in v2:
- moves the bit-definitions (for GRF registers) specific to the GMAC into the GMAC driver: these include interface speed selection and configuring the RGMII output mode
arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 1 + drivers/net/gmac_rockchip.c | 78 +++++++++++++++++++++++++ 2 files changed, 79 insertions(+)
arch/arm/include/asm/arch-rockchip/grf_rk3368.h +1 -0
@@ -129,4 +129,5 @@ enum {MCU_CODE_BASE_BIT31_BIT28_SHIFT =0 , MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0), }; +#endif
drivers/net/gmac_rockchip.c +78 -0
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Signature · 1 line
2.1.4
PATCH v3 48/66 net: gmac_rockchip: Add support for the RK3368 GMAC
Hi Philipp,
Quoted 17 lines · Philipp Tomsich
The GMAC in the RK3368 once again is identical to the incarnation in the RK3288 and the RK3399, except for where some of the configuration and control registers are located in the GRF.
This adds the RK3368-specific logic necessary to reuse this driver.
Signed-off-by Philipp Tomsich <[email protected]>Acked-by Joe Hershberger <[email protected]>---
Changes in v3: None
Changes in v2:
- moves the bit-definitions (for GRF registers) specific to the GMAC into the GMAC driver: these include interface speed selection and configuring the RGMII output mode
Quoted 4 lines
arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 1 + drivers/net/gmac_rockchip.c | 78 +++++++++++++++++++++++++ 2 files changed, 79 insertions(+)
Reviewed-by Simon Glass <[email protected]>
I still think we should look at splitting these out into (e.g.) ioctl operations on syscon.
PATCH v3 48/66 net: gmac_rockchip: Add support for the RK3368 GMAC
Simon,
Quoted 28 lines · Simon Glass
Hi Philipp,
Quoted 17 lines · Philipp Tomsich
The GMAC in the RK3368 once again is identical to the incarnation in the RK3288 and the RK3399, except for where some of the configuration and control registers are located in the GRF.
This adds the RK3368-specific logic necessary to reuse this driver.
Signed-off-by Philipp Tomsich <[email protected]>Acked-by Joe Hershberger <[email protected]>---
Changes in v3: None
Changes in v2:
- moves the bit-definitions (for GRF registers) specific to the GMAC into the GMAC driver: these include interface speed selection and configuring the RGMII output modeQuoted 4 lines
arch/arm/include/asm/arch-rockchip/grf_rk3368.h| 1 +drivers/net/gmac_rockchip.c| 78 +++++++++++++++++++++++++2 files changed, 79 insertions(+)
Quoted 4 lines
Reviewed-by Simon Glass <[email protected]>I still think we should look at splitting these out into (e.g.) ioctl operations on syscon.
I still agree with you and plan to look into this for the next cycle.
Thanks,
Philipp.
PATCH v3 49/66 rockchip: Makefile: streamline SPL/TPL configuration
In reply to Philipp TomsichHandling TPL and SPL in the Makefile for mach-rockchip was based on nested if checks and/or if-else-if paths. This can be simplified and made more readable by using $(SPL_TPL_) and by introducing intermediate variables for the aggregation of SPL and TPL features.
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/Makefile | 46 +++++++++++++++++++++++++---------------- 1 file changed, 28 insertions(+), 18 deletions(-)
arch/arm/mach-rockchip/Makefile +28 -18
@@ -4,37 +4,47 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o -obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o +# We don't want the bootrom-helper present in a full U-Boot build, as +# this may have entered from ATF with the stack-pointer pointing to +# inaccessible/protected memory (and the bootrom-helper assumes that +# the stack-pointer is valid before switching to the U-Boot stack). +obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o +obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o + +obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o + +obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o -ifdef CONFIG_TPL_BUILD -obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o -obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o -else ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o -obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o -obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o -obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o -obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o -obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o -else +ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o endif + +obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o + ifndef CONFIG_ARM64 obj-y += rk_timer.o endif -obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ - -ifndef CONFIG_TPL_BUILD -obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ -endif +obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ +obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/ obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/ obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/ + +# Clear out SPL objects, in case this is a TPL build +obj-spl-$(CONFIG_TPL_BUILD) = + +# Now add SPL/TPL objects back into the main build +obj-$(CONFIG_SPL_BUILD) += $(obj-spl-y) +obj-$(CONFIG_TPL_BUILD) += $(obj-tpl-y)
Signature · 1 line
2.1.4
PATCH v3 50/66 rockchip: rk3368: add DRAM controller driver with DRAM initialisation
In reply to Philipp TomsichThis adds a DRAM controller driver for the RK3368 and places it in drivers/ram/rockchip (where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually).
At this stage, only the following feature-set is supported:
- DDR3
- 32-bit configuration (i.e. fully populated)
- dual-rank (i.e. no auto-detection of ranks)
- DDR3-1600K speed-bin
This driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code).
Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time).
The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation.
As part of this change, DDRC0_CON0 is also added to the GRF structure definition (at offset 0x600).
Signed-off-by Philipp Tomsich <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v3:
- correctly states the location of the driver in the commit message
Changes in v2: None
arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++ arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 + arch/arm/mach-rockchip/rk3368/Makefile | 1 - arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 -- .../clock/rockchip,rk3368-dmc.txt | 67 ++ drivers/ram/Makefile | 2 + drivers/ram/rockchip/Makefile | 7 + drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++ include/dt-bindings/memory/rk3368-dmc.h | 30 + 9 files changed, 1286 insertions(+), 61 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt create mode 100644 drivers/ram/rockchip/Makefile create mode 100644 drivers/ram/rockchip/dmc-rk3368.c create mode 100644 include/dt-bindings/memory/rk3368-dmc.h
arch/arm/include/asm/arch-rockchip/ddr_rk3368.h new file +187 -0
@@ -0,0 +1,187 @@ +/* +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_DDR_RK3368_H__ +#define __ASM_ARCH_DDR_RK3368_H__ + +/* +* The RK3368 DDR PCTL differs from the incarnation in the RK3288 only +* in a few details. Most notably, it has an additional field to track +* tREFI in controller cycles (i.e. trefi_mem_ddr3). +*/ +struct rk3368_ddr_pctl { +u32 scfg; +u32 sctl; +u32 stat; +u32 intrstat; +u32 reserved0[12 ]; +u32 mcmd; +u32 powctl; +u32 powstat; +u32 cmdtstat; +u32 cmdtstaten; +u32 reserved1[3 ]; +u32 mrrcfg0; +u32 mrrstat0; +u32 mrrstat1; +u32 reserved2[4 ]; +u32 mcfg1; +u32 mcfg; +u32 ppcfg; +u32 mstat; +u32 lpddr2zqcfg; +u32 reserved3; +u32 dtupdes; +u32 dtuna; +u32 dtune; +u32 dtuprd0; +u32 dtuprd1; +u32 dtuprd2; +u32 dtuprd3; +u32 dtuawdt; +u32 reserved4[3 ]; +u32 togcnt1u; +u32 tinit; +u32 trsth; +u32 togcnt100n; +u32 trefi; +u32 tmrd; +u32 trfc; +u32 trp; +u32 trtw; +u32 tal; +u32 tcl; +u32 tcwl; +u32 tras; +u32 trc; +u32 trcd; +u32 trrd; +u32 trtp; +u32 twr; +u32 twtr; +u32 texsr; +u32 txp; +u32 txpdll; +u32 tzqcs; +u32 tzqcsi; +u32 tdqs; +u32 tcksre; +u32 tcksrx; +u32 tcke; +u32 tmod; +u32 trstl; +u32 tzqcl; +u32 tmrr; +u32 tckesr; +u32 tdpd; +u32 trefi_mem_ddr3; +u32 reserved5[45 ]; +u32 dtuwactl; +u32 dturactl; +u32 dtucfg; +u32 dtuectl; +u32 dtuwd0; +u32 dtuwd1; +u32 dtuwd2; +u32 dtuwd3; +u32 dtuwdm; +u32 dturd0; +u32 dturd1; +u32 dturd2; +u32 dturd3; +u32 dtulfsrwd; +u32 dtulfsrrd; +u32 dtueaf; +u32 dfitctrldelay; +u32 dfiodtcfg; +u32 dfiodtcfg1; +u32 dfiodtrankmap; +u32 dfitphywrdata; +u32 dfitphywrlat; +u32 reserved7[2 ]; +u32 dfitrddataen; +u32 dfitphyrdlat; +u32 reserved8[2 ]; +u32 dfitphyupdtype0; +u32 dfitphyupdtype1; +u32 dfitphyupdtype2; +u32 dfitphyupdtype3; +u32 dfitctrlupdmin; +u32 dfitctrlupdmax; +u32 dfitctrlupddly; +u32 reserved9; +u32 dfiupdcfg; +u32 dfitrefmski; +u32 dfitctrlupdi; +u32 reserved10[4 ]; +u32 dfitrcfg0; +u32 dfitrstat0; +u32 dfitrwrlvlen; +u32 dfitrrdlvlen; +u32 dfitrrdlvlgateen; +u32 dfiststat0; +u32 dfistcfg0; +u32 dfistcfg1; +u32 reserved11; +u32 dfitdramclken; +u32 dfitdramclkdis; +u32 dfistcfg2; +u32 dfistparclr; +u32 dfistparlog; +u32 reserved12[3 ]; +u32 dfilpcfg0; +u32 reserved13[3 ]; +u32 dfitrwrlvlresp0; +u32 dfitrwrlvlresp1; +u32 dfitrwrlvlresp2; +u32 dfitrrdlvlresp0; +u32 dfitrrdlvlresp1; +u32 dfitrrdlvlresp2; +u32 dfitrwrlvldelay0; +u32 dfitrwrlvldelay1; +u32 dfitrwrlvldelay2; +u32 dfitrrdlvldelay0; +u32 dfitrrdlvldelay1; +u32 dfitrrdlvldelay2; +u32 dfitrrdlvlgatedelay0; +u32 dfitrrdlvlgatedelay1; +u32 dfitrrdlvlgatedelay2; +u32 dfitrcmd; +u32 reserved14[46 ]; +u32 ipvr; +u32 iptr; +}; +check_member (rk3368_ddr_pctl, iptr,0x03fc ); + +struct rk3368_ddrphy { +u32 reg[0x100 ]; +}; +check_member (rk3368_ddrphy, reg[0xff ],0x03fc ); + +struct rk3368_msch { +u32 coreid; +u32 revisionid; +u32 ddrconf; +u32 ddrtiming; +u32 ddrmode; +u32 readlatency; +u32 reserved1[8 ]; +u32 activate; +u32 devtodev; +}; +check_member (rk3368_msch, devtodev,0x003c ); + +/* GRF_SOC_CON0 */ +enum { +NOC_RSP_ERR_STALL =BIT (9 ), +MOBILE_DDR_SEL =BIT (4 ), +DDR0_16BIT_EN =BIT (3 ), +MSCH0_MAINDDR3_DDR3 =BIT (2 ), +MSCH0_MAINPARTIALPOP =BIT (1 ), +UPCTL_C_ACTIVE =BIT (0 ), +}; + +#endif
arch/arm/include/asm/arch-rockchip/grf_rk3368.h +3 -0
@@ -76,8 +76,11 @@ struct rk3368_grf {u32 soc_con15;u32 soc_con16;u32 soc_con17; +u32 reserved5[0x6e ]; +u32 ddrc0_con0; };check_member (rk3368_grf, soc_con17,0x444 ); +check_member (rk3368_grf, ddrc0_con0,0x600 );struct rk3368_pmu_grf {u32 gpio0a_iomux;
arch/arm/mach-rockchip/rk3368/Makefile +0 -1
@@ -5,5 +5,4 @@ # obj-y += clk_rk3368.o obj-y += rk3368.o -obj-y += sdram_rk3368.o obj-y += syscon_rk3368.o
arch/arm/mach-rockchip/rk3368/sdram_rk3368.c deleted +0 -60
60 lines not on this page · raw message
doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt new file +67 -0
67 lines not on this page · raw message
drivers/ram/Makefile +2 -0
@@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o + +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
drivers/ram/rockchip/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
drivers/ram/rockchip/dmc-rk3368.c new file +990 -0
990 lines not on this page · raw message
include/dt-bindings/memory/rk3368-dmc.h new file +30 -0
@@ -0,0 +1,30 @@ +#ifndef DT_BINDINGS_RK3368_DMC_H +#define DT_BINDINGS_RK3368_DMC_H + +#define DMC_MSCH_CBDR 0x0 +#define DMC_MSCH_CBRD 0x1 +#define DMC_MSCH_CRBD 0x2 + +#define DDR3_800D 0 +#define DDR3_800E 1 +#define DDR3_1066E 2 +#define DDR3_1066F 3 +#define DDR3_1066G 4 +#define DDR3_1333F 5 +#define DDR3_1333G 6 +#define DDR3_1333H 7 +#define DDR3_1333J 8 +#define DDR3_1600G 9 +#define DDR3_1600H 10 +#define DDR3_1600J 11 +#define DDR3_1600K 12 +#define DDR3_1866J 13 +#define DDR3_1866K 14 +#define DDR3_1866L 15 +#define DDR3_1866M 16 +#define DDR3_2133K 17 +#define DDR3_2133L 18 +#define DDR3_2133M 19 +#define DDR3_2133N 20 + +#endif
Signature · 1 line
2.1.4
PATCH v3 50/66 rockchip: rk3368: add DRAM controller driver with DRAM initialisation
add Tony from our dram team, maybe he has some ideas for this patch.
Quoted 1,467 lines · Philipp Tomsich
This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip(where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually).At this stage, only the following feature-set is supported:
- DDR3
- 32-bit configuration (i.e. fully populated)
- dual-rank (i.e. no auto-detection of ranks)
- DDR3-1600K speed-binThis driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the
os_reg2in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code).Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time).
The RK3368 also has the
DDRC0_CON0(DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation.
As part of this change,DDRC0_CON0is also added to the GRF structure definition (at offset0x600).Signed-off-by Philipp Tomsich <[email protected]>Reviewed-by Simon Glass <[email protected]>---
Changes in v3:
- correctly states the location of the driver in the commit messageChanges in v2: None
arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++ arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 + arch/arm/mach-rockchip/rk3368/Makefile | 1 - arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 -- .../clock/rockchip,rk3368-dmc.txt | 67 ++ drivers/ram/Makefile | 2 + drivers/ram/rockchip/Makefile | 7 + drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++ include/dt-bindings/memory/rk3368-dmc.h | 30 + 9 files changed, 1286 insertions(+), 61 deletions(-)create mode 100644
arch/arm/include/asm/arch-rockchip/ddr_rk3368.hdelete mode 100644arch/arm/mach-rockchip/rk3368/sdram_rk3368.ccreate mode 100644doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txtcreate mode 100644drivers/ram/rockchip/Makefile
create mode 100644drivers/ram/rockchip/dmc-rk3368.c
create mode 100644include/dt-bindings/memory/rk3368-dmc.harch/arm/include/asm/arch-rockchip/ddr_rk3368.h new file +187
-0@@ -0,0 +1,187 @@ +/* +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_DDR_RK3368_H__ +#define __ASM_ARCH_DDR_RK3368_H__ + +/* +* The RK3368 DDR PCTL differs from the incarnation in the RK3288 only +* in a few details. Most notably, it has an additional field to track +* tREFI in controller cycles (i.e. trefi_mem_ddr3). +*/ +struct rk3368_ddr_pctl { +u32 scfg; +u32 sctl; +u32 stat; +u32 intrstat; +u32 reserved0[12 ]; +u32 mcmd; +u32 powctl; +u32 powstat; +u32 cmdtstat; +u32 cmdtstaten; +u32 reserved1[3 ]; +u32 mrrcfg0; +u32 mrrstat0; +u32 mrrstat1; +u32 reserved2[4 ]; +u32 mcfg1; +u32 mcfg; +u32 ppcfg; +u32 mstat; +u32 lpddr2zqcfg; +u32 reserved3; +u32 dtupdes; +u32 dtuna; +u32 dtune; +u32 dtuprd0; +u32 dtuprd1; +u32 dtuprd2; +u32 dtuprd3; +u32 dtuawdt; +u32 reserved4[3 ]; +u32 togcnt1u; +u32 tinit; +u32 trsth; +u32 togcnt100n; +u32 trefi; +u32 tmrd; +u32 trfc; +u32 trp; +u32 trtw; +u32 tal; +u32 tcl; +u32 tcwl; +u32 tras; +u32 trc; +u32 trcd; +u32 trrd; +u32 trtp; +u32 twr; +u32 twtr; +u32 texsr; +u32 txp; +u32 txpdll; +u32 tzqcs; +u32 tzqcsi; +u32 tdqs; +u32 tcksre; +u32 tcksrx; +u32 tcke; +u32 tmod; +u32 trstl; +u32 tzqcl; +u32 tmrr; +u32 tckesr; +u32 tdpd; +u32 trefi_mem_ddr3; +u32 reserved5[45 ]; +u32 dtuwactl; +u32 dturactl; +u32 dtucfg; +u32 dtuectl; +u32 dtuwd0; +u32 dtuwd1; +u32 dtuwd2; +u32 dtuwd3; +u32 dtuwdm; +u32 dturd0; +u32 dturd1; +u32 dturd2; +u32 dturd3; +u32 dtulfsrwd; +u32 dtulfsrrd; +u32 dtueaf; +u32 dfitctrldelay; +u32 dfiodtcfg; +u32 dfiodtcfg1; +u32 dfiodtrankmap; +u32 dfitphywrdata; +u32 dfitphywrlat; +u32 reserved7[2 ]; +u32 dfitrddataen; +u32 dfitphyrdlat; +u32 reserved8[2 ]; +u32 dfitphyupdtype0; +u32 dfitphyupdtype1; +u32 dfitphyupdtype2; +u32 dfitphyupdtype3; +u32 dfitctrlupdmin; +u32 dfitctrlupdmax; +u32 dfitctrlupddly; +u32 reserved9; +u32 dfiupdcfg; +u32 dfitrefmski; +u32 dfitctrlupdi; +u32 reserved10[4 ]; +u32 dfitrcfg0; +u32 dfitrstat0; +u32 dfitrwrlvlen; +u32 dfitrrdlvlen; +u32 dfitrrdlvlgateen; +u32 dfiststat0; +u32 dfistcfg0; +u32 dfistcfg1; +u32 reserved11; +u32 dfitdramclken; +u32 dfitdramclkdis; +u32 dfistcfg2; +u32 dfistparclr; +u32 dfistparlog; +u32 reserved12[3 ]; +u32 dfilpcfg0; +u32 reserved13[3 ]; +u32 dfitrwrlvlresp0; +u32 dfitrwrlvlresp1; +u32 dfitrwrlvlresp2; +u32 dfitrrdlvlresp0; +u32 dfitrrdlvlresp1; +u32 dfitrrdlvlresp2; +u32 dfitrwrlvldelay0; +u32 dfitrwrlvldelay1; +u32 dfitrwrlvldelay2; +u32 dfitrrdlvldelay0; +u32 dfitrrdlvldelay1; +u32 dfitrrdlvldelay2; +u32 dfitrrdlvlgatedelay0; +u32 dfitrrdlvlgatedelay1; +u32 dfitrrdlvlgatedelay2; +u32 dfitrcmd; +u32 reserved14[46 ]; +u32 ipvr; +u32 iptr; +}; +check_member (rk3368_ddr_pctl, iptr,0x03fc ); + +struct rk3368_ddrphy { +u32 reg[0x100 ]; +}; +check_member (rk3368_ddrphy, reg[0xff ],0x03fc ); + +struct rk3368_msch { +u32 coreid; +u32 revisionid; +u32 ddrconf; +u32 ddrtiming; +u32 ddrmode; +u32 readlatency; +u32 reserved1[8 ]; +u32 activate; +u32 devtodev; +}; +check_member (rk3368_msch, devtodev,0x003c ); + +/* GRF_SOC_CON0 */ +enum { +NOC_RSP_ERR_STALL =BIT (9 ), +MOBILE_DDR_SEL =BIT (4 ), +DDR0_16BIT_EN =BIT (3 ), +MSCH0_MAINDDR3_DDR3 =BIT (2 ), +MSCH0_MAINPARTIALPOP =BIT (1 ), +UPCTL_C_ACTIVE =BIT (0 ), +}; + +#endif arch/arm/include/asm/arch-rockchip/grf_rk3368.h +3
-0@@ -76,8 +76,11 @@ struct rk3368_grf {u32 soc_con15;u32 soc_con16;u32 soc_con17; +u32 reserved5[0x6e ]; +u32 ddrc0_con0; };check_member (rk3368_grf, soc_con17,0x444 ); +check_member (rk3368_grf, ddrc0_con0,0x600 );struct rk3368_pmu_grf {u32 gpio0a_iomux;arch/arm/mach-rockchip/rk3368/Makefile +0
-1@@ -5,5 +5,4 @@ # obj-y += clk_rk3368.o obj-y += rk3368.o -obj-y += sdram_rk3368.o obj-y += syscon_rk3368.oarch/arm/mach-rockchip/rk3368/sdram_rk3368.c deleted +0
-60@@ -1,60 +0,0 @@ -/* -* (C) Copyright 2016 Rockchip Electronics Co., Ltd. -* -* SPDX-License-Identifier: GPL-2.0 -*/ - -#include <common.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/sdram_common.h> - -DECLARE_GLOBAL_DATA_PTR ; -struct dram_info { -struct ram_info info; -struct rk3368_pmu_grf *pmugrf; -}; - -static int rk3368_dmc_probe (struct udevice *dev) -{ -struct dram_info *priv =dev_get_priv (dev); - - priv->pmugrf =syscon_get_first_range (ROCKCHIP_SYSCON_PMUGRF ); -debug ("%s: grf=%p\n" , __func__, priv->pmugrf); - priv->info.base =CONFIG_SYS_SDRAM_BASE ; - priv->info.size =rockchip_sdram_size ( - (phys_addr_t)&priv->pmugrf->os_reg[2 ]); - -return 0 ; -} - -static int rk3368_dmc_get_info (struct udevice *dev,struct ram_info *info) -{ -struct dram_info *priv =dev_get_priv (dev); - - *info = priv->info; - -return 0 ; -} - -static struct ram_ops rk3368_dmc_ops = { - .get_info = rk3368_dmc_get_info, -}; - - -static const struct udevice_id rk3368_dmc_ids[] = { - { .compatible ="rockchip,rk3368-dmc" }, - { } -}; - -U_BOOT_DRIVER (dmc_rk3368) = { - .name ="rockchip_rk3368_dmc" , - .id =UCLASS_RAM , - .of_match = rk3368_dmc_ids, - .ops = &rk3368_dmc_ops, - .probe = rk3368_dmc_probe, - .priv_auto_alloc_size =sizeof (struct dram_info ), -};doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt new file +67
-0@@ -0,0 +1,67 @@ +RK3368 dynamic memory controller driver +======================================= + +The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation +during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on +the following key configuration data: + (a) a target-frequency (i.e. operating point) for the memory operation + (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware + (c) a memory-schedule (i.e. mapping from physical addresses to the address + pins of the memory bus) + +Required properties +------------------- + +- compatible: "rockchip,rk3368-dmc" +- reg + protocol controller (PCTL) address and PHY controller (DDRPHY) address +- rockchip,ddr-speed-bin + the DDR3 device's speed-bin (as specified according to JESD-79) + DDR3_800D (5-5-5) + DDR3_800E (6-6-6) + DDR3_1066E (6-6-6) + DDR3_1066F (7-7-7) + DDR3_1066G (8-8-8) + DDR3_1333F (7-7-7) + DDR3_1333G (8-8-8) + DDR3_1333H (9-9-9) + DDR3_1333J (10-10-10) + DDR3_1600G (8-8-8) + DDR3_1600H (9-9-9) + DDR3_1600J (10-10-10) + DDR3_1600K (11-11-11) + DDR3_1866J (10-10-10) + DDR3_1866K (11-11-11) + DDR3_1866L (12-12-12) + DDR3_1866M (13-13-13) + DDR3_2133K (11-11-11) + DDR3_2133L (12-12-12) + DDR3_2133M (13-13-13) + DDR3_2133N (14-14-14) +- rockchip,ddr-frequency: + target DDR clock frequency in Hz (not all frequencies may be supported, + as there's some cooperation from the clock-driver required) +- rockchip,memory-schedule: + controls the decoding of physical addresses to DRAM addressing (i.e. how + the physical address maps onto the address pins/chip-select of the device) + DMC_MSCH_CBDR: column -> bank -> device -> row + DMC_MSCH_CBRD: column -> band -> row -> device + DMC_MSCH_CRBD: column -> row -> band -> device + +Example (for DDR3-1600K and 800MHz) +----------------------------------- + + #include <dt-bindings/memory/rk3368-dmc.h> + + dmc: dmc at ff610000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3368-dmc"; + reg = <0 0xff610000 0 0x400 + 0 0xff620000 0 0x400>; + }; + + &dmc { + rockchip,ddr-speed-bin = <DDR3_1600K>; + rockchip,ddr-frequency = <800000000>; + rockchip,memory-schedule = <DMC_MSCH_CBRD>; + };drivers/ram/Makefile +2
-0@@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o + +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/drivers/ram/rockchip/Makefile new file +7
-0@@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.odrivers/ram/rockchip/dmc-rk3368.c new file +990
-0@@ -0,0 +1,990 @@ +/* +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dt-bindings/memory/rk3368-dmc.h> +#include <dt-structs.h> +#include <ram.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3368.h> +#include <asm/arch/grf_rk3368.h> +#include <asm/arch/ddr_rk3368.h> +#include <asm/arch/sdram.h> +#include <asm/arch/sdram_common.h> + +DECLARE_GLOBAL_DATA_PTR ; + +struct dram_info { +struct ram_info info; +struct clk ddr_clk; +struct rk3368_cru *cru; +struct rk3368_grf *grf; +struct rk3368_ddr_pctl *pctl; +struct rk3368_ddrphy *phy; +struct rk3368_pmu_grf *pmugrf; +struct rk3368_msch *msch; +}; + +struct rk3368_sdram_params { +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +struct dtd_rockchip_rk3368_dmc of_plat; +#endif +struct rk3288_sdram_pctl_timing pctl_timing; +u32 trefi_mem_ddr3; +struct rk3288_sdram_channel chan; +struct regmap *map; +u32 ddr_freq; +u32 memory_schedule; +u32 ddr_speed_bin; +u32 tfaw_mult; +}; + +/* PTCL bits */ +enum { +/* PCTL_DFISTCFG0 */ +DFI_INIT_START =BIT (0 ), +DFI_DATA_BYTE_DISABLE_EN =BIT (2 ), + +/* PCTL_DFISTCFG1 */ +DFI_DRAM_CLK_SR_EN =BIT (0 ), +DFI_DRAM_CLK_DPD_EN =BIT (1 ), +ODT_LEN_BL8_W_SHIFT =16 , + +/* PCTL_DFISTCFG2 */ +DFI_PARITY_INTR_EN =BIT (0 ), +DFI_PARITY_EN =BIT (1 ), + +/* PCTL_DFILPCFG0 */ +TLP_RESP_TIME_SHIFT =16 , +LP_SR_EN =BIT (8 ), +LP_PD_EN =BIT (0 ), + +/* PCTL_DFIODTCFG */ +RANK0_ODT_WRITE_SEL =BIT (3 ), +RANK1_ODT_WRITE_SEL =BIT (11 ), + +/* PCTL_SCFG */ +HW_LOW_POWER_EN =BIT (0 ), + +/* PCTL_MCMD */ +START_CMD =BIT (31 ), +MCMD_RANK0 =BIT (20 ), +MCMD_RANK1 =BIT (21 ), +DESELECT_CMD =0 , +PREA_CMD , +REF_CMD , +MRS_CMD , +ZQCS_CMD , +ZQCL_CMD , +RSTL_CMD , +MRR_CMD =8 , +DPDE_CMD , + +/* PCTL_POWCTL */ +POWER_UP_START =BIT (0 ), + +/* PCTL_POWSTAT */ +POWER_UP_DONE =BIT (0 ), + +/* PCTL_SCTL */ +INIT_STATE =0 , +CFG_STATE , +GO_STATE , +SLEEP_STATE , +WAKEUP_STATE , + +/* PCTL_STAT */ +LP_TRIG_SHIFT =4 , +LP_TRIG_MASK =7 , +PCTL_STAT_MSK =7 , +INIT_MEM =0 , +CONFIG , +CONFIG_REQ , +ACCESS , +ACCESS_REQ , +LOW_POWER , +LOW_POWER_ENTRY_REQ , +LOW_POWER_EXIT_REQ , + +/* PCTL_MCFG */ +DDR2_DDR3_BL_8 =BIT (0 ), +DDR3_EN =BIT (5 ), +TFAW_TRRD_MULT4 = (0 <<18 ), +TFAW_TRRD_MULT5 = (1 <<18 ), +TFAW_TRRD_MULT6 = (2 <<18 ), +}; + +#define DDR3_MR0_WR (n) \ + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9)) +#define DDR3_MR0_CL (n) \ + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2)) +#define DDR3_MR0_BL8 \ + (0 << 0) +#define DDR3_MR0_DLL_RESET \ + (1 << 8) +#define DDR3_MR1_RTT120OHM \ + ((0 << 9) | (1 << 6) | (0 << 2)) +#define DDR3_MR2_TWL (n) \ + (((n - 5) & 0x7) << 3) + + +#ifdef CONFIG_TPL_BUILD + +static void ddr_set_noc_spr_err_stall (struct rk3368_grf *grf,bool enable) +{ +if (enable) +rk_setreg (&grf->ddrc0_con0,NOC_RSP_ERR_STALL ); +else +rk_clrreg (&grf->ddrc0_con0,NOC_RSP_ERR_STALL ); +} + +static void ddr_set_ddr3_mode (struct rk3368_grf *grf,bool ddr3_mode) +{ +if (ddr3_mode) +rk_setreg (&grf->ddrc0_con0,MSCH0_MAINDDR3_DDR3 ); +else +rk_clrreg (&grf->ddrc0_con0,MSCH0_MAINDDR3_DDR3 ); +} + +static void ddrphy_config (struct rk3368_ddrphy *phy, +u32 tcl,u32 tal,u32 tcwl) +{ +int i; + +/* Set to DDR3 mode */ +clrsetbits_le32 (&phy->reg[1 ],0x3 ,0x0 ); + +/* DDRPHY_REGB: CL, AL */ +clrsetbits_le32 (&phy->reg[0xb ],0xff , tcl <<4 | tal); +/* DDRPHY_REGC: CWL */ +clrsetbits_le32 (&phy->reg[0xc ],0x0f , tcwl); + +/* Update drive-strength */ +writel (0xcc , &phy->reg[0x11 ]); +writel (0xaa , &phy->reg[0x16 ]); +/* +* Update NRCOMP/PRCOMP for all 4 channels (for details of all +* affected registers refer to the documentation of DDRPHY_REG20 +* and DDRPHY_REG21 in the RK3368 TRM. +*/ +for (i =0 ; i <4 ; ++i) { +writel (0xcc , &phy->reg[0x20 + i *0x10 ]); +writel (0x44 , &phy->reg[0x21 + i *0x10 ]); + } + +/* Enable write-leveling calibration bypass */ +setbits_le32 (&phy->reg[2 ],BIT (3 )); +} + +static void copy_to_reg (u32 *dest,const u32 *src,u32 n) +{ +int i; + +for (i =0 ; i < n /sizeof (u32); i++) +writel (*src++, dest++); +} + +static void send_command (struct rk3368_ddr_pctl *pctl,u32 rank,u32 cmd) +{ +u32 mcmd =START_CMD | cmd | rank; + +debug ("%s: writing %x to MCMD\n" , __func__, mcmd); +writel (mcmd, &pctl->mcmd); +while (readl (&pctl->mcmd) &START_CMD ) +/* spin */ ; +} + +static void send_mrs (struct rk3368_ddr_pctl *pctl, +u32 rank,u32 mr_num,u32 mr_data) +{ +u32 mcmd =START_CMD |MRS_CMD | rank | (mr_num <<17 ) | (mr_data <<4 ); + +debug ("%s: writing %x to MCMD\n" , __func__, mcmd); +writel (mcmd, &pctl->mcmd); +while (readl (&pctl->mcmd) &START_CMD ) +/* spin */ ; +} + +static int memory_init (struct rk3368_ddr_pctl *pctl, +struct rk3368_sdram_params *params) +{ +u32 mr[4 ]; +const ulong timeout_ms =500 ; +ulong tmp; + +/* +* Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and +* wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register +* of PCTL. +*/ +writel (POWER_UP_START , &pctl->powctl); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: POWER_UP_START did not complete in %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while (!(readl (&pctl->powstat) &POWER_UP_DONE )); + +/* Configure MR0 through MR3 */ + mr[0 ] =DDR3_MR0_WR (params->pctl_timing.twr) | +DDR3_MR0_CL (params->pctl_timing.tcl) | +DDR3_MR0_DLL_RESET ; + mr[1 ] =DDR3_MR1_RTT120OHM ; + mr[2 ] =DDR3_MR2_TWL (params->pctl_timing.tcwl); + mr[3 ] =0 ; + +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.2 Initialization (DDR3 Initialization Sequence)" +*/ +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,DESELECT_CMD ); +udelay (1 ); +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,PREA_CMD ); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,2 , mr[2 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,3 , mr[3 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,1 , mr[1 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,0 , mr[0 ]); +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,ZQCL_CMD ); + +return 0 ; +} + +static void move_to_config_state (struct rk3368_ddr_pctl *pctl) +{ +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.1 State transition of PCTL (Moving to Config State)" +*/ +u32 state =readl (&pctl->stat) &PCTL_STAT_MSK ; + +switch (state) { +case LOW_POWER : +writel (WAKEUP_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=ACCESS ) +/* spin */ ; + +/* fall-through */ +case ACCESS : +case INIT_MEM : +writel (CFG_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=CONFIG ) +/* spin */ ; +break ; + +case CONFIG : +return ; + +default : +break ; + } +} + +static void move_to_access_state (struct rk3368_ddr_pctl *pctl) +{ +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.1 State transition of PCTL (Moving to Access State)" +*/ +u32 state =readl (&pctl->stat) &PCTL_STAT_MSK ; + +switch (state) { +case LOW_POWER : +if (((readl (&pctl->stat) >>LP_TRIG_SHIFT ) & +LP_TRIG_MASK ) ==1 ) +return ; + +writel (WAKEUP_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=ACCESS ) +/* spin */ ; + +/* fall-through */ +case INIT_MEM : +writel (CFG_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=CONFIG ) +/* spin */ ; + +/* fall-through */ +case CONFIG : +writel (GO_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) ==CONFIG ) +/* spin */ ; +break ; + +case ACCESS : +return ; + +default : +break ; + } +} + +static void ddrctl_reset (struct rk3368_cru *cru) +{ +const u32 ctl_reset =BIT (3 ) |BIT (2 ); +const u32 phy_reset =BIT (1 ) |BIT (0 ); + +rk_setreg (&cru->softrst_con[10 ], ctl_reset | phy_reset); +udelay (1 ); +rk_clrreg (&cru->softrst_con[10 ], ctl_reset | phy_reset); +} + +static void ddrphy_reset (struct rk3368_ddrphy *ddrphy) +{ +clrbits_le32 (&ddrphy->reg[0 ],BIT (3 ) |BIT (2 )); +udelay (1 ); +setbits_le32 (&ddrphy->reg[0 ],BIT (3 ) |BIT (2 )); +} + +static void ddrphy_config_delays (struct rk3368_ddrphy *ddrphy,u32 freq) +{ +u32 dqs_dll_delay; + +setbits_le32 (&ddrphy->reg[0x13 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x14 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x26 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x27 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x36 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x37 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x46 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x47 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x56 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x57 ],BIT (3 )); + +if (freq <=400000000 ) +setbits_le32 (&ddrphy->reg[0xa4 ],0x1f ); +else +clrbits_le32 (&ddrphy->reg[0xa4 ],0x1f ); + +if (freq <681000000 ) + dqs_dll_delay =3 ;/* 67.5 degree delay */ +else + dqs_dll_delay =2 ;/* 45 degree delay */ + +writel (dqs_dll_delay, &ddrphy->reg[0x28 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x38 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x48 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x58 ]); +} + +static int dfi_cfg (struct rk3368_ddr_pctl *pctl) +{ +const ulong timeout_ms =200 ; +ulong tmp; + +writel (DFI_DATA_BYTE_DISABLE_EN , &pctl->dfistcfg0); + +writel (DFI_DRAM_CLK_SR_EN |DFI_DRAM_CLK_DPD_EN , + &pctl->dfistcfg1); +writel (DFI_PARITY_INTR_EN |DFI_PARITY_EN , &pctl->dfistcfg2); +writel (7 <<TLP_RESP_TIME_SHIFT |LP_SR_EN |LP_PD_EN , + &pctl->dfilpcfg0); + +writel (1 , &pctl->dfitphyupdtype0); + +writel (0x1f , &pctl->dfitphyrdlat); +writel (0 , &pctl->dfitphywrdata); +writel (0 , &pctl->dfiupdcfg);/* phyupd and ctrlupd disabled */ + +setbits_le32 (&pctl->dfistcfg0,DFI_INIT_START ); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: DFI init did not complete within %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while ((readl (&pctl->dfiststat0) &1 ) ==0 ); + +return 0 ; +} + +static inline u32 ps_to_tCK (const u32 ps,const ulong freq) +{ +const ulong MHz =1000000 ; +return DIV_ROUND_UP (ps * freq,1000000 * MHz); +} + +static inline u32 ns_to_tCK (const u32 ns,const ulong freq) +{ +return ps_to_tCK (ns *1000 , freq); +} + +static inline u32 tCK_to_ps (const ulong tCK,const ulong freq) +{ +const ulong MHz =1000000 ; +return DIV_ROUND_UP (tCK *1000000 * MHz, freq); +} + +static int pctl_calc_timings (struct rk3368_sdram_params *params, +ulong freq) +{ +struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing; +const ulong MHz =1000000 ; +u32 tccd; +u32 tfaw_as_ps; + +if (params->ddr_speed_bin !=DDR3_1600K ) { +error ("%s: unimplemented DDR3 speed bin %d\n" , + __func__, params->ddr_speed_bin); +return -1 ; + } + +/* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */ + pctl_timing->togcnt1u =DIV_ROUND_UP (freq,2 * MHz); + pctl_timing->togcnt100n =DIV_ROUND_UP (freq /10 ,2 * MHz); + + pctl_timing->tinit =200 ;/* 200 usec */ + pctl_timing->trsth =500 ;/* 500 usec */ + pctl_timing->trefi =78 ;/* 7.8usec = 78 * 100ns */ + params->trefi_mem_ddr3 =ns_to_tCK (pctl_timing->trefi *100 , freq); + +if (freq <= (400 * MHz)) { + pctl_timing->tcl =6 ; + pctl_timing->tcwl =10 ; + }else if (freq <= (533 * MHz)) { + pctl_timing->tcl =8 ; + pctl_timing->tcwl =6 ; + }else if (freq <= (666 * MHz)) { + pctl_timing->tcl =10 ; + pctl_timing->tcwl =7 ; + }else { + pctl_timing->tcl =11 ; + pctl_timing->tcwl =8 ; + } + + pctl_timing->tmrd =4 ;/* 4 tCK (all speed bins) */ + pctl_timing->trfc =ns_to_tCK (350 , freq);/* tRFC: 350 (max) @ 8GBit */ + pctl_timing->trp =max (4u ,ps_to_tCK (13750 , freq)); +/* +* JESD-79: +* READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL +*/ + tccd =4 ; + pctl_timing->trtw = pctl_timing->tcl + tccd/2 +2 - pctl_timing->tcwl; + pctl_timing->tal =0 ; + pctl_timing->tras =ps_to_tCK (35000 , freq); + pctl_timing->trc =ps_to_tCK (48750 , freq); + pctl_timing->trcd =ps_to_tCK (13750 , freq); + pctl_timing->trrd =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->trtp =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->twr =ps_to_tCK (15000 , freq); +/* The DDR3 mode-register does only support even values for tWR > 8. */ +if (pctl_timing->twr >8 ) + pctl_timing->twr = (pctl_timing->twr +1 ) & ~1 ; + pctl_timing->twtr =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->texsr =512 ;/* tEXSR(max) is tDLLLK */ + pctl_timing->txp =max (3u ,ps_to_tCK (6000 , freq)); + pctl_timing->txpdll =max (10u ,ps_to_tCK (24000 , freq)); + pctl_timing->tzqcs =max (64u ,ps_to_tCK (80000 , freq)); + pctl_timing->tzqcsi =10000 ;/* as used by Rockchip */ + pctl_timing->tdqs =1 ;/* fixed for DDR3 */ + pctl_timing->tcksre =max (5u ,ps_to_tCK (10000 , freq)); + pctl_timing->tcksrx =max (5u ,ps_to_tCK (10000 , freq)); + pctl_timing->tcke =max (3u ,ps_to_tCK (5000 , freq)); + pctl_timing->tmod =max (12u ,ps_to_tCK (15000 , freq)); + pctl_timing->trstl =ns_to_tCK (100 , freq); + pctl_timing->tzqcl =max (256u ,ps_to_tCK (320000 , freq));/* tZQoper */ + pctl_timing->tmrr =0 ; + pctl_timing->tckesr = pctl_timing->tcke +1 ;/* JESD-79: tCKE + 1tCK */ + pctl_timing->tdpd =0 ;/* RK3368 TRM: "allowed values for DDR3: 0" */ + + +/* +* The controller can represent tFAW as 4x, 5x or 6x tRRD only. +* We want to use the smallest multiplier that satisfies the tFAW +* requirements of the given speed-bin. If necessary, we stretch out +* tRRD to allow us to operate on a 6x multiplier for tFAW. +*/ + tfaw_as_ps =40000 ;/* 40ns: tFAW for DDR3-1600K, 2KB page-size */ +if (tCK_to_ps (pctl_timing->trrd *6 , freq) < tfaw_as_ps) { +/* If tFAW is > 6 x tRRD, we need to stretch tRRD */ + pctl_timing->trrd =ps_to_tCK (DIV_ROUND_UP (40000 ,6 ), freq); + params->tfaw_mult =TFAW_TRRD_MULT6 ; + }else if (tCK_to_ps (pctl_timing->trrd *5 , freq) < tfaw_as_ps) { + params->tfaw_mult =TFAW_TRRD_MULT6 ; + }else if (tCK_to_ps (pctl_timing->trrd *4 , freq) < tfaw_as_ps) { + params->tfaw_mult =TFAW_TRRD_MULT5 ; + }else { + params->tfaw_mult =TFAW_TRRD_MULT4 ; + } + +return 0 ; +} + +static void pctl_cfg (struct rk3368_ddr_pctl *pctl, +struct rk3368_sdram_params *params, +struct rk3368_grf *grf) +{ +/* Configure PCTL timing registers */ + params->pctl_timing.trefi |=BIT (31 );/* see PCTL_TREFI */ +copy_to_reg (&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u, +sizeof (params->pctl_timing)); +writel (params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3); + +/* Set up ODT write selector and ODT write length */ +writel ((RANK0_ODT_WRITE_SEL |RANK1_ODT_WRITE_SEL ), &pctl->dfiodtcfg); +writel (7 <<ODT_LEN_BL8_W_SHIFT , &pctl->dfiodtcfg1); + +/* Set up the CL/CWL-dependent timings of DFI */ +writel ((params->pctl_timing.tcl -1 ) /2 -1 , &pctl->dfitrddataen); +writel ((params->pctl_timing.tcwl -1 ) /2 -1 , &pctl->dfitphywrlat); + +/* DDR3 */ +writel (params->tfaw_mult |DDR3_EN |DDR2_DDR3_BL_8 , &pctl->mcfg); +writel (0x001c0004 , &grf->ddrc0_con0); + +setbits_le32 (&pctl->scfg,HW_LOW_POWER_EN ); +} + +static int ddrphy_data_training (struct rk3368_ddr_pctl *pctl, +struct rk3368_ddrphy *ddrphy) +{ +const u32 trefi =readl (&pctl->trefi); +const ulong timeout_ms =500 ; +ulong tmp; + +/* disable auto-refresh */ +writel (0 |BIT (31 ), &pctl->trefi); + +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x20 ); +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x21 ); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: did not complete within %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while ((readl (&ddrphy->reg[0xff ]) &0xf ) !=0xf ); + +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,PREA_CMD ); +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x20 ); +/* resume auto-refresh */ +writel (trefi |BIT (31 ), &pctl->trefi); + +return 0 ; +} + +static int sdram_col_row_detect (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_sdram_params *params =dev_get_platdata (dev); +struct rk3368_ddr_pctl *pctl = priv->pctl; +struct rk3368_msch *msch = priv->msch; +const u32 test_pattern =0x5aa5f00f ; +int row, col; +uintptr_t addr; + +move_to_config_state (pctl); +writel (6 , &msch->ddrconf); +move_to_access_state (pctl); + +/* Detect col */ +for (col =11 ; col >=9 ; col--) { +writel (0 ,CONFIG_SYS_SDRAM_BASE ); + addr =CONFIG_SYS_SDRAM_BASE + + (1 << (col + params->chan.bw -1 )); +writel (test_pattern, addr); +if ((readl (addr) == test_pattern) && + (readl (CONFIG_SYS_SDRAM_BASE ) ==0 )) +break ; + } + +if (col ==8 ) { +error ("%s: col detect error\n" , __func__); +return -EINVAL ; + } + +move_to_config_state (pctl); +writel (15 , &msch->ddrconf); +move_to_access_state (pctl); + +/* Detect row*/ +for (row =16 ; row >=12 ; row--) { +writel (0 ,CONFIG_SYS_SDRAM_BASE ); + addr =CONFIG_SYS_SDRAM_BASE + (1 << (row +15 -1 )); +writel (test_pattern, addr); +if ((readl (addr) == test_pattern) && + (readl (CONFIG_SYS_SDRAM_BASE ) ==0 )) +break ; + } + +if (row ==11 ) { +error ("%s: row detect error\n" , __func__); +return -EINVAL ; + } + +/* Record results */ +debug ("%s: col %d, row %d\n" , __func__, col, row); + params->chan.col = col; + params->chan.cs0_row = row; + params->chan.cs1_row = row; + params->chan.row_3_4 =0 ; + +return 0 ; +} + +static int msch_niu_config (struct rk3368_msch *msch, +struct rk3368_sdram_params *params) +{ +int i; +const u8 cols = params->chan.col - ((params->chan.bw ==2 ) ?0 :1 ); +const u8 rows = params->chan.cs0_row; + +/* +* The DDR address-translation table always assumes a 32bit +* bus and the comparison below takes care of adjusting for +* a 16bit bus (i.e. one column-address is consumed). +*/ +const struct { +u8 rows; +u8 columns; +u8 type; + } ddrconf_table[] = { +/* +* C-B-R-D patterns are first. For these we require an +* exact match for the columns and rows (as there's +* one entry per possible configuration). +*/ + [0 ] = { .rows =13 , .columns =10 , .type =DMC_MSCH_CBRD }, + [1 ] = { .rows =14 , .columns =10 , .type =DMC_MSCH_CBRD }, + [2 ] = { .rows =15 , .columns =10 , .type =DMC_MSCH_CBRD }, + [3 ] = { .rows =16 , .columns =10 , .type =DMC_MSCH_CBRD }, + [4 ] = { .rows =14 , .columns =11 , .type =DMC_MSCH_CBRD }, + [5 ] = { .rows =15 , .columns =11 , .type =DMC_MSCH_CBRD }, + [6 ] = { .rows =16 , .columns =11 , .type =DMC_MSCH_CBRD }, + [7 ] = { .rows =13 , .columns =9 , .type =DMC_MSCH_CBRD }, + [8 ] = { .rows =14 , .columns =9 , .type =DMC_MSCH_CBRD }, + [9 ] = { .rows =15 , .columns =9 , .type =DMC_MSCH_CBRD }, + [10 ] = { .rows =16 , .columns =9 , .type =DMC_MSCH_CBRD }, +/* +* 11 through 13 are C-R-B-D patterns. These are +* matched for an exact number of columns and to +* ensure that the hardware uses at least as many rows +* as the pattern requires (i.e. we make sure that +* there's no gaps up until we hit the device/chip-select; +* however, these patterns can accept up to 16 rows, +* as the row-address continues right after the CS +* switching) +*/ + [11 ] = { .rows =15 , .columns =10 , .type =DMC_MSCH_CRBD }, + [12 ] = { .rows =14 , .columns =11 , .type =DMC_MSCH_CRBD }, + [13 ] = { .rows =13 , .columns =10 , .type =DMC_MSCH_CRBD }, +/* +* 14 and 15 are catch-all variants using a C-B-D-R +* scheme (i.e. alternating the chip-select every time +* C-B overflows) and stuffing the remaining C-bits +* into the top. Matching needs to make sure that the +* number of columns is either an exact match (i.e. we +* can use less the the maximum number of rows) -or- +* that the columns exceed what is given in this table +* and the rows are an exact match (in which case the +* remaining C-bits will be stuffed onto the top after +* the device/chip-select switches). +*/ + [14 ] = { .rows =16 , .columns =10 , .type =DMC_MSCH_CBDR }, + [15 ] = { .rows =16 , .columns =9 , .type =DMC_MSCH_CBDR }, + }; + +/* +* For C-B-R-D, we need an exact match (i.e. both for the number of +* columns and rows), while for C-B-D-R, only the the number of +* columns needs to match. +*/ +for (i =0 ; i <ARRAY_SIZE (ddrconf_table); i++) { +bool match = false; + +/* If this entry if for a different matcher, then skip it */ +if (ddrconf_table[i].type != params->memory_schedule) +continue ; + +/* +* Match according to the rules (exact/inexact/at-least) +* documented in the ddrconf_table above. +*/ +switch (params->memory_schedule) { +case DMC_MSCH_CBRD : + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows == rows); +break ; + +case DMC_MSCH_CRBD : + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows <= rows); +break ; + +case DMC_MSCH_CBDR : + match = (ddrconf_table[i].columns == cols) || + ((ddrconf_table[i].columns <= cols) && + (ddrconf_table[i].rows == rows)); +break ; + +default : +break ; + } + +if (match) { +debug ("%s: setting ddrconf 0x%x\n" , __func__, i); +writel (i, &msch->ddrconf); +return 0 ; + } + } + +error ("%s: ddrconf (NIU config) not found\n" , __func__); +return -EINVAL ; +} + +static void dram_all_config (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_pmu_grf *pmugrf = priv->pmugrf; +struct rk3368_sdram_params *params =dev_get_platdata (dev); +const struct rk3288_sdram_channel *info = ¶ms->chan; +u32 sys_reg =0 ; +const int chan =0 ; + + sys_reg |=DDR3 <<SYS_REG_DDRTYPE_SHIFT ; + sys_reg |=0 <<SYS_REG_NUM_CH_SHIFT ; + + sys_reg |= info->row_3_4 <<SYS_REG_ROW_3_4_SHIFT (chan); + sys_reg |=1 <<SYS_REG_CHINFO_SHIFT (chan); + sys_reg |= (info->rank -1 ) <<SYS_REG_RANK_SHIFT (chan); + sys_reg |= (info->col -9 ) <<SYS_REG_COL_SHIFT (chan); + sys_reg |= info->bk ==3 ?0 :1 <<SYS_REG_BK_SHIFT (chan); + sys_reg |= (info->cs0_row -13 ) <<SYS_REG_CS0_ROW_SHIFT (chan); + sys_reg |= (info->cs1_row -13 ) <<SYS_REG_CS1_ROW_SHIFT (chan); + sys_reg |= (2 >> info->bw) <<SYS_REG_BW_SHIFT (chan); + sys_reg |= (2 >> info->dbw) <<SYS_REG_DBW_SHIFT (chan); + +writel (sys_reg, &pmugrf->os_reg[2 ]); +} + +static int setup_sdram (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_sdram_params *params =dev_get_platdata (dev); + +struct rk3368_ddr_pctl *pctl = priv->pctl; +struct rk3368_ddrphy *ddrphy = priv->phy; +struct rk3368_cru *cru = priv->cru; +struct rk3368_grf *grf = priv->grf; +struct rk3368_msch *msch = priv->msch; + +int ret; + +/* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */ + ret =clk_set_rate (&priv->ddr_clk,2 * params->ddr_freq); +if (ret <0 ) { +debug ("%s: could not set DDR clock: %d\n" , __func__, ret); +return ret; + } + +/* Update the read-latency for the RK3368 */ +writel (0x32 , &msch->readlatency); + +/* Initialise the DDR PCTL and DDR PHY */ +ddrctl_reset (cru); +ddrphy_reset (ddrphy); +ddrphy_config_delays (ddrphy, params->ddr_freq); +dfi_cfg (pctl); +/* Configure relative system information of grf_ddrc0_con0 register */ +ddr_set_ddr3_mode (grf, true); +ddr_set_noc_spr_err_stall (grf, true); +/* Calculate timings */ +pctl_calc_timings (params, params->ddr_freq); +/* Initialise the device timings in protocol controller */ +pctl_cfg (pctl, params, grf); +/* Configure AL, CL ... information of PHY registers */ +ddrphy_config (ddrphy, + params->pctl_timing.tcl, + params->pctl_timing.tal, + params->pctl_timing.tcwl); + +/* Initialize DRAM and configure with mode-register values */ + ret =memory_init (pctl, params); +if (ret) + goto error; + +move_to_config_state (pctl); +/* Perform data-training */ +ddrphy_data_training (pctl, ddrphy); +move_to_access_state (pctl); + +/* TODO(prt): could detect rank in training... */ + params->chan.rank =2 ; +/* TODO(prt): bus width is not auto-detected (yet)... */ + params->chan.bw =2 ;/* 32bit wide bus */ + params->chan.dbw = params->chan.dbw;/* 32bit wide bus */ + +/* DDR3 is always 8 bank */ + params->chan.bk =3 ; +/* Detect col and row number */ + ret =sdram_col_row_detect (dev); +if (ret) + goto error; + +/* Configure NIU DDR configuration */ + ret =msch_niu_config (msch, params); +if (ret) + goto error; + +/* set up OS_REG to communicate w/ next stage and OS */ +dram_all_config (dev); + +return 0 ; + +error: +printf ("DRAM init failed!\n" ); +hang (); +} +#endif + +static int rk3368_dmc_ofdata_to_platdata (struct udevice *dev) +{ +int ret =0 ; + +#if !CONFIG_IS_ENABLED (OF_PLATDATA ) +struct rk3368_sdram_params *plat =dev_get_platdata (dev); + + ret =regmap_init_mem (dev, &plat->map); +if (ret) +return ret; +#endif + +return ret; +} + +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +static int conv_of_platdata (struct udevice *dev) +{ +struct rk3368_sdram_params *plat =dev_get_platdata (dev); +struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat; +int ret; + + plat->ddr_freq = of_plat->rockchip_ddr_frequency; + plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin; + plat->memory_schedule = of_plat->rockchip_memory_schedule; + + ret =regmap_init_mem_platdata (dev, of_plat->reg, +ARRAY_SIZE (of_plat->reg) /2 , + &plat->map); +if (ret) +return ret; + +return 0 ; +} +#endif + +static int rk3368_dmc_probe (struct udevice *dev) +{ +#ifdef CONFIG_TPL_BUILD +struct rk3368_sdram_params *plat =dev_get_platdata (dev); +struct rk3368_ddr_pctl *pctl; +struct rk3368_ddrphy *ddrphy; +struct rk3368_cru *cru; +struct rk3368_grf *grf; +struct rk3368_msch *msch; +int ret; +struct udevice *dev_clk; +#endif +struct dram_info *priv =dev_get_priv (dev); + +#if CONFIG_IS_ENABLED (OF_PLATDATA ) + ret =conv_of_platdata (dev); +if (ret) +return ret; +#endif + + priv->pmugrf =syscon_get_first_range (ROCKCHIP_SYSCON_PMUGRF ); +debug ("%s: pmugrf=%p\n" , __func__, priv->pmugrf); + +#ifdef CONFIG_TPL_BUILD + pctl =regmap_get_range (plat->map,0 ); + ddrphy =regmap_get_range (plat->map,1 ); + msch =syscon_get_first_range (ROCKCHIP_SYSCON_MSCH ); + grf =syscon_get_first_range (ROCKCHIP_SYSCON_GRF ); + + priv->pctl = pctl; + priv->phy = ddrphy; + priv->msch = msch; + priv->grf = grf; + + ret =rockchip_get_clk (&dev_clk); +if (ret) +return ret; + priv->ddr_clk.id =CLK_DDR ; + ret =clk_request (dev_clk, &priv->ddr_clk); +if (ret) +return ret; + + cru =rockchip_get_cru (); + priv->cru = cru; +if (IS_ERR (priv->cru)) +return PTR_ERR (priv->cru); + + ret =setup_sdram (dev); +if (ret) +return ret; +#endif + + priv->info.base =0 ; + priv->info.size = +rockchip_sdram_size ((phys_addr_t)&priv->pmugrf->os_reg[2 ]); + +/* +* we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff +* is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is +* inaccessible for some IP controller. +*/ + priv->info.size =min (priv->info.size, (size_t )0xfe000000 ); + +return 0 ; +} + +static int rk3368_dmc_get_info (struct udevice *dev,struct ram_info *info) +{ +struct dram_info *priv =dev_get_priv (dev); + + *info = priv->info; +return 0 ; +} + +static struct ram_ops rk3368_dmc_ops = { + .get_info = rk3368_dmc_get_info, +}; + + +static const struct udevice_id rk3368_dmc_ids[] = { + { .compatible ="rockchip,rk3368-dmc" }, + { } +}; + +U_BOOT_DRIVER (dmc_rk3368) = { + .name ="rockchip_rk3368_dmc" , + .id =UCLASS_RAM , + .of_match = rk3368_dmc_ids, + .ops = &rk3368_dmc_ops, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size =sizeof (struct dram_info ), + .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size =sizeof (struct dram_info ), + .platdata_auto_alloc_size =sizeof (struct rk3368_sdram_params ), +};include/dt-bindings/memory/rk3368-dmc.h new file +30
-0@@ -0,0 +1,30 @@ +#ifndef DT_BINDINGS_RK3368_DMC_H +#define DT_BINDINGS_RK3368_DMC_H + +#define DMC_MSCH_CBDR 0x0 +#define DMC_MSCH_CBRD 0x1 +#define DMC_MSCH_CRBD 0x2 + +#define DDR3_800D 0 +#define DDR3_800E 1 +#define DDR3_1066E 2 +#define DDR3_1066F 3 +#define DDR3_1066G 4 +#define DDR3_1333F 5 +#define DDR3_1333G 6 +#define DDR3_1333H 7 +#define DDR3_1333J 8 +#define DDR3_1600G 9 +#define DDR3_1600H 10 +#define DDR3_1600J 11 +#define DDR3_1600K 12 +#define DDR3_1866J 13 +#define DDR3_1866K 14 +#define DDR3_1866L 15 +#define DDR3_1866M 16 +#define DDR3_2133K 17 +#define DDR3_2133L 18 +#define DDR3_2133M 19 +#define DDR3_2133N 20 + +#endif
PATCH v3 50/66 rockchip: rk3368: add DRAM controller driver with DRAM initialisation
Dear Tomsich：
see as below，
drivers/ram/rockchip/dmc-rk3368.c +11 -4
@@ -333,17 +333,25 @@ static void ddrctl_reset(struct rk3368_cru *cru) {const u32 ctl_reset =BIT (3 ) |BIT (2 );const u32 phy_reset =BIT (1 ) |BIT (0 ); - +/* should de-reset phy before de-reset pctl */ rk_setreg (&cru->softrst_con[10 ], ctl_reset | phy_reset);udelay (1 ); -rk_clrreg (&cru->softrst_con[10 ], ctl_reset | phy_reset); +rk_clrreg (&cru->softrst_con[10 ], phy_reset); +udelay (5 ); +rk_clrreg (&cru->softrst_con[10 ], ctl_reset); }static void ddrphy_reset (struct rk3368_ddrphy *ddrphy) { +/* +* phy de-reset should de-reset analog part before +* digital part abort 1000 dram cycle. +*/ clrbits_le32 (&ddrphy->reg[0 ],BIT (3 ) |BIT (2 ));udelay (1 ); -setbits_le32 (&ddrphy->reg[0 ],BIT (3 ) |BIT (2 )); +setbits_le32 (&ddrphy->reg[0 ],BIT (2 )); +udelay (5 ); +setbits_le32 (&ddrphy->reg[0 ],BIT (3 )); }
@@ -984,7 +992,6 @@ U_BOOT_DRIVER(dmc_rk3368) = { .probe = rk3368_dmc_probe, .priv_auto_alloc_size = sizeof(struct dram_info), .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata, - .probe = rk3368_dmc_probe, .priv_auto_alloc_size = sizeof(struct dram_info), .platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params), };
Thanks
--------------
汤云平
福州瑞芯微电子有限公司
Fuzhou Rockchip Electronics Co.Ltd
福建省福州市铜盘路软件大道89号软件园A区21号楼 (350003)
No. 21 Building, A District, No.89,software Boulevard Fuzhou,Fujian,PRC
mail: typ at rock-chips.com
phone of Fuzhou：0591－83991906/07 -8884
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From: Andy Yan
Date: 2017-08-01 09:30
To: Philipp Tomsich; u-boot
CC: Kever Yang; Klaus Goger; Simon Glass; Andreas Färber; Álvaro Fernández Rojas; Albert Aribaud; Vikas Manocha; Joe Hershberger; tony.tang
Subject: Re: [PATCH v3 50/66] rockchip: rk3368: add DRAM controller driver with DRAM initialisation
add Tony from our dram team, maybe he has some ideas for this patch.
Quoted 1,467 lines · Philipp Tomsich
This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip(where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually).At this stage, only the following feature-set is supported:
- DDR3
- 32-bit configuration (i.e. fully populated)
- dual-rank (i.e. no auto-detection of ranks)
- DDR3-1600K speed-binThis driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the
os_reg2in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code).Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time).
The RK3368 also has the
DDRC0_CON0(DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation.
As part of this change,DDRC0_CON0is also added to the GRF structure definition (at offset0x600).Signed-off-by Philipp Tomsich <[email protected]>Reviewed-by Simon Glass <[email protected]>---
Changes in v3:
- correctly states the location of the driver in the commit messageChanges in v2: None
arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++ arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 + arch/arm/mach-rockchip/rk3368/Makefile | 1 - arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 -- .../clock/rockchip,rk3368-dmc.txt | 67 ++ drivers/ram/Makefile | 2 + drivers/ram/rockchip/Makefile | 7 + drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++ include/dt-bindings/memory/rk3368-dmc.h | 30 + 9 files changed, 1286 insertions(+), 61 deletions(-)create mode 100644
arch/arm/include/asm/arch-rockchip/ddr_rk3368.hdelete mode 100644arch/arm/mach-rockchip/rk3368/sdram_rk3368.ccreate mode 100644doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txtcreate mode 100644drivers/ram/rockchip/Makefile
create mode 100644drivers/ram/rockchip/dmc-rk3368.c
create mode 100644include/dt-bindings/memory/rk3368-dmc.harch/arm/include/asm/arch-rockchip/ddr_rk3368.h new file +187
-0@@ -0,0 +1,187 @@ +/* +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_DDR_RK3368_H__ +#define __ASM_ARCH_DDR_RK3368_H__ + +/* +* The RK3368 DDR PCTL differs from the incarnation in the RK3288 only +* in a few details. Most notably, it has an additional field to track +* tREFI in controller cycles (i.e. trefi_mem_ddr3). +*/ +struct rk3368_ddr_pctl { +u32 scfg; +u32 sctl; +u32 stat; +u32 intrstat; +u32 reserved0[12 ]; +u32 mcmd; +u32 powctl; +u32 powstat; +u32 cmdtstat; +u32 cmdtstaten; +u32 reserved1[3 ]; +u32 mrrcfg0; +u32 mrrstat0; +u32 mrrstat1; +u32 reserved2[4 ]; +u32 mcfg1; +u32 mcfg; +u32 ppcfg; +u32 mstat; +u32 lpddr2zqcfg; +u32 reserved3; +u32 dtupdes; +u32 dtuna; +u32 dtune; +u32 dtuprd0; +u32 dtuprd1; +u32 dtuprd2; +u32 dtuprd3; +u32 dtuawdt; +u32 reserved4[3 ]; +u32 togcnt1u; +u32 tinit; +u32 trsth; +u32 togcnt100n; +u32 trefi; +u32 tmrd; +u32 trfc; +u32 trp; +u32 trtw; +u32 tal; +u32 tcl; +u32 tcwl; +u32 tras; +u32 trc; +u32 trcd; +u32 trrd; +u32 trtp; +u32 twr; +u32 twtr; +u32 texsr; +u32 txp; +u32 txpdll; +u32 tzqcs; +u32 tzqcsi; +u32 tdqs; +u32 tcksre; +u32 tcksrx; +u32 tcke; +u32 tmod; +u32 trstl; +u32 tzqcl; +u32 tmrr; +u32 tckesr; +u32 tdpd; +u32 trefi_mem_ddr3; +u32 reserved5[45 ]; +u32 dtuwactl; +u32 dturactl; +u32 dtucfg; +u32 dtuectl; +u32 dtuwd0; +u32 dtuwd1; +u32 dtuwd2; +u32 dtuwd3; +u32 dtuwdm; +u32 dturd0; +u32 dturd1; +u32 dturd2; +u32 dturd3; +u32 dtulfsrwd; +u32 dtulfsrrd; +u32 dtueaf; +u32 dfitctrldelay; +u32 dfiodtcfg; +u32 dfiodtcfg1; +u32 dfiodtrankmap; +u32 dfitphywrdata; +u32 dfitphywrlat; +u32 reserved7[2 ]; +u32 dfitrddataen; +u32 dfitphyrdlat; +u32 reserved8[2 ]; +u32 dfitphyupdtype0; +u32 dfitphyupdtype1; +u32 dfitphyupdtype2; +u32 dfitphyupdtype3; +u32 dfitctrlupdmin; +u32 dfitctrlupdmax; +u32 dfitctrlupddly; +u32 reserved9; +u32 dfiupdcfg; +u32 dfitrefmski; +u32 dfitctrlupdi; +u32 reserved10[4 ]; +u32 dfitrcfg0; +u32 dfitrstat0; +u32 dfitrwrlvlen; +u32 dfitrrdlvlen; +u32 dfitrrdlvlgateen; +u32 dfiststat0; +u32 dfistcfg0; +u32 dfistcfg1; +u32 reserved11; +u32 dfitdramclken; +u32 dfitdramclkdis; +u32 dfistcfg2; +u32 dfistparclr; +u32 dfistparlog; +u32 reserved12[3 ]; +u32 dfilpcfg0; +u32 reserved13[3 ]; +u32 dfitrwrlvlresp0; +u32 dfitrwrlvlresp1; +u32 dfitrwrlvlresp2; +u32 dfitrrdlvlresp0; +u32 dfitrrdlvlresp1; +u32 dfitrrdlvlresp2; +u32 dfitrwrlvldelay0; +u32 dfitrwrlvldelay1; +u32 dfitrwrlvldelay2; +u32 dfitrrdlvldelay0; +u32 dfitrrdlvldelay1; +u32 dfitrrdlvldelay2; +u32 dfitrrdlvlgatedelay0; +u32 dfitrrdlvlgatedelay1; +u32 dfitrrdlvlgatedelay2; +u32 dfitrcmd; +u32 reserved14[46 ]; +u32 ipvr; +u32 iptr; +}; +check_member (rk3368_ddr_pctl, iptr,0x03fc ); + +struct rk3368_ddrphy { +u32 reg[0x100 ]; +}; +check_member (rk3368_ddrphy, reg[0xff ],0x03fc ); + +struct rk3368_msch { +u32 coreid; +u32 revisionid; +u32 ddrconf; +u32 ddrtiming; +u32 ddrmode; +u32 readlatency; +u32 reserved1[8 ]; +u32 activate; +u32 devtodev; +}; +check_member (rk3368_msch, devtodev,0x003c ); + +/* GRF_SOC_CON0 */ +enum { +NOC_RSP_ERR_STALL =BIT (9 ), +MOBILE_DDR_SEL =BIT (4 ), +DDR0_16BIT_EN =BIT (3 ), +MSCH0_MAINDDR3_DDR3 =BIT (2 ), +MSCH0_MAINPARTIALPOP =BIT (1 ), +UPCTL_C_ACTIVE =BIT (0 ), +}; + +#endif arch/arm/include/asm/arch-rockchip/grf_rk3368.h +3
-0@@ -76,8 +76,11 @@ struct rk3368_grf {u32 soc_con15;u32 soc_con16;u32 soc_con17; +u32 reserved5[0x6e ]; +u32 ddrc0_con0; };check_member (rk3368_grf, soc_con17,0x444 ); +check_member (rk3368_grf, ddrc0_con0,0x600 );struct rk3368_pmu_grf {u32 gpio0a_iomux;arch/arm/mach-rockchip/rk3368/Makefile +0
-1@@ -5,5 +5,4 @@ # obj-y += clk_rk3368.o obj-y += rk3368.o -obj-y += sdram_rk3368.o obj-y += syscon_rk3368.oarch/arm/mach-rockchip/rk3368/sdram_rk3368.c deleted +0
-60@@ -1,60 +0,0 @@ -/* -* (C) Copyright 2016 Rockchip Electronics Co., Ltd. -* -* SPDX-License-Identifier: GPL-2.0 -*/ - -#include <common.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/sdram_common.h> - -DECLARE_GLOBAL_DATA_PTR ; -struct dram_info { -struct ram_info info; -struct rk3368_pmu_grf *pmugrf; -}; - -static int rk3368_dmc_probe (struct udevice *dev) -{ -struct dram_info *priv =dev_get_priv (dev); - - priv->pmugrf =syscon_get_first_range (ROCKCHIP_SYSCON_PMUGRF ); -debug ("%s: grf=%p\n" , __func__, priv->pmugrf); - priv->info.base =CONFIG_SYS_SDRAM_BASE ; - priv->info.size =rockchip_sdram_size ( - (phys_addr_t)&priv->pmugrf->os_reg[2 ]); - -return 0 ; -} - -static int rk3368_dmc_get_info (struct udevice *dev,struct ram_info *info) -{ -struct dram_info *priv =dev_get_priv (dev); - - *info = priv->info; - -return 0 ; -} - -static struct ram_ops rk3368_dmc_ops = { - .get_info = rk3368_dmc_get_info, -}; - - -static const struct udevice_id rk3368_dmc_ids[] = { - { .compatible ="rockchip,rk3368-dmc" }, - { } -}; - -U_BOOT_DRIVER (dmc_rk3368) = { - .name ="rockchip_rk3368_dmc" , - .id =UCLASS_RAM , - .of_match = rk3368_dmc_ids, - .ops = &rk3368_dmc_ops, - .probe = rk3368_dmc_probe, - .priv_auto_alloc_size =sizeof (struct dram_info ), -};doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt new file +67
-0@@ -0,0 +1,67 @@ +RK3368 dynamic memory controller driver +======================================= + +The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation +during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on +the following key configuration data: + (a) a target-frequency (i.e. operating point) for the memory operation + (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware + (c) a memory-schedule (i.e. mapping from physical addresses to the address + pins of the memory bus) + +Required properties +------------------- + +- compatible: "rockchip,rk3368-dmc" +- reg + protocol controller (PCTL) address and PHY controller (DDRPHY) address +- rockchip,ddr-speed-bin + the DDR3 device's speed-bin (as specified according to JESD-79) + DDR3_800D (5-5-5) + DDR3_800E (6-6-6) + DDR3_1066E (6-6-6) + DDR3_1066F (7-7-7) + DDR3_1066G (8-8-8) + DDR3_1333F (7-7-7) + DDR3_1333G (8-8-8) + DDR3_1333H (9-9-9) + DDR3_1333J (10-10-10) + DDR3_1600G (8-8-8) + DDR3_1600H (9-9-9) + DDR3_1600J (10-10-10) + DDR3_1600K (11-11-11) + DDR3_1866J (10-10-10) + DDR3_1866K (11-11-11) + DDR3_1866L (12-12-12) + DDR3_1866M (13-13-13) + DDR3_2133K (11-11-11) + DDR3_2133L (12-12-12) + DDR3_2133M (13-13-13) + DDR3_2133N (14-14-14) +- rockchip,ddr-frequency: + target DDR clock frequency in Hz (not all frequencies may be supported, + as there's some cooperation from the clock-driver required) +- rockchip,memory-schedule: + controls the decoding of physical addresses to DRAM addressing (i.e. how + the physical address maps onto the address pins/chip-select of the device) + DMC_MSCH_CBDR: column -> bank -> device -> row + DMC_MSCH_CBRD: column -> band -> row -> device + DMC_MSCH_CRBD: column -> row -> band -> device + +Example (for DDR3-1600K and 800MHz) +----------------------------------- + + #include <dt-bindings/memory/rk3368-dmc.h> + + dmc: dmc at ff610000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3368-dmc"; + reg = <0 0xff610000 0 0x400 + 0 0xff620000 0 0x400>; + }; + + &dmc { + rockchip,ddr-speed-bin = <DDR3_1600K>; + rockchip,ddr-frequency = <800000000>; + rockchip,memory-schedule = <DMC_MSCH_CBRD>; + };drivers/ram/Makefile +2
-0@@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o + +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/drivers/ram/rockchip/Makefile new file +7
-0@@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.odrivers/ram/rockchip/dmc-rk3368.c new file +990
-0@@ -0,0 +1,990 @@ +/* +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dt-bindings/memory/rk3368-dmc.h> +#include <dt-structs.h> +#include <ram.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3368.h> +#include <asm/arch/grf_rk3368.h> +#include <asm/arch/ddr_rk3368.h> +#include <asm/arch/sdram.h> +#include <asm/arch/sdram_common.h> + +DECLARE_GLOBAL_DATA_PTR ; + +struct dram_info { +struct ram_info info; +struct clk ddr_clk; +struct rk3368_cru *cru; +struct rk3368_grf *grf; +struct rk3368_ddr_pctl *pctl; +struct rk3368_ddrphy *phy; +struct rk3368_pmu_grf *pmugrf; +struct rk3368_msch *msch; +}; + +struct rk3368_sdram_params { +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +struct dtd_rockchip_rk3368_dmc of_plat; +#endif +struct rk3288_sdram_pctl_timing pctl_timing; +u32 trefi_mem_ddr3; +struct rk3288_sdram_channel chan; +struct regmap *map; +u32 ddr_freq; +u32 memory_schedule; +u32 ddr_speed_bin; +u32 tfaw_mult; +}; + +/* PTCL bits */ +enum { +/* PCTL_DFISTCFG0 */ +DFI_INIT_START =BIT (0 ), +DFI_DATA_BYTE_DISABLE_EN =BIT (2 ), + +/* PCTL_DFISTCFG1 */ +DFI_DRAM_CLK_SR_EN =BIT (0 ), +DFI_DRAM_CLK_DPD_EN =BIT (1 ), +ODT_LEN_BL8_W_SHIFT =16 , + +/* PCTL_DFISTCFG2 */ +DFI_PARITY_INTR_EN =BIT (0 ), +DFI_PARITY_EN =BIT (1 ), + +/* PCTL_DFILPCFG0 */ +TLP_RESP_TIME_SHIFT =16 , +LP_SR_EN =BIT (8 ), +LP_PD_EN =BIT (0 ), + +/* PCTL_DFIODTCFG */ +RANK0_ODT_WRITE_SEL =BIT (3 ), +RANK1_ODT_WRITE_SEL =BIT (11 ), + +/* PCTL_SCFG */ +HW_LOW_POWER_EN =BIT (0 ), + +/* PCTL_MCMD */ +START_CMD =BIT (31 ), +MCMD_RANK0 =BIT (20 ), +MCMD_RANK1 =BIT (21 ), +DESELECT_CMD =0 , +PREA_CMD , +REF_CMD , +MRS_CMD , +ZQCS_CMD , +ZQCL_CMD , +RSTL_CMD , +MRR_CMD =8 , +DPDE_CMD , + +/* PCTL_POWCTL */ +POWER_UP_START =BIT (0 ), + +/* PCTL_POWSTAT */ +POWER_UP_DONE =BIT (0 ), + +/* PCTL_SCTL */ +INIT_STATE =0 , +CFG_STATE , +GO_STATE , +SLEEP_STATE , +WAKEUP_STATE , + +/* PCTL_STAT */ +LP_TRIG_SHIFT =4 , +LP_TRIG_MASK =7 , +PCTL_STAT_MSK =7 , +INIT_MEM =0 , +CONFIG , +CONFIG_REQ , +ACCESS , +ACCESS_REQ , +LOW_POWER , +LOW_POWER_ENTRY_REQ , +LOW_POWER_EXIT_REQ , + +/* PCTL_MCFG */ +DDR2_DDR3_BL_8 =BIT (0 ), +DDR3_EN =BIT (5 ), +TFAW_TRRD_MULT4 = (0 <<18 ), +TFAW_TRRD_MULT5 = (1 <<18 ), +TFAW_TRRD_MULT6 = (2 <<18 ), +}; + +#define DDR3_MR0_WR (n) \ + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9)) +#define DDR3_MR0_CL (n) \ + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2)) +#define DDR3_MR0_BL8 \ + (0 << 0) +#define DDR3_MR0_DLL_RESET \ + (1 << 8) +#define DDR3_MR1_RTT120OHM \ + ((0 << 9) | (1 << 6) | (0 << 2)) +#define DDR3_MR2_TWL (n) \ + (((n - 5) & 0x7) << 3) + + +#ifdef CONFIG_TPL_BUILD + +static void ddr_set_noc_spr_err_stall (struct rk3368_grf *grf,bool enable) +{ +if (enable) +rk_setreg (&grf->ddrc0_con0,NOC_RSP_ERR_STALL ); +else +rk_clrreg (&grf->ddrc0_con0,NOC_RSP_ERR_STALL ); +} + +static void ddr_set_ddr3_mode (struct rk3368_grf *grf,bool ddr3_mode) +{ +if (ddr3_mode) +rk_setreg (&grf->ddrc0_con0,MSCH0_MAINDDR3_DDR3 ); +else +rk_clrreg (&grf->ddrc0_con0,MSCH0_MAINDDR3_DDR3 ); +} + +static void ddrphy_config (struct rk3368_ddrphy *phy, +u32 tcl,u32 tal,u32 tcwl) +{ +int i; + +/* Set to DDR3 mode */ +clrsetbits_le32 (&phy->reg[1 ],0x3 ,0x0 ); + +/* DDRPHY_REGB: CL, AL */ +clrsetbits_le32 (&phy->reg[0xb ],0xff , tcl <<4 | tal); +/* DDRPHY_REGC: CWL */ +clrsetbits_le32 (&phy->reg[0xc ],0x0f , tcwl); + +/* Update drive-strength */ +writel (0xcc , &phy->reg[0x11 ]); +writel (0xaa , &phy->reg[0x16 ]); +/* +* Update NRCOMP/PRCOMP for all 4 channels (for details of all +* affected registers refer to the documentation of DDRPHY_REG20 +* and DDRPHY_REG21 in the RK3368 TRM. +*/ +for (i =0 ; i <4 ; ++i) { +writel (0xcc , &phy->reg[0x20 + i *0x10 ]); +writel (0x44 , &phy->reg[0x21 + i *0x10 ]); + } + +/* Enable write-leveling calibration bypass */ +setbits_le32 (&phy->reg[2 ],BIT (3 )); +} + +static void copy_to_reg (u32 *dest,const u32 *src,u32 n) +{ +int i; + +for (i =0 ; i < n /sizeof (u32); i++) +writel (*src++, dest++); +} + +static void send_command (struct rk3368_ddr_pctl *pctl,u32 rank,u32 cmd) +{ +u32 mcmd =START_CMD | cmd | rank; + +debug ("%s: writing %x to MCMD\n" , __func__, mcmd); +writel (mcmd, &pctl->mcmd); +while (readl (&pctl->mcmd) &START_CMD ) +/* spin */ ; +} + +static void send_mrs (struct rk3368_ddr_pctl *pctl, +u32 rank,u32 mr_num,u32 mr_data) +{ +u32 mcmd =START_CMD |MRS_CMD | rank | (mr_num <<17 ) | (mr_data <<4 ); + +debug ("%s: writing %x to MCMD\n" , __func__, mcmd); +writel (mcmd, &pctl->mcmd); +while (readl (&pctl->mcmd) &START_CMD ) +/* spin */ ; +} + +static int memory_init (struct rk3368_ddr_pctl *pctl, +struct rk3368_sdram_params *params) +{ +u32 mr[4 ]; +const ulong timeout_ms =500 ; +ulong tmp; + +/* +* Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and +* wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register +* of PCTL. +*/ +writel (POWER_UP_START , &pctl->powctl); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: POWER_UP_START did not complete in %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while (!(readl (&pctl->powstat) &POWER_UP_DONE )); + +/* Configure MR0 through MR3 */ + mr[0 ] =DDR3_MR0_WR (params->pctl_timing.twr) | +DDR3_MR0_CL (params->pctl_timing.tcl) | +DDR3_MR0_DLL_RESET ; + mr[1 ] =DDR3_MR1_RTT120OHM ; + mr[2 ] =DDR3_MR2_TWL (params->pctl_timing.tcwl); + mr[3 ] =0 ; + +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.2 Initialization (DDR3 Initialization Sequence)" +*/ +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,DESELECT_CMD ); +udelay (1 ); +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,PREA_CMD ); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,2 , mr[2 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,3 , mr[3 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,1 , mr[1 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,0 , mr[0 ]); +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,ZQCL_CMD ); + +return 0 ; +} + +static void move_to_config_state (struct rk3368_ddr_pctl *pctl) +{ +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.1 State transition of PCTL (Moving to Config State)" +*/ +u32 state =readl (&pctl->stat) &PCTL_STAT_MSK ; + +switch (state) { +case LOW_POWER : +writel (WAKEUP_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=ACCESS ) +/* spin */ ; + +/* fall-through */ +case ACCESS : +case INIT_MEM : +writel (CFG_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=CONFIG ) +/* spin */ ; +break ; + +case CONFIG : +return ; + +default : +break ; + } +} + +static void move_to_access_state (struct rk3368_ddr_pctl *pctl) +{ +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.1 State transition of PCTL (Moving to Access State)" +*/ +u32 state =readl (&pctl->stat) &PCTL_STAT_MSK ; + +switch (state) { +case LOW_POWER : +if (((readl (&pctl->stat) >>LP_TRIG_SHIFT ) & +LP_TRIG_MASK ) ==1 ) +return ; + +writel (WAKEUP_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=ACCESS ) +/* spin */ ; + +/* fall-through */ +case INIT_MEM : +writel (CFG_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=CONFIG ) +/* spin */ ; + +/* fall-through */ +case CONFIG : +writel (GO_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) ==CONFIG ) +/* spin */ ; +break ; + +case ACCESS : +return ; + +default : +break ; + } +} + +static void ddrctl_reset (struct rk3368_cru *cru) +{ +const u32 ctl_reset =BIT (3 ) |BIT (2 ); +const u32 phy_reset =BIT (1 ) |BIT (0 ); + +rk_setreg (&cru->softrst_con[10 ], ctl_reset | phy_reset); +udelay (1 ); +rk_clrreg (&cru->softrst_con[10 ], ctl_reset | phy_reset); +} + +static void ddrphy_reset (struct rk3368_ddrphy *ddrphy) +{ +clrbits_le32 (&ddrphy->reg[0 ],BIT (3 ) |BIT (2 )); +udelay (1 ); +setbits_le32 (&ddrphy->reg[0 ],BIT (3 ) |BIT (2 )); +} + +static void ddrphy_config_delays (struct rk3368_ddrphy *ddrphy,u32 freq) +{ +u32 dqs_dll_delay; + +setbits_le32 (&ddrphy->reg[0x13 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x14 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x26 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x27 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x36 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x37 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x46 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x47 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x56 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x57 ],BIT (3 )); + +if (freq <=400000000 ) +setbits_le32 (&ddrphy->reg[0xa4 ],0x1f ); +else +clrbits_le32 (&ddrphy->reg[0xa4 ],0x1f ); + +if (freq <681000000 ) + dqs_dll_delay =3 ;/* 67.5 degree delay */ +else + dqs_dll_delay =2 ;/* 45 degree delay */ + +writel (dqs_dll_delay, &ddrphy->reg[0x28 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x38 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x48 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x58 ]); +} + +static int dfi_cfg (struct rk3368_ddr_pctl *pctl) +{ +const ulong timeout_ms =200 ; +ulong tmp; + +writel (DFI_DATA_BYTE_DISABLE_EN , &pctl->dfistcfg0); + +writel (DFI_DRAM_CLK_SR_EN |DFI_DRAM_CLK_DPD_EN , + &pctl->dfistcfg1); +writel (DFI_PARITY_INTR_EN |DFI_PARITY_EN , &pctl->dfistcfg2); +writel (7 <<TLP_RESP_TIME_SHIFT |LP_SR_EN |LP_PD_EN , + &pctl->dfilpcfg0); + +writel (1 , &pctl->dfitphyupdtype0); + +writel (0x1f , &pctl->dfitphyrdlat); +writel (0 , &pctl->dfitphywrdata); +writel (0 , &pctl->dfiupdcfg);/* phyupd and ctrlupd disabled */ + +setbits_le32 (&pctl->dfistcfg0,DFI_INIT_START ); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: DFI init did not complete within %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while ((readl (&pctl->dfiststat0) &1 ) ==0 ); + +return 0 ; +} + +static inline u32 ps_to_tCK (const u32 ps,const ulong freq) +{ +const ulong MHz =1000000 ; +return DIV_ROUND_UP (ps * freq,1000000 * MHz); +} + +static inline u32 ns_to_tCK (const u32 ns,const ulong freq) +{ +return ps_to_tCK (ns *1000 , freq); +} + +static inline u32 tCK_to_ps (const ulong tCK,const ulong freq) +{ +const ulong MHz =1000000 ; +return DIV_ROUND_UP (tCK *1000000 * MHz, freq); +} + +static int pctl_calc_timings (struct rk3368_sdram_params *params, +ulong freq) +{ +struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing; +const ulong MHz =1000000 ; +u32 tccd; +u32 tfaw_as_ps; + +if (params->ddr_speed_bin !=DDR3_1600K ) { +error ("%s: unimplemented DDR3 speed bin %d\n" , + __func__, params->ddr_speed_bin); +return -1 ; + } + +/* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */ + pctl_timing->togcnt1u =DIV_ROUND_UP (freq,2 * MHz); + pctl_timing->togcnt100n =DIV_ROUND_UP (freq /10 ,2 * MHz); + + pctl_timing->tinit =200 ;/* 200 usec */ + pctl_timing->trsth =500 ;/* 500 usec */ + pctl_timing->trefi =78 ;/* 7.8usec = 78 * 100ns */ + params->trefi_mem_ddr3 =ns_to_tCK (pctl_timing->trefi *100 , freq); + +if (freq <= (400 * MHz)) { + pctl_timing->tcl =6 ; + pctl_timing->tcwl =10 ; + }else if (freq <= (533 * MHz)) { + pctl_timing->tcl =8 ; + pctl_timing->tcwl =6 ; + }else if (freq <= (666 * MHz)) { + pctl_timing->tcl =10 ; + pctl_timing->tcwl =7 ; + }else { + pctl_timing->tcl =11 ; + pctl_timing->tcwl =8 ; + } + + pctl_timing->tmrd =4 ;/* 4 tCK (all speed bins) */ + pctl_timing->trfc =ns_to_tCK (350 , freq);/* tRFC: 350 (max) @ 8GBit */ + pctl_timing->trp =max (4u ,ps_to_tCK (13750 , freq)); +/* +* JESD-79: +* READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL +*/ + tccd =4 ; + pctl_timing->trtw = pctl_timing->tcl + tccd/2 +2 - pctl_timing->tcwl; + pctl_timing->tal =0 ; + pctl_timing->tras =ps_to_tCK (35000 , freq); + pctl_timing->trc =ps_to_tCK (48750 , freq); + pctl_timing->trcd =ps_to_tCK (13750 , freq); + pctl_timing->trrd =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->trtp =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->twr =ps_to_tCK (15000 , freq); +/* The DDR3 mode-register does only support even values for tWR > 8. */ +if (pctl_timing->twr >8 ) + pctl_timing->twr = (pctl_timing->twr +1 ) & ~1 ; + pctl_timing->twtr =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->texsr =512 ;/* tEXSR(max) is tDLLLK */ + pctl_timing->txp =max (3u ,ps_to_tCK (6000 , freq)); + pctl_timing->txpdll =max (10u ,ps_to_tCK (24000 , freq)); + pctl_timing->tzqcs =max (64u ,ps_to_tCK (80000 , freq)); + pctl_timing->tzqcsi =10000 ;/* as used by Rockchip */ + pctl_timing->tdqs =1 ;/* fixed for DDR3 */ + pctl_timing->tcksre =max (5u ,ps_to_tCK (10000 , freq)); + pctl_timing->tcksrx =max (5u ,ps_to_tCK (10000 , freq)); + pctl_timing->tcke =max (3u ,ps_to_tCK (5000 , freq)); + pctl_timing->tmod =max (12u ,ps_to_tCK (15000 , freq)); + pctl_timing->trstl =ns_to_tCK (100 , freq); + pctl_timing->tzqcl =max (256u ,ps_to_tCK (320000 , freq));/* tZQoper */ + pctl_timing->tmrr =0 ; + pctl_timing->tckesr = pctl_timing->tcke +1 ;/* JESD-79: tCKE + 1tCK */ + pctl_timing->tdpd =0 ;/* RK3368 TRM: "allowed values for DDR3: 0" */ + + +/* +* The controller can represent tFAW as 4x, 5x or 6x tRRD only. +* We want to use the smallest multiplier that satisfies the tFAW +* requirements of the given speed-bin. If necessary, we stretch out +* tRRD to allow us to operate on a 6x multiplier for tFAW. +*/ + tfaw_as_ps =40000 ;/* 40ns: tFAW for DDR3-1600K, 2KB page-size */ +if (tCK_to_ps (pctl_timing->trrd *6 , freq) < tfaw_as_ps) { +/* If tFAW is > 6 x tRRD, we need to stretch tRRD */ + pctl_timing->trrd =ps_to_tCK (DIV_ROUND_UP (40000 ,6 ), freq); + params->tfaw_mult =TFAW_TRRD_MULT6 ; + }else if (tCK_to_ps (pctl_timing->trrd *5 , freq) < tfaw_as_ps) { + params->tfaw_mult =TFAW_TRRD_MULT6 ; + }else if (tCK_to_ps (pctl_timing->trrd *4 , freq) < tfaw_as_ps) { + params->tfaw_mult =TFAW_TRRD_MULT5 ; + }else { + params->tfaw_mult =TFAW_TRRD_MULT4 ; + } + +return 0 ; +} + +static void pctl_cfg (struct rk3368_ddr_pctl *pctl, +struct rk3368_sdram_params *params, +struct rk3368_grf *grf) +{ +/* Configure PCTL timing registers */ + params->pctl_timing.trefi |=BIT (31 );/* see PCTL_TREFI */ +copy_to_reg (&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u, +sizeof (params->pctl_timing)); +writel (params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3); + +/* Set up ODT write selector and ODT write length */ +writel ((RANK0_ODT_WRITE_SEL |RANK1_ODT_WRITE_SEL ), &pctl->dfiodtcfg); +writel (7 <<ODT_LEN_BL8_W_SHIFT , &pctl->dfiodtcfg1); + +/* Set up the CL/CWL-dependent timings of DFI */ +writel ((params->pctl_timing.tcl -1 ) /2 -1 , &pctl->dfitrddataen); +writel ((params->pctl_timing.tcwl -1 ) /2 -1 , &pctl->dfitphywrlat); + +/* DDR3 */ +writel (params->tfaw_mult |DDR3_EN |DDR2_DDR3_BL_8 , &pctl->mcfg); +writel (0x001c0004 , &grf->ddrc0_con0); + +setbits_le32 (&pctl->scfg,HW_LOW_POWER_EN ); +} + +static int ddrphy_data_training (struct rk3368_ddr_pctl *pctl, +struct rk3368_ddrphy *ddrphy) +{ +const u32 trefi =readl (&pctl->trefi); +const ulong timeout_ms =500 ; +ulong tmp; + +/* disable auto-refresh */ +writel (0 |BIT (31 ), &pctl->trefi); + +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x20 ); +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x21 ); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: did not complete within %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while ((readl (&ddrphy->reg[0xff ]) &0xf ) !=0xf ); + +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,PREA_CMD ); +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x20 ); +/* resume auto-refresh */ +writel (trefi |BIT (31 ), &pctl->trefi); + +return 0 ; +} + +static int sdram_col_row_detect (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_sdram_params *params =dev_get_platdata (dev); +struct rk3368_ddr_pctl *pctl = priv->pctl; +struct rk3368_msch *msch = priv->msch; +const u32 test_pattern =0x5aa5f00f ; +int row, col; +uintptr_t addr; + +move_to_config_state (pctl); +writel (6 , &msch->ddrconf); +move_to_access_state (pctl); + +/* Detect col */ +for (col =11 ; col >=9 ; col--) { +writel (0 ,CONFIG_SYS_SDRAM_BASE ); + addr =CONFIG_SYS_SDRAM_BASE + + (1 << (col + params->chan.bw -1 )); +writel (test_pattern, addr); +if ((readl (addr) == test_pattern) && + (readl (CONFIG_SYS_SDRAM_BASE ) ==0 )) +break ; + } + +if (col ==8 ) { +error ("%s: col detect error\n" , __func__); +return -EINVAL ; + } + +move_to_config_state (pctl); +writel (15 , &msch->ddrconf); +move_to_access_state (pctl); + +/* Detect row*/ +for (row =16 ; row >=12 ; row--) { +writel (0 ,CONFIG_SYS_SDRAM_BASE ); + addr =CONFIG_SYS_SDRAM_BASE + (1 << (row +15 -1 )); +writel (test_pattern, addr); +if ((readl (addr) == test_pattern) && + (readl (CONFIG_SYS_SDRAM_BASE ) ==0 )) +break ; + } + +if (row ==11 ) { +error ("%s: row detect error\n" , __func__); +return -EINVAL ; + } + +/* Record results */ +debug ("%s: col %d, row %d\n" , __func__, col, row); + params->chan.col = col; + params->chan.cs0_row = row; + params->chan.cs1_row = row; + params->chan.row_3_4 =0 ; + +return 0 ; +} + +static int msch_niu_config (struct rk3368_msch *msch, +struct rk3368_sdram_params *params) +{ +int i; +const u8 cols = params->chan.col - ((params->chan.bw ==2 ) ?0 :1 ); +const u8 rows = params->chan.cs0_row; + +/* +* The DDR address-translation table always assumes a 32bit +* bus and the comparison below takes care of adjusting for +* a 16bit bus (i.e. one column-address is consumed). +*/ +const struct { +u8 rows; +u8 columns; +u8 type; + } ddrconf_table[] = { +/* +* C-B-R-D patterns are first. For these we require an +* exact match for the columns and rows (as there's +* one entry per possible configuration). +*/ + [0 ] = { .rows =13 , .columns =10 , .type =DMC_MSCH_CBRD }, + [1 ] = { .rows =14 , .columns =10 , .type =DMC_MSCH_CBRD }, + [2 ] = { .rows =15 , .columns =10 , .type =DMC_MSCH_CBRD }, + [3 ] = { .rows =16 , .columns =10 , .type =DMC_MSCH_CBRD }, + [4 ] = { .rows =14 , .columns =11 , .type =DMC_MSCH_CBRD }, + [5 ] = { .rows =15 , .columns =11 , .type =DMC_MSCH_CBRD }, + [6 ] = { .rows =16 , .columns =11 , .type =DMC_MSCH_CBRD }, + [7 ] = { .rows =13 , .columns =9 , .type =DMC_MSCH_CBRD }, + [8 ] = { .rows =14 , .columns =9 , .type =DMC_MSCH_CBRD }, + [9 ] = { .rows =15 , .columns =9 , .type =DMC_MSCH_CBRD }, + [10 ] = { .rows =16 , .columns =9 , .type =DMC_MSCH_CBRD }, +/* +* 11 through 13 are C-R-B-D patterns. These are +* matched for an exact number of columns and to +* ensure that the hardware uses at least as many rows +* as the pattern requires (i.e. we make sure that +* there's no gaps up until we hit the device/chip-select; +* however, these patterns can accept up to 16 rows, +* as the row-address continues right after the CS +* switching) +*/ + [11 ] = { .rows =15 , .columns =10 , .type =DMC_MSCH_CRBD }, + [12 ] = { .rows =14 , .columns =11 , .type =DMC_MSCH_CRBD }, + [13 ] = { .rows =13 , .columns =10 , .type =DMC_MSCH_CRBD }, +/* +* 14 and 15 are catch-all variants using a C-B-D-R +* scheme (i.e. alternating the chip-select every time +* C-B overflows) and stuffing the remaining C-bits +* into the top. Matching needs to make sure that the +* number of columns is either an exact match (i.e. we +* can use less the the maximum number of rows) -or- +* that the columns exceed what is given in this table +* and the rows are an exact match (in which case the +* remaining C-bits will be stuffed onto the top after +* the device/chip-select switches). +*/ + [14 ] = { .rows =16 , .columns =10 , .type =DMC_MSCH_CBDR }, + [15 ] = { .rows =16 , .columns =9 , .type =DMC_MSCH_CBDR }, + }; + +/* +* For C-B-R-D, we need an exact match (i.e. both for the number of +* columns and rows), while for C-B-D-R, only the the number of +* columns needs to match. +*/ +for (i =0 ; i <ARRAY_SIZE (ddrconf_table); i++) { +bool match = false; + +/* If this entry if for a different matcher, then skip it */ +if (ddrconf_table[i].type != params->memory_schedule) +continue ; + +/* +* Match according to the rules (exact/inexact/at-least) +* documented in the ddrconf_table above. +*/ +switch (params->memory_schedule) { +case DMC_MSCH_CBRD : + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows == rows); +break ; + +case DMC_MSCH_CRBD : + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows <= rows); +break ; + +case DMC_MSCH_CBDR : + match = (ddrconf_table[i].columns == cols) || + ((ddrconf_table[i].columns <= cols) && + (ddrconf_table[i].rows == rows)); +break ; + +default : +break ; + } + +if (match) { +debug ("%s: setting ddrconf 0x%x\n" , __func__, i); +writel (i, &msch->ddrconf); +return 0 ; + } + } + +error ("%s: ddrconf (NIU config) not found\n" , __func__); +return -EINVAL ; +} + +static void dram_all_config (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_pmu_grf *pmugrf = priv->pmugrf; +struct rk3368_sdram_params *params =dev_get_platdata (dev); +const struct rk3288_sdram_channel *info = ¶ms->chan; +u32 sys_reg =0 ; +const int chan =0 ; + + sys_reg |=DDR3 <<SYS_REG_DDRTYPE_SHIFT ; + sys_reg |=0 <<SYS_REG_NUM_CH_SHIFT ; + + sys_reg |= info->row_3_4 <<SYS_REG_ROW_3_4_SHIFT (chan); + sys_reg |=1 <<SYS_REG_CHINFO_SHIFT (chan); + sys_reg |= (info->rank -1 ) <<SYS_REG_RANK_SHIFT (chan); + sys_reg |= (info->col -9 ) <<SYS_REG_COL_SHIFT (chan); + sys_reg |= info->bk ==3 ?0 :1 <<SYS_REG_BK_SHIFT (chan); + sys_reg |= (info->cs0_row -13 ) <<SYS_REG_CS0_ROW_SHIFT (chan); + sys_reg |= (info->cs1_row -13 ) <<SYS_REG_CS1_ROW_SHIFT (chan); + sys_reg |= (2 >> info->bw) <<SYS_REG_BW_SHIFT (chan); + sys_reg |= (2 >> info->dbw) <<SYS_REG_DBW_SHIFT (chan); + +writel (sys_reg, &pmugrf->os_reg[2 ]); +} + +static int setup_sdram (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_sdram_params *params =dev_get_platdata (dev); + +struct rk3368_ddr_pctl *pctl = priv->pctl; +struct rk3368_ddrphy *ddrphy = priv->phy; +struct rk3368_cru *cru = priv->cru; +struct rk3368_grf *grf = priv->grf; +struct rk3368_msch *msch = priv->msch; + +int ret; + +/* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */ + ret =clk_set_rate (&priv->ddr_clk,2 * params->ddr_freq); +if (ret <0 ) { +debug ("%s: could not set DDR clock: %d\n" , __func__, ret); +return ret; + } + +/* Update the read-latency for the RK3368 */ +writel (0x32 , &msch->readlatency); + +/* Initialise the DDR PCTL and DDR PHY */ +ddrctl_reset (cru); +ddrphy_reset (ddrphy); +ddrphy_config_delays (ddrphy, params->ddr_freq); +dfi_cfg (pctl); +/* Configure relative system information of grf_ddrc0_con0 register */ +ddr_set_ddr3_mode (grf, true); +ddr_set_noc_spr_err_stall (grf, true); +/* Calculate timings */ +pctl_calc_timings (params, params->ddr_freq); +/* Initialise the device timings in protocol controller */ +pctl_cfg (pctl, params, grf); +/* Configure AL, CL ... information of PHY registers */ +ddrphy_config (ddrphy, + params->pctl_timing.tcl, + params->pctl_timing.tal, + params->pctl_timing.tcwl); + +/* Initialize DRAM and configure with mode-register values */ + ret =memory_init (pctl, params); +if (ret) + goto error; + +move_to_config_state (pctl); +/* Perform data-training */ +ddrphy_data_training (pctl, ddrphy); +move_to_access_state (pctl); + +/* TODO(prt): could detect rank in training... */ + params->chan.rank =2 ; +/* TODO(prt): bus width is not auto-detected (yet)... */ + params->chan.bw =2 ;/* 32bit wide bus */ + params->chan.dbw = params->chan.dbw;/* 32bit wide bus */ + +/* DDR3 is always 8 bank */ + params->chan.bk =3 ; +/* Detect col and row number */ + ret =sdram_col_row_detect (dev); +if (ret) + goto error; + +/* Configure NIU DDR configuration */ + ret =msch_niu_config (msch, params); +if (ret) + goto error; + +/* set up OS_REG to communicate w/ next stage and OS */ +dram_all_config (dev); + +return 0 ; + +error: +printf ("DRAM init failed!\n" ); +hang (); +} +#endif + +static int rk3368_dmc_ofdata_to_platdata (struct udevice *dev) +{ +int ret =0 ; + +#if !CONFIG_IS_ENABLED (OF_PLATDATA ) +struct rk3368_sdram_params *plat =dev_get_platdata (dev); + + ret =regmap_init_mem (dev, &plat->map); +if (ret) +return ret; +#endif + +return ret; +} + +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +static int conv_of_platdata (struct udevice *dev) +{ +struct rk3368_sdram_params *plat =dev_get_platdata (dev); +struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat; +int ret; + + plat->ddr_freq = of_plat->rockchip_ddr_frequency; + plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin; + plat->memory_schedule = of_plat->rockchip_memory_schedule; + + ret =regmap_init_mem_platdata (dev, of_plat->reg, +ARRAY_SIZE (of_plat->reg) /2 , + &plat->map); +if (ret) +return ret; + +return 0 ; +} +#endif + +static int rk3368_dmc_probe (struct udevice *dev) +{ +#ifdef CONFIG_TPL_BUILD +struct rk3368_sdram_params *plat =dev_get_platdata (dev); +struct rk3368_ddr_pctl *pctl; +struct rk3368_ddrphy *ddrphy; +struct rk3368_cru *cru; +struct rk3368_grf *grf; +struct rk3368_msch *msch; +int ret; +struct udevice *dev_clk; +#endif +struct dram_info *priv =dev_get_priv (dev); + +#if CONFIG_IS_ENABLED (OF_PLATDATA ) + ret =conv_of_platdata (dev); +if (ret) +return ret; +#endif + + priv->pmugrf =syscon_get_first_range (ROCKCHIP_SYSCON_PMUGRF ); +debug ("%s: pmugrf=%p\n" , __func__, priv->pmugrf); + +#ifdef CONFIG_TPL_BUILD + pctl =regmap_get_range (plat->map,0 ); + ddrphy =regmap_get_range (plat->map,1 ); + msch =syscon_get_first_range (ROCKCHIP_SYSCON_MSCH ); + grf =syscon_get_first_range (ROCKCHIP_SYSCON_GRF ); + + priv->pctl = pctl; + priv->phy = ddrphy; + priv->msch = msch; + priv->grf = grf; + + ret =rockchip_get_clk (&dev_clk); +if (ret) +return ret; + priv->ddr_clk.id =CLK_DDR ; + ret =clk_request (dev_clk, &priv->ddr_clk); +if (ret) +return ret; + + cru =rockchip_get_cru (); + priv->cru = cru; +if (IS_ERR (priv->cru)) +return PTR_ERR (priv->cru); + + ret =setup_sdram (dev); +if (ret) +return ret; +#endif + + priv->info.base =0 ; + priv->info.size = +rockchip_sdram_size ((phys_addr_t)&priv->pmugrf->os_reg[2 ]); + +/* +* we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff +* is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is +* inaccessible for some IP controller. +*/ + priv->info.size =min (priv->info.size, (size_t )0xfe000000 ); + +return 0 ; +} + +static int rk3368_dmc_get_info (struct udevice *dev,struct ram_info *info) +{ +struct dram_info *priv =dev_get_priv (dev); + + *info = priv->info; +return 0 ; +} + +static struct ram_ops rk3368_dmc_ops = { + .get_info = rk3368_dmc_get_info, +}; + + +static const struct udevice_id rk3368_dmc_ids[] = { + { .compatible ="rockchip,rk3368-dmc" }, + { } +}; + +U_BOOT_DRIVER (dmc_rk3368) = { + .name ="rockchip_rk3368_dmc" , + .id =UCLASS_RAM , + .of_match = rk3368_dmc_ids, + .ops = &rk3368_dmc_ops, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size =sizeof (struct dram_info ), + .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size =sizeof (struct dram_info ), + .platdata_auto_alloc_size =sizeof (struct rk3368_sdram_params ), +};include/dt-bindings/memory/rk3368-dmc.h new file +30
-0@@ -0,0 +1,30 @@ +#ifndef DT_BINDINGS_RK3368_DMC_H +#define DT_BINDINGS_RK3368_DMC_H + +#define DMC_MSCH_CBDR 0x0 +#define DMC_MSCH_CBRD 0x1 +#define DMC_MSCH_CRBD 0x2 + +#define DDR3_800D 0 +#define DDR3_800E 1 +#define DDR3_1066E 2 +#define DDR3_1066F 3 +#define DDR3_1066G 4 +#define DDR3_1333F 5 +#define DDR3_1333G 6 +#define DDR3_1333H 7 +#define DDR3_1333J 8 +#define DDR3_1600G 9 +#define DDR3_1600H 10 +#define DDR3_1600J 11 +#define DDR3_1600K 12 +#define DDR3_1866J 13 +#define DDR3_1866K 14 +#define DDR3_1866L 15 +#define DDR3_1866M 16 +#define DDR3_2133K 17 +#define DDR3_2133L 18 +#define DDR3_2133M 19 +#define DDR3_2133N 20 + +#endif
PATCH v3 50/66 rockchip: rk3368: add DRAM controller driver with DRAM initialisation
In reply to Philipp TomsichHi Philipp:
Quoted 1,750 lines · Philipp Tomsich
This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip(where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually).At this stage, only the following feature-set is supported:
- DDR3
- 32-bit configuration (i.e. fully populated)
- dual-rank (i.e. no auto-detection of ranks)
- DDR3-1600K speed-binThis driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the
os_reg2in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code).Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time).
The RK3368 also has the
DDRC0_CON0(DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation.
As part of this change,DDRC0_CON0is also added to the GRF structure definition (at offset0x600).Signed-off-by Philipp Tomsich <[email protected]>Reviewed-by Simon Glass <[email protected]>---
Changes in v3:
- correctly states the location of the driver in the commit messageChanges in v2: None
arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++ arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 + arch/arm/mach-rockchip/rk3368/Makefile | 1 - arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 -- .../clock/rockchip,rk3368-dmc.txt | 67 ++ drivers/ram/Makefile | 2 + drivers/ram/rockchip/Makefile | 7 + drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++ include/dt-bindings/memory/rk3368-dmc.h | 30 + 9 files changed, 1286 insertions(+), 61 deletions(-)create mode 100644
arch/arm/include/asm/arch-rockchip/ddr_rk3368.hdelete mode 100644arch/arm/mach-rockchip/rk3368/sdram_rk3368.ccreate mode 100644doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txtcreate mode 100644drivers/ram/rockchip/Makefile
create mode 100644drivers/ram/rockchip/dmc-rk3368.c
create mode 100644include/dt-bindings/memory/rk3368-dmc.harch/arm/include/asm/arch-rockchip/ddr_rk3368.h new file +79
-0@@ -0,0 +1,187 @@ +/* +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_DDR_RK3368_H__ +#define __ASM_ARCH_DDR_RK3368_H__ + +/* + * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only + * in a few details. Most notably, it has an additional field to track + * tREFI in controller cycles (i.e. trefi_mem_ddr3). + */ +struct rk3368_ddr_pctl { + u32 scfg; + u32 sctl; + u32 stat; + u32 intrstat; + u32 reserved0[12]; + u32 mcmd; + u32 powctl; + u32 powstat; + u32 cmdtstat; + u32 cmdtstaten; + u32 reserved1[3]; + u32 mrrcfg0; + u32 mrrstat0; + u32 mrrstat1; + u32 reserved2[4]; + u32 mcfg1; + u32 mcfg; + u32 ppcfg; + u32 mstat; + u32 lpddr2zqcfg; + u32 reserved3; + u32 dtupdes; + u32 dtuna; + u32 dtune; + u32 dtuprd0; + u32 dtuprd1; + u32 dtuprd2; + u32 dtuprd3; + u32 dtuawdt; + u32 reserved4[3]; + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tHi Philipp:
Quoted 268 lines · Philipp Tomsich
This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip(where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually).At this stage, only the following feature-set is supported:
- DDR3
- 32-bit configuration (i.e. fully populated)
- dual-rank (i.e. no auto-detection of ranks)
- DDR3-1600K speed-binThis driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the
os_reg2in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code).Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time).
The RK3368 also has the
DDRC0_CON0(DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation.
As part of this change,DDRC0_CON0is also added to the GRF structure definition (at offset0x600).Signed-off-by Philipp Tomsich <[email protected]>Reviewed-by Simon Glass <[email protected]>---
Changes in v3:
- correctly states the location of the driver in the commit messageChanges in v2: None
arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++ arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 + arch/arm/mach-rockchip/rk3368/Makefile | 1 - arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 -- .../clock/rockchip,rk3368-dmc.txt | 67 ++ drivers/ram/Makefile | 2 + drivers/ram/rockchip/Makefile | 7 + drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++ include/dt-bindings/memory/rk3368-dmc.h | 30 + 9 files changed, 1286 insertions(+), 61 deletions(-)create mode 100644
arch/arm/include/asm/arch-rockchip/ddr_rk3368.hdelete mode 100644arch/arm/mach-rockchip/rk3368/sdram_rk3368.ccreate mode 100644doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txtcreate mode 100644drivers/ram/rockchip/Makefile
create mode 100644drivers/ram/rockchip/dmc-rk3368.c
create mode 100644include/dt-bindings/memory/rk3368-dmc.harch/arm/include/asm/arch-rockchip/ddr_rk3368.h new file +187
-0@@ -0,0 +1,187 @@ +/* +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_DDR_RK3368_H__ +#define __ASM_ARCH_DDR_RK3368_H__ + +/* +* The RK3368 DDR PCTL differs from the incarnation in the RK3288 only +* in a few details. Most notably, it has an additional field to track +* tREFI in controller cycles (i.e. trefi_mem_ddr3). +*/ +struct rk3368_ddr_pctl { +u32 scfg; +u32 sctl; +u32 stat; +u32 intrstat; +u32 reserved0[12 ]; +u32 mcmd; +u32 powctl; +u32 powstat; +u32 cmdtstat; +u32 cmdtstaten; +u32 reserved1[3 ]; +u32 mrrcfg0; +u32 mrrstat0; +u32 mrrstat1; +u32 reserved2[4 ]; +u32 mcfg1; +u32 mcfg; +u32 ppcfg; +u32 mstat; +u32 lpddr2zqcfg; +u32 reserved3; +u32 dtupdes; +u32 dtuna; +u32 dtune; +u32 dtuprd0; +u32 dtuprd1; +u32 dtuprd2; +u32 dtuprd3; +u32 dtuawdt; +u32 reserved4[3 ]; +u32 togcnt1u; +u32 tinit; +u32 trsth; +u32 togcnt100n; +u32 trefi; +u32 tmrd; +u32 trfc; +u32 trp; +u32 trtw; +u32 tal; +u32 tcl; +u32 tcwl; +u32 tras; +u32 trc; +u32 trcd; +u32 trrd; +u32 trtp; +u32 twr; +u32 twtr; +u32 texsr; +u32 txp; +u32 txpdll; +u32 tzqcs; +u32 tzqcsi; +u32 tdqs; +u32 tcksre; +u32 tcksrx; +u32 tcke; +u32 tmod; +u32 trstl; +u32 tzqcl; +u32 tmrr; +u32 tckesr; +u32 tdpd; +u32 trefi_mem_ddr3; +u32 reserved5[45 ]; +u32 dtuwactl; +u32 dturactl; +u32 dtucfg; +u32 dtuectl; +u32 dtuwd0; +u32 dtuwd1; +u32 dtuwd2; +u32 dtuwd3; +u32 dtuwdm; +u32 dturd0; +u32 dturd1; +u32 dturd2; +u32 dturd3; +u32 dtulfsrwd; +u32 dtulfsrrd; +u32 dtueaf; +u32 dfitctrldelay; +u32 dfiodtcfg; +u32 dfiodtcfg1; +u32 dfiodtrankmap; +u32 dfitphywrdata; +u32 dfitphywrlat; +u32 reserved7[2 ]; +u32 dfitrddataen; +u32 dfitphyrdlat; +u32 reserved8[2 ]; +u32 dfitphyupdtype0; +u32 dfitphyupdtype1; +u32 dfitphyupdtype2; +u32 dfitphyupdtype3; +u32 dfitctrlupdmin; +u32 dfitctrlupdmax; +u32 dfitctrlupddly; +u32 reserved9; +u32 dfiupdcfg; +u32 dfitrefmski; +u32 dfitctrlupdi; +u32 reserved10[4 ]; +u32 dfitrcfg0; +u32 dfitrstat0; +u32 dfitrwrlvlen; +u32 dfitrrdlvlen; +u32 dfitrrdlvlgateen; +u32 dfiststat0; +u32 dfistcfg0; +u32 dfistcfg1; +u32 reserved11; +u32 dfitdramclken; +u32 dfitdramclkdis; +u32 dfistcfg2; +u32 dfistparclr; +u32 dfistparlog; +u32 reserved12[3 ]; +u32 dfilpcfg0; +u32 reserved13[3 ]; +u32 dfitrwrlvlresp0; +u32 dfitrwrlvlresp1; +u32 dfitrwrlvlresp2; +u32 dfitrrdlvlresp0; +u32 dfitrrdlvlresp1; +u32 dfitrrdlvlresp2; +u32 dfitrwrlvldelay0; +u32 dfitrwrlvldelay1; +u32 dfitrwrlvldelay2; +u32 dfitrrdlvldelay0; +u32 dfitrrdlvldelay1; +u32 dfitrrdlvldelay2; +u32 dfitrrdlvlgatedelay0; +u32 dfitrrdlvlgatedelay1; +u32 dfitrrdlvlgatedelay2; +u32 dfitrcmd; +u32 reserved14[46 ]; +u32 ipvr; +u32 iptr; +}; +check_member (rk3368_ddr_pctl, iptr,0x03fc ); + +struct rk3368_ddrphy { +u32 reg[0x100 ]; +}; +check_member (rk3368_ddrphy, reg[0xff ],0x03fc ); + +struct rk3368_msch { +u32 coreid; +u32 revisionid; +u32 ddrconf; +u32 ddrtiming; +u32 ddrmode; +u32 readlatency; +u32 reserved1[8 ]; +u32 activate; +u32 devtodev; +}; +check_member (rk3368_msch, devtodev,0x003c ); + +/* GRF_SOC_CON0 */ +enum { +NOC_RSP_ERR_STALL =BIT (9 ), +MOBILE_DDR_SEL =BIT (4 ), +DDR0_16BIT_EN =BIT (3 ), +MSCH0_MAINDDR3_DDR3 =BIT (2 ), +MSCH0_MAINPARTIALPOP =BIT (1 ), +UPCTL_C_ACTIVE =BIT (0 ), +}; + +#endif arch/arm/include/asm/arch-rockchip/grf_rk3368.h +3
-0@@ -76,8 +76,11 @@ struct rk3368_grf {u32 soc_con15;u32 soc_con16;u32 soc_con17; +u32 reserved5[0x6e ]; +u32 ddrc0_con0; };check_member (rk3368_grf, soc_con17,0x444 ); +check_member (rk3368_grf, ddrc0_con0,0x600 );struct rk3368_pmu_grf {u32 gpio0a_iomux;arch/arm/mach-rockchip/rk3368/Makefile +0
-0arch/arm/mach-rockchip/rk3368/Makefile line 8
Quoted 5 lines
arch/arm/mach-rockchip/rk3368/Makefile +0
-1@@ -5,5 +5,4 @@ # obj-y += clk_rk3368.o obj-y += rk3368.o -obj-y += sdram_rk3368.o obj-y += syscon_rk3368.othe current PX5 EVB and Sheep board(they don't use spl now) depend on
thesdram_rk3368driver to get the sdram capacity, and so is the geekbox.
They will be broken when this driver removed.We got the boot failed log on PX5 like bellow:
Quoted 1,184 lines
arch/arm/mach-rockchip/rk3368/sdram_rk3368.c deleted +0
-60@@ -1,60 +0,0 @@ -/* -* (C) Copyright 2016 Rockchip Electronics Co., Ltd. -* -* SPDX-License-Identifier: GPL-2.0 -*/ - -#include <common.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/sdram_common.h> - -DECLARE_GLOBAL_DATA_PTR ; -struct dram_info { -struct ram_info info; -struct rk3368_pmu_grf *pmugrf; -}; - -static int rk3368_dmc_probe (struct udevice *dev) -{ -struct dram_info *priv =dev_get_priv (dev); - - priv->pmugrf =syscon_get_first_range (ROCKCHIP_SYSCON_PMUGRF ); -debug ("%s: grf=%p\n" , __func__, priv->pmugrf); - priv->info.base =CONFIG_SYS_SDRAM_BASE ; - priv->info.size =rockchip_sdram_size ( - (phys_addr_t)&priv->pmugrf->os_reg[2 ]); - -return 0 ; -} - -static int rk3368_dmc_get_info (struct udevice *dev,struct ram_info *info) -{ -struct dram_info *priv =dev_get_priv (dev); - - *info = priv->info; - -return 0 ; -} - -static struct ram_ops rk3368_dmc_ops = { - .get_info = rk3368_dmc_get_info, -}; - - -static const struct udevice_id rk3368_dmc_ids[] = { - { .compatible ="rockchip,rk3368-dmc" }, - { } -}; - -U_BOOT_DRIVER (dmc_rk3368) = { - .name ="rockchip_rk3368_dmc" , - .id =UCLASS_RAM , - .of_match = rk3368_dmc_ids, - .ops = &rk3368_dmc_ops, - .probe = rk3368_dmc_probe, - .priv_auto_alloc_size =sizeof (struct dram_info ), -};doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt new file +67
-0@@ -0,0 +1,67 @@ +RK3368 dynamic memory controller driver +======================================= + +The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation +during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on +the following key configuration data: + (a) a target-frequency (i.e. operating point) for the memory operation + (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware + (c) a memory-schedule (i.e. mapping from physical addresses to the address + pins of the memory bus) + +Required properties +------------------- + +- compatible: "rockchip,rk3368-dmc" +- reg + protocol controller (PCTL) address and PHY controller (DDRPHY) address +- rockchip,ddr-speed-bin + the DDR3 device's speed-bin (as specified according to JESD-79) + DDR3_800D (5-5-5) + DDR3_800E (6-6-6) + DDR3_1066E (6-6-6) + DDR3_1066F (7-7-7) + DDR3_1066G (8-8-8) + DDR3_1333F (7-7-7) + DDR3_1333G (8-8-8) + DDR3_1333H (9-9-9) + DDR3_1333J (10-10-10) + DDR3_1600G (8-8-8) + DDR3_1600H (9-9-9) + DDR3_1600J (10-10-10) + DDR3_1600K (11-11-11) + DDR3_1866J (10-10-10) + DDR3_1866K (11-11-11) + DDR3_1866L (12-12-12) + DDR3_1866M (13-13-13) + DDR3_2133K (11-11-11) + DDR3_2133L (12-12-12) + DDR3_2133M (13-13-13) + DDR3_2133N (14-14-14) +- rockchip,ddr-frequency: + target DDR clock frequency in Hz (not all frequencies may be supported, + as there's some cooperation from the clock-driver required) +- rockchip,memory-schedule: + controls the decoding of physical addresses to DRAM addressing (i.e. how + the physical address maps onto the address pins/chip-select of the device) + DMC_MSCH_CBDR: column -> bank -> device -> row + DMC_MSCH_CBRD: column -> band -> row -> device + DMC_MSCH_CRBD: column -> row -> band -> device + +Example (for DDR3-1600K and 800MHz) +----------------------------------- + + #include <dt-bindings/memory/rk3368-dmc.h> + + dmc: dmc at ff610000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3368-dmc"; + reg = <0 0xff610000 0 0x400 + 0 0xff620000 0 0x400>; + }; + + &dmc { + rockchip,ddr-speed-bin = <DDR3_1600K>; + rockchip,ddr-frequency = <800000000>; + rockchip,memory-schedule = <DMC_MSCH_CBRD>; + };drivers/ram/Makefile +2
-0@@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o + +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/drivers/ram/rockchip/Makefile new file +7
-0@@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.odrivers/ram/rockchip/dmc-rk3368.c new file +990
-0@@ -0,0 +1,990 @@ +/* +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dt-bindings/memory/rk3368-dmc.h> +#include <dt-structs.h> +#include <ram.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3368.h> +#include <asm/arch/grf_rk3368.h> +#include <asm/arch/ddr_rk3368.h> +#include <asm/arch/sdram.h> +#include <asm/arch/sdram_common.h> + +DECLARE_GLOBAL_DATA_PTR ; + +struct dram_info { +struct ram_info info; +struct clk ddr_clk; +struct rk3368_cru *cru; +struct rk3368_grf *grf; +struct rk3368_ddr_pctl *pctl; +struct rk3368_ddrphy *phy; +struct rk3368_pmu_grf *pmugrf; +struct rk3368_msch *msch; +}; + +struct rk3368_sdram_params { +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +struct dtd_rockchip_rk3368_dmc of_plat; +#endif +struct rk3288_sdram_pctl_timing pctl_timing; +u32 trefi_mem_ddr3; +struct rk3288_sdram_channel chan; +struct regmap *map; +u32 ddr_freq; +u32 memory_schedule; +u32 ddr_speed_bin; +u32 tfaw_mult; +}; + +/* PTCL bits */ +enum { +/* PCTL_DFISTCFG0 */ +DFI_INIT_START =BIT (0 ), +DFI_DATA_BYTE_DISABLE_EN =BIT (2 ), + +/* PCTL_DFISTCFG1 */ +DFI_DRAM_CLK_SR_EN =BIT (0 ), +DFI_DRAM_CLK_DPD_EN =BIT (1 ), +ODT_LEN_BL8_W_SHIFT =16 , + +/* PCTL_DFISTCFG2 */ +DFI_PARITY_INTR_EN =BIT (0 ), +DFI_PARITY_EN =BIT (1 ), + +/* PCTL_DFILPCFG0 */ +TLP_RESP_TIME_SHIFT =16 , +LP_SR_EN =BIT (8 ), +LP_PD_EN =BIT (0 ), + +/* PCTL_DFIODTCFG */ +RANK0_ODT_WRITE_SEL =BIT (3 ), +RANK1_ODT_WRITE_SEL =BIT (11 ), + +/* PCTL_SCFG */ +HW_LOW_POWER_EN =BIT (0 ), + +/* PCTL_MCMD */ +START_CMD =BIT (31 ), +MCMD_RANK0 =BIT (20 ), +MCMD_RANK1 =BIT (21 ), +DESELECT_CMD =0 , +PREA_CMD , +REF_CMD , +MRS_CMD , +ZQCS_CMD , +ZQCL_CMD , +RSTL_CMD , +MRR_CMD =8 , +DPDE_CMD , + +/* PCTL_POWCTL */ +POWER_UP_START =BIT (0 ), + +/* PCTL_POWSTAT */ +POWER_UP_DONE =BIT (0 ), + +/* PCTL_SCTL */ +INIT_STATE =0 , +CFG_STATE , +GO_STATE , +SLEEP_STATE , +WAKEUP_STATE , + +/* PCTL_STAT */ +LP_TRIG_SHIFT =4 , +LP_TRIG_MASK =7 , +PCTL_STAT_MSK =7 , +INIT_MEM =0 , +CONFIG , +CONFIG_REQ , +ACCESS , +ACCESS_REQ , +LOW_POWER , +LOW_POWER_ENTRY_REQ , +LOW_POWER_EXIT_REQ , + +/* PCTL_MCFG */ +DDR2_DDR3_BL_8 =BIT (0 ), +DDR3_EN =BIT (5 ), +TFAW_TRRD_MULT4 = (0 <<18 ), +TFAW_TRRD_MULT5 = (1 <<18 ), +TFAW_TRRD_MULT6 = (2 <<18 ), +}; + +#define DDR3_MR0_WR (n) \ + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9)) +#define DDR3_MR0_CL (n) \ + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2)) +#define DDR3_MR0_BL8 \ + (0 << 0) +#define DDR3_MR0_DLL_RESET \ + (1 << 8) +#define DDR3_MR1_RTT120OHM \ + ((0 << 9) | (1 << 6) | (0 << 2)) +#define DDR3_MR2_TWL (n) \ + (((n - 5) & 0x7) << 3) + + +#ifdef CONFIG_TPL_BUILD + +static void ddr_set_noc_spr_err_stall (struct rk3368_grf *grf,bool enable) +{ +if (enable) +rk_setreg (&grf->ddrc0_con0,NOC_RSP_ERR_STALL ); +else +rk_clrreg (&grf->ddrc0_con0,NOC_RSP_ERR_STALL ); +} + +static void ddr_set_ddr3_mode (struct rk3368_grf *grf,bool ddr3_mode) +{ +if (ddr3_mode) +rk_setreg (&grf->ddrc0_con0,MSCH0_MAINDDR3_DDR3 ); +else +rk_clrreg (&grf->ddrc0_con0,MSCH0_MAINDDR3_DDR3 ); +} + +static void ddrphy_config (struct rk3368_ddrphy *phy, +u32 tcl,u32 tal,u32 tcwl) +{ +int i; + +/* Set to DDR3 mode */ +clrsetbits_le32 (&phy->reg[1 ],0x3 ,0x0 ); + +/* DDRPHY_REGB: CL, AL */ +clrsetbits_le32 (&phy->reg[0xb ],0xff , tcl <<4 | tal); +/* DDRPHY_REGC: CWL */ +clrsetbits_le32 (&phy->reg[0xc ],0x0f , tcwl); + +/* Update drive-strength */ +writel (0xcc , &phy->reg[0x11 ]); +writel (0xaa , &phy->reg[0x16 ]); +/* +* Update NRCOMP/PRCOMP for all 4 channels (for details of all +* affected registers refer to the documentation of DDRPHY_REG20 +* and DDRPHY_REG21 in the RK3368 TRM. +*/ +for (i =0 ; i <4 ; ++i) { +writel (0xcc , &phy->reg[0x20 + i *0x10 ]); +writel (0x44 , &phy->reg[0x21 + i *0x10 ]); + } + +/* Enable write-leveling calibration bypass */ +setbits_le32 (&phy->reg[2 ],BIT (3 )); +} + +static void copy_to_reg (u32 *dest,const u32 *src,u32 n) +{ +int i; + +for (i =0 ; i < n /sizeof (u32); i++) +writel (*src++, dest++); +} + +static void send_command (struct rk3368_ddr_pctl *pctl,u32 rank,u32 cmd) +{ +u32 mcmd =START_CMD | cmd | rank; + +debug ("%s: writing %x to MCMD\n" , __func__, mcmd); +writel (mcmd, &pctl->mcmd); +while (readl (&pctl->mcmd) &START_CMD ) +/* spin */ ; +} + +static void send_mrs (struct rk3368_ddr_pctl *pctl, +u32 rank,u32 mr_num,u32 mr_data) +{ +u32 mcmd =START_CMD |MRS_CMD | rank | (mr_num <<17 ) | (mr_data <<4 ); + +debug ("%s: writing %x to MCMD\n" , __func__, mcmd); +writel (mcmd, &pctl->mcmd); +while (readl (&pctl->mcmd) &START_CMD ) +/* spin */ ; +} + +static int memory_init (struct rk3368_ddr_pctl *pctl, +struct rk3368_sdram_params *params) +{ +u32 mr[4 ]; +const ulong timeout_ms =500 ; +ulong tmp; + +/* +* Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and +* wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register +* of PCTL. +*/ +writel (POWER_UP_START , &pctl->powctl); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: POWER_UP_START did not complete in %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while (!(readl (&pctl->powstat) &POWER_UP_DONE )); + +/* Configure MR0 through MR3 */ + mr[0 ] =DDR3_MR0_WR (params->pctl_timing.twr) | +DDR3_MR0_CL (params->pctl_timing.tcl) | +DDR3_MR0_DLL_RESET ; + mr[1 ] =DDR3_MR1_RTT120OHM ; + mr[2 ] =DDR3_MR2_TWL (params->pctl_timing.tcwl); + mr[3 ] =0 ; + +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.2 Initialization (DDR3 Initialization Sequence)" +*/ +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,DESELECT_CMD ); +udelay (1 ); +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,PREA_CMD ); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,2 , mr[2 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,3 , mr[3 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,1 , mr[1 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,0 , mr[0 ]); +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,ZQCL_CMD ); + +return 0 ; +} + +static void move_to_config_state (struct rk3368_ddr_pctl *pctl) +{ +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.1 State transition of PCTL (Moving to Config State)" +*/ +u32 state =readl (&pctl->stat) &PCTL_STAT_MSK ; + +switch (state) { +case LOW_POWER : +writel (WAKEUP_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=ACCESS ) +/* spin */ ; + +/* fall-through */ +case ACCESS : +case INIT_MEM : +writel (CFG_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=CONFIG ) +/* spin */ ; +break ; + +case CONFIG : +return ; + +default : +break ; + } +} + +static void move_to_access_state (struct rk3368_ddr_pctl *pctl) +{ +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.1 State transition of PCTL (Moving to Access State)" +*/ +u32 state =readl (&pctl->stat) &PCTL_STAT_MSK ; + +switch (state) { +case LOW_POWER : +if (((readl (&pctl->stat) >>LP_TRIG_SHIFT ) & +LP_TRIG_MASK ) ==1 ) +return ; + +writel (WAKEUP_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=ACCESS ) +/* spin */ ; + +/* fall-through */ +case INIT_MEM : +writel (CFG_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=CONFIG ) +/* spin */ ; + +/* fall-through */ +case CONFIG : +writel (GO_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) ==CONFIG ) +/* spin */ ; +break ; + +case ACCESS : +return ; + +default : +break ; + } +} + +static void ddrctl_reset (struct rk3368_cru *cru) +{ +const u32 ctl_reset =BIT (3 ) |BIT (2 ); +const u32 phy_reset =BIT (1 ) |BIT (0 ); + +rk_setreg (&cru->softrst_con[10 ], ctl_reset | phy_reset); +udelay (1 ); +rk_clrreg (&cru->softrst_con[10 ], ctl_reset | phy_reset); +} + +static void ddrphy_reset (struct rk3368_ddrphy *ddrphy) +{ +clrbits_le32 (&ddrphy->reg[0 ],BIT (3 ) |BIT (2 )); +udelay (1 ); +setbits_le32 (&ddrphy->reg[0 ],BIT (3 ) |BIT (2 )); +} + +static void ddrphy_config_delays (struct rk3368_ddrphy *ddrphy,u32 freq) +{ +u32 dqs_dll_delay; + +setbits_le32 (&ddrphy->reg[0x13 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x14 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x26 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x27 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x36 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x37 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x46 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x47 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x56 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x57 ],BIT (3 )); + +if (freq <=400000000 ) +setbits_le32 (&ddrphy->reg[0xa4 ],0x1f ); +else +clrbits_le32 (&ddrphy->reg[0xa4 ],0x1f ); + +if (freq <681000000 ) + dqs_dll_delay =3 ;/* 67.5 degree delay */ +else + dqs_dll_delay =2 ;/* 45 degree delay */ + +writel (dqs_dll_delay, &ddrphy->reg[0x28 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x38 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x48 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x58 ]); +} + +static int dfi_cfg (struct rk3368_ddr_pctl *pctl) +{ +const ulong timeout_ms =200 ; +ulong tmp; + +writel (DFI_DATA_BYTE_DISABLE_EN , &pctl->dfistcfg0); + +writel (DFI_DRAM_CLK_SR_EN |DFI_DRAM_CLK_DPD_EN , + &pctl->dfistcfg1); +writel (DFI_PARITY_INTR_EN |DFI_PARITY_EN , &pctl->dfistcfg2); +writel (7 <<TLP_RESP_TIME_SHIFT |LP_SR_EN |LP_PD_EN , + &pctl->dfilpcfg0); + +writel (1 , &pctl->dfitphyupdtype0); + +writel (0x1f , &pctl->dfitphyrdlat); +writel (0 , &pctl->dfitphywrdata); +writel (0 , &pctl->dfiupdcfg);/* phyupd and ctrlupd disabled */ + +setbits_le32 (&pctl->dfistcfg0,DFI_INIT_START ); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: DFI init did not complete within %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while ((readl (&pctl->dfiststat0) &1 ) ==0 ); + +return 0 ; +} + +static inline u32 ps_to_tCK (const u32 ps,const ulong freq) +{ +const ulong MHz =1000000 ; +return DIV_ROUND_UP (ps * freq,1000000 * MHz); +} + +static inline u32 ns_to_tCK (const u32 ns,const ulong freq) +{ +return ps_to_tCK (ns *1000 , freq); +} + +static inline u32 tCK_to_ps (const ulong tCK,const ulong freq) +{ +const ulong MHz =1000000 ; +return DIV_ROUND_UP (tCK *1000000 * MHz, freq); +} + +static int pctl_calc_timings (struct rk3368_sdram_params *params, +ulong freq) +{ +struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing; +const ulong MHz =1000000 ; +u32 tccd; +u32 tfaw_as_ps; + +if (params->ddr_speed_bin !=DDR3_1600K ) { +error ("%s: unimplemented DDR3 speed bin %d\n" , + __func__, params->ddr_speed_bin); +return -1 ; + } + +/* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */ + pctl_timing->togcnt1u =DIV_ROUND_UP (freq,2 * MHz); + pctl_timing->togcnt100n =DIV_ROUND_UP (freq /10 ,2 * MHz); + + pctl_timing->tinit =200 ;/* 200 usec */ + pctl_timing->trsth =500 ;/* 500 usec */ + pctl_timing->trefi =78 ;/* 7.8usec = 78 * 100ns */ + params->trefi_mem_ddr3 =ns_to_tCK (pctl_timing->trefi *100 , freq); + +if (freq <= (400 * MHz)) { + pctl_timing->tcl =6 ; + pctl_timing->tcwl =10 ; + }else if (freq <= (533 * MHz)) { + pctl_timing->tcl =8 ; + pctl_timing->tcwl =6 ; + }else if (freq <= (666 * MHz)) { + pctl_timing->tcl =10 ; + pctl_timing->tcwl =7 ; + }else { + pctl_timing->tcl =11 ; + pctl_timing->tcwl =8 ; + } + + pctl_timing->tmrd =4 ;/* 4 tCK (all speed bins) */ + pctl_timing->trfc =ns_to_tCK (350 , freq);/* tRFC: 350 (max) @ 8GBit */ + pctl_timing->trp =max (4u ,ps_to_tCK (13750 , freq)); +/* +* JESD-79: +* READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL +*/ + tccd =4 ; + pctl_timing->trtw = pctl_timing->tcl + tccd/2 +2 - pctl_timing->tcwl; + pctl_timing->tal =0 ; + pctl_timing->tras =ps_to_tCK (35000 , freq); + pctl_timing->trc =ps_to_tCK (48750 , freq); + pctl_timing->trcd =ps_to_tCK (13750 , freq); + pctl_timing->trrd =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->trtp =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->twr =ps_to_tCK (15000 , freq); +/* The DDR3 mode-register does only support even values for tWR > 8. */ +if (pctl_timing->twr >8 ) + pctl_timing->twr = (pctl_timing->twr +1 ) & ~1 ; + pctl_timing->twtr =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->texsr =512 ;/* tEXSR(max) is tDLLLK */ + pctl_timing->txp =max (3u ,ps_to_tCK (6000 , freq)); + pctl_timing->txpdll =max (10u ,ps_to_tCK (24000 , freq)); + pctl_timing->tzqcs =max (64u ,ps_to_tCK (80000 , freq)); + pctl_timing->tzqcsi =10000 ;/* as used by Rockchip */ + pctl_timing->tdqs =1 ;/* fixed for DDR3 */ + pctl_timing->tcksre =max (5u ,ps_to_tCK (10000 , freq)); + pctl_timing->tcksrx =max (5u ,ps_to_tCK (10000 , freq)); + pctl_timing->tcke =max (3u ,ps_to_tCK (5000 , freq)); + pctl_timing->tmod =max (12u ,ps_to_tCK (15000 , freq)); + pctl_timing->trstl =ns_to_tCK (100 , freq); + pctl_timing->tzqcl =max (256u ,ps_to_tCK (320000 , freq));/* tZQoper */ + pctl_timing->tmrr =0 ; + pctl_timing->tckesr = pctl_timing->tcke +1 ;/* JESD-79: tCKE + 1tCK */ + pctl_timing->tdpd =0 ;/* RK3368 TRM: "allowed values for DDR3: 0" */ + + +/* +* The controller can represent tFAW as 4x, 5x or 6x tRRD only. +* We want to use the smallest multiplier that satisfies the tFAW +* requirements of the given speed-bin. If necessary, we stretch out +* tRRD to allow us to operate on a 6x multiplier for tFAW. +*/ + tfaw_as_ps =40000 ;/* 40ns: tFAW for DDR3-1600K, 2KB page-size */ +if (tCK_to_ps (pctl_timing->trrd *6 , freq) < tfaw_as_ps) { +/* If tFAW is > 6 x tRRD, we need to stretch tRRD */ + pctl_timing->trrd =ps_to_tCK (DIV_ROUND_UP (40000 ,6 ), freq); + params->tfaw_mult =TFAW_TRRD_MULT6 ; + }else if (tCK_to_ps (pctl_timing->trrd *5 , freq) < tfaw_as_ps) { + params->tfaw_mult =TFAW_TRRD_MULT6 ; + }else if (tCK_to_ps (pctl_timing->trrd *4 , freq) < tfaw_as_ps) { + params->tfaw_mult =TFAW_TRRD_MULT5 ; + }else { + params->tfaw_mult =TFAW_TRRD_MULT4 ; + } + +return 0 ; +} + +static void pctl_cfg (struct rk3368_ddr_pctl *pctl, +struct rk3368_sdram_params *params, +struct rk3368_grf *grf) +{ +/* Configure PCTL timing registers */ + params->pctl_timing.trefi |=BIT (31 );/* see PCTL_TREFI */ +copy_to_reg (&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u, +sizeof (params->pctl_timing)); +writel (params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3); + +/* Set up ODT write selector and ODT write length */ +writel ((RANK0_ODT_WRITE_SEL |RANK1_ODT_WRITE_SEL ), &pctl->dfiodtcfg); +writel (7 <<ODT_LEN_BL8_W_SHIFT , &pctl->dfiodtcfg1); + +/* Set up the CL/CWL-dependent timings of DFI */ +writel ((params->pctl_timing.tcl -1 ) /2 -1 , &pctl->dfitrddataen); +writel ((params->pctl_timing.tcwl -1 ) /2 -1 , &pctl->dfitphywrlat); + +/* DDR3 */ +writel (params->tfaw_mult |DDR3_EN |DDR2_DDR3_BL_8 , &pctl->mcfg); +writel (0x001c0004 , &grf->ddrc0_con0); + +setbits_le32 (&pctl->scfg,HW_LOW_POWER_EN ); +} + +static int ddrphy_data_training (struct rk3368_ddr_pctl *pctl, +struct rk3368_ddrphy *ddrphy) +{ +const u32 trefi =readl (&pctl->trefi); +const ulong timeout_ms =500 ; +ulong tmp; + +/* disable auto-refresh */ +writel (0 |BIT (31 ), &pctl->trefi); + +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x20 ); +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x21 ); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: did not complete within %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while ((readl (&ddrphy->reg[0xff ]) &0xf ) !=0xf ); + +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,PREA_CMD ); +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x20 ); +/* resume auto-refresh */ +writel (trefi |BIT (31 ), &pctl->trefi); + +return 0 ; +} + +static int sdram_col_row_detect (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_sdram_params *params =dev_get_platdata (dev); +struct rk3368_ddr_pctl *pctl = priv->pctl; +struct rk3368_msch *msch = priv->msch; +const u32 test_pattern =0x5aa5f00f ; +int row, col; +uintptr_t addr; + +move_to_config_state (pctl); +writel (6 , &msch->ddrconf); +move_to_access_state (pctl); + +/* Detect col */ +for (col =11 ; col >=9 ; col--) { +writel (0 ,CONFIG_SYS_SDRAM_BASE ); + addr =CONFIG_SYS_SDRAM_BASE + + (1 << (col + params->chan.bw -1 )); +writel (test_pattern, addr); +if ((readl (addr) == test_pattern) && + (readl (CONFIG_SYS_SDRAM_BASE ) ==0 )) +break ; + } + +if (col ==8 ) { +error ("%s: col detect error\n" , __func__); +return -EINVAL ; + } + +move_to_config_state (pctl); +writel (15 , &msch->ddrconf); +move_to_access_state (pctl); + +/* Detect row*/ +for (row =16 ; row >=12 ; row--) { +writel (0 ,CONFIG_SYS_SDRAM_BASE ); + addr =CONFIG_SYS_SDRAM_BASE + (1 << (row +15 -1 )); +writel (test_pattern, addr); +if ((readl (addr) == test_pattern) && + (readl (CONFIG_SYS_SDRAM_BASE ) ==0 )) +break ; + } + +if (row ==11 ) { +error ("%s: row detect error\n" , __func__); +return -EINVAL ; + } + +/* Record results */ +debug ("%s: col %d, row %d\n" , __func__, col, row); + params->chan.col = col; + params->chan.cs0_row = row; + params->chan.cs1_row = row; + params->chan.row_3_4 =0 ; + +return 0 ; +} + +static int msch_niu_config (struct rk3368_msch *msch, +struct rk3368_sdram_params *params) +{ +int i; +const u8 cols = params->chan.col - ((params->chan.bw ==2 ) ?0 :1 ); +const u8 rows = params->chan.cs0_row; + +/* +* The DDR address-translation table always assumes a 32bit +* bus and the comparison below takes care of adjusting for +* a 16bit bus (i.e. one column-address is consumed). +*/ +const struct { +u8 rows; +u8 columns; +u8 type; + } ddrconf_table[] = { +/* +* C-B-R-D patterns are first. For these we require an +* exact match for the columns and rows (as there's +* one entry per possible configuration). +*/ + [0 ] = { .rows =13 , .columns =10 , .type =DMC_MSCH_CBRD }, + [1 ] = { .rows =14 , .columns =10 , .type =DMC_MSCH_CBRD }, + [2 ] = { .rows =15 , .columns =10 , .type =DMC_MSCH_CBRD }, + [3 ] = { .rows =16 , .columns =10 , .type =DMC_MSCH_CBRD }, + [4 ] = { .rows =14 , .columns =11 , .type =DMC_MSCH_CBRD }, + [5 ] = { .rows =15 , .columns =11 , .type =DMC_MSCH_CBRD }, + [6 ] = { .rows =16 , .columns =11 , .type =DMC_MSCH_CBRD }, + [7 ] = { .rows =13 , .columns =9 , .type =DMC_MSCH_CBRD }, + [8 ] = { .rows =14 , .columns =9 , .type =DMC_MSCH_CBRD }, + [9 ] = { .rows =15 , .columns =9 , .type =DMC_MSCH_CBRD }, + [10 ] = { .rows =16 , .columns =9 , .type =DMC_MSCH_CBRD }, +/* +* 11 through 13 are C-R-B-D patterns. These are +* matched for an exact number of columns and to +* ensure that the hardware uses at least as many rows +* as the pattern requires (i.e. we make sure that +* there's no gaps up until we hit the device/chip-select; +* however, these patterns can accept up to 16 rows, +* as the row-address continues right after the CS +* switching) +*/ + [11 ] = { .rows =15 , .columns =10 , .type =DMC_MSCH_CRBD }, + [12 ] = { .rows =14 , .columns =11 , .type =DMC_MSCH_CRBD }, + [13 ] = { .rows =13 , .columns =10 , .type =DMC_MSCH_CRBD }, +/* +* 14 and 15 are catch-all variants using a C-B-D-R +* scheme (i.e. alternating the chip-select every time +* C-B overflows) and stuffing the remaining C-bits +* into the top. Matching needs to make sure that the +* number of columns is either an exact match (i.e. we +* can use less the the maximum number of rows) -or- +* that the columns exceed what is given in this table +* and the rows are an exact match (in which case the +* remaining C-bits will be stuffed onto the top after +* the device/chip-select switches). +*/ + [14 ] = { .rows =16 , .columns =10 , .type =DMC_MSCH_CBDR }, + [15 ] = { .rows =16 , .columns =9 , .type =DMC_MSCH_CBDR }, + }; + +/* +* For C-B-R-D, we need an exact match (i.e. both for the number of +* columns and rows), while for C-B-D-R, only the the number of +* columns needs to match. +*/ +for (i =0 ; i <ARRAY_SIZE (ddrconf_table); i++) { +bool match = false; + +/* If this entry if for a different matcher, then skip it */ +if (ddrconf_table[i].type != params->memory_schedule) +continue ; + +/* +* Match according to the rules (exact/inexact/at-least) +* documented in the ddrconf_table above. +*/ +switch (params->memory_schedule) { +case DMC_MSCH_CBRD : + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows == rows); +break ; + +case DMC_MSCH_CRBD : + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows <= rows); +break ; + +case DMC_MSCH_CBDR : + match = (ddrconf_table[i].columns == cols) || + ((ddrconf_table[i].columns <= cols) && + (ddrconf_table[i].rows == rows)); +break ; + +default : +break ; + } + +if (match) { +debug ("%s: setting ddrconf 0x%x\n" , __func__, i); +writel (i, &msch->ddrconf); +return 0 ; + } + } + +error ("%s: ddrconf (NIU config) not found\n" , __func__); +return -EINVAL ; +} + +static void dram_all_config (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_pmu_grf *pmugrf = priv->pmugrf; +struct rk3368_sdram_params *params =dev_get_platdata (dev); +const struct rk3288_sdram_channel *info = ¶ms->chan; +u32 sys_reg =0 ; +const int chan =0 ; + + sys_reg |=DDR3 <<SYS_REG_DDRTYPE_SHIFT ; + sys_reg |=0 <<SYS_REG_NUM_CH_SHIFT ; + + sys_reg |= info->row_3_4 <<SYS_REG_ROW_3_4_SHIFT (chan); + sys_reg |=1 <<SYS_REG_CHINFO_SHIFT (chan); + sys_reg |= (info->rank -1 ) <<SYS_REG_RANK_SHIFT (chan); + sys_reg |= (info->col -9 ) <<SYS_REG_COL_SHIFT (chan); + sys_reg |= info->bk ==3 ?0 :1 <<SYS_REG_BK_SHIFT (chan); + sys_reg |= (info->cs0_row -13 ) <<SYS_REG_CS0_ROW_SHIFT (chan); + sys_reg |= (info->cs1_row -13 ) <<SYS_REG_CS1_ROW_SHIFT (chan); + sys_reg |= (2 >> info->bw) <<SYS_REG_BW_SHIFT (chan); + sys_reg |= (2 >> info->dbw) <<SYS_REG_DBW_SHIFT (chan); + +writel (sys_reg, &pmugrf->os_reg[2 ]); +} + +static int setup_sdram (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_sdram_params *params =dev_get_platdata (dev); + +struct rk3368_ddr_pctl *pctl = priv->pctl; +struct rk3368_ddrphy *ddrphy = priv->phy; +struct rk3368_cru *cru = priv->cru; +struct rk3368_grf *grf = priv->grf; +struct rk3368_msch *msch = priv->msch; + +int ret; + +/* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */ + ret =clk_set_rate (&priv->ddr_clk,2 * params->ddr_freq); +if (ret <0 ) { +debug ("%s: could not set DDR clock: %d\n" , __func__, ret); +return ret; + } + +/* Update the read-latency for the RK3368 */ +writel (0x32 , &msch->readlatency); + +/* Initialise the DDR PCTL and DDR PHY */ +ddrctl_reset (cru); +ddrphy_reset (ddrphy); +ddrphy_config_delays (ddrphy, params->ddr_freq); +dfi_cfg (pctl); +/* Configure relative system information of grf_ddrc0_con0 register */ +ddr_set_ddr3_mode (grf, true); +ddr_set_noc_spr_err_stall (grf, true); +/* Calculate timings */ +pctl_calc_timings (params, params->ddr_freq); +/* Initialise the device timings in protocol controller */ +pctl_cfg (pctl, params, grf); +/* Configure AL, CL ... information of PHY registers */ +ddrphy_config (ddrphy, + params->pctl_timing.tcl, + params->pctl_timing.tal, + params->pctl_timing.tcwl); + +/* Initialize DRAM and configure with mode-register values */ + ret =memory_init (pctl, params); +if (ret) + goto error; + +move_to_config_state (pctl); +/* Perform data-training */ +ddrphy_data_training (pctl, ddrphy); +move_to_access_state (pctl); + +/* TODO(prt): could detect rank in training... */ + params->chan.rank =2 ; +/* TODO(prt): bus width is not auto-detected (yet)... */ + params->chan.bw =2 ;/* 32bit wide bus */ + params->chan.dbw = params->chan.dbw;/* 32bit wide bus */ + +/* DDR3 is always 8 bank */ + params->chan.bk =3 ; +/* Detect col and row number */ + ret =sdram_col_row_detect (dev); +if (ret) + goto error; + +/* Configure NIU DDR configuration */ + ret =msch_niu_config (msch, params); +if (ret) + goto error; + +/* set up OS_REG to communicate w/ next stage and OS */ +dram_all_config (dev); + +return 0 ; + +error: +printf ("DRAM init failed!\n" ); +hang (); +} +#endif + +static int rk3368_dmc_ofdata_to_platdata (struct udevice *dev) +{ +int ret =0 ; + +#if !CONFIG_IS_ENABLED (OF_PLATDATA ) +struct rk3368_sdram_params *plat =dev_get_platdata (dev); + + ret =regmap_init_mem (dev, &plat->map); +if (ret) +return ret; +#endif + +return ret; +} + +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +static int conv_of_platdata (struct udevice *dev) +{ +struct rk3368_sdram_params *plat =dev_get_platdata (dev); +struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat; +int ret; + + plat->ddr_freq = of_plat->rockchip_ddr_frequency; + plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin; + plat->memory_schedule = of_plat->rockchip_memory_schedule; + + ret =regmap_init_mem_platdata (dev, of_plat->reg, +ARRAY_SIZE (of_plat->reg) /2 , + &plat->map); +if (ret) +return ret; + +return 0 ; +} +#endif + +static int rk3368_dmc_probe (struct udevice *dev) +{ +#ifdef CONFIG_TPL_BUILD +struct rk3368_sdram_params *plat =dev_get_platdata (dev); +struct rk3368_ddr_pctl *pctl; +struct rk3368_ddrphy *ddrphy; +struct rk3368_cru *cru; +struct rk3368_grf *grf; +struct rk3368_msch *msch; +int ret; +struct udevice *dev_clk; +#endif +struct dram_info *priv =dev_get_priv (dev); + +#if CONFIG_IS_ENABLED (OF_PLATDATA ) + ret =conv_of_platdata (dev); +if (ret) +return ret; +#endif + + priv->pmugrf =syscon_get_first_range (ROCKCHIP_SYSCON_PMUGRF ); +debug ("%s: pmugrf=%p\n" , __func__, priv->pmugrf); + +#ifdef CONFIG_TPL_BUILD + pctl =regmap_get_range (plat->map,0 ); + ddrphy =regmap_get_range (plat->map,1 ); + msch =syscon_get_first_range (ROCKCHIP_SYSCON_MSCH ); + grf =syscon_get_first_range (ROCKCHIP_SYSCON_GRF ); + + priv->pctl = pctl; + priv->phy = ddrphy; + priv->msch = msch; + priv->grf = grf; + + ret =rockchip_get_clk (&dev_clk); +if (ret) +return ret; + priv->ddr_clk.id =CLK_DDR ; + ret =clk_request (dev_clk, &priv->ddr_clk); +if (ret) +return ret; + + cru =rockchip_get_cru (); + priv->cru = cru; +if (IS_ERR (priv->cru)) +return PTR_ERR (priv->cru); + + ret =setup_sdram (dev); +if (ret) +return ret; +#endif + + priv->info.base =0 ; + priv->info.size = +rockchip_sdram_size ((phys_addr_t)&priv->pmugrf->os_reg[2 ]); + +/* +* we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff +* is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is +* inaccessible for some IP controller. +*/ + priv->info.size =min (priv->info.size, (size_t )0xfe000000 ); + +return 0 ; +} + +static int rk3368_dmc_get_info (struct udevice *dev,struct ram_info *info) +{ +struct dram_info *priv =dev_get_priv (dev); + + *info = priv->info; +return 0 ; +} + +static struct ram_ops rk3368_dmc_ops = { + .get_info = rk3368_dmc_get_info, +}; + + +static const struct udevice_id rk3368_dmc_ids[] = { + { .compatible ="rockchip,rk3368-dmc" }, + { } +}; + +U_BOOT_DRIVER (dmc_rk3368) = { + .name ="rockchip_rk3368_dmc" , + .id =UCLASS_RAM , + .of_match = rk3368_dmc_ids, + .ops = &rk3368_dmc_ops, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size =sizeof (struct dram_info ), + .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size =sizeof (struct dram_info ), + .platdata_auto_alloc_size =sizeof (struct rk3368_sdram_params ), +};include/dt-bindings/memory/rk3368-dmc.h new file +20
-0@@ -0,0 +1,30 @@ +#ifndef DT_BINDINGS_RK3368_DMC_H +#define DT_BINDINGS_RK3368_DMC_H + +#define DMC_MSCH_CBDR 0x0 +#define DMC_MSCH_CBRD 0x1 +#define DMC_MSCH_CRBD 0x2 + +#define DDR3_800D 0 +#define DDR3_800E 1 +#define DDR3_1066E 2 +#define DDR3_1066F 3 +#define DDR3_1066G 4 +#define DDR3_1333F 5 +#define DDR3_1333G 6 +#define DDR3_1333H 7 +#define DDR3_1333J 8 +#define DDR3_1600G 9 +#define DDR3_1600H 10 +#define DDR3_1600J 11 +#define DDR3_1600K 12include/dt-bindings/memory/rk3368-dmc.h line 30
Quoted 10 lines
include/dt-bindings/memory/rk3368-dmc.h new file +10
-0+#define DDR3_1866J 13 +#define DDR3_1866K 14 +#define DDR3_1866L 15 +#define DDR3_1866M 16 +#define DDR3_2133K 17 +#define DDR3_2133L 18 +#define DDR3_2133M 19 +#define DDR3_2133N 20 + +#endif dpd;
arch/arm/include/asm/arch-rockchip/ddr_rk3368.h new file +108
-0+u32 trefi_mem_ddr3; +u32 reserved5[45 ]; +u32 dtuwactl; +u32 dturactl; +u32 dtucfg; +u32 dtuectl; +u32 dtuwd0; +u32 dtuwd1; +u32 dtuwd2; +u32 dtuwd3; +u32 dtuwdm; +u32 dturd0; +u32 dturd1; +u32 dturd2; +u32 dturd3; +u32 dtulfsrwd; +u32 dtulfsrrd; +u32 dtueaf; +u32 dfitctrldelay; +u32 dfiodtcfg; +u32 dfiodtcfg1; +u32 dfiodtrankmap; +u32 dfitphywrdata; +u32 dfitphywrlat; +u32 reserved7[2 ]; +u32 dfitrddataen; +u32 dfitphyrdlat; +u32 reserved8[2 ]; +u32 dfitphyupdtype0; +u32 dfitphyupdtype1; +u32 dfitphyupdtype2; +u32 dfitphyupdtype3; +u32 dfitctrlupdmin; +u32 dfitctrlupdmax; +u32 dfitctrlupddly; +u32 reserved9; +u32 dfiupdcfg; +u32 dfitrefmski; +u32 dfitctrlupdi; +u32 reserved10[4 ]; +u32 dfitrcfg0; +u32 dfitrstat0; +u32 dfitrwrlvlen; +u32 dfitrrdlvlen; +u32 dfitrrdlvlgateen; +u32 dfiststat0; +u32 dfistcfg0; +u32 dfistcfg1; +u32 reserved11; +u32 dfitdramclken; +u32 dfitdramclkdis; +u32 dfistcfg2; +u32 dfistparclr; +u32 dfistparlog; +u32 reserved12[3 ]; +u32 dfilpcfg0; +u32 reserved13[3 ]; +u32 dfitrwrlvlresp0; +u32 dfitrwrlvlresp1; +u32 dfitrwrlvlresp2; +u32 dfitrrdlvlresp0; +u32 dfitrrdlvlresp1; +u32 dfitrrdlvlresp2; +u32 dfitrwrlvldelay0; +u32 dfitrwrlvldelay1; +u32 dfitrwrlvldelay2; +u32 dfitrrdlvldelay0; +u32 dfitrrdlvldelay1; +u32 dfitrrdlvldelay2; +u32 dfitrrdlvlgatedelay0; +u32 dfitrrdlvlgatedelay1; +u32 dfitrrdlvlgatedelay2; +u32 dfitrcmd; +u32 reserved14[46 ]; +u32 ipvr; + u32 iptr; +}; +check_member (rk3368_ddr_pctl, iptr,0x03fc ); + +struct rk3368_ddrphy { +u32 reg[0x100 ]; +}; +check_member (rk3368_ddrphy, reg[0xff ],0x03fc ); + +struct rk3368_msch { +u32 coreid; +u32 revisionid; +u32 ddrconf; +u32 ddrtiming; +u32 ddrmode; +u32 readlatency; +u32 reserved1[8 ]; +u32 activate; +u32 devtodev; +}; +check_member (rk3368_msch, devtodev,0x003c ); + +/* GRF_SOC_CON0 */ +enum { +NOC_RSP_ERR_STALL =BIT (9 ), +MOBILE_DDR_SEL =BIT (4 ), +DDR0_16BIT_EN =BIT (3 ), +MSCH0_MAINDDR3_DDR3 =BIT (2 ), +MSCH0_MAINPARTIALPOP =BIT (1 ), +UPCTL_C_ACTIVE =BIT (0 ), +}; + +#endif arch/arm/include/asm/arch-rockchip/grf_rk3368.h +3
-0@@ -76,8 +76,11 @@ struct rk3368_grf {u32 soc_con15;u32 soc_con16;u32 soc_con17; +u32 reserved5[0x6e ]; +u32 ddrc0_con0; };check_member (rk3368_grf, soc_con17,0x444 ); +check_member (rk3368_grf, ddrc0_con0,0x600 );struct rk3368_pmu_grf {u32 gpio0a_iomux;arch/arm/mach-rockchip/rk3368/Makefile +0
-0
arch/arm/mach-rockchip/rk3368/Makefile line 8
Quoted 5 lines
arch/arm/mach-rockchip/rk3368/Makefile +0
-1@@ -5,5 +5,4 @@ # obj-y += clk_rk3368.o obj-y += rk3368.o -obj-y += sdram_rk3368.o obj-y += syscon_rk3368.o
The current PX5 EVB and Sheep board(they have no spl now) depend on
this sdram_rk3368.c
to get the sdram capacity, and so is the geekbox board.
These boards will be broken when this driver removed.
We got the failed log like this on PX5 EVB:
DRAM: DRAM init failed: -19
initcall sequence 000000002d=378208 failed at call 02023f0 (err=-19) ### ERROR ### Please RESET the board ###
Quoted 1,194 lines
arch/arm/mach-rockchip/rk3368/sdram_rk3368.c deleted +0
-60@@ -1,60 +0,0 @@ -/* -* (C) Copyright 2016 Rockchip Electronics Co., Ltd. -* -* SPDX-License-Identifier: GPL-2.0 -*/ - -#include <common.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/sdram_common.h> - -DECLARE_GLOBAL_DATA_PTR ; -struct dram_info { -struct ram_info info; -struct rk3368_pmu_grf *pmugrf; -}; - -static int rk3368_dmc_probe (struct udevice *dev) -{ -struct dram_info *priv =dev_get_priv (dev); - - priv->pmugrf =syscon_get_first_range (ROCKCHIP_SYSCON_PMUGRF ); -debug ("%s: grf=%p\n" , __func__, priv->pmugrf); - priv->info.base =CONFIG_SYS_SDRAM_BASE ; - priv->info.size =rockchip_sdram_size ( - (phys_addr_t)&priv->pmugrf->os_reg[2 ]); - -return 0 ; -} - -static int rk3368_dmc_get_info (struct udevice *dev,struct ram_info *info) -{ -struct dram_info *priv =dev_get_priv (dev); - - *info = priv->info; - -return 0 ; -} - -static struct ram_ops rk3368_dmc_ops = { - .get_info = rk3368_dmc_get_info, -}; - - -static const struct udevice_id rk3368_dmc_ids[] = { - { .compatible ="rockchip,rk3368-dmc" }, - { } -}; - -U_BOOT_DRIVER (dmc_rk3368) = { - .name ="rockchip_rk3368_dmc" , - .id =UCLASS_RAM , - .of_match = rk3368_dmc_ids, - .ops = &rk3368_dmc_ops, - .probe = rk3368_dmc_probe, - .priv_auto_alloc_size =sizeof (struct dram_info ), -};doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt new file +67
-0@@ -0,0 +1,67 @@ +RK3368 dynamic memory controller driver +======================================= + +The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation +during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on +the following key configuration data: + (a) a target-frequency (i.e. operating point) for the memory operation + (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware + (c) a memory-schedule (i.e. mapping from physical addresses to the address + pins of the memory bus) + +Required properties +------------------- + +- compatible: "rockchip,rk3368-dmc" +- reg + protocol controller (PCTL) address and PHY controller (DDRPHY) address +- rockchip,ddr-speed-bin + the DDR3 device's speed-bin (as specified according to JESD-79) + DDR3_800D (5-5-5) + DDR3_800E (6-6-6) + DDR3_1066E (6-6-6) + DDR3_1066F (7-7-7) + DDR3_1066G (8-8-8) + DDR3_1333F (7-7-7) + DDR3_1333G (8-8-8) + DDR3_1333H (9-9-9) + DDR3_1333J (10-10-10) + DDR3_1600G (8-8-8) + DDR3_1600H (9-9-9) + DDR3_1600J (10-10-10) + DDR3_1600K (11-11-11) + DDR3_1866J (10-10-10) + DDR3_1866K (11-11-11) + DDR3_1866L (12-12-12) + DDR3_1866M (13-13-13) + DDR3_2133K (11-11-11) + DDR3_2133L (12-12-12) + DDR3_2133M (13-13-13) + DDR3_2133N (14-14-14) +- rockchip,ddr-frequency: + target DDR clock frequency in Hz (not all frequencies may be supported, + as there's some cooperation from the clock-driver required) +- rockchip,memory-schedule: + controls the decoding of physical addresses to DRAM addressing (i.e. how + the physical address maps onto the address pins/chip-select of the device) + DMC_MSCH_CBDR: column -> bank -> device -> row + DMC_MSCH_CBRD: column -> band -> row -> device + DMC_MSCH_CRBD: column -> row -> band -> device + +Example (for DDR3-1600K and 800MHz) +----------------------------------- + + #include <dt-bindings/memory/rk3368-dmc.h> + + dmc: dmc at ff610000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3368-dmc"; + reg = <0 0xff610000 0 0x400 + 0 0xff620000 0 0x400>; + }; + + &dmc { + rockchip,ddr-speed-bin = <DDR3_1600K>; + rockchip,ddr-frequency = <800000000>; + rockchip,memory-schedule = <DMC_MSCH_CBRD>; + };drivers/ram/Makefile +2
-0@@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o + +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/drivers/ram/rockchip/Makefile new file +7
-0@@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.odrivers/ram/rockchip/dmc-rk3368.c new file +990
-0@@ -0,0 +1,990 @@ +/* +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dt-bindings/memory/rk3368-dmc.h> +#include <dt-structs.h> +#include <ram.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3368.h> +#include <asm/arch/grf_rk3368.h> +#include <asm/arch/ddr_rk3368.h> +#include <asm/arch/sdram.h> +#include <asm/arch/sdram_common.h> + +DECLARE_GLOBAL_DATA_PTR ; + +struct dram_info { +struct ram_info info; +struct clk ddr_clk; +struct rk3368_cru *cru; +struct rk3368_grf *grf; +struct rk3368_ddr_pctl *pctl; +struct rk3368_ddrphy *phy; +struct rk3368_pmu_grf *pmugrf; +struct rk3368_msch *msch; +}; + +struct rk3368_sdram_params { +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +struct dtd_rockchip_rk3368_dmc of_plat; +#endif +struct rk3288_sdram_pctl_timing pctl_timing; +u32 trefi_mem_ddr3; +struct rk3288_sdram_channel chan; +struct regmap *map; +u32 ddr_freq; +u32 memory_schedule; +u32 ddr_speed_bin; +u32 tfaw_mult; +}; + +/* PTCL bits */ +enum { +/* PCTL_DFISTCFG0 */ +DFI_INIT_START =BIT (0 ), +DFI_DATA_BYTE_DISABLE_EN =BIT (2 ), + +/* PCTL_DFISTCFG1 */ +DFI_DRAM_CLK_SR_EN =BIT (0 ), +DFI_DRAM_CLK_DPD_EN =BIT (1 ), +ODT_LEN_BL8_W_SHIFT =16 , + +/* PCTL_DFISTCFG2 */ +DFI_PARITY_INTR_EN =BIT (0 ), +DFI_PARITY_EN =BIT (1 ), + +/* PCTL_DFILPCFG0 */ +TLP_RESP_TIME_SHIFT =16 , +LP_SR_EN =BIT (8 ), +LP_PD_EN =BIT (0 ), + +/* PCTL_DFIODTCFG */ +RANK0_ODT_WRITE_SEL =BIT (3 ), +RANK1_ODT_WRITE_SEL =BIT (11 ), + +/* PCTL_SCFG */ +HW_LOW_POWER_EN =BIT (0 ), + +/* PCTL_MCMD */ +START_CMD =BIT (31 ), +MCMD_RANK0 =BIT (20 ), +MCMD_RANK1 =BIT (21 ), +DESELECT_CMD =0 , +PREA_CMD , +REF_CMD , +MRS_CMD , +ZQCS_CMD , +ZQCL_CMD , +RSTL_CMD , +MRR_CMD =8 , +DPDE_CMD , + +/* PCTL_POWCTL */ +POWER_UP_START =BIT (0 ), + +/* PCTL_POWSTAT */ +POWER_UP_DONE =BIT (0 ), + +/* PCTL_SCTL */ +INIT_STATE =0 , +CFG_STATE , +GO_STATE , +SLEEP_STATE , +WAKEUP_STATE , + +/* PCTL_STAT */ +LP_TRIG_SHIFT =4 , +LP_TRIG_MASK =7 , +PCTL_STAT_MSK =7 , +INIT_MEM =0 , +CONFIG , +CONFIG_REQ , +ACCESS , +ACCESS_REQ , +LOW_POWER , +LOW_POWER_ENTRY_REQ , +LOW_POWER_EXIT_REQ , + +/* PCTL_MCFG */ +DDR2_DDR3_BL_8 =BIT (0 ), +DDR3_EN =BIT (5 ), +TFAW_TRRD_MULT4 = (0 <<18 ), +TFAW_TRRD_MULT5 = (1 <<18 ), +TFAW_TRRD_MULT6 = (2 <<18 ), +}; + +#define DDR3_MR0_WR (n) \ + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9)) +#define DDR3_MR0_CL (n) \ + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2)) +#define DDR3_MR0_BL8 \ + (0 << 0) +#define DDR3_MR0_DLL_RESET \ + (1 << 8) +#define DDR3_MR1_RTT120OHM \ + ((0 << 9) | (1 << 6) | (0 << 2)) +#define DDR3_MR2_TWL (n) \ + (((n - 5) & 0x7) << 3) + + +#ifdef CONFIG_TPL_BUILD + +static void ddr_set_noc_spr_err_stall (struct rk3368_grf *grf,bool enable) +{ +if (enable) +rk_setreg (&grf->ddrc0_con0,NOC_RSP_ERR_STALL ); +else +rk_clrreg (&grf->ddrc0_con0,NOC_RSP_ERR_STALL ); +} + +static void ddr_set_ddr3_mode (struct rk3368_grf *grf,bool ddr3_mode) +{ +if (ddr3_mode) +rk_setreg (&grf->ddrc0_con0,MSCH0_MAINDDR3_DDR3 ); +else +rk_clrreg (&grf->ddrc0_con0,MSCH0_MAINDDR3_DDR3 ); +} + +static void ddrphy_config (struct rk3368_ddrphy *phy, +u32 tcl,u32 tal,u32 tcwl) +{ +int i; + +/* Set to DDR3 mode */ +clrsetbits_le32 (&phy->reg[1 ],0x3 ,0x0 ); + +/* DDRPHY_REGB: CL, AL */ +clrsetbits_le32 (&phy->reg[0xb ],0xff , tcl <<4 | tal); +/* DDRPHY_REGC: CWL */ +clrsetbits_le32 (&phy->reg[0xc ],0x0f , tcwl); + +/* Update drive-strength */ +writel (0xcc , &phy->reg[0x11 ]); +writel (0xaa , &phy->reg[0x16 ]); +/* +* Update NRCOMP/PRCOMP for all 4 channels (for details of all +* affected registers refer to the documentation of DDRPHY_REG20 +* and DDRPHY_REG21 in the RK3368 TRM. +*/ +for (i =0 ; i <4 ; ++i) { +writel (0xcc , &phy->reg[0x20 + i *0x10 ]); +writel (0x44 , &phy->reg[0x21 + i *0x10 ]); + } + +/* Enable write-leveling calibration bypass */ +setbits_le32 (&phy->reg[2 ],BIT (3 )); +} + +static void copy_to_reg (u32 *dest,const u32 *src,u32 n) +{ +int i; + +for (i =0 ; i < n /sizeof (u32); i++) +writel (*src++, dest++); +} + +static void send_command (struct rk3368_ddr_pctl *pctl,u32 rank,u32 cmd) +{ +u32 mcmd =START_CMD | cmd | rank; + +debug ("%s: writing %x to MCMD\n" , __func__, mcmd); +writel (mcmd, &pctl->mcmd); +while (readl (&pctl->mcmd) &START_CMD ) +/* spin */ ; +} + +static void send_mrs (struct rk3368_ddr_pctl *pctl, +u32 rank,u32 mr_num,u32 mr_data) +{ +u32 mcmd =START_CMD |MRS_CMD | rank | (mr_num <<17 ) | (mr_data <<4 ); + +debug ("%s: writing %x to MCMD\n" , __func__, mcmd); +writel (mcmd, &pctl->mcmd); +while (readl (&pctl->mcmd) &START_CMD ) +/* spin */ ; +} + +static int memory_init (struct rk3368_ddr_pctl *pctl, +struct rk3368_sdram_params *params) +{ +u32 mr[4 ]; +const ulong timeout_ms =500 ; +ulong tmp; + +/* +* Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and +* wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register +* of PCTL. +*/ +writel (POWER_UP_START , &pctl->powctl); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: POWER_UP_START did not complete in %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while (!(readl (&pctl->powstat) &POWER_UP_DONE )); + +/* Configure MR0 through MR3 */ + mr[0 ] =DDR3_MR0_WR (params->pctl_timing.twr) | +DDR3_MR0_CL (params->pctl_timing.tcl) | +DDR3_MR0_DLL_RESET ; + mr[1 ] =DDR3_MR1_RTT120OHM ; + mr[2 ] =DDR3_MR2_TWL (params->pctl_timing.tcwl); + mr[3 ] =0 ; + +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.2 Initialization (DDR3 Initialization Sequence)" +*/ +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,DESELECT_CMD ); +udelay (1 ); +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,PREA_CMD ); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,2 , mr[2 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,3 , mr[3 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,1 , mr[1 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,0 , mr[0 ]); +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,ZQCL_CMD ); + +return 0 ; +} + +static void move_to_config_state (struct rk3368_ddr_pctl *pctl) +{ +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.1 State transition of PCTL (Moving to Config State)" +*/ +u32 state =readl (&pctl->stat) &PCTL_STAT_MSK ; + +switch (state) { +case LOW_POWER : +writel (WAKEUP_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=ACCESS ) +/* spin */ ; + +/* fall-through */ +case ACCESS : +case INIT_MEM : +writel (CFG_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=CONFIG ) +/* spin */ ; +break ; + +case CONFIG : +return ; + +default : +break ; + } +} + +static void move_to_access_state (struct rk3368_ddr_pctl *pctl) +{ +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.1 State transition of PCTL (Moving to Access State)" +*/ +u32 state =readl (&pctl->stat) &PCTL_STAT_MSK ; + +switch (state) { +case LOW_POWER : +if (((readl (&pctl->stat) >>LP_TRIG_SHIFT ) & +LP_TRIG_MASK ) ==1 ) +return ; + +writel (WAKEUP_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=ACCESS ) +/* spin */ ; + +/* fall-through */ +case INIT_MEM : +writel (CFG_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=CONFIG ) +/* spin */ ; + +/* fall-through */ +case CONFIG : +writel (GO_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) ==CONFIG ) +/* spin */ ; +break ; + +case ACCESS : +return ; + +default : +break ; + } +} + +static void ddrctl_reset (struct rk3368_cru *cru) +{ +const u32 ctl_reset =BIT (3 ) |BIT (2 ); +const u32 phy_reset =BIT (1 ) |BIT (0 ); + +rk_setreg (&cru->softrst_con[10 ], ctl_reset | phy_reset); +udelay (1 ); +rk_clrreg (&cru->softrst_con[10 ], ctl_reset | phy_reset); +} + +static void ddrphy_reset (struct rk3368_ddrphy *ddrphy) +{ +clrbits_le32 (&ddrphy->reg[0 ],BIT (3 ) |BIT (2 )); +udelay (1 ); +setbits_le32 (&ddrphy->reg[0 ],BIT (3 ) |BIT (2 )); +} + +static void ddrphy_config_delays (struct rk3368_ddrphy *ddrphy,u32 freq) +{ +u32 dqs_dll_delay; + +setbits_le32 (&ddrphy->reg[0x13 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x14 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x26 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x27 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x36 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x37 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x46 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x47 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x56 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x57 ],BIT (3 )); + +if (freq <=400000000 ) +setbits_le32 (&ddrphy->reg[0xa4 ],0x1f ); +else +clrbits_le32 (&ddrphy->reg[0xa4 ],0x1f ); + +if (freq <681000000 ) + dqs_dll_delay =3 ;/* 67.5 degree delay */ +else + dqs_dll_delay =2 ;/* 45 degree delay */ + +writel (dqs_dll_delay, &ddrphy->reg[0x28 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x38 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x48 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x58 ]); +} + +static int dfi_cfg (struct rk3368_ddr_pctl *pctl) +{ +const ulong timeout_ms =200 ; +ulong tmp; + +writel (DFI_DATA_BYTE_DISABLE_EN , &pctl->dfistcfg0); + +writel (DFI_DRAM_CLK_SR_EN |DFI_DRAM_CLK_DPD_EN , + &pctl->dfistcfg1); +writel (DFI_PARITY_INTR_EN |DFI_PARITY_EN , &pctl->dfistcfg2); +writel (7 <<TLP_RESP_TIME_SHIFT |LP_SR_EN |LP_PD_EN , + &pctl->dfilpcfg0); + +writel (1 , &pctl->dfitphyupdtype0); + +writel (0x1f , &pctl->dfitphyrdlat); +writel (0 , &pctl->dfitphywrdata); +writel (0 , &pctl->dfiupdcfg);/* phyupd and ctrlupd disabled */ + +setbits_le32 (&pctl->dfistcfg0,DFI_INIT_START ); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: DFI init did not complete within %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while ((readl (&pctl->dfiststat0) &1 ) ==0 ); + +return 0 ; +} + +static inline u32 ps_to_tCK (const u32 ps,const ulong freq) +{ +const ulong MHz =1000000 ; +return DIV_ROUND_UP (ps * freq,1000000 * MHz); +} + +static inline u32 ns_to_tCK (const u32 ns,const ulong freq) +{ +return ps_to_tCK (ns *1000 , freq); +} + +static inline u32 tCK_to_ps (const ulong tCK,const ulong freq) +{ +const ulong MHz =1000000 ; +return DIV_ROUND_UP (tCK *1000000 * MHz, freq); +} + +static int pctl_calc_timings (struct rk3368_sdram_params *params, +ulong freq) +{ +struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing; +const ulong MHz =1000000 ; +u32 tccd; +u32 tfaw_as_ps; + +if (params->ddr_speed_bin !=DDR3_1600K ) { +error ("%s: unimplemented DDR3 speed bin %d\n" , + __func__, params->ddr_speed_bin); +return -1 ; + } + +/* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */ + pctl_timing->togcnt1u =DIV_ROUND_UP (freq,2 * MHz); + pctl_timing->togcnt100n =DIV_ROUND_UP (freq /10 ,2 * MHz); + + pctl_timing->tinit =200 ;/* 200 usec */ + pctl_timing->trsth =500 ;/* 500 usec */ + pctl_timing->trefi =78 ;/* 7.8usec = 78 * 100ns */ + params->trefi_mem_ddr3 =ns_to_tCK (pctl_timing->trefi *100 , freq); + +if (freq <= (400 * MHz)) { + pctl_timing->tcl =6 ; + pctl_timing->tcwl =10 ; + }else if (freq <= (533 * MHz)) { + pctl_timing->tcl =8 ; + pctl_timing->tcwl =6 ; + }else if (freq <= (666 * MHz)) { + pctl_timing->tcl =10 ; + pctl_timing->tcwl =7 ; + }else { + pctl_timing->tcl =11 ; + pctl_timing->tcwl =8 ; + } + + pctl_timing->tmrd =4 ;/* 4 tCK (all speed bins) */ + pctl_timing->trfc =ns_to_tCK (350 , freq);/* tRFC: 350 (max) @ 8GBit */ + pctl_timing->trp =max (4u ,ps_to_tCK (13750 , freq)); +/* +* JESD-79: +* READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL +*/ + tccd =4 ; + pctl_timing->trtw = pctl_timing->tcl + tccd/2 +2 - pctl_timing->tcwl; + pctl_timing->tal =0 ; + pctl_timing->tras =ps_to_tCK (35000 , freq); + pctl_timing->trc =ps_to_tCK (48750 , freq); + pctl_timing->trcd =ps_to_tCK (13750 , freq); + pctl_timing->trrd =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->trtp =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->twr =ps_to_tCK (15000 , freq); +/* The DDR3 mode-register does only support even values for tWR > 8. */ +if (pctl_timing->twr >8 ) + pctl_timing->twr = (pctl_timing->twr +1 ) & ~1 ; + pctl_timing->twtr =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->texsr =512 ;/* tEXSR(max) is tDLLLK */ + pctl_timing->txp =max (3u ,ps_to_tCK (6000 , freq)); + pctl_timing->txpdll =max (10u ,ps_to_tCK (24000 , freq)); + pctl_timing->tzqcs =max (64u ,ps_to_tCK (80000 , freq)); + pctl_timing->tzqcsi =10000 ;/* as used by Rockchip */ + pctl_timing->tdqs =1 ;/* fixed for DDR3 */ + pctl_timing->tcksre =max (5u ,ps_to_tCK (10000 , freq)); + pctl_timing->tcksrx =max (5u ,ps_to_tCK (10000 , freq)); + pctl_timing->tcke =max (3u ,ps_to_tCK (5000 , freq)); + pctl_timing->tmod =max (12u ,ps_to_tCK (15000 , freq)); + pctl_timing->trstl =ns_to_tCK (100 , freq); + pctl_timing->tzqcl =max (256u ,ps_to_tCK (320000 , freq));/* tZQoper */ + pctl_timing->tmrr =0 ; + pctl_timing->tckesr = pctl_timing->tcke +1 ;/* JESD-79: tCKE + 1tCK */ + pctl_timing->tdpd =0 ;/* RK3368 TRM: "allowed values for DDR3: 0" */ + + +/* +* The controller can represent tFAW as 4x, 5x or 6x tRRD only. +* We want to use the smallest multiplier that satisfies the tFAW +* requirements of the given speed-bin. If necessary, we stretch out +* tRRD to allow us to operate on a 6x multiplier for tFAW. +*/ + tfaw_as_ps =40000 ;/* 40ns: tFAW for DDR3-1600K, 2KB page-size */ +if (tCK_to_ps (pctl_timing->trrd *6 , freq) < tfaw_as_ps) { +/* If tFAW is > 6 x tRRD, we need to stretch tRRD */ + pctl_timing->trrd =ps_to_tCK (DIV_ROUND_UP (40000 ,6 ), freq); + params->tfaw_mult =TFAW_TRRD_MULT6 ; + }else if (tCK_to_ps (pctl_timing->trrd *5 , freq) < tfaw_as_ps) { + params->tfaw_mult =TFAW_TRRD_MULT6 ; + }else if (tCK_to_ps (pctl_timing->trrd *4 , freq) < tfaw_as_ps) { + params->tfaw_mult =TFAW_TRRD_MULT5 ; + }else { + params->tfaw_mult =TFAW_TRRD_MULT4 ; + } + +return 0 ; +} + +static void pctl_cfg (struct rk3368_ddr_pctl *pctl, +struct rk3368_sdram_params *params, +struct rk3368_grf *grf) +{ +/* Configure PCTL timing registers */ + params->pctl_timing.trefi |=BIT (31 );/* see PCTL_TREFI */ +copy_to_reg (&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u, +sizeof (params->pctl_timing)); +writel (params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3); + +/* Set up ODT write selector and ODT write length */ +writel ((RANK0_ODT_WRITE_SEL |RANK1_ODT_WRITE_SEL ), &pctl->dfiodtcfg); +writel (7 <<ODT_LEN_BL8_W_SHIFT , &pctl->dfiodtcfg1); + +/* Set up the CL/CWL-dependent timings of DFI */ +writel ((params->pctl_timing.tcl -1 ) /2 -1 , &pctl->dfitrddataen); +writel ((params->pctl_timing.tcwl -1 ) /2 -1 , &pctl->dfitphywrlat); + +/* DDR3 */ +writel (params->tfaw_mult |DDR3_EN |DDR2_DDR3_BL_8 , &pctl->mcfg); +writel (0x001c0004 , &grf->ddrc0_con0); + +setbits_le32 (&pctl->scfg,HW_LOW_POWER_EN ); +} + +static int ddrphy_data_training (struct rk3368_ddr_pctl *pctl, +struct rk3368_ddrphy *ddrphy) +{ +const u32 trefi =readl (&pctl->trefi); +const ulong timeout_ms =500 ; +ulong tmp; + +/* disable auto-refresh */ +writel (0 |BIT (31 ), &pctl->trefi); + +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x20 ); +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x21 ); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: did not complete within %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while ((readl (&ddrphy->reg[0xff ]) &0xf ) !=0xf ); + +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,PREA_CMD ); +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x20 ); +/* resume auto-refresh */ +writel (trefi |BIT (31 ), &pctl->trefi); + +return 0 ; +} + +static int sdram_col_row_detect (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_sdram_params *params =dev_get_platdata (dev); +struct rk3368_ddr_pctl *pctl = priv->pctl; +struct rk3368_msch *msch = priv->msch; +const u32 test_pattern =0x5aa5f00f ; +int row, col; +uintptr_t addr; + +move_to_config_state (pctl); +writel (6 , &msch->ddrconf); +move_to_access_state (pctl); + +/* Detect col */ +for (col =11 ; col >=9 ; col--) { +writel (0 ,CONFIG_SYS_SDRAM_BASE ); + addr =CONFIG_SYS_SDRAM_BASE + + (1 << (col + params->chan.bw -1 )); +writel (test_pattern, addr); +if ((readl (addr) == test_pattern) && + (readl (CONFIG_SYS_SDRAM_BASE ) ==0 )) +break ; + } + +if (col ==8 ) { +error ("%s: col detect error\n" , __func__); +return -EINVAL ; + } + +move_to_config_state (pctl); +writel (15 , &msch->ddrconf); +move_to_access_state (pctl); + +/* Detect row*/ +for (row =16 ; row >=12 ; row--) { +writel (0 ,CONFIG_SYS_SDRAM_BASE ); + addr =CONFIG_SYS_SDRAM_BASE + (1 << (row +15 -1 )); +writel (test_pattern, addr); +if ((readl (addr) == test_pattern) && + (readl (CONFIG_SYS_SDRAM_BASE ) ==0 )) +break ; + } + +if (row ==11 ) { +error ("%s: row detect error\n" , __func__); +return -EINVAL ; + } + +/* Record results */ +debug ("%s: col %d, row %d\n" , __func__, col, row); + params->chan.col = col; + params->chan.cs0_row = row; + params->chan.cs1_row = row; + params->chan.row_3_4 =0 ; + +return 0 ; +} + +static int msch_niu_config (struct rk3368_msch *msch, +struct rk3368_sdram_params *params) +{ +int i; +const u8 cols = params->chan.col - ((params->chan.bw ==2 ) ?0 :1 ); +const u8 rows = params->chan.cs0_row; + +/* +* The DDR address-translation table always assumes a 32bit +* bus and the comparison below takes care of adjusting for +* a 16bit bus (i.e. one column-address is consumed). +*/ +const struct { +u8 rows; +u8 columns; +u8 type; + } ddrconf_table[] = { +/* +* C-B-R-D patterns are first. For these we require an +* exact match for the columns and rows (as there's +* one entry per possible configuration). +*/ + [0 ] = { .rows =13 , .columns =10 , .type =DMC_MSCH_CBRD }, + [1 ] = { .rows =14 , .columns =10 , .type =DMC_MSCH_CBRD }, + [2 ] = { .rows =15 , .columns =10 , .type =DMC_MSCH_CBRD }, + [3 ] = { .rows =16 , .columns =10 , .type =DMC_MSCH_CBRD }, + [4 ] = { .rows =14 , .columns =11 , .type =DMC_MSCH_CBRD }, + [5 ] = { .rows =15 , .columns =11 , .type =DMC_MSCH_CBRD }, + [6 ] = { .rows =16 , .columns =11 , .type =DMC_MSCH_CBRD }, + [7 ] = { .rows =13 , .columns =9 , .type =DMC_MSCH_CBRD }, + [8 ] = { .rows =14 , .columns =9 , .type =DMC_MSCH_CBRD }, + [9 ] = { .rows =15 , .columns =9 , .type =DMC_MSCH_CBRD }, + [10 ] = { .rows =16 , .columns =9 , .type =DMC_MSCH_CBRD }, +/* +* 11 through 13 are C-R-B-D patterns. These are +* matched for an exact number of columns and to +* ensure that the hardware uses at least as many rows +* as the pattern requires (i.e. we make sure that +* there's no gaps up until we hit the device/chip-select; +* however, these patterns can accept up to 16 rows, +* as the row-address continues right after the CS +* switching) +*/ + [11 ] = { .rows =15 , .columns =10 , .type =DMC_MSCH_CRBD }, + [12 ] = { .rows =14 , .columns =11 , .type =DMC_MSCH_CRBD }, + [13 ] = { .rows =13 , .columns =10 , .type =DMC_MSCH_CRBD }, +/* +* 14 and 15 are catch-all variants using a C-B-D-R +* scheme (i.e. alternating the chip-select every time +* C-B overflows) and stuffing the remaining C-bits +* into the top. Matching needs to make sure that the +* number of columns is either an exact match (i.e. we +* can use less the the maximum number of rows) -or- +* that the columns exceed what is given in this table +* and the rows are an exact match (in which case the +* remaining C-bits will be stuffed onto the top after +* the device/chip-select switches). +*/ + [14 ] = { .rows =16 , .columns =10 , .type =DMC_MSCH_CBDR }, + [15 ] = { .rows =16 , .columns =9 , .type =DMC_MSCH_CBDR }, + }; + +/* +* For C-B-R-D, we need an exact match (i.e. both for the number of +* columns and rows), while for C-B-D-R, only the the number of +* columns needs to match. +*/ +for (i =0 ; i <ARRAY_SIZE (ddrconf_table); i++) { +bool match = false; + +/* If this entry if for a different matcher, then skip it */ +if (ddrconf_table[i].type != params->memory_schedule) +continue ; + +/* +* Match according to the rules (exact/inexact/at-least) +* documented in the ddrconf_table above. +*/ +switch (params->memory_schedule) { +case DMC_MSCH_CBRD : + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows == rows); +break ; + +case DMC_MSCH_CRBD : + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows <= rows); +break ; + +case DMC_MSCH_CBDR : + match = (ddrconf_table[i].columns == cols) || + ((ddrconf_table[i].columns <= cols) && + (ddrconf_table[i].rows == rows)); +break ; + +default : +break ; + } + +if (match) { +debug ("%s: setting ddrconf 0x%x\n" , __func__, i); +writel (i, &msch->ddrconf); +return 0 ; + } + } + +error ("%s: ddrconf (NIU config) not found\n" , __func__); +return -EINVAL ; +} + +static void dram_all_config (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_pmu_grf *pmugrf = priv->pmugrf; +struct rk3368_sdram_params *params =dev_get_platdata (dev); +const struct rk3288_sdram_channel *info = ¶ms->chan; +u32 sys_reg =0 ; +const int chan =0 ; + + sys_reg |=DDR3 <<SYS_REG_DDRTYPE_SHIFT ; + sys_reg |=0 <<SYS_REG_NUM_CH_SHIFT ; + + sys_reg |= info->row_3_4 <<SYS_REG_ROW_3_4_SHIFT (chan); + sys_reg |=1 <<SYS_REG_CHINFO_SHIFT (chan); + sys_reg |= (info->rank -1 ) <<SYS_REG_RANK_SHIFT (chan); + sys_reg |= (info->col -9 ) <<SYS_REG_COL_SHIFT (chan); + sys_reg |= info->bk ==3 ?0 :1 <<SYS_REG_BK_SHIFT (chan); + sys_reg |= (info->cs0_row -13 ) <<SYS_REG_CS0_ROW_SHIFT (chan); + sys_reg |= (info->cs1_row -13 ) <<SYS_REG_CS1_ROW_SHIFT (chan); + sys_reg |= (2 >> info->bw) <<SYS_REG_BW_SHIFT (chan); + sys_reg |= (2 >> info->dbw) <<SYS_REG_DBW_SHIFT (chan); + +writel (sys_reg, &pmugrf->os_reg[2 ]); +} + +static int setup_sdram (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_sdram_params *params =dev_get_platdata (dev); + +struct rk3368_ddr_pctl *pctl = priv->pctl; +struct rk3368_ddrphy *ddrphy = priv->phy; +struct rk3368_cru *cru = priv->cru; +struct rk3368_grf *grf = priv->grf; +struct rk3368_msch *msch = priv->msch; + +int ret; + +/* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */ + ret =clk_set_rate (&priv->ddr_clk,2 * params->ddr_freq); +if (ret <0 ) { +debug ("%s: could not set DDR clock: %d\n" , __func__, ret); +return ret; + } + +/* Update the read-latency for the RK3368 */ +writel (0x32 , &msch->readlatency); + +/* Initialise the DDR PCTL and DDR PHY */ +ddrctl_reset (cru); +ddrphy_reset (ddrphy); +ddrphy_config_delays (ddrphy, params->ddr_freq); +dfi_cfg (pctl); +/* Configure relative system information of grf_ddrc0_con0 register */ +ddr_set_ddr3_mode (grf, true); +ddr_set_noc_spr_err_stall (grf, true); +/* Calculate timings */ +pctl_calc_timings (params, params->ddr_freq); +/* Initialise the device timings in protocol controller */ +pctl_cfg (pctl, params, grf); +/* Configure AL, CL ... information of PHY registers */ +ddrphy_config (ddrphy, + params->pctl_timing.tcl, + params->pctl_timing.tal, + params->pctl_timing.tcwl); + +/* Initialize DRAM and configure with mode-register values */ + ret =memory_init (pctl, params); +if (ret) + goto error; + +move_to_config_state (pctl); +/* Perform data-training */ +ddrphy_data_training (pctl, ddrphy); +move_to_access_state (pctl); + +/* TODO(prt): could detect rank in training... */ + params->chan.rank =2 ; +/* TODO(prt): bus width is not auto-detected (yet)... */ + params->chan.bw =2 ;/* 32bit wide bus */ + params->chan.dbw = params->chan.dbw;/* 32bit wide bus */ + +/* DDR3 is always 8 bank */ + params->chan.bk =3 ; +/* Detect col and row number */ + ret =sdram_col_row_detect (dev); +if (ret) + goto error; + +/* Configure NIU DDR configuration */ + ret =msch_niu_config (msch, params); +if (ret) + goto error; + +/* set up OS_REG to communicate w/ next stage and OS */ +dram_all_config (dev); + +return 0 ; + +error: +printf ("DRAM init failed!\n" ); +hang (); +} +#endif + +static int rk3368_dmc_ofdata_to_platdata (struct udevice *dev) +{ +int ret =0 ; + +#if !CONFIG_IS_ENABLED (OF_PLATDATA ) +struct rk3368_sdram_params *plat =dev_get_platdata (dev); + + ret =regmap_init_mem (dev, &plat->map); +if (ret) +return ret; +#endif + +return ret; +} + +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +static int conv_of_platdata (struct udevice *dev) +{ +struct rk3368_sdram_params *plat =dev_get_platdata (dev); +struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat; +int ret; + + plat->ddr_freq = of_plat->rockchip_ddr_frequency; + plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin; + plat->memory_schedule = of_plat->rockchip_memory_schedule; + + ret =regmap_init_mem_platdata (dev, of_plat->reg, +ARRAY_SIZE (of_plat->reg) /2 , + &plat->map); +if (ret) +return ret; + +return 0 ; +} +#endif + +static int rk3368_dmc_probe (struct udevice *dev) +{ +#ifdef CONFIG_TPL_BUILD +struct rk3368_sdram_params *plat =dev_get_platdata (dev); +struct rk3368_ddr_pctl *pctl; +struct rk3368_ddrphy *ddrphy; +struct rk3368_cru *cru; +struct rk3368_grf *grf; +struct rk3368_msch *msch; +int ret; +struct udevice *dev_clk; +#endif +struct dram_info *priv =dev_get_priv (dev); + +#if CONFIG_IS_ENABLED (OF_PLATDATA ) + ret =conv_of_platdata (dev); +if (ret) +return ret; +#endif + + priv->pmugrf =syscon_get_first_range (ROCKCHIP_SYSCON_PMUGRF ); +debug ("%s: pmugrf=%p\n" , __func__, priv->pmugrf); + +#ifdef CONFIG_TPL_BUILD + pctl =regmap_get_range (plat->map,0 ); + ddrphy =regmap_get_range (plat->map,1 ); + msch =syscon_get_first_range (ROCKCHIP_SYSCON_MSCH ); + grf =syscon_get_first_range (ROCKCHIP_SYSCON_GRF ); + + priv->pctl = pctl; + priv->phy = ddrphy; + priv->msch = msch; + priv->grf = grf; + + ret =rockchip_get_clk (&dev_clk); +if (ret) +return ret; + priv->ddr_clk.id =CLK_DDR ; + ret =clk_request (dev_clk, &priv->ddr_clk); +if (ret) +return ret; + + cru =rockchip_get_cru (); + priv->cru = cru; +if (IS_ERR (priv->cru)) +return PTR_ERR (priv->cru); + + ret =setup_sdram (dev); +if (ret) +return ret; +#endif + + priv->info.base =0 ; + priv->info.size = +rockchip_sdram_size ((phys_addr_t)&priv->pmugrf->os_reg[2 ]); + +/* +* we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff +* is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is +* inaccessible for some IP controller. +*/ + priv->info.size =min (priv->info.size, (size_t )0xfe000000 ); + +return 0 ; +} + +static int rk3368_dmc_get_info (struct udevice *dev,struct ram_info *info) +{ +struct dram_info *priv =dev_get_priv (dev); + + *info = priv->info; +return 0 ; +} + +static struct ram_ops rk3368_dmc_ops = { + .get_info = rk3368_dmc_get_info, +}; + + +static const struct udevice_id rk3368_dmc_ids[] = { + { .compatible ="rockchip,rk3368-dmc" }, + { } +}; + +U_BOOT_DRIVER (dmc_rk3368) = { + .name ="rockchip_rk3368_dmc" , + .id =UCLASS_RAM , + .of_match = rk3368_dmc_ids, + .ops = &rk3368_dmc_ops, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size =sizeof (struct dram_info ), + .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size =sizeof (struct dram_info ), + .platdata_auto_alloc_size =sizeof (struct rk3368_sdram_params ), +};include/dt-bindings/memory/rk3368-dmc.h new file +30
-0@@ -0,0 +1,30 @@ +#ifndef DT_BINDINGS_RK3368_DMC_H +#define DT_BINDINGS_RK3368_DMC_H + +#define DMC_MSCH_CBDR 0x0 +#define DMC_MSCH_CBRD 0x1 +#define DMC_MSCH_CRBD 0x2 + +#define DDR3_800D 0 +#define DDR3_800E 1 +#define DDR3_1066E 2 +#define DDR3_1066F 3 +#define DDR3_1066G 4 +#define DDR3_1333F 5 +#define DDR3_1333G 6 +#define DDR3_1333H 7 +#define DDR3_1333J 8 +#define DDR3_1600G 9 +#define DDR3_1600H 10 +#define DDR3_1600J 11 +#define DDR3_1600K 12 +#define DDR3_1866J 13 +#define DDR3_1866K 14 +#define DDR3_1866L 15 +#define DDR3_1866M 16 +#define DDR3_2133K 17 +#define DDR3_2133L 18 +#define DDR3_2133M 19 +#define DDR3_2133N 20 + +#endif
PATCH v3 50/66 rockchip: rk3368: add DRAM controller driver with DRAM initialisation
Andy,
The functionality of the new driver should be equivalent for the non-TPL case. All the code from the original driver is still present in the new driver for non-TPL (see rk3368_dmc_probe).
Seeing that -19 is -ENODEV, I suspect that something went wrong in the DM binding/probing: did you set 'status = “okay”’ for the DMC?
Regards,
Phil.
Quoted 2,962 lines · Andy Yan
Hi Philipp:
Quoted 1,747 lines · Philipp Tomsich
This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip(where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually).At this stage, only the following feature-set is supported:
- DDR3
- 32-bit configuration (i.e. fully populated)
- dual-rank (i.e. no auto-detection of ranks)
- DDR3-1600K speed-binThis driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the
os_reg2in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code).Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time).
The RK3368 also has the
DDRC0_CON0(DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation.
As part of this change,DDRC0_CON0is also added to the GRF structure definition (at offset0x600).Signed-off-by Philipp Tomsich <[email protected]>Reviewed-by Simon Glass <[email protected]>---
Changes in v3:
- correctly states the location of the driver in the commit messageChanges in v2: None
arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++ arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 + arch/arm/mach-rockchip/rk3368/Makefile | 1 - arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 -- .../clock/rockchip,rk3368-dmc.txt | 67 ++ drivers/ram/Makefile | 2 + drivers/ram/rockchip/Makefile | 7 + drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++ include/dt-bindings/memory/rk3368-dmc.h | 30 + 9 files changed, 1286 insertions(+), 61 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt create mode 100644 drivers/ram/rockchip/Makefile create mode 100644 drivers/ram/rockchip/dmc-rk3368.c create mode 100644 include/dt-bindings/memory/rk3368-dmc.harch/arm/include/asm/arch-rockchip/ddr_rk3368.h new file +79
-0@@ -0,0 +1,187 @@ +/* +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_DDR_RK3368_H__ +#define __ASM_ARCH_DDR_RK3368_H__ + +/* + * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only + * in a few details. Most notably, it has an additional field to track + * tREFI in controller cycles (i.e. trefi_mem_ddr3). + */ +struct rk3368_ddr_pctl { + u32 scfg; + u32 sctl; + u32 stat; + u32 intrstat; + u32 reserved0[12]; + u32 mcmd; + u32 powctl; + u32 powstat; + u32 cmdtstat; + u32 cmdtstaten; + u32 reserved1[3]; + u32 mrrcfg0; + u32 mrrstat0; + u32 mrrstat1; + u32 reserved2[4]; + u32 mcfg1; + u32 mcfg; + u32 ppcfg; + u32 mstat; + u32 lpddr2zqcfg; + u32 reserved3; + u32 dtupdes; + u32 dtuna; + u32 dtune; + u32 dtuprd0; + u32 dtuprd1; + u32 dtuprd2; + u32 dtuprd3; + u32 dtuawdt; + u32 reserved4[3]; + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tHi Philipp:
Quoted 267 lines · Philipp Tomsich
This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip(where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually).At this stage, only the following feature-set is supported:
- DDR3
- 32-bit configuration (i.e. fully populated)
- dual-rank (i.e. no auto-detection of ranks)
- DDR3-1600K speed-binThis driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the
os_reg2in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code).Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time).
The RK3368 also has the
DDRC0_CON0(DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation.
As part of this change,DDRC0_CON0is also added to the GRF structure definition (at offset0x600).Signed-off-by Philipp Tomsich <[email protected]>Reviewed-by Simon Glass <[email protected]>---
Changes in v3:
- correctly states the location of the driver in the commit messageChanges in v2: None
arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++ arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 + arch/arm/mach-rockchip/rk3368/Makefile | 1 - arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 -- .../clock/rockchip,rk3368-dmc.txt | 67 ++ drivers/ram/Makefile | 2 + drivers/ram/rockchip/Makefile | 7 + drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++ include/dt-bindings/memory/rk3368-dmc.h | 30 + 9 files changed, 1286 insertions(+), 61 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt create mode 100644 drivers/ram/rockchip/Makefile create mode 100644 drivers/ram/rockchip/dmc-rk3368.c create mode 100644 include/dt-bindings/memory/rk3368-dmc.harch/arm/include/asm/arch-rockchip/ddr_rk3368.h new file +187
-0@@ -0,0 +1,187 @@ +/* +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_DDR_RK3368_H__ +#define __ASM_ARCH_DDR_RK3368_H__ + +/* +* The RK3368 DDR PCTL differs from the incarnation in the RK3288 only +* in a few details. Most notably, it has an additional field to track +* tREFI in controller cycles (i.e. trefi_mem_ddr3). +*/ +struct rk3368_ddr_pctl { +u32 scfg; +u32 sctl; +u32 stat; +u32 intrstat; +u32 reserved0[12 ]; +u32 mcmd; +u32 powctl; +u32 powstat; +u32 cmdtstat; +u32 cmdtstaten; +u32 reserved1[3 ]; +u32 mrrcfg0; +u32 mrrstat0; +u32 mrrstat1; +u32 reserved2[4 ]; +u32 mcfg1; +u32 mcfg; +u32 ppcfg; +u32 mstat; +u32 lpddr2zqcfg; +u32 reserved3; +u32 dtupdes; +u32 dtuna; +u32 dtune; +u32 dtuprd0; +u32 dtuprd1; +u32 dtuprd2; +u32 dtuprd3; +u32 dtuawdt; +u32 reserved4[3 ]; +u32 togcnt1u; +u32 tinit; +u32 trsth; +u32 togcnt100n; +u32 trefi; +u32 tmrd; +u32 trfc; +u32 trp; +u32 trtw; +u32 tal; +u32 tcl; +u32 tcwl; +u32 tras; +u32 trc; +u32 trcd; +u32 trrd; +u32 trtp; +u32 twr; +u32 twtr; +u32 texsr; +u32 txp; +u32 txpdll; +u32 tzqcs; +u32 tzqcsi; +u32 tdqs; +u32 tcksre; +u32 tcksrx; +u32 tcke; +u32 tmod; +u32 trstl; +u32 tzqcl; +u32 tmrr; +u32 tckesr; +u32 tdpd; +u32 trefi_mem_ddr3; +u32 reserved5[45 ]; +u32 dtuwactl; +u32 dturactl; +u32 dtucfg; +u32 dtuectl; +u32 dtuwd0; +u32 dtuwd1; +u32 dtuwd2; +u32 dtuwd3; +u32 dtuwdm; +u32 dturd0; +u32 dturd1; +u32 dturd2; +u32 dturd3; +u32 dtulfsrwd; +u32 dtulfsrrd; +u32 dtueaf; +u32 dfitctrldelay; +u32 dfiodtcfg; +u32 dfiodtcfg1; +u32 dfiodtrankmap; +u32 dfitphywrdata; +u32 dfitphywrlat; +u32 reserved7[2 ]; +u32 dfitrddataen; +u32 dfitphyrdlat; +u32 reserved8[2 ]; +u32 dfitphyupdtype0; +u32 dfitphyupdtype1; +u32 dfitphyupdtype2; +u32 dfitphyupdtype3; +u32 dfitctrlupdmin; +u32 dfitctrlupdmax; +u32 dfitctrlupddly; +u32 reserved9; +u32 dfiupdcfg; +u32 dfitrefmski; +u32 dfitctrlupdi; +u32 reserved10[4 ]; +u32 dfitrcfg0; +u32 dfitrstat0; +u32 dfitrwrlvlen; +u32 dfitrrdlvlen; +u32 dfitrrdlvlgateen; +u32 dfiststat0; +u32 dfistcfg0; +u32 dfistcfg1; +u32 reserved11; +u32 dfitdramclken; +u32 dfitdramclkdis; +u32 dfistcfg2; +u32 dfistparclr; +u32 dfistparlog; +u32 reserved12[3 ]; +u32 dfilpcfg0; +u32 reserved13[3 ]; +u32 dfitrwrlvlresp0; +u32 dfitrwrlvlresp1; +u32 dfitrwrlvlresp2; +u32 dfitrrdlvlresp0; +u32 dfitrrdlvlresp1; +u32 dfitrrdlvlresp2; +u32 dfitrwrlvldelay0; +u32 dfitrwrlvldelay1; +u32 dfitrwrlvldelay2; +u32 dfitrrdlvldelay0; +u32 dfitrrdlvldelay1; +u32 dfitrrdlvldelay2; +u32 dfitrrdlvlgatedelay0; +u32 dfitrrdlvlgatedelay1; +u32 dfitrrdlvlgatedelay2; +u32 dfitrcmd; +u32 reserved14[46 ]; +u32 ipvr; +u32 iptr; +}; +check_member (rk3368_ddr_pctl, iptr,0x03fc ); + +struct rk3368_ddrphy { +u32 reg[0x100 ]; +}; +check_member (rk3368_ddrphy, reg[0xff ],0x03fc ); + +struct rk3368_msch { +u32 coreid; +u32 revisionid; +u32 ddrconf; +u32 ddrtiming; +u32 ddrmode; +u32 readlatency; +u32 reserved1[8 ]; +u32 activate; +u32 devtodev; +}; +check_member (rk3368_msch, devtodev,0x003c ); + +/* GRF_SOC_CON0 */ +enum { +NOC_RSP_ERR_STALL =BIT (9 ), +MOBILE_DDR_SEL =BIT (4 ), +DDR0_16BIT_EN =BIT (3 ), +MSCH0_MAINDDR3_DDR3 =BIT (2 ), +MSCH0_MAINPARTIALPOP =BIT (1 ), +UPCTL_C_ACTIVE =BIT (0 ), +}; + +#endif arch/arm/include/asm/arch-rockchip/grf_rk3368.h +3
-0@@ -76,8 +76,11 @@ struct rk3368_grf {u32 soc_con15;u32 soc_con16;u32 soc_con17; +u32 reserved5[0x6e ]; +u32 ddrc0_con0; };check_member (rk3368_grf, soc_con17,0x444 ); +check_member (rk3368_grf, ddrc0_con0,0x600 );struct rk3368_pmu_grf {u32 gpio0a_iomux;arch/arm/mach-rockchip/rk3368/Makefile +0
-0arch/arm/mach-rockchip/rk3368/Makefile line 8
Quoted 5 lines
arch/arm/mach-rockchip/rk3368/Makefile +0
-1@@ -5,5 +5,4 @@ # obj-y += clk_rk3368.o obj-y += rk3368.o -obj-y += sdram_rk3368.o obj-y += syscon_rk3368.othe current PX5 EVB and Sheep board(they don't use spl now) depend on
thesdram_rk3368driver to get the sdram capacity, and so is the geekbox.
They will be broken when this driver removed.We got the boot failed log on PX5 like bellow:
Quoted 1,184 lines
arch/arm/mach-rockchip/rk3368/sdram_rk3368.c deleted +0
-60@@ -1,60 +0,0 @@ -/* -* (C) Copyright 2016 Rockchip Electronics Co., Ltd. -* -* SPDX-License-Identifier: GPL-2.0 -*/ - -#include <common.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/sdram_common.h> - -DECLARE_GLOBAL_DATA_PTR ; -struct dram_info { -struct ram_info info; -struct rk3368_pmu_grf *pmugrf; -}; - -static int rk3368_dmc_probe (struct udevice *dev) -{ -struct dram_info *priv =dev_get_priv (dev); - - priv->pmugrf =syscon_get_first_range (ROCKCHIP_SYSCON_PMUGRF ); -debug ("%s: grf=%p\n" , __func__, priv->pmugrf); - priv->info.base =CONFIG_SYS_SDRAM_BASE ; - priv->info.size =rockchip_sdram_size ( - (phys_addr_t)&priv->pmugrf->os_reg[2 ]); - -return 0 ; -} - -static int rk3368_dmc_get_info (struct udevice *dev,struct ram_info *info) -{ -struct dram_info *priv =dev_get_priv (dev); - - *info = priv->info; - -return 0 ; -} - -static struct ram_ops rk3368_dmc_ops = { - .get_info = rk3368_dmc_get_info, -}; - - -static const struct udevice_id rk3368_dmc_ids[] = { - { .compatible ="rockchip,rk3368-dmc" }, - { } -}; - -U_BOOT_DRIVER (dmc_rk3368) = { - .name ="rockchip_rk3368_dmc" , - .id =UCLASS_RAM , - .of_match = rk3368_dmc_ids, - .ops = &rk3368_dmc_ops, - .probe = rk3368_dmc_probe, - .priv_auto_alloc_size =sizeof (struct dram_info ), -};doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt new file +67
-0@@ -0,0 +1,67 @@ +RK3368 dynamic memory controller driver +======================================= + +The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation +during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on +the following key configuration data: + (a) a target-frequency (i.e. operating point) for the memory operation + (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware + (c) a memory-schedule (i.e. mapping from physical addresses to the address + pins of the memory bus) + +Required properties +------------------- + +- compatible: "rockchip,rk3368-dmc" +- reg + protocol controller (PCTL) address and PHY controller (DDRPHY) address +- rockchip,ddr-speed-bin + the DDR3 device's speed-bin (as specified according to JESD-79) + DDR3_800D (5-5-5) + DDR3_800E (6-6-6) + DDR3_1066E (6-6-6) + DDR3_1066F (7-7-7) + DDR3_1066G (8-8-8) + DDR3_1333F (7-7-7) + DDR3_1333G (8-8-8) + DDR3_1333H (9-9-9) + DDR3_1333J (10-10-10) + DDR3_1600G (8-8-8) + DDR3_1600H (9-9-9) + DDR3_1600J (10-10-10) + DDR3_1600K (11-11-11) + DDR3_1866J (10-10-10) + DDR3_1866K (11-11-11) + DDR3_1866L (12-12-12) + DDR3_1866M (13-13-13) + DDR3_2133K (11-11-11) + DDR3_2133L (12-12-12) + DDR3_2133M (13-13-13) + DDR3_2133N (14-14-14) +- rockchip,ddr-frequency: + target DDR clock frequency in Hz (not all frequencies may be supported, + as there's some cooperation from the clock-driver required) +- rockchip,memory-schedule: + controls the decoding of physical addresses to DRAM addressing (i.e. how + the physical address maps onto the address pins/chip-select of the device) + DMC_MSCH_CBDR: column -> bank -> device -> row + DMC_MSCH_CBRD: column -> band -> row -> device + DMC_MSCH_CRBD: column -> row -> band -> device + +Example (for DDR3-1600K and 800MHz) +----------------------------------- + + #include <dt-bindings/memory/rk3368-dmc.h> + + dmc: dmc at ff610000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3368-dmc"; + reg = <0 0xff610000 0 0x400 + 0 0xff620000 0 0x400>; + }; + + &dmc { + rockchip,ddr-speed-bin = <DDR3_1600K>; + rockchip,ddr-frequency = <800000000>; + rockchip,memory-schedule = <DMC_MSCH_CBRD>; + };drivers/ram/Makefile +2
-0@@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o + +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/drivers/ram/rockchip/Makefile new file +7
-0@@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.odrivers/ram/rockchip/dmc-rk3368.c new file +990
-0@@ -0,0 +1,990 @@ +/* +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dt-bindings/memory/rk3368-dmc.h> +#include <dt-structs.h> +#include <ram.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3368.h> +#include <asm/arch/grf_rk3368.h> +#include <asm/arch/ddr_rk3368.h> +#include <asm/arch/sdram.h> +#include <asm/arch/sdram_common.h> + +DECLARE_GLOBAL_DATA_PTR ; + +struct dram_info { +struct ram_info info; +struct clk ddr_clk; +struct rk3368_cru *cru; +struct rk3368_grf *grf; +struct rk3368_ddr_pctl *pctl; +struct rk3368_ddrphy *phy; +struct rk3368_pmu_grf *pmugrf; +struct rk3368_msch *msch; +}; + +struct rk3368_sdram_params { +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +struct dtd_rockchip_rk3368_dmc of_plat; +#endif +struct rk3288_sdram_pctl_timing pctl_timing; +u32 trefi_mem_ddr3; +struct rk3288_sdram_channel chan; +struct regmap *map; +u32 ddr_freq; +u32 memory_schedule; +u32 ddr_speed_bin; +u32 tfaw_mult; +}; + +/* PTCL bits */ +enum { +/* PCTL_DFISTCFG0 */ +DFI_INIT_START =BIT (0 ), +DFI_DATA_BYTE_DISABLE_EN =BIT (2 ), + +/* PCTL_DFISTCFG1 */ +DFI_DRAM_CLK_SR_EN =BIT (0 ), +DFI_DRAM_CLK_DPD_EN =BIT (1 ), +ODT_LEN_BL8_W_SHIFT =16 , + +/* PCTL_DFISTCFG2 */ +DFI_PARITY_INTR_EN =BIT (0 ), +DFI_PARITY_EN =BIT (1 ), + +/* PCTL_DFILPCFG0 */ +TLP_RESP_TIME_SHIFT =16 , +LP_SR_EN =BIT (8 ), +LP_PD_EN =BIT (0 ), + +/* PCTL_DFIODTCFG */ +RANK0_ODT_WRITE_SEL =BIT (3 ), +RANK1_ODT_WRITE_SEL =BIT (11 ), + +/* PCTL_SCFG */ +HW_LOW_POWER_EN =BIT (0 ), + +/* PCTL_MCMD */ +START_CMD =BIT (31 ), +MCMD_RANK0 =BIT (20 ), +MCMD_RANK1 =BIT (21 ), +DESELECT_CMD =0 , +PREA_CMD , +REF_CMD , +MRS_CMD , +ZQCS_CMD , +ZQCL_CMD , +RSTL_CMD , +MRR_CMD =8 , +DPDE_CMD , + +/* PCTL_POWCTL */ +POWER_UP_START =BIT (0 ), + +/* PCTL_POWSTAT */ +POWER_UP_DONE =BIT (0 ), + +/* PCTL_SCTL */ +INIT_STATE =0 , +CFG_STATE , +GO_STATE , +SLEEP_STATE , +WAKEUP_STATE , + +/* PCTL_STAT */ +LP_TRIG_SHIFT =4 , +LP_TRIG_MASK =7 , +PCTL_STAT_MSK =7 , +INIT_MEM =0 , +CONFIG , +CONFIG_REQ , +ACCESS , +ACCESS_REQ , +LOW_POWER , +LOW_POWER_ENTRY_REQ , +LOW_POWER_EXIT_REQ , + +/* PCTL_MCFG */ +DDR2_DDR3_BL_8 =BIT (0 ), +DDR3_EN =BIT (5 ), +TFAW_TRRD_MULT4 = (0 <<18 ), +TFAW_TRRD_MULT5 = (1 <<18 ), +TFAW_TRRD_MULT6 = (2 <<18 ), +}; + +#define DDR3_MR0_WR (n) \ + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9)) +#define DDR3_MR0_CL (n) \ + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2)) +#define DDR3_MR0_BL8 \ + (0 << 0) +#define DDR3_MR0_DLL_RESET \ + (1 << 8) +#define DDR3_MR1_RTT120OHM \ + ((0 << 9) | (1 << 6) | (0 << 2)) +#define DDR3_MR2_TWL (n) \ + (((n - 5) & 0x7) << 3) + + +#ifdef CONFIG_TPL_BUILD + +static void ddr_set_noc_spr_err_stall (struct rk3368_grf *grf,bool enable) +{ +if (enable) +rk_setreg (&grf->ddrc0_con0,NOC_RSP_ERR_STALL ); +else +rk_clrreg (&grf->ddrc0_con0,NOC_RSP_ERR_STALL ); +} + +static void ddr_set_ddr3_mode (struct rk3368_grf *grf,bool ddr3_mode) +{ +if (ddr3_mode) +rk_setreg (&grf->ddrc0_con0,MSCH0_MAINDDR3_DDR3 ); +else +rk_clrreg (&grf->ddrc0_con0,MSCH0_MAINDDR3_DDR3 ); +} + +static void ddrphy_config (struct rk3368_ddrphy *phy, +u32 tcl,u32 tal,u32 tcwl) +{ +int i; + +/* Set to DDR3 mode */ +clrsetbits_le32 (&phy->reg[1 ],0x3 ,0x0 ); + +/* DDRPHY_REGB: CL, AL */ +clrsetbits_le32 (&phy->reg[0xb ],0xff , tcl <<4 | tal); +/* DDRPHY_REGC: CWL */ +clrsetbits_le32 (&phy->reg[0xc ],0x0f , tcwl); + +/* Update drive-strength */ +writel (0xcc , &phy->reg[0x11 ]); +writel (0xaa , &phy->reg[0x16 ]); +/* +* Update NRCOMP/PRCOMP for all 4 channels (for details of all +* affected registers refer to the documentation of DDRPHY_REG20 +* and DDRPHY_REG21 in the RK3368 TRM. +*/ +for (i =0 ; i <4 ; ++i) { +writel (0xcc , &phy->reg[0x20 + i *0x10 ]); +writel (0x44 , &phy->reg[0x21 + i *0x10 ]); + } + +/* Enable write-leveling calibration bypass */ +setbits_le32 (&phy->reg[2 ],BIT (3 )); +} + +static void copy_to_reg (u32 *dest,const u32 *src,u32 n) +{ +int i; + +for (i =0 ; i < n /sizeof (u32); i++) +writel (*src++, dest++); +} + +static void send_command (struct rk3368_ddr_pctl *pctl,u32 rank,u32 cmd) +{ +u32 mcmd =START_CMD | cmd | rank; + +debug ("%s: writing %x to MCMD\n" , __func__, mcmd); +writel (mcmd, &pctl->mcmd); +while (readl (&pctl->mcmd) &START_CMD ) +/* spin */ ; +} + +static void send_mrs (struct rk3368_ddr_pctl *pctl, +u32 rank,u32 mr_num,u32 mr_data) +{ +u32 mcmd =START_CMD |MRS_CMD | rank | (mr_num <<17 ) | (mr_data <<4 ); + +debug ("%s: writing %x to MCMD\n" , __func__, mcmd); +writel (mcmd, &pctl->mcmd); +while (readl (&pctl->mcmd) &START_CMD ) +/* spin */ ; +} + +static int memory_init (struct rk3368_ddr_pctl *pctl, +struct rk3368_sdram_params *params) +{ +u32 mr[4 ]; +const ulong timeout_ms =500 ; +ulong tmp; + +/* +* Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and +* wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register +* of PCTL. +*/ +writel (POWER_UP_START , &pctl->powctl); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: POWER_UP_START did not complete in %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while (!(readl (&pctl->powstat) &POWER_UP_DONE )); + +/* Configure MR0 through MR3 */ + mr[0 ] =DDR3_MR0_WR (params->pctl_timing.twr) | +DDR3_MR0_CL (params->pctl_timing.tcl) | +DDR3_MR0_DLL_RESET ; + mr[1 ] =DDR3_MR1_RTT120OHM ; + mr[2 ] =DDR3_MR2_TWL (params->pctl_timing.tcwl); + mr[3 ] =0 ; + +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.2 Initialization (DDR3 Initialization Sequence)" +*/ +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,DESELECT_CMD ); +udelay (1 ); +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,PREA_CMD ); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,2 , mr[2 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,3 , mr[3 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,1 , mr[1 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,0 , mr[0 ]); +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,ZQCL_CMD ); + +return 0 ; +} + +static void move_to_config_state (struct rk3368_ddr_pctl *pctl) +{ +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.1 State transition of PCTL (Moving to Config State)" +*/ +u32 state =readl (&pctl->stat) &PCTL_STAT_MSK ; + +switch (state) { +case LOW_POWER : +writel (WAKEUP_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=ACCESS ) +/* spin */ ; + +/* fall-through */ +case ACCESS : +case INIT_MEM : +writel (CFG_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=CONFIG ) +/* spin */ ; +break ; + +case CONFIG : +return ; + +default : +break ; + } +} + +static void move_to_access_state (struct rk3368_ddr_pctl *pctl) +{ +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.1 State transition of PCTL (Moving to Access State)" +*/ +u32 state =readl (&pctl->stat) &PCTL_STAT_MSK ; + +switch (state) { +case LOW_POWER : +if (((readl (&pctl->stat) >>LP_TRIG_SHIFT ) & +LP_TRIG_MASK ) ==1 ) +return ; + +writel (WAKEUP_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=ACCESS ) +/* spin */ ; + +/* fall-through */ +case INIT_MEM : +writel (CFG_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=CONFIG ) +/* spin */ ; + +/* fall-through */ +case CONFIG : +writel (GO_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) ==CONFIG ) +/* spin */ ; +break ; + +case ACCESS : +return ; + +default : +break ; + } +} + +static void ddrctl_reset (struct rk3368_cru *cru) +{ +const u32 ctl_reset =BIT (3 ) |BIT (2 ); +const u32 phy_reset =BIT (1 ) |BIT (0 ); + +rk_setreg (&cru->softrst_con[10 ], ctl_reset | phy_reset); +udelay (1 ); +rk_clrreg (&cru->softrst_con[10 ], ctl_reset | phy_reset); +} + +static void ddrphy_reset (struct rk3368_ddrphy *ddrphy) +{ +clrbits_le32 (&ddrphy->reg[0 ],BIT (3 ) |BIT (2 )); +udelay (1 ); +setbits_le32 (&ddrphy->reg[0 ],BIT (3 ) |BIT (2 )); +} + +static void ddrphy_config_delays (struct rk3368_ddrphy *ddrphy,u32 freq) +{ +u32 dqs_dll_delay; + +setbits_le32 (&ddrphy->reg[0x13 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x14 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x26 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x27 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x36 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x37 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x46 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x47 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x56 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x57 ],BIT (3 )); + +if (freq <=400000000 ) +setbits_le32 (&ddrphy->reg[0xa4 ],0x1f ); +else +clrbits_le32 (&ddrphy->reg[0xa4 ],0x1f ); + +if (freq <681000000 ) + dqs_dll_delay =3 ;/* 67.5 degree delay */ +else + dqs_dll_delay =2 ;/* 45 degree delay */ + +writel (dqs_dll_delay, &ddrphy->reg[0x28 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x38 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x48 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x58 ]); +} + +static int dfi_cfg (struct rk3368_ddr_pctl *pctl) +{ +const ulong timeout_ms =200 ; +ulong tmp; + +writel (DFI_DATA_BYTE_DISABLE_EN , &pctl->dfistcfg0); + +writel (DFI_DRAM_CLK_SR_EN |DFI_DRAM_CLK_DPD_EN , + &pctl->dfistcfg1); +writel (DFI_PARITY_INTR_EN |DFI_PARITY_EN , &pctl->dfistcfg2); +writel (7 <<TLP_RESP_TIME_SHIFT |LP_SR_EN |LP_PD_EN , + &pctl->dfilpcfg0); + +writel (1 , &pctl->dfitphyupdtype0); + +writel (0x1f , &pctl->dfitphyrdlat); +writel (0 , &pctl->dfitphywrdata); +writel (0 , &pctl->dfiupdcfg);/* phyupd and ctrlupd disabled */ + +setbits_le32 (&pctl->dfistcfg0,DFI_INIT_START ); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: DFI init did not complete within %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while ((readl (&pctl->dfiststat0) &1 ) ==0 ); + +return 0 ; +} + +static inline u32 ps_to_tCK (const u32 ps,const ulong freq) +{ +const ulong MHz =1000000 ; +return DIV_ROUND_UP (ps * freq,1000000 * MHz); +} + +static inline u32 ns_to_tCK (const u32 ns,const ulong freq) +{ +return ps_to_tCK (ns *1000 , freq); +} + +static inline u32 tCK_to_ps (const ulong tCK,const ulong freq) +{ +const ulong MHz =1000000 ; +return DIV_ROUND_UP (tCK *1000000 * MHz, freq); +} + +static int pctl_calc_timings (struct rk3368_sdram_params *params, +ulong freq) +{ +struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing; +const ulong MHz =1000000 ; +u32 tccd; +u32 tfaw_as_ps; + +if (params->ddr_speed_bin !=DDR3_1600K ) { +error ("%s: unimplemented DDR3 speed bin %d\n" , + __func__, params->ddr_speed_bin); +return -1 ; + } + +/* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */ + pctl_timing->togcnt1u =DIV_ROUND_UP (freq,2 * MHz); + pctl_timing->togcnt100n =DIV_ROUND_UP (freq /10 ,2 * MHz); + + pctl_timing->tinit =200 ;/* 200 usec */ + pctl_timing->trsth =500 ;/* 500 usec */ + pctl_timing->trefi =78 ;/* 7.8usec = 78 * 100ns */ + params->trefi_mem_ddr3 =ns_to_tCK (pctl_timing->trefi *100 , freq); + +if (freq <= (400 * MHz)) { + pctl_timing->tcl =6 ; + pctl_timing->tcwl =10 ; + }else if (freq <= (533 * MHz)) { + pctl_timing->tcl =8 ; + pctl_timing->tcwl =6 ; + }else if (freq <= (666 * MHz)) { + pctl_timing->tcl =10 ; + pctl_timing->tcwl =7 ; + }else { + pctl_timing->tcl =11 ; + pctl_timing->tcwl =8 ; + } + + pctl_timing->tmrd =4 ;/* 4 tCK (all speed bins) */ + pctl_timing->trfc =ns_to_tCK (350 , freq);/* tRFC: 350 (max) @ 8GBit */ + pctl_timing->trp =max (4u ,ps_to_tCK (13750 , freq)); +/* +* JESD-79: +* READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL +*/ + tccd =4 ; + pctl_timing->trtw = pctl_timing->tcl + tccd/2 +2 - pctl_timing->tcwl; + pctl_timing->tal =0 ; + pctl_timing->tras =ps_to_tCK (35000 , freq); + pctl_timing->trc =ps_to_tCK (48750 , freq); + pctl_timing->trcd =ps_to_tCK (13750 , freq); + pctl_timing->trrd =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->trtp =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->twr =ps_to_tCK (15000 , freq); +/* The DDR3 mode-register does only support even values for tWR > 8. */ +if (pctl_timing->twr >8 ) + pctl_timing->twr = (pctl_timing->twr +1 ) & ~1 ; + pctl_timing->twtr =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->texsr =512 ;/* tEXSR(max) is tDLLLK */ + pctl_timing->txp =max (3u ,ps_to_tCK (6000 , freq)); + pctl_timing->txpdll =max (10u ,ps_to_tCK (24000 , freq)); + pctl_timing->tzqcs =max (64u ,ps_to_tCK (80000 , freq)); + pctl_timing->tzqcsi =10000 ;/* as used by Rockchip */ + pctl_timing->tdqs =1 ;/* fixed for DDR3 */ + pctl_timing->tcksre =max (5u ,ps_to_tCK (10000 , freq)); + pctl_timing->tcksrx =max (5u ,ps_to_tCK (10000 , freq)); + pctl_timing->tcke =max (3u ,ps_to_tCK (5000 , freq)); + pctl_timing->tmod =max (12u ,ps_to_tCK (15000 , freq)); + pctl_timing->trstl =ns_to_tCK (100 , freq); + pctl_timing->tzqcl =max (256u ,ps_to_tCK (320000 , freq));/* tZQoper */ + pctl_timing->tmrr =0 ; + pctl_timing->tckesr = pctl_timing->tcke +1 ;/* JESD-79: tCKE + 1tCK */ + pctl_timing->tdpd =0 ;/* RK3368 TRM: "allowed values for DDR3: 0" */ + + +/* +* The controller can represent tFAW as 4x, 5x or 6x tRRD only. +* We want to use the smallest multiplier that satisfies the tFAW +* requirements of the given speed-bin. If necessary, we stretch out +* tRRD to allow us to operate on a 6x multiplier for tFAW. +*/ + tfaw_as_ps =40000 ;/* 40ns: tFAW for DDR3-1600K, 2KB page-size */ +if (tCK_to_ps (pctl_timing->trrd *6 , freq) < tfaw_as_ps) { +/* If tFAW is > 6 x tRRD, we need to stretch tRRD */ + pctl_timing->trrd =ps_to_tCK (DIV_ROUND_UP (40000 ,6 ), freq); + params->tfaw_mult =TFAW_TRRD_MULT6 ; + }else if (tCK_to_ps (pctl_timing->trrd *5 , freq) < tfaw_as_ps) { + params->tfaw_mult =TFAW_TRRD_MULT6 ; + }else if (tCK_to_ps (pctl_timing->trrd *4 , freq) < tfaw_as_ps) { + params->tfaw_mult =TFAW_TRRD_MULT5 ; + }else { + params->tfaw_mult =TFAW_TRRD_MULT4 ; + } + +return 0 ; +} + +static void pctl_cfg (struct rk3368_ddr_pctl *pctl, +struct rk3368_sdram_params *params, +struct rk3368_grf *grf) +{ +/* Configure PCTL timing registers */ + params->pctl_timing.trefi |=BIT (31 );/* see PCTL_TREFI */ +copy_to_reg (&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u, +sizeof (params->pctl_timing)); +writel (params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3); + +/* Set up ODT write selector and ODT write length */ +writel ((RANK0_ODT_WRITE_SEL |RANK1_ODT_WRITE_SEL ), &pctl->dfiodtcfg); +writel (7 <<ODT_LEN_BL8_W_SHIFT , &pctl->dfiodtcfg1); + +/* Set up the CL/CWL-dependent timings of DFI */ +writel ((params->pctl_timing.tcl -1 ) /2 -1 , &pctl->dfitrddataen); +writel ((params->pctl_timing.tcwl -1 ) /2 -1 , &pctl->dfitphywrlat); + +/* DDR3 */ +writel (params->tfaw_mult |DDR3_EN |DDR2_DDR3_BL_8 , &pctl->mcfg); +writel (0x001c0004 , &grf->ddrc0_con0); + +setbits_le32 (&pctl->scfg,HW_LOW_POWER_EN ); +} + +static int ddrphy_data_training (struct rk3368_ddr_pctl *pctl, +struct rk3368_ddrphy *ddrphy) +{ +const u32 trefi =readl (&pctl->trefi); +const ulong timeout_ms =500 ; +ulong tmp; + +/* disable auto-refresh */ +writel (0 |BIT (31 ), &pctl->trefi); + +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x20 ); +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x21 ); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: did not complete within %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while ((readl (&ddrphy->reg[0xff ]) &0xf ) !=0xf ); + +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,PREA_CMD ); +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x20 ); +/* resume auto-refresh */ +writel (trefi |BIT (31 ), &pctl->trefi); + +return 0 ; +} + +static int sdram_col_row_detect (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_sdram_params *params =dev_get_platdata (dev); +struct rk3368_ddr_pctl *pctl = priv->pctl; +struct rk3368_msch *msch = priv->msch; +const u32 test_pattern =0x5aa5f00f ; +int row, col; +uintptr_t addr; + +move_to_config_state (pctl); +writel (6 , &msch->ddrconf); +move_to_access_state (pctl); + +/* Detect col */ +for (col =11 ; col >=9 ; col--) { +writel (0 ,CONFIG_SYS_SDRAM_BASE ); + addr =CONFIG_SYS_SDRAM_BASE + + (1 << (col + params->chan.bw -1 )); +writel (test_pattern, addr); +if ((readl (addr) == test_pattern) && + (readl (CONFIG_SYS_SDRAM_BASE ) ==0 )) +break ; + } + +if (col ==8 ) { +error ("%s: col detect error\n" , __func__); +return -EINVAL ; + } + +move_to_config_state (pctl); +writel (15 , &msch->ddrconf); +move_to_access_state (pctl); + +/* Detect row*/ +for (row =16 ; row >=12 ; row--) { +writel (0 ,CONFIG_SYS_SDRAM_BASE ); + addr =CONFIG_SYS_SDRAM_BASE + (1 << (row +15 -1 )); +writel (test_pattern, addr); +if ((readl (addr) == test_pattern) && + (readl (CONFIG_SYS_SDRAM_BASE ) ==0 )) +break ; + } + +if (row ==11 ) { +error ("%s: row detect error\n" , __func__); +return -EINVAL ; + } + +/* Record results */ +debug ("%s: col %d, row %d\n" , __func__, col, row); + params->chan.col = col; + params->chan.cs0_row = row; + params->chan.cs1_row = row; + params->chan.row_3_4 =0 ; + +return 0 ; +} + +static int msch_niu_config (struct rk3368_msch *msch, +struct rk3368_sdram_params *params) +{ +int i; +const u8 cols = params->chan.col - ((params->chan.bw ==2 ) ?0 :1 ); +const u8 rows = params->chan.cs0_row; + +/* +* The DDR address-translation table always assumes a 32bit +* bus and the comparison below takes care of adjusting for +* a 16bit bus (i.e. one column-address is consumed). +*/ +const struct { +u8 rows; +u8 columns; +u8 type; + } ddrconf_table[] = { +/* +* C-B-R-D patterns are first. For these we require an +* exact match for the columns and rows (as there's +* one entry per possible configuration). +*/ + [0 ] = { .rows =13 , .columns =10 , .type =DMC_MSCH_CBRD }, + [1 ] = { .rows =14 , .columns =10 , .type =DMC_MSCH_CBRD }, + [2 ] = { .rows =15 , .columns =10 , .type =DMC_MSCH_CBRD }, + [3 ] = { .rows =16 , .columns =10 , .type =DMC_MSCH_CBRD }, + [4 ] = { .rows =14 , .columns =11 , .type =DMC_MSCH_CBRD }, + [5 ] = { .rows =15 , .columns =11 , .type =DMC_MSCH_CBRD }, + [6 ] = { .rows =16 , .columns =11 , .type =DMC_MSCH_CBRD }, + [7 ] = { .rows =13 , .columns =9 , .type =DMC_MSCH_CBRD }, + [8 ] = { .rows =14 , .columns =9 , .type =DMC_MSCH_CBRD }, + [9 ] = { .rows =15 , .columns =9 , .type =DMC_MSCH_CBRD }, + [10 ] = { .rows =16 , .columns =9 , .type =DMC_MSCH_CBRD }, +/* +* 11 through 13 are C-R-B-D patterns. These are +* matched for an exact number of columns and to +* ensure that the hardware uses at least as many rows +* as the pattern requires (i.e. we make sure that +* there's no gaps up until we hit the device/chip-select; +* however, these patterns can accept up to 16 rows, +* as the row-address continues right after the CS +* switching) +*/ + [11 ] = { .rows =15 , .columns =10 , .type =DMC_MSCH_CRBD }, + [12 ] = { .rows =14 , .columns =11 , .type =DMC_MSCH_CRBD }, + [13 ] = { .rows =13 , .columns =10 , .type =DMC_MSCH_CRBD }, +/* +* 14 and 15 are catch-all variants using a C-B-D-R +* scheme (i.e. alternating the chip-select every time +* C-B overflows) and stuffing the remaining C-bits +* into the top. Matching needs to make sure that the +* number of columns is either an exact match (i.e. we +* can use less the the maximum number of rows) -or- +* that the columns exceed what is given in this table +* and the rows are an exact match (in which case the +* remaining C-bits will be stuffed onto the top after +* the device/chip-select switches). +*/ + [14 ] = { .rows =16 , .columns =10 , .type =DMC_MSCH_CBDR }, + [15 ] = { .rows =16 , .columns =9 , .type =DMC_MSCH_CBDR }, + }; + +/* +* For C-B-R-D, we need an exact match (i.e. both for the number of +* columns and rows), while for C-B-D-R, only the the number of +* columns needs to match. +*/ +for (i =0 ; i <ARRAY_SIZE (ddrconf_table); i++) { +bool match = false; + +/* If this entry if for a different matcher, then skip it */ +if (ddrconf_table[i].type != params->memory_schedule) +continue ; + +/* +* Match according to the rules (exact/inexact/at-least) +* documented in the ddrconf_table above. +*/ +switch (params->memory_schedule) { +case DMC_MSCH_CBRD : + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows == rows); +break ; + +case DMC_MSCH_CRBD : + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows <= rows); +break ; + +case DMC_MSCH_CBDR : + match = (ddrconf_table[i].columns == cols) || + ((ddrconf_table[i].columns <= cols) && + (ddrconf_table[i].rows == rows)); +break ; + +default : +break ; + } + +if (match) { +debug ("%s: setting ddrconf 0x%x\n" , __func__, i); +writel (i, &msch->ddrconf); +return 0 ; + } + } + +error ("%s: ddrconf (NIU config) not found\n" , __func__); +return -EINVAL ; +} + +static void dram_all_config (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_pmu_grf *pmugrf = priv->pmugrf; +struct rk3368_sdram_params *params =dev_get_platdata (dev); +const struct rk3288_sdram_channel *info = ¶ms->chan; +u32 sys_reg =0 ; +const int chan =0 ; + + sys_reg |=DDR3 <<SYS_REG_DDRTYPE_SHIFT ; + sys_reg |=0 <<SYS_REG_NUM_CH_SHIFT ; + + sys_reg |= info->row_3_4 <<SYS_REG_ROW_3_4_SHIFT (chan); + sys_reg |=1 <<SYS_REG_CHINFO_SHIFT (chan); + sys_reg |= (info->rank -1 ) <<SYS_REG_RANK_SHIFT (chan); + sys_reg |= (info->col -9 ) <<SYS_REG_COL_SHIFT (chan); + sys_reg |= info->bk ==3 ?0 :1 <<SYS_REG_BK_SHIFT (chan); + sys_reg |= (info->cs0_row -13 ) <<SYS_REG_CS0_ROW_SHIFT (chan); + sys_reg |= (info->cs1_row -13 ) <<SYS_REG_CS1_ROW_SHIFT (chan); + sys_reg |= (2 >> info->bw) <<SYS_REG_BW_SHIFT (chan); + sys_reg |= (2 >> info->dbw) <<SYS_REG_DBW_SHIFT (chan); + +writel (sys_reg, &pmugrf->os_reg[2 ]); +} + +static int setup_sdram (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_sdram_params *params =dev_get_platdata (dev); + +struct rk3368_ddr_pctl *pctl = priv->pctl; +struct rk3368_ddrphy *ddrphy = priv->phy; +struct rk3368_cru *cru = priv->cru; +struct rk3368_grf *grf = priv->grf; +struct rk3368_msch *msch = priv->msch; + +int ret; + +/* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */ + ret =clk_set_rate (&priv->ddr_clk,2 * params->ddr_freq); +if (ret <0 ) { +debug ("%s: could not set DDR clock: %d\n" , __func__, ret); +return ret; + } + +/* Update the read-latency for the RK3368 */ +writel (0x32 , &msch->readlatency); + +/* Initialise the DDR PCTL and DDR PHY */ +ddrctl_reset (cru); +ddrphy_reset (ddrphy); +ddrphy_config_delays (ddrphy, params->ddr_freq); +dfi_cfg (pctl); +/* Configure relative system information of grf_ddrc0_con0 register */ +ddr_set_ddr3_mode (grf, true); +ddr_set_noc_spr_err_stall (grf, true); +/* Calculate timings */ +pctl_calc_timings (params, params->ddr_freq); +/* Initialise the device timings in protocol controller */ +pctl_cfg (pctl, params, grf); +/* Configure AL, CL ... information of PHY registers */ +ddrphy_config (ddrphy, + params->pctl_timing.tcl, + params->pctl_timing.tal, + params->pctl_timing.tcwl); + +/* Initialize DRAM and configure with mode-register values */ + ret =memory_init (pctl, params); +if (ret) + goto error; + +move_to_config_state (pctl); +/* Perform data-training */ +ddrphy_data_training (pctl, ddrphy); +move_to_access_state (pctl); + +/* TODO(prt): could detect rank in training... */ + params->chan.rank =2 ; +/* TODO(prt): bus width is not auto-detected (yet)... */ + params->chan.bw =2 ;/* 32bit wide bus */ + params->chan.dbw = params->chan.dbw;/* 32bit wide bus */ + +/* DDR3 is always 8 bank */ + params->chan.bk =3 ; +/* Detect col and row number */ + ret =sdram_col_row_detect (dev); +if (ret) + goto error; + +/* Configure NIU DDR configuration */ + ret =msch_niu_config (msch, params); +if (ret) + goto error; + +/* set up OS_REG to communicate w/ next stage and OS */ +dram_all_config (dev); + +return 0 ; + +error: +printf ("DRAM init failed!\n" ); +hang (); +} +#endif + +static int rk3368_dmc_ofdata_to_platdata (struct udevice *dev) +{ +int ret =0 ; + +#if !CONFIG_IS_ENABLED (OF_PLATDATA ) +struct rk3368_sdram_params *plat =dev_get_platdata (dev); + + ret =regmap_init_mem (dev, &plat->map); +if (ret) +return ret; +#endif + +return ret; +} + +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +static int conv_of_platdata (struct udevice *dev) +{ +struct rk3368_sdram_params *plat =dev_get_platdata (dev); +struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat; +int ret; + + plat->ddr_freq = of_plat->rockchip_ddr_frequency; + plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin; + plat->memory_schedule = of_plat->rockchip_memory_schedule; + + ret =regmap_init_mem_platdata (dev, of_plat->reg, +ARRAY_SIZE (of_plat->reg) /2 , + &plat->map); +if (ret) +return ret; + +return 0 ; +} +#endif + +static int rk3368_dmc_probe (struct udevice *dev) +{ +#ifdef CONFIG_TPL_BUILD +struct rk3368_sdram_params *plat =dev_get_platdata (dev); +struct rk3368_ddr_pctl *pctl; +struct rk3368_ddrphy *ddrphy; +struct rk3368_cru *cru; +struct rk3368_grf *grf; +struct rk3368_msch *msch; +int ret; +struct udevice *dev_clk; +#endif +struct dram_info *priv =dev_get_priv (dev); + +#if CONFIG_IS_ENABLED (OF_PLATDATA ) + ret =conv_of_platdata (dev); +if (ret) +return ret; +#endif + + priv->pmugrf =syscon_get_first_range (ROCKCHIP_SYSCON_PMUGRF ); +debug ("%s: pmugrf=%p\n" , __func__, priv->pmugrf); + +#ifdef CONFIG_TPL_BUILD + pctl =regmap_get_range (plat->map,0 ); + ddrphy =regmap_get_range (plat->map,1 ); + msch =syscon_get_first_range (ROCKCHIP_SYSCON_MSCH ); + grf =syscon_get_first_range (ROCKCHIP_SYSCON_GRF ); + + priv->pctl = pctl; + priv->phy = ddrphy; + priv->msch = msch; + priv->grf = grf; + + ret =rockchip_get_clk (&dev_clk); +if (ret) +return ret; + priv->ddr_clk.id =CLK_DDR ; + ret =clk_request (dev_clk, &priv->ddr_clk); +if (ret) +return ret; + + cru =rockchip_get_cru (); + priv->cru = cru; +if (IS_ERR (priv->cru)) +return PTR_ERR (priv->cru); + + ret =setup_sdram (dev); +if (ret) +return ret; +#endif + + priv->info.base =0 ; + priv->info.size = +rockchip_sdram_size ((phys_addr_t)&priv->pmugrf->os_reg[2 ]); + +/* +* we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff +* is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is +* inaccessible for some IP controller. +*/ + priv->info.size =min (priv->info.size, (size_t )0xfe000000 ); + +return 0 ; +} + +static int rk3368_dmc_get_info (struct udevice *dev,struct ram_info *info) +{ +struct dram_info *priv =dev_get_priv (dev); + + *info = priv->info; +return 0 ; +} + +static struct ram_ops rk3368_dmc_ops = { + .get_info = rk3368_dmc_get_info, +}; + + +static const struct udevice_id rk3368_dmc_ids[] = { + { .compatible ="rockchip,rk3368-dmc" }, + { } +}; + +U_BOOT_DRIVER (dmc_rk3368) = { + .name ="rockchip_rk3368_dmc" , + .id =UCLASS_RAM , + .of_match = rk3368_dmc_ids, + .ops = &rk3368_dmc_ops, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size =sizeof (struct dram_info ), + .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size =sizeof (struct dram_info ), + .platdata_auto_alloc_size =sizeof (struct rk3368_sdram_params ), +};include/dt-bindings/memory/rk3368-dmc.h new file +20
-0@@ -0,0 +1,30 @@ +#ifndef DT_BINDINGS_RK3368_DMC_H +#define DT_BINDINGS_RK3368_DMC_H + +#define DMC_MSCH_CBDR 0x0 +#define DMC_MSCH_CBRD 0x1 +#define DMC_MSCH_CRBD 0x2 + +#define DDR3_800D 0 +#define DDR3_800E 1 +#define DDR3_1066E 2 +#define DDR3_1066F 3 +#define DDR3_1066G 4 +#define DDR3_1333F 5 +#define DDR3_1333G 6 +#define DDR3_1333H 7 +#define DDR3_1333J 8 +#define DDR3_1600G 9 +#define DDR3_1600H 10 +#define DDR3_1600J 11 +#define DDR3_1600K 12include/dt-bindings/memory/rk3368-dmc.h line 30
Quoted 10 lines
include/dt-bindings/memory/rk3368-dmc.h new file +10
-0+#define DDR3_1866J 13 +#define DDR3_1866K 14 +#define DDR3_1866L 15 +#define DDR3_1866M 16 +#define DDR3_2133K 17 +#define DDR3_2133L 18 +#define DDR3_2133M 19 +#define DDR3_2133N 20 + +#endif dpd;
arch/arm/include/asm/arch-rockchip/ddr_rk3368.h new file +108
-0+u32 trefi_mem_ddr3; +u32 reserved5[45 ]; +u32 dtuwactl; +u32 dturactl; +u32 dtucfg; +u32 dtuectl; +u32 dtuwd0; +u32 dtuwd1; +u32 dtuwd2; +u32 dtuwd3; +u32 dtuwdm; +u32 dturd0; +u32 dturd1; +u32 dturd2; +u32 dturd3; +u32 dtulfsrwd; +u32 dtulfsrrd; +u32 dtueaf; +u32 dfitctrldelay; +u32 dfiodtcfg; +u32 dfiodtcfg1; +u32 dfiodtrankmap; +u32 dfitphywrdata; +u32 dfitphywrlat; +u32 reserved7[2 ]; +u32 dfitrddataen; +u32 dfitphyrdlat; +u32 reserved8[2 ]; +u32 dfitphyupdtype0; +u32 dfitphyupdtype1; +u32 dfitphyupdtype2; +u32 dfitphyupdtype3; +u32 dfitctrlupdmin; +u32 dfitctrlupdmax; +u32 dfitctrlupddly; +u32 reserved9; +u32 dfiupdcfg; +u32 dfitrefmski; +u32 dfitctrlupdi; +u32 reserved10[4 ]; +u32 dfitrcfg0; +u32 dfitrstat0; +u32 dfitrwrlvlen; +u32 dfitrrdlvlen; +u32 dfitrrdlvlgateen; +u32 dfiststat0; +u32 dfistcfg0; +u32 dfistcfg1; +u32 reserved11; +u32 dfitdramclken; +u32 dfitdramclkdis; +u32 dfistcfg2; +u32 dfistparclr; +u32 dfistparlog; +u32 reserved12[3 ]; +u32 dfilpcfg0; +u32 reserved13[3 ]; +u32 dfitrwrlvlresp0; +u32 dfitrwrlvlresp1; +u32 dfitrwrlvlresp2; +u32 dfitrrdlvlresp0; +u32 dfitrrdlvlresp1; +u32 dfitrrdlvlresp2; +u32 dfitrwrlvldelay0; +u32 dfitrwrlvldelay1; +u32 dfitrwrlvldelay2; +u32 dfitrrdlvldelay0; +u32 dfitrrdlvldelay1; +u32 dfitrrdlvldelay2; +u32 dfitrrdlvlgatedelay0; +u32 dfitrrdlvlgatedelay1; +u32 dfitrrdlvlgatedelay2; +u32 dfitrcmd; +u32 reserved14[46 ]; +u32 ipvr; + u32 iptr; +}; +check_member (rk3368_ddr_pctl, iptr,0x03fc ); + +struct rk3368_ddrphy { +u32 reg[0x100 ]; +}; +check_member (rk3368_ddrphy, reg[0xff ],0x03fc ); + +struct rk3368_msch { +u32 coreid; +u32 revisionid; +u32 ddrconf; +u32 ddrtiming; +u32 ddrmode; +u32 readlatency; +u32 reserved1[8 ]; +u32 activate; +u32 devtodev; +}; +check_member (rk3368_msch, devtodev,0x003c ); + +/* GRF_SOC_CON0 */ +enum { +NOC_RSP_ERR_STALL =BIT (9 ), +MOBILE_DDR_SEL =BIT (4 ), +DDR0_16BIT_EN =BIT (3 ), +MSCH0_MAINDDR3_DDR3 =BIT (2 ), +MSCH0_MAINPARTIALPOP =BIT (1 ), +UPCTL_C_ACTIVE =BIT (0 ), +}; + +#endif arch/arm/include/asm/arch-rockchip/grf_rk3368.h +3
-0@@ -76,8 +76,11 @@ struct rk3368_grf {u32 soc_con15;u32 soc_con16;u32 soc_con17; +u32 reserved5[0x6e ]; +u32 ddrc0_con0; };check_member (rk3368_grf, soc_con17,0x444 ); +check_member (rk3368_grf, ddrc0_con0,0x600 );struct rk3368_pmu_grf {u32 gpio0a_iomux;arch/arm/mach-rockchip/rk3368/Makefile +0
-0arch/arm/mach-rockchip/rk3368/Makefile line 8
Quoted 5 lines
arch/arm/mach-rockchip/rk3368/Makefile +0
-1@@ -5,5 +5,4 @@ # obj-y += clk_rk3368.o obj-y += rk3368.o -obj-y += sdram_rk3368.o obj-y += syscon_rk3368.oThe current PX5 EVB and Sheep board(they have no spl now) depend on this
sdram_rk3368.c
to get the sdram capacity, and so is the geekbox board.
These boards will be broken when this driver removed.
We got the failed log like this on PX5 EVB:DRAM: DRAM init failed: -19
initcall sequence 000000002d=378208 failed at call 02023f0 (err=-19) ### ERROR ### Please RESET the board ###Quoted 1,194 lines
arch/arm/mach-rockchip/rk3368/sdram_rk3368.c deleted +0
-60@@ -1,60 +0,0 @@ -/* -* (C) Copyright 2016 Rockchip Electronics Co., Ltd. -* -* SPDX-License-Identifier: GPL-2.0 -*/ - -#include <common.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/sdram_common.h> - -DECLARE_GLOBAL_DATA_PTR ; -struct dram_info { -struct ram_info info; -struct rk3368_pmu_grf *pmugrf; -}; - -static int rk3368_dmc_probe (struct udevice *dev) -{ -struct dram_info *priv =dev_get_priv (dev); - - priv->pmugrf =syscon_get_first_range (ROCKCHIP_SYSCON_PMUGRF ); -debug ("%s: grf=%p\n" , __func__, priv->pmugrf); - priv->info.base =CONFIG_SYS_SDRAM_BASE ; - priv->info.size =rockchip_sdram_size ( - (phys_addr_t)&priv->pmugrf->os_reg[2 ]); - -return 0 ; -} - -static int rk3368_dmc_get_info (struct udevice *dev,struct ram_info *info) -{ -struct dram_info *priv =dev_get_priv (dev); - - *info = priv->info; - -return 0 ; -} - -static struct ram_ops rk3368_dmc_ops = { - .get_info = rk3368_dmc_get_info, -}; - - -static const struct udevice_id rk3368_dmc_ids[] = { - { .compatible ="rockchip,rk3368-dmc" }, - { } -}; - -U_BOOT_DRIVER (dmc_rk3368) = { - .name ="rockchip_rk3368_dmc" , - .id =UCLASS_RAM , - .of_match = rk3368_dmc_ids, - .ops = &rk3368_dmc_ops, - .probe = rk3368_dmc_probe, - .priv_auto_alloc_size =sizeof (struct dram_info ), -};doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt new file +67
-0@@ -0,0 +1,67 @@ +RK3368 dynamic memory controller driver +======================================= + +The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation +during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on +the following key configuration data: + (a) a target-frequency (i.e. operating point) for the memory operation + (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware + (c) a memory-schedule (i.e. mapping from physical addresses to the address + pins of the memory bus) + +Required properties +------------------- + +- compatible: "rockchip,rk3368-dmc" +- reg + protocol controller (PCTL) address and PHY controller (DDRPHY) address +- rockchip,ddr-speed-bin + the DDR3 device's speed-bin (as specified according to JESD-79) + DDR3_800D (5-5-5) + DDR3_800E (6-6-6) + DDR3_1066E (6-6-6) + DDR3_1066F (7-7-7) + DDR3_1066G (8-8-8) + DDR3_1333F (7-7-7) + DDR3_1333G (8-8-8) + DDR3_1333H (9-9-9) + DDR3_1333J (10-10-10) + DDR3_1600G (8-8-8) + DDR3_1600H (9-9-9) + DDR3_1600J (10-10-10) + DDR3_1600K (11-11-11) + DDR3_1866J (10-10-10) + DDR3_1866K (11-11-11) + DDR3_1866L (12-12-12) + DDR3_1866M (13-13-13) + DDR3_2133K (11-11-11) + DDR3_2133L (12-12-12) + DDR3_2133M (13-13-13) + DDR3_2133N (14-14-14) +- rockchip,ddr-frequency: + target DDR clock frequency in Hz (not all frequencies may be supported, + as there's some cooperation from the clock-driver required) +- rockchip,memory-schedule: + controls the decoding of physical addresses to DRAM addressing (i.e. how + the physical address maps onto the address pins/chip-select of the device) + DMC_MSCH_CBDR: column -> bank -> device -> row + DMC_MSCH_CBRD: column -> band -> row -> device + DMC_MSCH_CRBD: column -> row -> band -> device + +Example (for DDR3-1600K and 800MHz) +----------------------------------- + + #include <dt-bindings/memory/rk3368-dmc.h> + + dmc: dmc at ff610000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3368-dmc"; + reg = <0 0xff610000 0 0x400 + 0 0xff620000 0 0x400>; + }; + + &dmc { + rockchip,ddr-speed-bin = <DDR3_1600K>; + rockchip,ddr-frequency = <800000000>; + rockchip,memory-schedule = <DMC_MSCH_CBRD>; + };drivers/ram/Makefile +2
-0@@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o + +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/drivers/ram/rockchip/Makefile new file +7
-0@@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.odrivers/ram/rockchip/dmc-rk3368.c new file +990
-0@@ -0,0 +1,990 @@ +/* +* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dt-bindings/memory/rk3368-dmc.h> +#include <dt-structs.h> +#include <ram.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3368.h> +#include <asm/arch/grf_rk3368.h> +#include <asm/arch/ddr_rk3368.h> +#include <asm/arch/sdram.h> +#include <asm/arch/sdram_common.h> + +DECLARE_GLOBAL_DATA_PTR ; + +struct dram_info { +struct ram_info info; +struct clk ddr_clk; +struct rk3368_cru *cru; +struct rk3368_grf *grf; +struct rk3368_ddr_pctl *pctl; +struct rk3368_ddrphy *phy; +struct rk3368_pmu_grf *pmugrf; +struct rk3368_msch *msch; +}; + +struct rk3368_sdram_params { +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +struct dtd_rockchip_rk3368_dmc of_plat; +#endif +struct rk3288_sdram_pctl_timing pctl_timing; +u32 trefi_mem_ddr3; +struct rk3288_sdram_channel chan; +struct regmap *map; +u32 ddr_freq; +u32 memory_schedule; +u32 ddr_speed_bin; +u32 tfaw_mult; +}; + +/* PTCL bits */ +enum { +/* PCTL_DFISTCFG0 */ +DFI_INIT_START =BIT (0 ), +DFI_DATA_BYTE_DISABLE_EN =BIT (2 ), + +/* PCTL_DFISTCFG1 */ +DFI_DRAM_CLK_SR_EN =BIT (0 ), +DFI_DRAM_CLK_DPD_EN =BIT (1 ), +ODT_LEN_BL8_W_SHIFT =16 , + +/* PCTL_DFISTCFG2 */ +DFI_PARITY_INTR_EN =BIT (0 ), +DFI_PARITY_EN =BIT (1 ), + +/* PCTL_DFILPCFG0 */ +TLP_RESP_TIME_SHIFT =16 , +LP_SR_EN =BIT (8 ), +LP_PD_EN =BIT (0 ), + +/* PCTL_DFIODTCFG */ +RANK0_ODT_WRITE_SEL =BIT (3 ), +RANK1_ODT_WRITE_SEL =BIT (11 ), + +/* PCTL_SCFG */ +HW_LOW_POWER_EN =BIT (0 ), + +/* PCTL_MCMD */ +START_CMD =BIT (31 ), +MCMD_RANK0 =BIT (20 ), +MCMD_RANK1 =BIT (21 ), +DESELECT_CMD =0 , +PREA_CMD , +REF_CMD , +MRS_CMD , +ZQCS_CMD , +ZQCL_CMD , +RSTL_CMD , +MRR_CMD =8 , +DPDE_CMD , + +/* PCTL_POWCTL */ +POWER_UP_START =BIT (0 ), + +/* PCTL_POWSTAT */ +POWER_UP_DONE =BIT (0 ), + +/* PCTL_SCTL */ +INIT_STATE =0 , +CFG_STATE , +GO_STATE , +SLEEP_STATE , +WAKEUP_STATE , + +/* PCTL_STAT */ +LP_TRIG_SHIFT =4 , +LP_TRIG_MASK =7 , +PCTL_STAT_MSK =7 , +INIT_MEM =0 , +CONFIG , +CONFIG_REQ , +ACCESS , +ACCESS_REQ , +LOW_POWER , +LOW_POWER_ENTRY_REQ , +LOW_POWER_EXIT_REQ , + +/* PCTL_MCFG */ +DDR2_DDR3_BL_8 =BIT (0 ), +DDR3_EN =BIT (5 ), +TFAW_TRRD_MULT4 = (0 <<18 ), +TFAW_TRRD_MULT5 = (1 <<18 ), +TFAW_TRRD_MULT6 = (2 <<18 ), +}; + +#define DDR3_MR0_WR (n) \ + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9)) +#define DDR3_MR0_CL (n) \ + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2)) +#define DDR3_MR0_BL8 \ + (0 << 0) +#define DDR3_MR0_DLL_RESET \ + (1 << 8) +#define DDR3_MR1_RTT120OHM \ + ((0 << 9) | (1 << 6) | (0 << 2)) +#define DDR3_MR2_TWL (n) \ + (((n - 5) & 0x7) << 3) + + +#ifdef CONFIG_TPL_BUILD + +static void ddr_set_noc_spr_err_stall (struct rk3368_grf *grf,bool enable) +{ +if (enable) +rk_setreg (&grf->ddrc0_con0,NOC_RSP_ERR_STALL ); +else +rk_clrreg (&grf->ddrc0_con0,NOC_RSP_ERR_STALL ); +} + +static void ddr_set_ddr3_mode (struct rk3368_grf *grf,bool ddr3_mode) +{ +if (ddr3_mode) +rk_setreg (&grf->ddrc0_con0,MSCH0_MAINDDR3_DDR3 ); +else +rk_clrreg (&grf->ddrc0_con0,MSCH0_MAINDDR3_DDR3 ); +} + +static void ddrphy_config (struct rk3368_ddrphy *phy, +u32 tcl,u32 tal,u32 tcwl) +{ +int i; + +/* Set to DDR3 mode */ +clrsetbits_le32 (&phy->reg[1 ],0x3 ,0x0 ); + +/* DDRPHY_REGB: CL, AL */ +clrsetbits_le32 (&phy->reg[0xb ],0xff , tcl <<4 | tal); +/* DDRPHY_REGC: CWL */ +clrsetbits_le32 (&phy->reg[0xc ],0x0f , tcwl); + +/* Update drive-strength */ +writel (0xcc , &phy->reg[0x11 ]); +writel (0xaa , &phy->reg[0x16 ]); +/* +* Update NRCOMP/PRCOMP for all 4 channels (for details of all +* affected registers refer to the documentation of DDRPHY_REG20 +* and DDRPHY_REG21 in the RK3368 TRM. +*/ +for (i =0 ; i <4 ; ++i) { +writel (0xcc , &phy->reg[0x20 + i *0x10 ]); +writel (0x44 , &phy->reg[0x21 + i *0x10 ]); + } + +/* Enable write-leveling calibration bypass */ +setbits_le32 (&phy->reg[2 ],BIT (3 )); +} + +static void copy_to_reg (u32 *dest,const u32 *src,u32 n) +{ +int i; + +for (i =0 ; i < n /sizeof (u32); i++) +writel (*src++, dest++); +} + +static void send_command (struct rk3368_ddr_pctl *pctl,u32 rank,u32 cmd) +{ +u32 mcmd =START_CMD | cmd | rank; + +debug ("%s: writing %x to MCMD\n" , __func__, mcmd); +writel (mcmd, &pctl->mcmd); +while (readl (&pctl->mcmd) &START_CMD ) +/* spin */ ; +} + +static void send_mrs (struct rk3368_ddr_pctl *pctl, +u32 rank,u32 mr_num,u32 mr_data) +{ +u32 mcmd =START_CMD |MRS_CMD | rank | (mr_num <<17 ) | (mr_data <<4 ); + +debug ("%s: writing %x to MCMD\n" , __func__, mcmd); +writel (mcmd, &pctl->mcmd); +while (readl (&pctl->mcmd) &START_CMD ) +/* spin */ ; +} + +static int memory_init (struct rk3368_ddr_pctl *pctl, +struct rk3368_sdram_params *params) +{ +u32 mr[4 ]; +const ulong timeout_ms =500 ; +ulong tmp; + +/* +* Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and +* wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register +* of PCTL. +*/ +writel (POWER_UP_START , &pctl->powctl); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: POWER_UP_START did not complete in %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while (!(readl (&pctl->powstat) &POWER_UP_DONE )); + +/* Configure MR0 through MR3 */ + mr[0 ] =DDR3_MR0_WR (params->pctl_timing.twr) | +DDR3_MR0_CL (params->pctl_timing.tcl) | +DDR3_MR0_DLL_RESET ; + mr[1 ] =DDR3_MR1_RTT120OHM ; + mr[2 ] =DDR3_MR2_TWL (params->pctl_timing.tcwl); + mr[3 ] =0 ; + +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.2 Initialization (DDR3 Initialization Sequence)" +*/ +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,DESELECT_CMD ); +udelay (1 ); +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,PREA_CMD ); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,2 , mr[2 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,3 , mr[3 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,1 , mr[1 ]); +send_mrs (pctl,MCMD_RANK0 |MCMD_RANK1 ,0 , mr[0 ]); +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,ZQCL_CMD ); + +return 0 ; +} + +static void move_to_config_state (struct rk3368_ddr_pctl *pctl) +{ +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.1 State transition of PCTL (Moving to Config State)" +*/ +u32 state =readl (&pctl->stat) &PCTL_STAT_MSK ; + +switch (state) { +case LOW_POWER : +writel (WAKEUP_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=ACCESS ) +/* spin */ ; + +/* fall-through */ +case ACCESS : +case INIT_MEM : +writel (CFG_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=CONFIG ) +/* spin */ ; +break ; + +case CONFIG : +return ; + +default : +break ; + } +} + +static void move_to_access_state (struct rk3368_ddr_pctl *pctl) +{ +/* +* Also see RK3368 Technical Reference Manual: +* "16.6.1 State transition of PCTL (Moving to Access State)" +*/ +u32 state =readl (&pctl->stat) &PCTL_STAT_MSK ; + +switch (state) { +case LOW_POWER : +if (((readl (&pctl->stat) >>LP_TRIG_SHIFT ) & +LP_TRIG_MASK ) ==1 ) +return ; + +writel (WAKEUP_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=ACCESS ) +/* spin */ ; + +/* fall-through */ +case INIT_MEM : +writel (CFG_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) !=CONFIG ) +/* spin */ ; + +/* fall-through */ +case CONFIG : +writel (GO_STATE , &pctl->sctl); +while ((readl (&pctl->stat) &PCTL_STAT_MSK ) ==CONFIG ) +/* spin */ ; +break ; + +case ACCESS : +return ; + +default : +break ; + } +} + +static void ddrctl_reset (struct rk3368_cru *cru) +{ +const u32 ctl_reset =BIT (3 ) |BIT (2 ); +const u32 phy_reset =BIT (1 ) |BIT (0 ); + +rk_setreg (&cru->softrst_con[10 ], ctl_reset | phy_reset); +udelay (1 ); +rk_clrreg (&cru->softrst_con[10 ], ctl_reset | phy_reset); +} + +static void ddrphy_reset (struct rk3368_ddrphy *ddrphy) +{ +clrbits_le32 (&ddrphy->reg[0 ],BIT (3 ) |BIT (2 )); +udelay (1 ); +setbits_le32 (&ddrphy->reg[0 ],BIT (3 ) |BIT (2 )); +} + +static void ddrphy_config_delays (struct rk3368_ddrphy *ddrphy,u32 freq) +{ +u32 dqs_dll_delay; + +setbits_le32 (&ddrphy->reg[0x13 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x14 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x26 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x27 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x36 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x37 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x46 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x47 ],BIT (3 )); + +setbits_le32 (&ddrphy->reg[0x56 ],BIT (4 )); +clrbits_le32 (&ddrphy->reg[0x57 ],BIT (3 )); + +if (freq <=400000000 ) +setbits_le32 (&ddrphy->reg[0xa4 ],0x1f ); +else +clrbits_le32 (&ddrphy->reg[0xa4 ],0x1f ); + +if (freq <681000000 ) + dqs_dll_delay =3 ;/* 67.5 degree delay */ +else + dqs_dll_delay =2 ;/* 45 degree delay */ + +writel (dqs_dll_delay, &ddrphy->reg[0x28 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x38 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x48 ]); +writel (dqs_dll_delay, &ddrphy->reg[0x58 ]); +} + +static int dfi_cfg (struct rk3368_ddr_pctl *pctl) +{ +const ulong timeout_ms =200 ; +ulong tmp; + +writel (DFI_DATA_BYTE_DISABLE_EN , &pctl->dfistcfg0); + +writel (DFI_DRAM_CLK_SR_EN |DFI_DRAM_CLK_DPD_EN , + &pctl->dfistcfg1); +writel (DFI_PARITY_INTR_EN |DFI_PARITY_EN , &pctl->dfistcfg2); +writel (7 <<TLP_RESP_TIME_SHIFT |LP_SR_EN |LP_PD_EN , + &pctl->dfilpcfg0); + +writel (1 , &pctl->dfitphyupdtype0); + +writel (0x1f , &pctl->dfitphyrdlat); +writel (0 , &pctl->dfitphywrdata); +writel (0 , &pctl->dfiupdcfg);/* phyupd and ctrlupd disabled */ + +setbits_le32 (&pctl->dfistcfg0,DFI_INIT_START ); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: DFI init did not complete within %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while ((readl (&pctl->dfiststat0) &1 ) ==0 ); + +return 0 ; +} + +static inline u32 ps_to_tCK (const u32 ps,const ulong freq) +{ +const ulong MHz =1000000 ; +return DIV_ROUND_UP (ps * freq,1000000 * MHz); +} + +static inline u32 ns_to_tCK (const u32 ns,const ulong freq) +{ +return ps_to_tCK (ns *1000 , freq); +} + +static inline u32 tCK_to_ps (const ulong tCK,const ulong freq) +{ +const ulong MHz =1000000 ; +return DIV_ROUND_UP (tCK *1000000 * MHz, freq); +} + +static int pctl_calc_timings (struct rk3368_sdram_params *params, +ulong freq) +{ +struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing; +const ulong MHz =1000000 ; +u32 tccd; +u32 tfaw_as_ps; + +if (params->ddr_speed_bin !=DDR3_1600K ) { +error ("%s: unimplemented DDR3 speed bin %d\n" , + __func__, params->ddr_speed_bin); +return -1 ; + } + +/* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */ + pctl_timing->togcnt1u =DIV_ROUND_UP (freq,2 * MHz); + pctl_timing->togcnt100n =DIV_ROUND_UP (freq /10 ,2 * MHz); + + pctl_timing->tinit =200 ;/* 200 usec */ + pctl_timing->trsth =500 ;/* 500 usec */ + pctl_timing->trefi =78 ;/* 7.8usec = 78 * 100ns */ + params->trefi_mem_ddr3 =ns_to_tCK (pctl_timing->trefi *100 , freq); + +if (freq <= (400 * MHz)) { + pctl_timing->tcl =6 ; + pctl_timing->tcwl =10 ; + }else if (freq <= (533 * MHz)) { + pctl_timing->tcl =8 ; + pctl_timing->tcwl =6 ; + }else if (freq <= (666 * MHz)) { + pctl_timing->tcl =10 ; + pctl_timing->tcwl =7 ; + }else { + pctl_timing->tcl =11 ; + pctl_timing->tcwl =8 ; + } + + pctl_timing->tmrd =4 ;/* 4 tCK (all speed bins) */ + pctl_timing->trfc =ns_to_tCK (350 , freq);/* tRFC: 350 (max) @ 8GBit */ + pctl_timing->trp =max (4u ,ps_to_tCK (13750 , freq)); +/* +* JESD-79: +* READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL +*/ + tccd =4 ; + pctl_timing->trtw = pctl_timing->tcl + tccd/2 +2 - pctl_timing->tcwl; + pctl_timing->tal =0 ; + pctl_timing->tras =ps_to_tCK (35000 , freq); + pctl_timing->trc =ps_to_tCK (48750 , freq); + pctl_timing->trcd =ps_to_tCK (13750 , freq); + pctl_timing->trrd =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->trtp =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->twr =ps_to_tCK (15000 , freq); +/* The DDR3 mode-register does only support even values for tWR > 8. */ +if (pctl_timing->twr >8 ) + pctl_timing->twr = (pctl_timing->twr +1 ) & ~1 ; + pctl_timing->twtr =max (4u ,ps_to_tCK (7500 , freq)); + pctl_timing->texsr =512 ;/* tEXSR(max) is tDLLLK */ + pctl_timing->txp =max (3u ,ps_to_tCK (6000 , freq)); + pctl_timing->txpdll =max (10u ,ps_to_tCK (24000 , freq)); + pctl_timing->tzqcs =max (64u ,ps_to_tCK (80000 , freq)); + pctl_timing->tzqcsi =10000 ;/* as used by Rockchip */ + pctl_timing->tdqs =1 ;/* fixed for DDR3 */ + pctl_timing->tcksre =max (5u ,ps_to_tCK (10000 , freq)); + pctl_timing->tcksrx =max (5u ,ps_to_tCK (10000 , freq)); + pctl_timing->tcke =max (3u ,ps_to_tCK (5000 , freq)); + pctl_timing->tmod =max (12u ,ps_to_tCK (15000 , freq)); + pctl_timing->trstl =ns_to_tCK (100 , freq); + pctl_timing->tzqcl =max (256u ,ps_to_tCK (320000 , freq));/* tZQoper */ + pctl_timing->tmrr =0 ; + pctl_timing->tckesr = pctl_timing->tcke +1 ;/* JESD-79: tCKE + 1tCK */ + pctl_timing->tdpd =0 ;/* RK3368 TRM: "allowed values for DDR3: 0" */ + + +/* +* The controller can represent tFAW as 4x, 5x or 6x tRRD only. +* We want to use the smallest multiplier that satisfies the tFAW +* requirements of the given speed-bin. If necessary, we stretch out +* tRRD to allow us to operate on a 6x multiplier for tFAW. +*/ + tfaw_as_ps =40000 ;/* 40ns: tFAW for DDR3-1600K, 2KB page-size */ +if (tCK_to_ps (pctl_timing->trrd *6 , freq) < tfaw_as_ps) { +/* If tFAW is > 6 x tRRD, we need to stretch tRRD */ + pctl_timing->trrd =ps_to_tCK (DIV_ROUND_UP (40000 ,6 ), freq); + params->tfaw_mult =TFAW_TRRD_MULT6 ; + }else if (tCK_to_ps (pctl_timing->trrd *5 , freq) < tfaw_as_ps) { + params->tfaw_mult =TFAW_TRRD_MULT6 ; + }else if (tCK_to_ps (pctl_timing->trrd *4 , freq) < tfaw_as_ps) { + params->tfaw_mult =TFAW_TRRD_MULT5 ; + }else { + params->tfaw_mult =TFAW_TRRD_MULT4 ; + } + +return 0 ; +} + +static void pctl_cfg (struct rk3368_ddr_pctl *pctl, +struct rk3368_sdram_params *params, +struct rk3368_grf *grf) +{ +/* Configure PCTL timing registers */ + params->pctl_timing.trefi |=BIT (31 );/* see PCTL_TREFI */ +copy_to_reg (&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u, +sizeof (params->pctl_timing)); +writel (params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3); + +/* Set up ODT write selector and ODT write length */ +writel ((RANK0_ODT_WRITE_SEL |RANK1_ODT_WRITE_SEL ), &pctl->dfiodtcfg); +writel (7 <<ODT_LEN_BL8_W_SHIFT , &pctl->dfiodtcfg1); + +/* Set up the CL/CWL-dependent timings of DFI */ +writel ((params->pctl_timing.tcl -1 ) /2 -1 , &pctl->dfitrddataen); +writel ((params->pctl_timing.tcwl -1 ) /2 -1 , &pctl->dfitphywrlat); + +/* DDR3 */ +writel (params->tfaw_mult |DDR3_EN |DDR2_DDR3_BL_8 , &pctl->mcfg); +writel (0x001c0004 , &grf->ddrc0_con0); + +setbits_le32 (&pctl->scfg,HW_LOW_POWER_EN ); +} + +static int ddrphy_data_training (struct rk3368_ddr_pctl *pctl, +struct rk3368_ddrphy *ddrphy) +{ +const u32 trefi =readl (&pctl->trefi); +const ulong timeout_ms =500 ; +ulong tmp; + +/* disable auto-refresh */ +writel (0 |BIT (31 ), &pctl->trefi); + +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x20 ); +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x21 ); + + tmp =get_timer (0 ); +do { +if (get_timer (tmp) > timeout_ms) { +error ("%s: did not complete within %ld ms\n" , + __func__, timeout_ms); +return -ETIME ; + } + }while ((readl (&ddrphy->reg[0xff ]) &0xf ) !=0xf ); + +send_command (pctl,MCMD_RANK0 |MCMD_RANK1 ,PREA_CMD ); +clrsetbits_le32 (&ddrphy->reg[2 ],0x33 ,0x20 ); +/* resume auto-refresh */ +writel (trefi |BIT (31 ), &pctl->trefi); + +return 0 ; +} + +static int sdram_col_row_detect (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_sdram_params *params =dev_get_platdata (dev); +struct rk3368_ddr_pctl *pctl = priv->pctl; +struct rk3368_msch *msch = priv->msch; +const u32 test_pattern =0x5aa5f00f ; +int row, col; +uintptr_t addr; + +move_to_config_state (pctl); +writel (6 , &msch->ddrconf); +move_to_access_state (pctl); + +/* Detect col */ +for (col =11 ; col >=9 ; col--) { +writel (0 ,CONFIG_SYS_SDRAM_BASE ); + addr =CONFIG_SYS_SDRAM_BASE + + (1 << (col + params->chan.bw -1 )); +writel (test_pattern, addr); +if ((readl (addr) == test_pattern) && + (readl (CONFIG_SYS_SDRAM_BASE ) ==0 )) +break ; + } + +if (col ==8 ) { +error ("%s: col detect error\n" , __func__); +return -EINVAL ; + } + +move_to_config_state (pctl); +writel (15 , &msch->ddrconf); +move_to_access_state (pctl); + +/* Detect row*/ +for (row =16 ; row >=12 ; row--) { +writel (0 ,CONFIG_SYS_SDRAM_BASE ); + addr =CONFIG_SYS_SDRAM_BASE + (1 << (row +15 -1 )); +writel (test_pattern, addr); +if ((readl (addr) == test_pattern) && + (readl (CONFIG_SYS_SDRAM_BASE ) ==0 )) +break ; + } + +if (row ==11 ) { +error ("%s: row detect error\n" , __func__); +return -EINVAL ; + } + +/* Record results */ +debug ("%s: col %d, row %d\n" , __func__, col, row); + params->chan.col = col; + params->chan.cs0_row = row; + params->chan.cs1_row = row; + params->chan.row_3_4 =0 ; + +return 0 ; +} + +static int msch_niu_config (struct rk3368_msch *msch, +struct rk3368_sdram_params *params) +{ +int i; +const u8 cols = params->chan.col - ((params->chan.bw ==2 ) ?0 :1 ); +const u8 rows = params->chan.cs0_row; + +/* +* The DDR address-translation table always assumes a 32bit +* bus and the comparison below takes care of adjusting for +* a 16bit bus (i.e. one column-address is consumed). +*/ +const struct { +u8 rows; +u8 columns; +u8 type; + } ddrconf_table[] = { +/* +* C-B-R-D patterns are first. For these we require an +* exact match for the columns and rows (as there's +* one entry per possible configuration). +*/ + [0 ] = { .rows =13 , .columns =10 , .type =DMC_MSCH_CBRD }, + [1 ] = { .rows =14 , .columns =10 , .type =DMC_MSCH_CBRD }, + [2 ] = { .rows =15 , .columns =10 , .type =DMC_MSCH_CBRD }, + [3 ] = { .rows =16 , .columns =10 , .type =DMC_MSCH_CBRD }, + [4 ] = { .rows =14 , .columns =11 , .type =DMC_MSCH_CBRD }, + [5 ] = { .rows =15 , .columns =11 , .type =DMC_MSCH_CBRD }, + [6 ] = { .rows =16 , .columns =11 , .type =DMC_MSCH_CBRD }, + [7 ] = { .rows =13 , .columns =9 , .type =DMC_MSCH_CBRD }, + [8 ] = { .rows =14 , .columns =9 , .type =DMC_MSCH_CBRD }, + [9 ] = { .rows =15 , .columns =9 , .type =DMC_MSCH_CBRD }, + [10 ] = { .rows =16 , .columns =9 , .type =DMC_MSCH_CBRD }, +/* +* 11 through 13 are C-R-B-D patterns. These are +* matched for an exact number of columns and to +* ensure that the hardware uses at least as many rows +* as the pattern requires (i.e. we make sure that +* there's no gaps up until we hit the device/chip-select; +* however, these patterns can accept up to 16 rows, +* as the row-address continues right after the CS +* switching) +*/ + [11 ] = { .rows =15 , .columns =10 , .type =DMC_MSCH_CRBD }, + [12 ] = { .rows =14 , .columns =11 , .type =DMC_MSCH_CRBD }, + [13 ] = { .rows =13 , .columns =10 , .type =DMC_MSCH_CRBD }, +/* +* 14 and 15 are catch-all variants using a C-B-D-R +* scheme (i.e. alternating the chip-select every time +* C-B overflows) and stuffing the remaining C-bits +* into the top. Matching needs to make sure that the +* number of columns is either an exact match (i.e. we +* can use less the the maximum number of rows) -or- +* that the columns exceed what is given in this table +* and the rows are an exact match (in which case the +* remaining C-bits will be stuffed onto the top after +* the device/chip-select switches). +*/ + [14 ] = { .rows =16 , .columns =10 , .type =DMC_MSCH_CBDR }, + [15 ] = { .rows =16 , .columns =9 , .type =DMC_MSCH_CBDR }, + }; + +/* +* For C-B-R-D, we need an exact match (i.e. both for the number of +* columns and rows), while for C-B-D-R, only the the number of +* columns needs to match. +*/ +for (i =0 ; i <ARRAY_SIZE (ddrconf_table); i++) { +bool match = false; + +/* If this entry if for a different matcher, then skip it */ +if (ddrconf_table[i].type != params->memory_schedule) +continue ; + +/* +* Match according to the rules (exact/inexact/at-least) +* documented in the ddrconf_table above. +*/ +switch (params->memory_schedule) { +case DMC_MSCH_CBRD : + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows == rows); +break ; + +case DMC_MSCH_CRBD : + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows <= rows); +break ; + +case DMC_MSCH_CBDR : + match = (ddrconf_table[i].columns == cols) || + ((ddrconf_table[i].columns <= cols) && + (ddrconf_table[i].rows == rows)); +break ; + +default : +break ; + } + +if (match) { +debug ("%s: setting ddrconf 0x%x\n" , __func__, i); +writel (i, &msch->ddrconf); +return 0 ; + } + } + +error ("%s: ddrconf (NIU config) not found\n" , __func__); +return -EINVAL ; +} + +static void dram_all_config (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_pmu_grf *pmugrf = priv->pmugrf; +struct rk3368_sdram_params *params =dev_get_platdata (dev); +const struct rk3288_sdram_channel *info = ¶ms->chan; +u32 sys_reg =0 ; +const int chan =0 ; + + sys_reg |=DDR3 <<SYS_REG_DDRTYPE_SHIFT ; + sys_reg |=0 <<SYS_REG_NUM_CH_SHIFT ; + + sys_reg |= info->row_3_4 <<SYS_REG_ROW_3_4_SHIFT (chan); + sys_reg |=1 <<SYS_REG_CHINFO_SHIFT (chan); + sys_reg |= (info->rank -1 ) <<SYS_REG_RANK_SHIFT (chan); + sys_reg |= (info->col -9 ) <<SYS_REG_COL_SHIFT (chan); + sys_reg |= info->bk ==3 ?0 :1 <<SYS_REG_BK_SHIFT (chan); + sys_reg |= (info->cs0_row -13 ) <<SYS_REG_CS0_ROW_SHIFT (chan); + sys_reg |= (info->cs1_row -13 ) <<SYS_REG_CS1_ROW_SHIFT (chan); + sys_reg |= (2 >> info->bw) <<SYS_REG_BW_SHIFT (chan); + sys_reg |= (2 >> info->dbw) <<SYS_REG_DBW_SHIFT (chan); + +writel (sys_reg, &pmugrf->os_reg[2 ]); +} + +static int setup_sdram (struct udevice *dev) +{ +struct dram_info *priv =dev_get_priv (dev); +struct rk3368_sdram_params *params =dev_get_platdata (dev); + +struct rk3368_ddr_pctl *pctl = priv->pctl; +struct rk3368_ddrphy *ddrphy = priv->phy; +struct rk3368_cru *cru = priv->cru; +struct rk3368_grf *grf = priv->grf; +struct rk3368_msch *msch = priv->msch; + +int ret; + +/* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */ + ret =clk_set_rate (&priv->ddr_clk,2 * params->ddr_freq); +if (ret <0 ) { +debug ("%s: could not set DDR clock: %d\n" , __func__, ret); +return ret; + } + +/* Update the read-latency for the RK3368 */ +writel (0x32 , &msch->readlatency); + +/* Initialise the DDR PCTL and DDR PHY */ +ddrctl_reset (cru); +ddrphy_reset (ddrphy); +ddrphy_config_delays (ddrphy, params->ddr_freq); +dfi_cfg (pctl); +/* Configure relative system information of grf_ddrc0_con0 register */ +ddr_set_ddr3_mode (grf, true); +ddr_set_noc_spr_err_stall (grf, true); +/* Calculate timings */ +pctl_calc_timings (params, params->ddr_freq); +/* Initialise the device timings in protocol controller */ +pctl_cfg (pctl, params, grf); +/* Configure AL, CL ... information of PHY registers */ +ddrphy_config (ddrphy, + params->pctl_timing.tcl, + params->pctl_timing.tal, + params->pctl_timing.tcwl); + +/* Initialize DRAM and configure with mode-register values */ + ret =memory_init (pctl, params); +if (ret) + goto error; + +move_to_config_state (pctl); +/* Perform data-training */ +ddrphy_data_training (pctl, ddrphy); +move_to_access_state (pctl); + +/* TODO(prt): could detect rank in training... */ + params->chan.rank =2 ; +/* TODO(prt): bus width is not auto-detected (yet)... */ + params->chan.bw =2 ;/* 32bit wide bus */ + params->chan.dbw = params->chan.dbw;/* 32bit wide bus */ + +/* DDR3 is always 8 bank */ + params->chan.bk =3 ; +/* Detect col and row number */ + ret =sdram_col_row_detect (dev); +if (ret) + goto error; + +/* Configure NIU DDR configuration */ + ret =msch_niu_config (msch, params); +if (ret) + goto error; + +/* set up OS_REG to communicate w/ next stage and OS */ +dram_all_config (dev); + +return 0 ; + +error: +printf ("DRAM init failed!\n" ); +hang (); +} +#endif + +static int rk3368_dmc_ofdata_to_platdata (struct udevice *dev) +{ +int ret =0 ; + +#if !CONFIG_IS_ENABLED (OF_PLATDATA ) +struct rk3368_sdram_params *plat =dev_get_platdata (dev); + + ret =regmap_init_mem (dev, &plat->map); +if (ret) +return ret; +#endif + +return ret; +} + +#if CONFIG_IS_ENABLED (OF_PLATDATA ) +static int conv_of_platdata (struct udevice *dev) +{ +struct rk3368_sdram_params *plat =dev_get_platdata (dev); +struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat; +int ret; + + plat->ddr_freq = of_plat->rockchip_ddr_frequency; + plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin; + plat->memory_schedule = of_plat->rockchip_memory_schedule; + + ret =regmap_init_mem_platdata (dev, of_plat->reg, +ARRAY_SIZE (of_plat->reg) /2 , + &plat->map); +if (ret) +return ret; + +return 0 ; +} +#endif + +static int rk3368_dmc_probe (struct udevice *dev) +{ +#ifdef CONFIG_TPL_BUILD +struct rk3368_sdram_params *plat =dev_get_platdata (dev); +struct rk3368_ddr_pctl *pctl; +struct rk3368_ddrphy *ddrphy; +struct rk3368_cru *cru; +struct rk3368_grf *grf; +struct rk3368_msch *msch; +int ret; +struct udevice *dev_clk; +#endif +struct dram_info *priv =dev_get_priv (dev); + +#if CONFIG_IS_ENABLED (OF_PLATDATA ) + ret =conv_of_platdata (dev); +if (ret) +return ret; +#endif + + priv->pmugrf =syscon_get_first_range (ROCKCHIP_SYSCON_PMUGRF ); +debug ("%s: pmugrf=%p\n" , __func__, priv->pmugrf); + +#ifdef CONFIG_TPL_BUILD + pctl =regmap_get_range (plat->map,0 ); + ddrphy =regmap_get_range (plat->map,1 ); + msch =syscon_get_first_range (ROCKCHIP_SYSCON_MSCH ); + grf =syscon_get_first_range (ROCKCHIP_SYSCON_GRF ); + + priv->pctl = pctl; + priv->phy = ddrphy; + priv->msch = msch; + priv->grf = grf; + + ret =rockchip_get_clk (&dev_clk); +if (ret) +return ret; + priv->ddr_clk.id =CLK_DDR ; + ret =clk_request (dev_clk, &priv->ddr_clk); +if (ret) +return ret; + + cru =rockchip_get_cru (); + priv->cru = cru; +if (IS_ERR (priv->cru)) +return PTR_ERR (priv->cru); + + ret =setup_sdram (dev); +if (ret) +return ret; +#endif + + priv->info.base =0 ; + priv->info.size = +rockchip_sdram_size ((phys_addr_t)&priv->pmugrf->os_reg[2 ]); + +/* +* we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff +* is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is +* inaccessible for some IP controller. +*/ + priv->info.size =min (priv->info.size, (size_t )0xfe000000 ); + +return 0 ; +} + +static int rk3368_dmc_get_info (struct udevice *dev,struct ram_info *info) +{ +struct dram_info *priv =dev_get_priv (dev); + + *info = priv->info; +return 0 ; +} + +static struct ram_ops rk3368_dmc_ops = { + .get_info = rk3368_dmc_get_info, +}; + + +static const struct udevice_id rk3368_dmc_ids[] = { + { .compatible ="rockchip,rk3368-dmc" }, + { } +}; + +U_BOOT_DRIVER (dmc_rk3368) = { + .name ="rockchip_rk3368_dmc" , + .id =UCLASS_RAM , + .of_match = rk3368_dmc_ids, + .ops = &rk3368_dmc_ops, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size =sizeof (struct dram_info ), + .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size =sizeof (struct dram_info ), + .platdata_auto_alloc_size =sizeof (struct rk3368_sdram_params ), +};include/dt-bindings/memory/rk3368-dmc.h new file +30
-0@@ -0,0 +1,30 @@ +#ifndef DT_BINDINGS_RK3368_DMC_H +#define DT_BINDINGS_RK3368_DMC_H + +#define DMC_MSCH_CBDR 0x0 +#define DMC_MSCH_CBRD 0x1 +#define DMC_MSCH_CRBD 0x2 + +#define DDR3_800D 0 +#define DDR3_800E 1 +#define DDR3_1066E 2 +#define DDR3_1066F 3 +#define DDR3_1066G 4 +#define DDR3_1333F 5 +#define DDR3_1333G 6 +#define DDR3_1333H 7 +#define DDR3_1333J 8 +#define DDR3_1600G 9 +#define DDR3_1600H 10 +#define DDR3_1600J 11 +#define DDR3_1600K 12 +#define DDR3_1866J 13 +#define DDR3_1866K 14 +#define DDR3_1866L 15 +#define DDR3_1866M 16 +#define DDR3_2133K 17 +#define DDR3_2133L 18 +#define DDR3_2133M 19 +#define DDR3_2133N 20 + +#endif