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dts: add ls2088a and 1088a pcie DT nodes

PATCH Superseded Zhiqiang Hou 2 participants 6 messages Aug 4, 2017 – Aug 7, 2017

Subsystems (2)
Device tree bindings Arm i.MX and Layerscape

v2 of 3 Superseded Latest is v3 →

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Zhiqiang Hou

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#0 lore raw

v2 cover dts: add ls2088a and 1088a pcie DT nodes

From: Hou Zhiqiang <[email protected]>

Add GICv3 ITS DT node for ls1088a, because the PCIe nodes must have a msi-parent.

Hou Zhiqiang (3):
dts: ls2088a: add pcie support
dts: ls1088a: add gicv3 ITS DT node
dts: ls1088a: add PCIe controller DT nodes

 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 81 ++++++++++++++++++++++++++
 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi |  4 ++
 2 files changed, 85 insertions(+)
Signature · 1 line
2.1.0.27.g96db324
author
#1 lore raw

PATCH v2 1/3 dts: ls2088a: add pcie support

From: Hou Zhiqiang <[email protected]>

The physical memory map address and CCSR registers map address are different between LS2088A and other LS2080A series SoCs.

Signed-off-by Hou Zhiqiang <[email protected]>

---
V2:
- None

 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +4 -0
index 5c695c6..7d26531 100644
@@ -134,6 +134,7 @@
 };
 
 &pcie1 {
+	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
 	reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 	       0x20 0x00000000 0x0 0x00002000>; /* configuration space */
 

@@ -142,6 +143,7 @@
 };
 
 &pcie2 {
+	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
 	reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 	       0x28 0x00000000 0x0 0x00002000>; /* configuration space */
 

@@ -150,6 +152,7 @@
 };
 
 &pcie3 {
+	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
 	reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 	       0x30 0x00000000 0x0 0x00002000>; /* configuration space */
 

@@ -158,6 +161,7 @@
 };
 
 &pcie4 {
+	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
 	reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
 	       0x38 0x00000000 0x0 0x00002000>; /* configuration space */
Signature · 1 line
2.1.0.27.g96db324
author
#2 lore raw

PATCH v2 2/3 dts: ls1088a: add gicv3 ITS DT node

In reply to Zhiqiang Hou

From: Hou Zhiqiang <[email protected]>

Add ITS device tree node, which will be used by PCIe controller.

Signed-off-by Hou Zhiqiang <[email protected]>

---
V2:
- None

 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +9 -0
index c144d06..5f35797 100644
@@ -126,6 +126,15 @@
 		      <0x0 0x0c0d0000 0 0x1000>, /* GICH */
 		      <0x0 0x0c0e0000 0 0x20000>; /* GICV */
 		interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		its: gic-its at 6020000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0x6020000 0 0x20000>;
+		};
 	};
 
 	timer {
Signature · 1 line
2.1.0.27.g96db324
author
#3 lore raw

PATCH v2 3/3 dts: ls1088a: add PCIe controller DT nodes

In reply to Zhiqiang Hou

From: Hou Zhiqiang <[email protected]>

The LS1088a implements 3 PCIe 3.0 controllers.

Signed-off-by Hou Zhiqiang <[email protected]>

---
V2:
- Remove the "fsl,ls2088a-pcie" from the compatible list.

 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 72 ++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +72 -0
index 5f35797..df83e19 100644
@@ -378,6 +378,78 @@
 			dma-coherent;
 			status = "disabled";
 		};
+		pcie at 3400000 {
+			compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
+			       0x20 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
+			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "aer";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			dma-coherent;
+			num-lanes = <4>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			msi-parent = <&its>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pcie at 3500000 {
+			compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
+			       0x28 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
+			interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "aer";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			dma-coherent;
+			num-lanes = <4>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			msi-parent = <&its>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pcie at 3600000 {
+			compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
+			       0x30 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
+			interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "aer";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			dma-coherent;
+			num-lanes = <8>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			msi-parent = <&its>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 	};
 
 };
Signature · 1 line
2.1.0.27.g96db324
#4 lore raw

v2 cover dts: add ls2088a and 1088a pcie DT nodes

In reply to Zhiqiang Hou
Quoted 9 lines · Zhiqiang Hou

From: Hou Zhiqiang <[email protected]>

Add GICv3 ITS DT node for ls1088a, because the PCIe nodes must have a msi-parent.

Hou Zhiqiang (3):
dts: ls2088a: add pcie support
dts: ls1088a: add gicv3 ITS DT node
dts: ls1088a: add PCIe controller DT nodes

Please have an additional 'arm64: ' prefix for these arm64 dts patches.

Shawn

Quoted 4 lines
 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 81 ++++++++++++++++++++++++++
 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi |  4 ++
 2 files changed, 85 insertions(+)
author
#5 lore raw

v2 cover dts: add ls2088a and 1088a pcie DT nodes

Hi Shawn,

Thanks a lot for your comments!

Quoted 15 lines

-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: 2017?8?5? 13:46
To: Z.q. Hou <[email protected]>
Cc: linux-arm-kernel at lists.infradead.org; devicetree at vger.kernel.org; robh+dt at kernel.org; mark.rutland at arm.com; catalin.marinas at arm.com; will.deacon at arm.com; Prabhakar Kushwaha <[email protected]>
Subject: Re: [PATCHv2 0/3] dts: add ls2088a and 1088a pcie DT nodes

Quoted 5 lines · Zhiqiang Hou

From: Hou Zhiqiang <[email protected]>

Add GICv3 ITS DT node for ls1088a, because the PCIe nodes must have a msi-parent.

Quoted 6 lines
Quoted 4 lines

Hou Zhiqiang (3):
dts: ls2088a: add pcie support
dts: ls1088a: add gicv3 ITS DT node
dts: ls1088a: add PCIe controller DT nodes

Please have an additional 'arm64: ' prefix for these arm64 dts patches.

yes, will add next version.

Thanks,
Zhiqiang