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Fix Skylake PEBS data source for perf v5

PATCH In review Andi Kleen 5 participants 15 messages Aug 16, 2017 – Aug 25, 2017

Subsystems (2)
x86 perf events
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Andi Kleen

author
#0 lore raw

Fix data source reporting for Skylake and Skylake Server. The encodings have changed to express support for L4 and persistent memory.

The first patch is a (independent) cleanup.

The second is for the kernel and the third/fourth for perf/tools. The kernel part and perf tools will compile independently.

Also available in
git://git.kernel.org/pub/scm/linux/kernel/git/ak/linux-misc.git perf/skx-data-src-7

v1:
Initial post
v2:
Merged some patches.
Change encoding to use special bit for each combination instead of modifiers.
v3:
Switch to new generic lvlnum indication
v4:
Repost. No changes.
v5:
ported to latest tree. Retested remote HITM.

author
#1 lore raw

PATCH v5 1/4 perf/x86: Move Nehalem PEBS code to flag

From: Andi Kleen <[email protected]>

Minor cleanup: use an explicit x86_pmu flag to handle the missing Lock / TLB information on Nehalem, instead of always checking the model number for each PEBS sample.

Signed-off-by Andi Kleen <[email protected]>
---
 arch/x86/events/intel/core.c | 1 +
 arch/x86/events/intel/ds.c   | 5 +----
 arch/x86/events/perf_event.h | 3 ++-
 3 files changed, 4 insertions(+), 5 deletions(-)
arch/x86/events/intel/core.c +1 -0
index 98b0f0729527..c3439a36dcf9 100644
@@ -3905,6 +3905,7 @@ __init int intel_pmu_init(void)
 
 		intel_pmu_pebs_data_source_nhm();
 		x86_add_quirk(intel_nehalem_quirk);
+		x86_pmu.pebs_no_tlb = 1;
 
 		pr_cont("Nehalem events, ");
 		break;
arch/x86/events/intel/ds.c +1 -4
index a322fed5f8ed..3ccdf8cb4495 100644
@@ -149,8 +149,6 @@ static u64 load_latency_data(u64 status)
 {
 	union intel_x86_pebs_dse dse;
 	u64 val;
-	int model = boot_cpu_data.x86_model;
-	int fam = boot_cpu_data.x86;
 
 	dse.val = status;
 

@@ -162,8 +160,7 @@ static u64 load_latency_data(u64 status)
 	/*
 	 * Nehalem models do not support TLB, Lock infos
 	 */
-	if (fam == 0x6 && (model == 26 || model == 30
-	    || model == 31 || model == 46)) {
+	if (x86_pmu.pebs_no_tlb) {
 		val |= P(TLB, NA) | P(LOCK, NA);
 		return val;
 	}
arch/x86/events/perf_event.h +2 -1
index 476aec3a4cab..2e9636e4068f 100644
@@ -591,7 +591,8 @@ struct x86_pmu {
 			pebs		:1,
 			pebs_active	:1,
 			pebs_broken	:1,
-			pebs_prec_dist	:1;
+			pebs_prec_dist	:1,
+			pebs_no_tlb	:1;
 	int		pebs_record_size;
 	int		pebs_buffer_size;
 	void		(*drain_pebs)(struct pt_regs *regs);
Signature · 1 line
2.9.4
merge bot
#2 lore raw

[tip:perf/core] perf/x86: Move Nehalem PEBS code to flag

perf/x86: Move Nehalem PEBS code to flag
Commit-ID:  95298355143f9765f0d40ed57dce7fa6571cc623
Gitweb:     http://git.kernel.org/tip/95298355143f9765f0d40ed57dce7fa6571cc623
Author:     Andi Kleen <[email protected]>
AuthorDate: Wed, 16 Aug 2017 15:21:53 -0700
Committer:  Ingo Molnar <[email protected]>
CommitDate: Fri, 25 Aug 2017 11:04:16 +0200

perf/x86: Move Nehalem PEBS code to flag

Minor cleanup: use an explicit x86_pmu flag to handle the missing Lock / TLB information on Nehalem, instead of always checking the model number for each PEBS sample.

Signed-off-by Andi Kleen <[email protected]>
Signed-off-by Peter Zijlstra (Intel) <[email protected]>
Cc Linus Torvalds <[email protected]>
Cc Peter Zijlstra <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc [email protected]
Cc [email protected]
Link http://lkml.kernel.org/r/[email protected] open here
Signed-off-by Ingo Molnar <[email protected]>
---
 arch/x86/events/intel/core.c | 1 +
 arch/x86/events/intel/ds.c   | 5 +----
 arch/x86/events/perf_event.h | 3 ++-
 3 files changed, 4 insertions(+), 5 deletions(-)
arch/x86/events/intel/core.c +1 -0
index 98b0f07..c3439a3 100644
@@ -3905,6 +3905,7 @@ __init int intel_pmu_init(void)
 
 		intel_pmu_pebs_data_source_nhm();
 		x86_add_quirk(intel_nehalem_quirk);
+		x86_pmu.pebs_no_tlb = 1;
 
 		pr_cont("Nehalem events, ");
 		break;
arch/x86/events/intel/ds.c +1 -4
index a322fed..3ccdf8c 100644
@@ -149,8 +149,6 @@ static u64 load_latency_data(u64 status)
 {
 	union intel_x86_pebs_dse dse;
 	u64 val;
-	int model = boot_cpu_data.x86_model;
-	int fam = boot_cpu_data.x86;
 
 	dse.val = status;
 

@@ -162,8 +160,7 @@ static u64 load_latency_data(u64 status)
 	/*
 	 * Nehalem models do not support TLB, Lock infos
 	 */
-	if (fam == 0x6 && (model == 26 || model == 30
-	    || model == 31 || model == 46)) {
+	if (x86_pmu.pebs_no_tlb) {
 		val |= P(TLB, NA) | P(LOCK, NA);
 		return val;
 	}
arch/x86/events/perf_event.h +2 -1
index 476aec3..2e9636e 100644
@@ -591,7 +591,8 @@ struct x86_pmu {
 			pebs		:1,
 			pebs_active	:1,
 			pebs_broken	:1,
-			pebs_prec_dist	:1;
+			pebs_prec_dist	:1,
+			pebs_no_tlb	:1;
 	int		pebs_record_size;
 	int		pebs_buffer_size;
 	void		(*drain_pebs)(struct pt_regs *regs);
author
#3 lore raw

PATCH v5 2/4 perf/x86: Fix data source decoding for Skylake

In reply to Andi Kleen

From: Andi Kleen <[email protected]>

Skylake changed the encoding of the PEBS data source field. Some combinations are not available anymore, but some new cases e.g. for L4 cache hit are added.

Fix up the conversion table for Skylake, similar as had been done for Nehalem.

On Skylake server the encoding for L4 actually means persistent memory. Handle this case too.

To properly describe it in the abstracted perf format I had to add some new fields. Since a hit can have only one level add a new field that is an enumeration, not a bit field to describe the level. It can describe any level. Some numbers are also used to describe PMEM and LFB.

Also add a new generic remote flag that can be combined with the generic level to signify a remote cache.

And there is an extension field for the snoop indication to handle the Forward state.

I didn't add a generic flag for hops because it's not needed for Skylake.

I changed the existing encodings for older CPUs to also fill in the new level and remote fields.

v2: Merge with persistent memory patch.
Add explicit bit for each case instead of using generic modifier.
v3: Rework with new lvlnum and remote fields.
Change older CPUs to report the new fields too.

Signed-off-by Andi Kleen <[email protected]>
---
 arch/x86/events/intel/core.c    |  2 ++
 arch/x86/events/intel/ds.c      | 51 ++++++++++++++++++++++++++---------------
 arch/x86/events/perf_event.h    |  2 ++
 include/uapi/linux/perf_event.h | 30 ++++++++++++++++++++++--
 4 files changed, 64 insertions(+), 21 deletions(-)
arch/x86/events/intel/core.c +2 -0
index c3439a36dcf9..6f342001ec6a 100644
@@ -4208,6 +4208,8 @@ __init int intel_pmu_init(void)
 						  skl_format_attr);
 		WARN_ON(!x86_pmu.format_attrs);
 		x86_pmu.cpu_events = hsw_events_attrs;
+		intel_pmu_pebs_data_source_skl(
+			boot_cpu_data.x86_model == INTEL_FAM6_SKYLAKE_X);
 		pr_cont("Skylake events, ");
 		break;
arch/x86/events/intel/ds.c +32 -19

66 lines not on this page · raw message

arch/x86/events/perf_event.h +2 -0
index 2e9636e4068f..0f7dad8bd358 100644
@@ -948,6 +948,8 @@ void intel_pmu_lbr_init_knl(void);
 
 void intel_pmu_pebs_data_source_nhm(void);
 
+void intel_pmu_pebs_data_source_skl(bool pmem);
+
 int intel_pmu_setup_lbr_filter(struct perf_event *event);
 
 void intel_pt_interrupt(void);
include/uapi/linux/perf_event.h +28 -2
index 642db5fa3286..2a37ae925d85 100644
@@ -954,14 +954,20 @@ union perf_mem_data_src {
 			mem_snoop:5,	/* snoop mode */
 			mem_lock:2,	/* lock instr */
 			mem_dtlb:7,	/* tlb access */
-			mem_rsvd:31;
+			mem_lvl_num:4,	/* memory hierarchy level number */
+			mem_remote:1,   /* remote */
+			mem_snoopx:2,	/* snoop mode, ext */
+			mem_rsvd:24;
 	};
 };
 #elif defined(__BIG_ENDIAN_BITFIELD)
 union perf_mem_data_src {
 	__u64 val;
 	struct {
-		__u64	mem_rsvd:31,
+		__u64	mem_rsvd:24,
+			mem_snoopx:2,	/* snoop mode, ext */
+			mem_remote:1,   /* remote */
+			mem_lvl_num:4,	/* memory hierarchy level number */
 			mem_dtlb:7,	/* tlb access */
 			mem_lock:2,	/* lock instr */
 			mem_snoop:5,	/* snoop mode */

@@ -998,6 +1004,22 @@ union perf_mem_data_src {
 #define PERF_MEM_LVL_UNC	0x2000 /* Uncached memory */
 #define PERF_MEM_LVL_SHIFT	5
 
+#define PERF_MEM_REMOTE_REMOTE	0x01  /* Remote */
+#define PERF_MEM_REMOTE_SHIFT	37
+
+#define PERF_MEM_LVLNUM_L1	0x01 /* L1 */
+#define PERF_MEM_LVLNUM_L2	0x02 /* L2 */
+#define PERF_MEM_LVLNUM_L3	0x03 /* L3 */
+#define PERF_MEM_LVLNUM_L4	0x04 /* L4 */
+/* 5-0xa available */
+#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */
+#define PERF_MEM_LVLNUM_LFB	0x0c /* LFB */
+#define PERF_MEM_LVLNUM_RAM	0x0d /* RAM */
+#define PERF_MEM_LVLNUM_PMEM	0x0e /* PMEM */
+#define PERF_MEM_LVLNUM_NA	0x0f /* N/A */
+
+#define PERF_MEM_LVLNUM_SHIFT	33
+
 /* snoop mode */
 #define PERF_MEM_SNOOP_NA	0x01 /* not available */
 #define PERF_MEM_SNOOP_NONE	0x02 /* no snoop */

@@ -1006,6 +1028,10 @@ union perf_mem_data_src {
 #define PERF_MEM_SNOOP_HITM	0x10 /* snoop hit modified */
 #define PERF_MEM_SNOOP_SHIFT	19
 
+#define PERF_MEM_SNOOPX_FWD	0x01 /* forward */
+/* 1 free */
+#define PERF_MEM_SNOOPX_SHIFT	37
+
 /* locked instruction */
 #define PERF_MEM_LOCK_NA	0x01 /* not available */
 #define PERF_MEM_LOCK_LOCKED	0x02 /* locked transaction */
Signature · 1 line
2.9.4
merge bot
#4 lore raw

[tip:perf/core] perf/x86: Fix data source decoding for Skylake

perf/x86: Fix data source decoding for Skylake
Commit-ID:  6ae5fa61d27dcb055f4198bcf6c8dbbf1bb33f52
Gitweb:     http://git.kernel.org/tip/6ae5fa61d27dcb055f4198bcf6c8dbbf1bb33f52
Author:     Andi Kleen <[email protected]>
AuthorDate: Wed, 16 Aug 2017 15:21:54 -0700
Committer:  Ingo Molnar <[email protected]>
CommitDate: Fri, 25 Aug 2017 11:04:17 +0200

perf/x86: Fix data source decoding for Skylake

Skylake changed the encoding of the PEBS data source field. Some combinations are not available anymore, but some new cases e.g. for L4 cache hit are added.

Fix up the conversion table for Skylake, similar as had been done for Nehalem.

On Skylake server the encoding for L4 actually means persistent memory. Handle this case too.

To properly describe it in the abstracted perf format I had to add some new fields. Since a hit can have only one level add a new field that is an enumeration, not a bit field to describe the level. It can describe any level. Some numbers are also used to describe PMEM and LFB.

Also add a new generic remote flag that can be combined with the generic level to signify a remote cache.

And there is an extension field for the snoop indication to handle the Forward state.

I didn't add a generic flag for hops because it's not needed for Skylake.

I changed the existing encodings for older CPUs to also fill in the new level and remote fields.

Signed-off-by Andi Kleen <[email protected]>
Signed-off-by Peter Zijlstra (Intel) <[email protected]>
Cc Linus Torvalds <[email protected]>
Cc Madhavan Srinivasan <[email protected]>
Cc Michael Ellerman <[email protected]>
Cc Peter Zijlstra <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc [email protected]
Cc [email protected]
Link http://lkml.kernel.org/r/[email protected] open here
Signed-off-by Ingo Molnar <[email protected]>
---
 arch/x86/events/intel/core.c    |  2 ++
 arch/x86/events/intel/ds.c      | 51 ++++++++++++++++++++++++++---------------
 arch/x86/events/perf_event.h    |  2 ++
 include/uapi/linux/perf_event.h | 30 ++++++++++++++++++++++--
 4 files changed, 64 insertions(+), 21 deletions(-)
arch/x86/events/intel/core.c +2 -0
index c3439a3..6f34200 100644
@@ -4208,6 +4208,8 @@ __init int intel_pmu_init(void)
 						  skl_format_attr);
 		WARN_ON(!x86_pmu.format_attrs);
 		x86_pmu.cpu_events = hsw_events_attrs;
+		intel_pmu_pebs_data_source_skl(
+			boot_cpu_data.x86_model == INTEL_FAM6_SKYLAKE_X);
 		pr_cont("Skylake events, ");
 		break;
arch/x86/events/intel/ds.c +32 -19

66 lines not on this page · raw message

arch/x86/events/perf_event.h +2 -0
index 2e9636e..0f7dad8 100644
@@ -948,6 +948,8 @@ void intel_pmu_lbr_init_knl(void);
 
 void intel_pmu_pebs_data_source_nhm(void);
 
+void intel_pmu_pebs_data_source_skl(bool pmem);
+
 int intel_pmu_setup_lbr_filter(struct perf_event *event);
 
 void intel_pt_interrupt(void);
include/uapi/linux/perf_event.h +28 -2
index 642db5f..2a37ae9 100644
@@ -954,14 +954,20 @@ union perf_mem_data_src {
 			mem_snoop:5,	/* snoop mode */
 			mem_lock:2,	/* lock instr */
 			mem_dtlb:7,	/* tlb access */
-			mem_rsvd:31;
+			mem_lvl_num:4,	/* memory hierarchy level number */
+			mem_remote:1,   /* remote */
+			mem_snoopx:2,	/* snoop mode, ext */
+			mem_rsvd:24;
 	};
 };
 #elif defined(__BIG_ENDIAN_BITFIELD)
 union perf_mem_data_src {
 	__u64 val;
 	struct {
-		__u64	mem_rsvd:31,
+		__u64	mem_rsvd:24,
+			mem_snoopx:2,	/* snoop mode, ext */
+			mem_remote:1,   /* remote */
+			mem_lvl_num:4,	/* memory hierarchy level number */
 			mem_dtlb:7,	/* tlb access */
 			mem_lock:2,	/* lock instr */
 			mem_snoop:5,	/* snoop mode */

@@ -998,6 +1004,22 @@ union perf_mem_data_src {
 #define PERF_MEM_LVL_UNC	0x2000 /* Uncached memory */
 #define PERF_MEM_LVL_SHIFT	5
 
+#define PERF_MEM_REMOTE_REMOTE	0x01  /* Remote */
+#define PERF_MEM_REMOTE_SHIFT	37
+
+#define PERF_MEM_LVLNUM_L1	0x01 /* L1 */
+#define PERF_MEM_LVLNUM_L2	0x02 /* L2 */
+#define PERF_MEM_LVLNUM_L3	0x03 /* L3 */
+#define PERF_MEM_LVLNUM_L4	0x04 /* L4 */
+/* 5-0xa available */
+#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */
+#define PERF_MEM_LVLNUM_LFB	0x0c /* LFB */
+#define PERF_MEM_LVLNUM_RAM	0x0d /* RAM */
+#define PERF_MEM_LVLNUM_PMEM	0x0e /* PMEM */
+#define PERF_MEM_LVLNUM_NA	0x0f /* N/A */
+
+#define PERF_MEM_LVLNUM_SHIFT	33
+
 /* snoop mode */
 #define PERF_MEM_SNOOP_NA	0x01 /* not available */
 #define PERF_MEM_SNOOP_NONE	0x02 /* no snoop */

@@ -1006,6 +1028,10 @@ union perf_mem_data_src {
 #define PERF_MEM_SNOOP_HITM	0x10 /* snoop hit modified */
 #define PERF_MEM_SNOOP_SHIFT	19
 
+#define PERF_MEM_SNOOPX_FWD	0x01 /* forward */
+/* 1 free */
+#define PERF_MEM_SNOOPX_SHIFT	37
+
 /* locked instruction */
 #define PERF_MEM_LOCK_NA	0x01 /* not available */
 #define PERF_MEM_LOCK_LOCKED	0x02 /* locked transaction */
author
#5 lore raw

PATCH v5 3/4 perf, tools: Add support for printing new mem_info encodings

In reply to Andi Kleen

From: Andi Kleen <[email protected]>

Add decoding for the new lvlx and snoopx field meminfo field added earlier to the kernel so that "perf mem report" and other tools can print it properly.

v2: Merge with persistent memory patch.
Switch to new bit encoding for each combination.
v3: Switch to generic lvlnum field.

Signed-off-by Andi Kleen <[email protected]>
---
 tools/include/uapi/linux/perf_event.h | 30 ++++++++++++++++++++++--
 tools/perf/util/mem-events.c          | 43 ++++++++++++++++++++++++++++++++---
 2 files changed, 68 insertions(+), 5 deletions(-)
tools/include/uapi/linux/perf_event.h +28 -2
index 642db5fa3286..2a37ae925d85 100644
@@ -954,14 +954,20 @@ union perf_mem_data_src {
 			mem_snoop:5,	/* snoop mode */
 			mem_lock:2,	/* lock instr */
 			mem_dtlb:7,	/* tlb access */
-			mem_rsvd:31;
+			mem_lvl_num:4,	/* memory hierarchy level number */
+			mem_remote:1,   /* remote */
+			mem_snoopx:2,	/* snoop mode, ext */
+			mem_rsvd:24;
 	};
 };
 #elif defined(__BIG_ENDIAN_BITFIELD)
 union perf_mem_data_src {
 	__u64 val;
 	struct {
-		__u64	mem_rsvd:31,
+		__u64	mem_rsvd:24,
+			mem_snoopx:2,	/* snoop mode, ext */
+			mem_remote:1,   /* remote */
+			mem_lvl_num:4,	/* memory hierarchy level number */
 			mem_dtlb:7,	/* tlb access */
 			mem_lock:2,	/* lock instr */
 			mem_snoop:5,	/* snoop mode */

@@ -998,6 +1004,22 @@ union perf_mem_data_src {
 #define PERF_MEM_LVL_UNC	0x2000 /* Uncached memory */
 #define PERF_MEM_LVL_SHIFT	5
 
+#define PERF_MEM_REMOTE_REMOTE	0x01  /* Remote */
+#define PERF_MEM_REMOTE_SHIFT	37
+
+#define PERF_MEM_LVLNUM_L1	0x01 /* L1 */
+#define PERF_MEM_LVLNUM_L2	0x02 /* L2 */
+#define PERF_MEM_LVLNUM_L3	0x03 /* L3 */
+#define PERF_MEM_LVLNUM_L4	0x04 /* L4 */
+/* 5-0xa available */
+#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */
+#define PERF_MEM_LVLNUM_LFB	0x0c /* LFB */
+#define PERF_MEM_LVLNUM_RAM	0x0d /* RAM */
+#define PERF_MEM_LVLNUM_PMEM	0x0e /* PMEM */
+#define PERF_MEM_LVLNUM_NA	0x0f /* N/A */
+
+#define PERF_MEM_LVLNUM_SHIFT	33
+
 /* snoop mode */
 #define PERF_MEM_SNOOP_NA	0x01 /* not available */
 #define PERF_MEM_SNOOP_NONE	0x02 /* no snoop */

@@ -1006,6 +1028,10 @@ union perf_mem_data_src {
 #define PERF_MEM_SNOOP_HITM	0x10 /* snoop hit modified */
 #define PERF_MEM_SNOOP_SHIFT	19
 
+#define PERF_MEM_SNOOPX_FWD	0x01 /* forward */
+/* 1 free */
+#define PERF_MEM_SNOOPX_SHIFT	37
+
 /* locked instruction */
 #define PERF_MEM_LOCK_NA	0x01 /* not available */
 #define PERF_MEM_LOCK_LOCKED	0x02 /* locked transaction */
tools/perf/util/mem-events.c +40 -3

74 lines not on this page · raw message

Signature · 1 line
2.9.4
#6 lore raw

Re: [PATCH v5 3/4] perf, tools: Add support for printing new mem_info encodings

On Wed, Aug 16, 2017 at 03:21:55PM -0700, Andi Kleen wrote:

SNIP

Quoted 10 lines

int perf_mem__lvl_scnprintf(char *out, size_t sz, struct mem_info *mem_info) {

tools/perf/util/mem-events.c +1 -0
 	size_t i, l = 0;
 	u64 m =  PERF_MEM_LVL_NA;
 	u64 hit, miss;
+	int printed;
 
 	if (mem_info)
 		m  = mem_info->data_src.mem_lvl;

tools/perf/util/mem-events.c int perf_mem__lvl_scnprintf(char *out, size_t sz, struct mem_info *mem_info) · line 200

Quoted 8 lines
tools/perf/util/mem-events.c +5 -0
@@ -184,17 +193,37 @@ int perf_mem__lvl_scnprintf(char *out, size_t sz, struct mem_info *mem_info)
 	/* already taken care of */
 	m &= ~(PERF_MEM_LVL_HIT|PERF_MEM_LVL_MISS);
 
+
+	if (mem_info && mem_info->data_src.mem_remote) {
+		strcat(out, "Remote ");
+		l += 7;
+	}

Andi,
how is this 'Remote' different from the remote levels in mem_lvl?

        "Remote RAM (1 hop)",
        "Remote RAM (2 hops)",
        "Remote Cache (1 hop)",
        "Remote Cache (2 hops)",

thanks,
jirka

Quoted 26 lines
tools/perf/util/mem-events.c +15 -3
+
+	printed = 0;
 	for (i = 0; m && i < ARRAY_SIZE(mem_lvl); i++, m >>= 1) {
 		if (!(m & 0x1))
 			continue;
-		if (l) {
+		if (printed++) {
 			strcat(out, " or ");
 			l += 4;
 		}
 		l += scnprintf(out + l, sz - l, mem_lvl[i]);
 	}
-	if (*out == '\0')
-		l += scnprintf(out, sz - l, "N/A");
+
+	if (mem_info && mem_info->data_src.mem_lvl_num) {
+		int lvl = mem_info->data_src.mem_lvl_num;
+		if (printed++) {
+			strcat(out, " or ");
+			l += 4;
+		}
+		if (mem_lvlnum[lvl])
+			l += scnprintf(out + l, sz - l, mem_lvlnum[lvl]);
+		else
+			l += scnprintf(out + l, sz - l, "L%d", lvl);
+	}
#7 lore raw

Re: [PATCH v5 3/4] perf, tools: Add support for printing new mem_info encodings

Quoted 7 lines

Andi,
how is this 'Remote' different from the remote levels in mem_lvl?

        "Remote RAM (1 hop)",
        "Remote RAM (2 hops)",
        "Remote Cache (1 hop)",
        "Remote Cache (2 hops)",

It applies to any other level. This is needed to express "Remote unknown level", as is reported by Skylake.

-Andi

#8 lore raw

Re: [PATCH v5 3/4] perf, tools: Add support for printing new mem_info encodings

Quoted 10 lines · Andi Kleen
Quoted 7 lines

Andi,
how is this 'Remote' different from the remote levels in mem_lvl?

        "Remote RAM (1 hop)",
        "Remote RAM (2 hops)",
        "Remote Cache (1 hop)",
        "Remote Cache (2 hops)",

It applies to any other level. This is needed to express "Remote unknown level", as is reported by Skylake.

so if I find HITM with this flag set I should count it as remote HITM then? something like attached.. untested

thanks,
jirka

---

tools/perf/util/mem-events.c +3 -2
index 06f5a3a4295c..65e22b9e59f9 100644
@@ -279,6 +279,7 @@ int c2c_decode_stats(struct c2c_stats *stats, struct mem_info *mi)
 	u64 lvl    = data_src->mem_lvl;
 	u64 snoop  = data_src->mem_snoop;
 	u64 lock   = data_src->mem_lock;
+	bool mr    = data_src->mem_remote;
 	int err = 0;
 
 #define HITM_INC(__f)		\

@@ -324,7 +325,7 @@ do {				\
 			}
 
 			if ((lvl & P(LVL, REM_RAM1)) ||
-			    (lvl & P(LVL, REM_RAM2))) {
+			    (lvl & P(LVL, REM_RAM2)) || mr) {
 				stats->rmt_dram++;
 				if (snoop & P(SNOOP, HIT))
 					stats->ld_shared++;

@@ -334,7 +335,7 @@ do {				\
 		}
 
 		if ((lvl & P(LVL, REM_CCE1)) ||
-		    (lvl & P(LVL, REM_CCE2))) {
+		    (lvl & P(LVL, REM_CCE2)) || mr) {
 			if (snoop & P(SNOOP, HIT))
 				stats->rmt_hit++;
 			else if (snoop & P(SNOOP, HITM))
author
#9 lore raw

Re: [PATCH v5 3/4] perf, tools: Add support for printing new mem_info encodings

Quoted 2 lines

so if I find HITM with this flag set I should count it as remote HITM then? something like attached.. untested

You mean for c2c? Yes looks reasonable.

-Andi

Quoted 36 lines

thanks,
jirka

---

tools/perf/util/mem-events.c +3 -2
index 06f5a3a4295c..65e22b9e59f9 100644
@@ -279,6 +279,7 @@ int c2c_decode_stats(struct c2c_stats *stats, struct mem_info *mi)
 	u64 lvl    = data_src->mem_lvl;
 	u64 snoop  = data_src->mem_snoop;
 	u64 lock   = data_src->mem_lock;
+	bool mr    = data_src->mem_remote;
 	int err = 0;
 
 #define HITM_INC(__f)		\

@@ -324,7 +325,7 @@ do {				\
 			}
 
 			if ((lvl & P(LVL, REM_RAM1)) ||
-			    (lvl & P(LVL, REM_RAM2))) {
+			    (lvl & P(LVL, REM_RAM2)) || mr) {
 				stats->rmt_dram++;
 				if (snoop & P(SNOOP, HIT))
 					stats->ld_shared++;

@@ -334,7 +335,7 @@ do {				\
 		}
 
 		if ((lvl & P(LVL, REM_CCE1)) ||
-		    (lvl & P(LVL, REM_CCE2))) {
+		    (lvl & P(LVL, REM_CCE2)) || mr) {
 			if (snoop & P(SNOOP, HIT))
 				stats->rmt_hit++;
 			else if (snoop & P(SNOOP, HITM))
#10 lore raw

Re: [PATCH v5 3/4] perf, tools: Add support for printing new mem_info encodings

Quoted 4 lines · Andi Kleen
Quoted 2 lines

so if I find HITM with this flag set I should count it as remote HITM then? something like attached.. untested

You mean for c2c? Yes looks reasonable.

yes, it seems to fix c2c to find remote HITMs again on skylake.. I'll post the full patch soon

thanks,
jirka

merge bot
#11 lore raw

[tip:perf/core] perf tools: Add support for printing new mem_info encodings

In reply to Andi Kleen
perf tools: Add support for printing new mem_info encodings
Commit-ID:  52839e653b5629bd237ad2ecdd8fdd897fcd5712
Gitweb:     http://git.kernel.org/tip/52839e653b5629bd237ad2ecdd8fdd897fcd5712
Author:     Andi Kleen <[email protected]>
AuthorDate: Wed, 16 Aug 2017 15:21:55 -0700
Committer:  Arnaldo Carvalho de Melo <[email protected]>
CommitDate: Tue, 22 Aug 2017 12:30:25 -0300

perf tools: Add support for printing new mem_info encodings

Add decoding for the new "lvlx" and "snoopx" meminfo fields added earlier to the kernel so that "perf mem report" and other tools can print it properly.

v2: Merge with persistent memory patch.
Switch to new bit encoding for each combination.

v3: Switch to generic lvlnum field.

Signed-off-by Andi Kleen <[email protected]>
Acked-by Peter Zijlstra <[email protected]>
Cc Jiri Olsa <[email protected]>
Link http://lkml.kernel.org/r/[email protected] open here
Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
---
 tools/include/uapi/linux/perf_event.h | 30 ++++++++++++++++++++++--
 tools/perf/util/mem-events.c          | 43 ++++++++++++++++++++++++++++++++---
 2 files changed, 68 insertions(+), 5 deletions(-)
tools/include/uapi/linux/perf_event.h +28 -2
index 642db5f..2a37ae9 100644
@@ -954,14 +954,20 @@ union perf_mem_data_src {
 			mem_snoop:5,	/* snoop mode */
 			mem_lock:2,	/* lock instr */
 			mem_dtlb:7,	/* tlb access */
-			mem_rsvd:31;
+			mem_lvl_num:4,	/* memory hierarchy level number */
+			mem_remote:1,   /* remote */
+			mem_snoopx:2,	/* snoop mode, ext */
+			mem_rsvd:24;
 	};
 };
 #elif defined(__BIG_ENDIAN_BITFIELD)
 union perf_mem_data_src {
 	__u64 val;
 	struct {
-		__u64	mem_rsvd:31,
+		__u64	mem_rsvd:24,
+			mem_snoopx:2,	/* snoop mode, ext */
+			mem_remote:1,   /* remote */
+			mem_lvl_num:4,	/* memory hierarchy level number */
 			mem_dtlb:7,	/* tlb access */
 			mem_lock:2,	/* lock instr */
 			mem_snoop:5,	/* snoop mode */

@@ -998,6 +1004,22 @@ union perf_mem_data_src {
 #define PERF_MEM_LVL_UNC	0x2000 /* Uncached memory */
 #define PERF_MEM_LVL_SHIFT	5
 
+#define PERF_MEM_REMOTE_REMOTE	0x01  /* Remote */
+#define PERF_MEM_REMOTE_SHIFT	37
+
+#define PERF_MEM_LVLNUM_L1	0x01 /* L1 */
+#define PERF_MEM_LVLNUM_L2	0x02 /* L2 */
+#define PERF_MEM_LVLNUM_L3	0x03 /* L3 */
+#define PERF_MEM_LVLNUM_L4	0x04 /* L4 */
+/* 5-0xa available */
+#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */
+#define PERF_MEM_LVLNUM_LFB	0x0c /* LFB */
+#define PERF_MEM_LVLNUM_RAM	0x0d /* RAM */
+#define PERF_MEM_LVLNUM_PMEM	0x0e /* PMEM */
+#define PERF_MEM_LVLNUM_NA	0x0f /* N/A */
+
+#define PERF_MEM_LVLNUM_SHIFT	33
+
 /* snoop mode */
 #define PERF_MEM_SNOOP_NA	0x01 /* not available */
 #define PERF_MEM_SNOOP_NONE	0x02 /* no snoop */

@@ -1006,6 +1028,10 @@ union perf_mem_data_src {
 #define PERF_MEM_SNOOP_HITM	0x10 /* snoop hit modified */
 #define PERF_MEM_SNOOP_SHIFT	19
 
+#define PERF_MEM_SNOOPX_FWD	0x01 /* forward */
+/* 1 free */
+#define PERF_MEM_SNOOPX_SHIFT	37
+
 /* locked instruction */
 #define PERF_MEM_LOCK_NA	0x01 /* not available */
 #define PERF_MEM_LOCK_LOCKED	0x02 /* locked transaction */
tools/perf/util/mem-events.c +40 -3

74 lines not on this page · raw message

author
#12 lore raw

PATCH v5 4/4 perf, tools: Add test cases for new data source encoding

In reply to Andi Kleen

From: Andi Kleen <[email protected]>

Add some simple tests to perf test to test data source printing.

v2: Make the tests actually checked for the correct name of Forward
v3: Adjust to new encoding

Signed-off-by Andi Kleen <[email protected]>
---
 tools/perf/tests/Build          |  1 +
 tools/perf/tests/builtin-test.c |  4 ++++
 tools/perf/tests/mem.c          | 53 +++++++++++++++++++++++++++++++++++++++++
 tools/perf/tests/tests.h        |  1 +
 4 files changed, 59 insertions(+)
 create mode 100644 tools/perf/tests/mem.c
tools/perf/tests/Build +1 -0
index 84222bdb8689..87bf3edb037c 100644
@@ -34,6 +34,7 @@ perf-y += thread-map.o
 perf-y += llvm.o llvm-src-base.o llvm-src-kbuild.o llvm-src-prologue.o llvm-src-relocation.o
 perf-y += bpf.o
 perf-y += topology.o
+perf-y += mem.o
 perf-y += cpumap.o
 perf-y += stat.o
 perf-y += event_update.o
tools/perf/tests/builtin-test.c +4 -0
index 9ecc44e68990..377bea009163 100644
@@ -48,6 +48,10 @@ static struct test generic_tests[] = {
 		.func = test__basic_mmap,
 	},
 	{
+		.desc = "Test data source output",
+		.func = test__mem,
+	},
+	{
 		.desc = "Parse event definition strings",
 		.func = test__parse_events,
 	},
tools/perf/tests/mem.c new file +53 -0

53 lines not on this page · raw message

tools/perf/tests/tests.h +1 -0
index c46ae818aac8..921412a6a880 100644
@@ -58,6 +58,7 @@ int test__python_use(struct test *test, int subtest);
 int test__bp_signal(struct test *test, int subtest);
 int test__bp_signal_overflow(struct test *test, int subtest);
 int test__task_exit(struct test *test, int subtest);
+int test__mem(struct test *test, int subtest);
 int test__sw_clock_freq(struct test *test, int subtest);
 int test__code_reading(struct test *test, int subtest);
 int test__sample_parsing(struct test *test, int subtest);
Signature · 1 line
2.9.4
merge bot
#13 lore raw

[tip:perf/core] perf test: Add test cases for new data source encoding

perf test: Add test cases for new data source encoding
Commit-ID:  3067eaa7ce2dbcde89d87277cdbc91c211480060
Gitweb:     http://git.kernel.org/tip/3067eaa7ce2dbcde89d87277cdbc91c211480060
Author:     Andi Kleen <[email protected]>
AuthorDate: Wed, 16 Aug 2017 15:21:56 -0700
Committer:  Arnaldo Carvalho de Melo <[email protected]>
CommitDate: Tue, 22 Aug 2017 13:23:10 -0300

perf test: Add test cases for new data source encoding

Add some simple tests to perf test to test data source printing.

v2: Make the tests actually checked for the correct name of Forward
v3: Adjust to new encoding

Committer notes:

Avoid the in place declaration to make this build with older compilers, for instance, in Debian 7 we get:

tests/mem.c: In function 'test__mem':
tests/mem.c:30:5: error: missing initializer [-Werror=missing-field-initializers]
tests/mem.c:30:5: error: (near initialization for '(anonymous).<anonymous>.mem_snoop') [-Werror=missing-field-initializers]

So just zero a struct, then go on building the unions as needed, reusing settings from the previous test, i.e. local -> remote, etc.

Signed-off-by Andi Kleen <[email protected]>
Acked-by Peter Zijlstra <[email protected]>
Cc Jiri Olsa <[email protected]>
Link http://lkml.kernel.org/r/[email protected] open here
Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
---
 tools/perf/tests/Build          |  1 +
 tools/perf/tests/builtin-test.c |  4 +++
 tools/perf/tests/mem.c          | 56 +++++++++++++++++++++++++++++++++++++++++
 tools/perf/tests/tests.h        |  1 +
 4 files changed, 62 insertions(+)
tools/perf/tests/Build +1 -0
index 84222bd..87bf3ed 100644
@@ -34,6 +34,7 @@ perf-y += thread-map.o
 perf-y += llvm.o llvm-src-base.o llvm-src-kbuild.o llvm-src-prologue.o llvm-src-relocation.o
 perf-y += bpf.o
 perf-y += topology.o
+perf-y += mem.o
 perf-y += cpumap.o
 perf-y += stat.o
 perf-y += event_update.o
tools/perf/tests/builtin-test.c +4 -0
index 9ecc44e..377bea0 100644
@@ -48,6 +48,10 @@ static struct test generic_tests[] = {
 		.func = test__basic_mmap,
 	},
 	{
+		.desc = "Test data source output",
+		.func = test__mem,
+	},
+	{
 		.desc = "Parse event definition strings",
 		.func = test__parse_events,
 	},
tools/perf/tests/mem.c new file +56 -0

56 lines not on this page · raw message

tools/perf/tests/tests.h +1 -0
index c46ae81..921412a 100644
@@ -58,6 +58,7 @@ int test__python_use(struct test *test, int subtest);
 int test__bp_signal(struct test *test, int subtest);
 int test__bp_signal_overflow(struct test *test, int subtest);
 int test__task_exit(struct test *test, int subtest);
+int test__mem(struct test *test, int subtest);
 int test__sw_clock_freq(struct test *test, int subtest);
 int test__code_reading(struct test *test, int subtest);
 int test__sample_parsing(struct test *test, int subtest);
maintainer
#14 lore raw
In reply to Andi Kleen

Em Wed, Aug 16, 2017 at 03:21:52PM -0700, Andi Kleen escreveu:

Quoted 8 lines

Fix data source reporting for Skylake and Skylake Server. The encodings have changed to express support for L4 and persistent memory.

The first patch is a (independent) cleanup.

The second is for the kernel and the third/fourth for perf/tools. The kernel part and perf tools will compile independently.

I got the tools part, Peter had some trouble applying it, will get all merged soon in tip, thanks,

- Arnaldo

Quoted 16 lines

Also available in
git://git.kernel.org/pub/scm/linux/kernel/git/ak/linux-misc.git perf/skx-data-src-7

v1:
Initial post
v2:
Merged some patches.
Change encoding to use special bit for each combination instead of modifiers.
v3:
Switch to new generic lvlnum indication
v4:
Repost. No changes.
v5:
ported to latest tree. Retested remote HITM.