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x86/CPU: Align CR3 defines

PATCH New Borislav Petkov 2 participants 2 messages Aug 21, 2017 x86

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Borislav Petkov

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#0 lore raw

PATCH 1/1 x86/CPU: Align CR3 defines

From: Borislav Petkov <[email protected]>

Align them vertically for better readability and use BIT_ULL() macro.

No functionality change.

Cc Andy Lutomirski <[email protected]>
Cc Tom Lendacky <[email protected]>
---
 arch/x86/include/asm/processor-flags.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)
arch/x86/include/asm/processor-flags.h +6 -6
index 8a6d89fc9a79..dc723b64acf0 100644
@@ -34,17 +34,17 @@
  */
 #ifdef CONFIG_X86_64
 /* Mask off the address space ID and SME encryption bits. */
-#define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull)
-#define CR3_PCID_MASK 0xFFFull
-#define CR3_NOFLUSH (1UL << 63)
+#define CR3_ADDR_MASK	__sme_clr(0x7FFFFFFFFFFFF000ull)
+#define CR3_PCID_MASK	0xFFFull
+#define CR3_NOFLUSH	BIT_ULL(63)
 #else
 /*
  * CR3_ADDR_MASK needs at least bits 31:5 set on PAE systems, and we save
  * a tiny bit of code size by setting all the bits.
  */
-#define CR3_ADDR_MASK 0xFFFFFFFFull
-#define CR3_PCID_MASK 0ull
-#define CR3_NOFLUSH 0
+#define CR3_ADDR_MASK	0xFFFFFFFFull
+#define CR3_PCID_MASK	0ull
+#define CR3_NOFLUSH	0
 #endif
 
 #endif /* _ASM_X86_PROCESSOR_FLAGS_H */
Signature · 1 line
2.13.0
#1 lore raw
x86/CPU: Align CR3 defines
Commit-ID:  d6c8103b0265d8db30e20e948a4f06382bbdaea7
Gitweb:     http://git.kernel.org/tip/d6c8103b0265d8db30e20e948a4f06382bbdaea7
Author:     Borislav Petkov <[email protected]>
AuthorDate: Mon, 21 Aug 2017 10:06:51 +0200
Committer:  Ingo Molnar <[email protected]>
CommitDate: Mon, 21 Aug 2017 11:35:50 +0200

x86/CPU: Align CR3 defines

Align them vertically for better readability and use BIT_ULL() macro.

No functionality change.

---
 arch/x86/include/asm/processor-flags.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)
arch/x86/include/asm/processor-flags.h +6 -6
index 8a6d89f..dc723b6 100644
@@ -34,17 +34,17 @@
  */
 #ifdef CONFIG_X86_64
 /* Mask off the address space ID and SME encryption bits. */
-#define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull)
-#define CR3_PCID_MASK 0xFFFull
-#define CR3_NOFLUSH (1UL << 63)
+#define CR3_ADDR_MASK	__sme_clr(0x7FFFFFFFFFFFF000ull)
+#define CR3_PCID_MASK	0xFFFull
+#define CR3_NOFLUSH	BIT_ULL(63)
 #else
 /*
  * CR3_ADDR_MASK needs at least bits 31:5 set on PAE systems, and we save
  * a tiny bit of code size by setting all the bits.
  */
-#define CR3_ADDR_MASK 0xFFFFFFFFull
-#define CR3_PCID_MASK 0ull
-#define CR3_NOFLUSH 0
+#define CR3_ADDR_MASK	0xFFFFFFFFull
+#define CR3_PCID_MASK	0ull
+#define CR3_NOFLUSH	0
 #endif
 
 #endif /* _ASM_X86_PROCESSOR_FLAGS_H */