Optimise 64-bit IOVA allocations
Subsystems (6)
Robin Murphy
maintainerv3 cover Optimise 64-bit IOVA allocations
Hi all,
Just a quick repost of v2[1] with a small fix for the bug reported by Nate. To recap, whilst this mostly only improves worst-case performance, those worst-cases have a tendency to be pathologically bad:
Ard reports general desktop performance with Chromium on AMD Seattle going from ~1-2FPS to perfectly usable.
Leizhen reports gigabit ethernet throughput going from ~6.5Mbit/s to line speed.
I also inadvertantly found that the HiSilicon hns_dsaf driver was taking ~35s to probe simply becuase of the number of DMA buffers it maps on startup (perf shows around 76% of that was spent under the lock in alloc_iova()). With this series applied it takes a mere ~1s, mostly of unrelated mdelay()s, with alloc_iova() entirely lost in the noise.
Robin.
[1] https://www.mail-archive.com/[email protected]/msg19139.html
Robin Murphy (1):
iommu/iova: Extend rbtree node caching
Zhen Lei (3):
iommu/iova: Optimise rbtree searching
iommu/iova: Optimise the padding calculation
iommu/iova: Make dma_32bit_pfn implicit
drivers/gpu/drm/tegra/drm.c | 3 +- drivers/gpu/host1x/dev.c | 3 +- drivers/iommu/amd_iommu.c | 7 +-- drivers/iommu/dma-iommu.c | 18 +------ drivers/iommu/intel-iommu.c | 11 ++-- drivers/iommu/iova.c | 114 +++++++++++++++++---------------------- drivers/misc/mic/scif/scif_rma.c | 3 +- include/linux/iova.h | 8 +-- 8 files changed, 62 insertions(+), 105 deletions(-)
Signature · 1 line
2.13.4.dirty
Robin Murphy
maintainerPATCH v3 1/4 iommu/iova: Optimise rbtree searching
From: Zhen Lei <[email protected]>
Checking the IOVA bounds separately before deciding which direction to continue the search (if necessary) results in redundantly comparing both pfns twice each. GCC can already determine that the final comparison op is redundant and optimise it down to 3 in total, but we can go one further with a little tweak of the ordering (which makes the intent of the code that much cleaner as a bonus).
---
v3: No change
drivers/iommu/iova.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-)
drivers/iommu/iova.c +3 -6
@@ -289,15 +289,12 @@ private_find_iova(struct iova_domain *iovad, unsigned long pfn)while (node) { struct iova *iova = rb_entry(node, struct iova, node); -/* If pfn falls within iova's range, return iova */ -if ((pfn >= iova->pfn_lo) && (pfn <= iova->pfn_hi)) { -return iova; - } -if (pfn < iova->pfn_lo) node = node->rb_left; -else if (pfn > iova->pfn_lo) +else if (pfn > iova->pfn_hi) node = node->rb_right; +else +return iova;/* pfn falls within iova's range */ }return NULL ;
Signature · 1 line
2.13.4.dirty
Robin Murphy
maintainerPATCH v3 2/4 iommu/iova: Optimise the padding calculation
In reply to Robin MurphyFrom: Zhen Lei <[email protected]>
The mask for calculating the padding size doesn't change, so there's no need to recalculate it every loop iteration. Furthermore, Once we've done that, it becomes clear that we don't actually need to calculate a padding size at all - by flipping the arithmetic around, we can just combine the upper limit, size, and mask directly to check against the lower limit.
For an arm64 build, this alone knocks 16% off the size of the entire alloc_iova() function!
---
v3: No change
drivers/iommu/iova.c | 40 ++++++++++++++-------------------------- 1 file changed, 14 insertions(+), 26 deletions(-)
drivers/iommu/iova.c +14 -26
@@ -129,16 +129,6 @@ iova_insert_rbtree(struct rb_root *root, struct iova *iova,rb_insert_color (&iova->node, root); } -/* -* Computes the padding size required, to make the start address -* naturally aligned on the power-of-two order of its size -*/ -static unsigned int -iova_get_pad_size (unsigned int size,unsigned int limit_pfn) -{ -return (limit_pfn - size) & (__roundup_pow_of_two (size) -1 ); -} -static int __alloc_and_insert_iova_range (struct iova_domain *iovad,unsigned long size,unsigned long limit_pfn,struct iova *new,bool size_aligned)
@@ -146,7 +136,10 @@ static int __alloc_and_insert_iova_range(struct iova_domain *iovad,struct rb_node *prev, *curr =NULL ;unsigned long flags;unsigned long saved_pfn; -unsigned int pad_size =0 ; +unsigned long align_mask = ~0UL ; + +if (size_aligned) + align_mask <<=__fls (size);/* Walk the tree backwards */ spin_lock_irqsave (&iovad->iova_rbtree_lock, flags);
@@ -156,31 +149,26 @@ static int __alloc_and_insert_iova_range(struct iova_domain *iovad,while (curr) { struct iova *curr_iova = rb_entry(curr, struct iova, node); -if (limit_pfn <= curr_iova->pfn_lo) { +if (limit_pfn <= curr_iova->pfn_lo) goto move_left; - }else if (limit_pfn > curr_iova->pfn_hi) { -if (size_aligned) - pad_size =iova_get_pad_size (size, limit_pfn); -if ((curr_iova->pfn_hi + size + pad_size) < limit_pfn) -break ;/* found a free slot */ - } + +if (((limit_pfn - size) & align_mask) > curr_iova->pfn_hi) +break ;/* found a free slot */ + limit_pfn = curr_iova->pfn_lo; move_left: prev = curr; curr =rb_prev (curr); } -if (!curr) { -if (size_aligned) - pad_size =iova_get_pad_size (size, limit_pfn); -if ((iovad->start_pfn + size + pad_size) > limit_pfn) { -spin_unlock_irqrestore (&iovad->iova_rbtree_lock, flags); -return -ENOMEM ; - } +if (limit_pfn < size || + (!curr && ((limit_pfn - size) & align_mask) < iovad->start_pfn)) { +spin_unlock_irqrestore (&iovad->iova_rbtree_lock, flags); +return -ENOMEM ; }/* pfn_lo will point to size aligned address if size_aligned is set */ - new->pfn_lo = limit_pfn - (size + pad_size); + new->pfn_lo = (limit_pfn - size) & align_mask; new->pfn_hi = new->pfn_lo + size -1 ;/* If we have 'prev', it's a valid place to start the insertion. */
Signature · 1 line
2.13.4.dirty
Robin Murphy
maintainerPATCH v3 3/4 iommu/iova: Extend rbtree node caching
In reply to Robin MurphyThe cached node mechanism provides a significant performance benefit for allocations using a 32-bit DMA mask, but in the case of non-PCI devices or where the 32-bit space is full, the loss of this benefit can be significant - on large systems there can be many thousands of entries in the tree, such that traversing to the end then walking all the way down to find free space every time becomes increasingly awful.
Maintain a similar cached node for the whole IOVA space as a superset of the 32-bit space so that performance can remain much more consistent.
Inspired by work by Zhen Lei <[email protected]>.
---
v3: Fix potential null dereference on deletion
drivers/iommu/iova.c | 61 ++++++++++++++++++++++++++-------------------------- include/linux/iova.h | 3 ++- 2 files changed, 32 insertions(+), 32 deletions(-)
drivers/iommu/iova.c +30 -31
@@ -46,6 +46,7 @@ init_iova_domain(struct iova_domain *iovad, unsigned long granule,spin_lock_init (&iovad->iova_rbtree_lock); iovad->rbroot =RB_ROOT ; + iovad->cached_node =NULL ; iovad->cached32_node =NULL ; iovad->granule = granule; iovad->start_pfn = start_pfn;
@@ -57,48 +58,48 @@ EXPORT_SYMBOL_GPL(init_iova_domain);static struct rb_node *__get_cached_rbnode (struct iova_domain *iovad,unsigned long *limit_pfn) { -if ((*limit_pfn > iovad->dma_32bit_pfn) || - (iovad->cached32_node ==NULL )) +struct rb_node *cached_node =NULL ; +struct iova *curr_iova; + +if (*limit_pfn <= iovad->dma_32bit_pfn) + cached_node = iovad->cached32_node; +if (!cached_node) + cached_node = iovad->cached_node; +if (!cached_node)return rb_last (&iovad->rbroot); -else { -struct rb_node *prev_node =rb_prev (iovad->cached32_node); -struct iova *curr_iova = - rb_entry(iovad->cached32_node, struct iova, node); - *limit_pfn = curr_iova->pfn_lo; -return prev_node; - } + + curr_iova = rb_entry(cached_node, struct iova, node); + *limit_pfn =min (*limit_pfn, curr_iova->pfn_lo); + +return rb_prev (cached_node); }static void -__cached_rbnode_insert_update (struct iova_domain *iovad, -unsigned long limit_pfn,struct iova *new) +__cached_rbnode_insert_update (struct iova_domain *iovad,struct iova *new) { -if (limit_pfn != iovad->dma_32bit_pfn) -return ; - iovad->cached32_node = &new->node; +if (new->pfn_lo > iovad->dma_32bit_pfn) + iovad->cached_node = &new->node; +else + iovad->cached32_node = &new->node; }static void __cached_rbnode_delete_update (struct iova_domain *iovad,struct iova *free) {struct iova *cached_iova; -struct rb_node *curr; +struct rb_node **curr =NULL ; -if (!iovad->cached32_node) +if (free->pfn_hi < iovad->dma_32bit_pfn) + curr = &iovad->cached32_node; +if (!curr) + curr = &iovad->cached_node; + +if (!*curr)return ; - curr = iovad->cached32_node; - cached_iova = rb_entry(curr, struct iova, node); + cached_iova = rb_entry(*curr, struct iova, node); -if (free->pfn_lo >= cached_iova->pfn_lo) { -struct rb_node *node =rb_next (&free->node); - struct iova *iova = rb_entry(node, struct iova, node); - -/* only cache if it's below 32bit pfn */ -if (node && iova->pfn_lo < iovad->dma_32bit_pfn) - iovad->cached32_node = node; -else - iovad->cached32_node =NULL ; - } +if (free->pfn_lo >= cached_iova->pfn_lo) + *curr =rb_next (&free->node); }/* Insert the iova into domain rbtree by holding writer lock */
@@ -135,7 +136,6 @@ static int __alloc_and_insert_iova_range(struct iova_domain *iovad, {struct rb_node *prev, *curr =NULL ;unsigned long flags; -unsigned long saved_pfn;unsigned long align_mask = ~0UL ;if (size_aligned)
@@ -143,7 +143,6 @@ static int __alloc_and_insert_iova_range(struct iova_domain *iovad,/* Walk the tree backwards */ spin_lock_irqsave (&iovad->iova_rbtree_lock, flags); - saved_pfn = limit_pfn; curr =__get_cached_rbnode (iovad, &limit_pfn); prev = curr;while (curr) {
@@ -173,7 +172,7 @@ static int __alloc_and_insert_iova_range(struct iova_domain *iovad,/* If we have 'prev', it's a valid place to start the insertion. */ iova_insert_rbtree (&iovad->rbroot, new, prev); -__cached_rbnode_insert_update (iovad, saved_pfn, new); +__cached_rbnode_insert_update (iovad, new);spin_unlock_irqrestore (&iovad->iova_rbtree_lock, flags);
include/linux/iova.h +2 -1
@@ -40,7 +40,8 @@ struct iova_rcache {struct iova_domain {spinlock_t iova_rbtree_lock;/* Lock to protect update of rbtree */ struct rb_root rbroot;/* iova domain rbtree root */ -struct rb_node *cached32_node;/* Save last alloced node */ +struct rb_node *cached_node;/* Save last alloced node */ +struct rb_node *cached32_node;/* Save last 32-bit alloced node */ unsigned long granule;/* pfn granularity for this domain */ unsigned long start_pfn;/* Lower limit for this domain */ unsigned long dma_32bit_pfn;
Signature · 1 line
2.13.4.dirty
Robin Murphy
maintainerPATCH v3 4/4 iommu/iova: Make dma_32bit_pfn implicit
In reply to Robin MurphyFrom: Zhen Lei <[email protected]>
Now that the cached node optimisation can apply to all allocations, the couple of users which were playing tricks with dma_32bit_pfn in order to benefit from it can stop doing so. Conversely, there is also no need for all the other users to explicitly calculate a 'real' 32-bit PFN, when init_iova_domain() can happily do that itself from the page granularity.
---
v3: No change
drivers/gpu/drm/tegra/drm.c | 3 +-- drivers/gpu/host1x/dev.c | 3 +-- drivers/iommu/amd_iommu.c | 7 ++----- drivers/iommu/dma-iommu.c | 18 +----------------- drivers/iommu/intel-iommu.c | 11 +++-------- drivers/iommu/iova.c | 4 ++-- drivers/misc/mic/scif/scif_rma.c | 3 +-- include/linux/iova.h | 5 ++--- 8 files changed, 13 insertions(+), 41 deletions(-)
drivers/gpu/drm/tegra/drm.c +1 -2
@@ -150,8 +150,7 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags) order =__ffs (tegra->domain->pgsize_bitmap);init_iova_domain (&tegra->carveout.domain,1UL << order, - carveout_start >> order, - carveout_end >> order); + carveout_start >> order); tegra->carveout.shift =iova_shift (&tegra->carveout.domain); tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
drivers/gpu/host1x/dev.c +1 -2
@@ -193,8 +193,7 @@ static int host1x_probe(struct platform_device *pdev) order =__ffs (host->domain->pgsize_bitmap);init_iova_domain (&host->iova,1UL << order, - geometry->aperture_start >> order, - geometry->aperture_end >> order); + geometry->aperture_start >> order); host->iova_end = geometry->aperture_end; }
drivers/iommu/amd_iommu.c +2 -5
@@ -63,7 +63,6 @@/* IO virtual address start page frame number */ #define IOVA_START_PFN (1)#define IOVA_PFN (addr) ((addr) >> PAGE_SHIFT) -#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))/* Reserved IOVA ranges */ #define MSI_RANGE_START (0xfee00000)
@@ -2010,8 +2009,7 @@ static struct dma_ops_domain *dma_ops_domain_alloc(void)if (!dma_dom->domain.pt_root) goto free_dma_dom; -init_iova_domain (&dma_dom->iovad,PAGE_SIZE , -IOVA_START_PFN ,DMA_32BIT_PFN ); +init_iova_domain (&dma_dom->iovad,PAGE_SIZE ,IOVA_START_PFN );/* Initialize reserved ranges */ copy_reserved_iova (&reserved_iova_ranges, &dma_dom->iovad);
@@ -2912,8 +2910,7 @@ static int init_reserved_iova_ranges(void)struct pci_dev *pdev =NULL ;struct iova *val; -init_iova_domain (&reserved_iova_ranges,PAGE_SIZE , -IOVA_START_PFN ,DMA_32BIT_PFN ); +init_iova_domain (&reserved_iova_ranges,PAGE_SIZE ,IOVA_START_PFN );lockdep_set_class (&reserved_iova_ranges.iova_rbtree_lock, &reserved_rbtree_key);
drivers/iommu/dma-iommu.c +1 -17
@@ -292,18 +292,7 @@ int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base,/* ...then finally give it a kicking to make sure it fits */ base_pfn = max_t(unsigned long, base_pfn, domain->geometry.aperture_start >> order); - end_pfn = min_t(unsigned long, end_pfn, - domain->geometry.aperture_end >> order); } -/* -* PCI devices may have larger DMA masks, but still prefer allocating -* within a 32-bit mask to avoid DAC addressing. Such limitations don't -* apply to the typical platform device, so for those we may as well -* leave the cache limit at the top of their range to save an rb_last() -* traversal on every allocation. -*/ -if (dev &&dev_is_pci (dev)) - end_pfn &=DMA_BIT_MASK (32 ) >> order;/* start_pfn is always nonzero for an already-initialised domain */ if (iovad->start_pfn) {
@@ -312,16 +301,11 @@ int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base,pr_warn ("Incompatible range for DMA domain\n" );return -EFAULT ; } -/* -* If we have devices with different DMA masks, move the free -* area cache limit down for the benefit of the smaller one. -*/ - iovad->dma_32bit_pfn =min (end_pfn +1 , iovad->dma_32bit_pfn);return 0 ; } -init_iova_domain (iovad,1UL << order, base_pfn, end_pfn); +init_iova_domain (iovad,1UL << order, base_pfn);if (!dev)return 0 ;
drivers/iommu/intel-iommu.c +3 -8
@@ -82,8 +82,6 @@#define IOVA_START_PFN (1)#define IOVA_PFN (addr) ((addr) >> PAGE_SHIFT) -#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32)) -#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))/* page table handling */ #define LEVEL_STRIDE (9)
@@ -1874,8 +1872,7 @@ static int dmar_init_reserved_ranges(void)struct iova *iova;int i; -init_iova_domain (&reserved_iova_list,VTD_PAGE_SIZE ,IOVA_START_PFN , -DMA_32BIT_PFN ); +init_iova_domain (&reserved_iova_list,VTD_PAGE_SIZE ,IOVA_START_PFN );lockdep_set_class (&reserved_iova_list.iova_rbtree_lock, &reserved_rbtree_key);
@@ -1933,8 +1930,7 @@ static int domain_init(struct dmar_domain *domain, struct intel_iommu *iommu,int adjust_width, agaw;unsigned long sagaw; -init_iova_domain (&domain->iovad,VTD_PAGE_SIZE ,IOVA_START_PFN , -DMA_32BIT_PFN ); +init_iova_domain (&domain->iovad,VTD_PAGE_SIZE ,IOVA_START_PFN );domain_reserve_special_ranges (domain);/* calculate AGAW */
@@ -4989,8 +4985,7 @@ static int md_domain_init(struct dmar_domain *domain, int guest_width) {int adjust_width; -init_iova_domain (&domain->iovad,VTD_PAGE_SIZE ,IOVA_START_PFN , -DMA_32BIT_PFN ); +init_iova_domain (&domain->iovad,VTD_PAGE_SIZE ,IOVA_START_PFN );domain_reserve_special_ranges (domain);/* calculate AGAW */
drivers/iommu/iova.c +2 -2
@@ -35,7 +35,7 @@ static void free_iova_rcaches(struct iova_domain *iovad);void init_iova_domain (struct iova_domain *iovad,unsigned long granule, -unsigned long start_pfn,unsigned long pfn_32bit) +unsigned long start_pfn) {/* * IOVA granularity will normally be equal to the smallest
@@ -50,7 +50,7 @@ init_iova_domain(struct iova_domain *iovad, unsigned long granule, iovad->cached32_node =NULL ; iovad->granule = granule; iovad->start_pfn = start_pfn; - iovad->dma_32bit_pfn = pfn_32bit +1 ; + iovad->dma_32bit_pfn =1UL << (32 -iova_shift (iovad));init_iova_rcaches (iovad); }EXPORT_SYMBOL_GPL (init_iova_domain);
drivers/misc/mic/scif/scif_rma.c +1 -2
@@ -39,8 +39,7 @@ void scif_rma_ep_init(struct scif_endpt *ep)struct scif_endpt_rma_info *rma = &ep->rma_info;mutex_init (&rma->rma_lock); -init_iova_domain (&rma->iovad,PAGE_SIZE ,SCIF_IOVA_START_PFN , -SCIF_DMA_64BIT_PFN ); +init_iova_domain (&rma->iovad,PAGE_SIZE ,SCIF_IOVA_START_PFN );spin_lock_init (&rma->tc_lock);mutex_init (&rma->mmn_lock);INIT_LIST_HEAD (&rma->reg_list);
include/linux/iova.h +2 -3
@@ -102,7 +102,7 @@ struct iova *reserve_iova(struct iova_domain *iovad, unsigned long pfn_lo, unsigned long pfn_hi);void copy_reserved_iova (struct iova_domain *from,struct iova_domain *to);void init_iova_domain (struct iova_domain *iovad,unsigned long granule, -unsigned long start_pfn,unsigned long pfn_32bit); +unsigned long start_pfn);struct iova *find_iova (struct iova_domain *iovad,unsigned long pfn);void put_iova_domain (struct iova_domain *iovad); struct iova *split_and_remove_iova(struct iova_domain *iovad,
@@ -170,8 +170,7 @@ static inline void copy_reserved_iova(struct iova_domain *from,static inline void init_iova_domain (struct iova_domain *iovad,unsigned long granule, -unsigned long start_pfn, -unsigned long pfn_32bit) +unsigned long start_pfn) { }
Signature · 1 line
2.13.4.dirty
Hi Robin,
Quoted 3 lines · Robin Murphy
Hi all,
Just a quick repost of v2[1] with a small fix for the bug reported by Nate.
I tested the series and can confirm that the crash I reported on v2 no longer occurs with this version.
Quoted 6 lines
To recap, whilst this mostly only improves worst-case performance, those worst-cases have a tendency to be pathologically bad:
Ard reports general desktop performance with Chromium on AMD Seattle going from ~1-2FPS to perfectly usable.
Quoted 8 lines
Leizhen reports gigabit ethernet throughput going from ~6.5Mbit/s to line speed.
I also inadvertantly found that the HiSilicon
hns_dsafdriver was taking ~35s to probe simply becuase of the number of DMA buffers it maps on startup (perf shows around 76% of that was spent under the lock inalloc_iova()). With this series applied it takes a mere ~1s, mostly of unrelated mdelay()s, withalloc_iova()entirely lost in the noise.
Are any of these cases PCI devices attached to domains that have run out of 32-bit IOVAs and have to retry the allocation using dma_limit?
iommu_dma_alloc_iova() {
[...]
if (dma_limit > DMA_BIT_MASK(32) && dev_is_pci(dev)) [<- TRUE]
iova = alloc_iova_fast(DMA_BIT_MASK(32)); [<- NULL]
if (!iova)
iova = alloc_iova_fast(dma_limit); [<- OK ]
[...]
}I am asking because, when using 64k pages, the Mellanox CX4 adapter exhausts the supply 32-bit IOVAs simply allocating per-cpu IOVA space during 'ifconfig up' so the code path outlined above is taken for nearly all subsequent allocations. Although I do see a notable (~2x) performance improvement with this series, I would still characterize it as "pathologically bad" at < 10% of iommu passthrough performance.
This was a bit surprising to me as I thought the iova_rcache would have eliminated the need to walk the rbtree for runtime allocations. Unfortunately, it looks like the failed attempt to allocate a 32-bit IOVA actually drops the cached IOVAs that we could have used when subsequently performing the allocation at dma_limit.
alloc_iova_fast() {
[...]
iova_pfn = iova_rcache_get(...); [<- Fail, no 32-bit IOVAs]
if (iova_pfn)
return iova_pfn;retry:
new_iova = alloc_iova(...); [<- Fail, no 32-bit IOVAs]
if (!new_iova) {
unsigned int cpu;
if (flushed_rcache)
return 0;
/* Try replenishing IOVAs by flushing rcache. */
flushed_rcache = true;
for_each_online_cpu(cpu)
free_cpu_cached_iovas(cpu, iovad); [<- :( ]
goto retry;
}
}As an experiment, I added code to skip the rcache flushing/retry for the 32-bit allocations. In this configuration, 100% of passthrough mode performance was achieved. I made the same change in the baseline and measured performance at ~95% of passthrough mode.
I also got similar results by altogether removing the 32-bit allocation from iommu_dma_alloc_iova() which makes me wonder why we even bother. What (PCIe) workloads have been shown to actually benefit from it?
-Nate
Quoted 23 lines
Robin.
Robin Murphy (1):
iommu/iova: Extend rbtree node cachingZhen Lei (3):
iommu/iova: Optimise rbtree searching
iommu/iova: Optimise the padding calculation
iommu/iova: Makedma_32bit_pfnimplicitdrivers/gpu/drm/tegra/drm.c | 3 +- drivers/gpu/host1x/dev.c | 3 +- drivers/iommu/amd_iommu.c | 7 +-- drivers/iommu/dma-iommu.c | 18 +------ drivers/iommu/intel-iommu.c | 11 ++-- drivers/iommu/iova.c | 114 +++++++++++++++++---------------------- drivers/misc/mic/scif/scif_rma.c | 3 +- include/linux/iova.h | 8 +-- 8 files changed, 62 insertions(+), 105 deletions(-)
Signature · 2 lines
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
Joerg Roedel
maintainerHey Robin, Nate,
Quoted 1 line · Nate Watterson
Tested-by Nate Watterson <[email protected]>
If nobody has objections here anymore I would merge these patches when v4.14-rc1 is released. Given that these changes are a bit more intrusive and the code is shared between a couple of drivers, I'd like to give it more testing in linux-next.
Robin, can you rebase these patches to v4.14-rc1 when it is released, add Nate's Tested-by, and resend them to me please?
Thanks,
Joerg