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ARC: clk: introduce HSDK pll driver

PATCH Applied Eugeniy Paltsev 3 participants 3 messages Aug 25, 2017 – Aug 31, 2017

Subsystems (4)
Device tree bindings Common clk Synopsys ARC architecture Synopsys ARC hsdk sdp pll clock driver
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Eugeniy Paltsev

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#0 lore raw

PATCH v4 1/1 ARC: clk: introduce HSDK pll driver

HSDK board manages its clocks using various PLLs. These PLL have same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs.

Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers.

We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value.

As of today we add support for PLLs that generate clock for the HSDK arc cpus, system, ddr, AXI tunnel and hdmi.

By this patch we add support for several plls (arc cpus pll and others), so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll and regular probing for others plls.

Signed-off-by Eugeniy Paltsev <[email protected]>

---
Changes v3 -> v4:
* Rename HSDKv1 to HSDK

Changes v2 -> v3:
* Add special management of arc core interface divider.

Changes v1 -> v2:
* Remove all MODULE* defines as this driver can't be build as module.
* Simplified hsdk_pll_is_err and hsdk_pll_is_locked functions.
* Use unsigned long fo best_rate in hsdk_pll_round_rate.
* Use of_clk_get_parent_count to get num_parents.
* Other small changes.

 .../bindings/clock/snps,hsdk-pll-clock.txt         |  28 ++
 MAINTAINERS                                        |   6 +
 drivers/clk/Kconfig                                |   7 +
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clk-hsdk-pll.c                         | 431 +++++++++++++++++++++
 5 files changed, 473 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt
 create mode 100644 drivers/clk/clk-hsdk-pll.c
Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt new file +28 -0
new file mode 100644
index 0000000..c56c755
@@ -0,0 +1,28 @@
+Binding for the HSDK Generic PLL clock
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: should be "snps,hsdk-<name>-pll-clock"
+  "snps,hsdk-core-pll-clock"
+  "snps,hsdk-gp-pll-clock"
+  "snps,hsdk-hdmi-pll-clock"
+- reg : should contain base register location and length.
+- clocks: shall be the input parent clock phandle for the PLL.
+- #clock-cells: from common clock binding; Should always be set to 0.
+
+Example:
+	input_clk: input-clk {
+		clock-frequency = <33333333>;
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+	};
+
+	cpu_clk: cpu-clk@0 {
+		compatible = "snps,hsdk-core-pll-clock";
+		reg = <0x00 0x10>;
+		#clock-cells = <0>;
+		clocks = <&input_clk>;
+	};
MAINTAINERS +6 -0
index 7c62dff..412b2d7 100644
@@ -12744,6 +12744,12 @@ F:	drivers/clocksource/arc_timer.c
 F:	drivers/tty/serial/arc_uart.c
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git
 
+SYNOPSYS ARC HSDK SDP pll clock driver
+M:	Eugeniy Paltsev <[email protected]>
+S:	Supported
+F:	drivers/clk/clk-hsdk-pll.c
+F:	Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt
+
 SYNOPSYS ARC SDP clock driver
 M:	Eugeniy Paltsev <[email protected]>
 S:	Supported
drivers/clk/Kconfig +7 -0
index a874b72..fdc9908 100644
@@ -31,6 +31,13 @@ config COMMON_CLK_WM831X
 
 source "drivers/clk/versatile/Kconfig"
 
+config CLK_HSDK
+	bool "PLL Driver for HSDK platform"
+	depends on OF || COMPILE_TEST
+	---help---
+	  This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
+	  control.
+
 config COMMON_CLK_MAX77686
 	tristate "Clock driver for Maxim 77620/77686/77802 MFD"
 	depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
drivers/clk/Makefile +1 -0
index cd376b3..72e7c0e 100644
@@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CS2000_CP)	+= clk-cs2000-cp.o
 obj-$(CONFIG_ARCH_EFM32)		+= clk-efm32gg.o
 obj-$(CONFIG_COMMON_CLK_GEMINI)		+= clk-gemini.o
 obj-$(CONFIG_ARCH_HIGHBANK)		+= clk-highbank.o
+obj-$(CONFIG_CLK_HSDK)			+= clk-hsdk-pll.o
 obj-$(CONFIG_COMMON_CLK_MAX77686)	+= clk-max77686.o
 obj-$(CONFIG_ARCH_MB86S7X)		+= clk-mb86s7x.o
 obj-$(CONFIG_ARCH_MOXART)		+= clk-moxart.o
drivers/clk/clk-hsdk-pll.c new file +431 -0

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Signature · 1 line
2.9.3
Reviewed-by on v4 1/1
#1 lore raw
Quoted 32 lines · Eugeniy Paltsev

HSDK board manages its clocks using various PLLs. These PLL have same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs.

Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers.

We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value.

As of today we add support for PLLs that generate clock for the HSDK arc cpus, system, ddr, AXI tunnel and hdmi.

By this patch we add support for several plls (arc cpus pll and others), so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll and regular probing for others plls.

Signed-off-by Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>

---
Changes v3 -> v4:
* Rename HSDKv1 to HSDK

Changes v2 -> v3:
* Add special management of arc core interface divider.

Changes v1 -> v2:
* Remove all MODULE* defines as this driver can't be build as module.
* Simplified hsdk_pll_is_err and hsdk_pll_is_locked functions.
* Use unsigned long fo best_rate in hsdk_pll_round_rate.
* Use of_clk_get_parent_count to get num_parents.
* Other small changes.

Quoted 8 lines
  .../bindings/clock/snps,hsdk-pll-clock.txt         |  28 ++
  MAINTAINERS                                        |   6 +
  drivers/clk/Kconfig                                |   7 +
  drivers/clk/Makefile                               |   1 +
  drivers/clk/clk-hsdk-pll.c                         | 431 +++++++++++++++++++++
  5 files changed, 473 insertions(+)

create mode 100644 Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt create mode 100644 drivers/clk/clk-hsdk-pll.c

Reviewed-by Vineet Gupta <vgupta at synopsys.com>

P.S. Stephen I'd be nice if this can make it into 4.14 as we are slated to add the hasdk platform support in there.

Thx,
-Vineet

Applied
#2 lore raw
In reply to Eugeniy Paltsev
Quoted 13 lines · Eugeniy Paltsev

HSDK board manages its clocks using various PLLs. These PLL have same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs.

Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers.

We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value.

As of today we add support for PLLs that generate clock for the HSDK arc cpus, system, ddr, AXI tunnel and hdmi.

Quoted 6 lines

By this patch we add support for several plls (arc cpus pll and others), so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll and regular probing for others plls.

Signed-off-by Eugeniy Paltsev <[email protected]>

---

Applied to clk-next

Signature · 2 lines
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