x86/perf: Enable free running pebs for REGS_USER/INTR
Subsystems (2)
PATCH 1/1 x86/perf: Enable free running pebs for REGS_USER/INTR
From: Andi Kleen <[email protected]>
Currently free running PEBS is disabled when user or interrupt registers are requested. Most of the registers are actually available in the PEBS record and can be supported.
So we just need to check for the supported registers and then allow it: it is all except for the segment register.
For user registers this only works when the counter is limited to ring 3 only, so this also needs to be checked.
Signed-off-by Andi Kleen <[email protected]>
--- arch/x86/events/intel/core.c | 4 ++++ arch/x86/events/perf_event.h | 24 +++++++++++++++++++++++- 2 files changed, 27 insertions(+), 1 deletion(-)
arch/x86/events/intel/core.c +4 -0
@@ -2958,6 +2958,10 @@ static unsigned long intel_pmu_free_running_flags(struct perf_event *event)if (event->attr.use_clockid) flags &= ~PERF_SAMPLE_TIME ; +if (!event->attr.exclude_kernel) + flags &= ~PERF_SAMPLE_REGS_USER ; +if (event->attr.sample_regs_user & ~PEBS_REGS ) + flags &= ~(PERF_SAMPLE_REGS_USER |PERF_SAMPLE_REGS_INTR );return flags; }
arch/x86/events/perf_event.h +23 -1
@@ -85,13 +85,15 @@ struct amd_nb {* Flags PEBS can handle without an PMI. * * TID can only be handled by flushing at context switch. +* REGS_USER can be handled for events limited to ring 3. * */ #define PEBS_FREERUNNING_FLAGS \ (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ - PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR) + PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ + PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER)/* * A debug store configuration.
@@ -110,6 +112,26 @@ struct debug_store {u64 pebs_event_reset[MAX_PEBS_EVENTS ]; }; +#define PEBS_REGS \ + (PERF_REG_X86_AX | \ + PERF_REG_X86_BX | \ + PERF_REG_X86_CX | \ + PERF_REG_X86_DX | \ + PERF_REG_X86_DI | \ + PERF_REG_X86_SI | \ + PERF_REG_X86_SP | \ + PERF_REG_X86_BP | \ + PERF_REG_X86_IP | \ + PERF_REG_X86_FLAGS | \ + PERF_REG_X86_R8 | \ + PERF_REG_X86_R9 | \ + PERF_REG_X86_R10 | \ + PERF_REG_X86_R11 | \ + PERF_REG_X86_R12 | \ + PERF_REG_X86_R13 | \ + PERF_REG_X86_R14 | \ + PERF_REG_X86_R15) +/* * Per register state. */
Signature · 1 line
2.9.5
tip-bot for Andi Kleen
merge bot[tip:perf/core] perf/x86: Enable free running PEBS for REGS_USER/INTR
perf/x86: Enable free running PEBS for REGS_USER/INTR
Commit-ID: a47ba4d77e1236d214e5116b5631bc4c2d6e6369 Gitweb: https://git.kernel.org/tip/a47ba4d77e1236d214e5116b5631bc4c2d6e6369 Author: Andi Kleen <[email protected]> AuthorDate: Thu, 31 Aug 2017 14:46:30 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Fri, 29 Sep 2017 13:28:31 +0200
perf/x86: Enable free running PEBS for REGS_USER/INTR
Currently free running PEBS is disabled when user or interrupt registers are requested. Most of the registers are actually available in the PEBS record and can be supported.
So we just need to check for the supported registers and then allow it: it is all except for the segment register.
For user registers this only works when the counter is limited to ring 3 only, so this also needs to be checked.
Signed-off-by Andi Kleen <[email protected]>
Signed-off-by Peter Zijlstra (Intel) <[email protected]>
Cc Linus Torvalds <[email protected]>
Cc Peter Zijlstra <[email protected]>
Cc Thomas Gleixner <[email protected]>
Signed-off-by Ingo Molnar <[email protected]>
--- arch/x86/events/intel/core.c | 4 ++++ arch/x86/events/perf_event.h | 24 +++++++++++++++++++++++- 2 files changed, 27 insertions(+), 1 deletion(-)
arch/x86/events/intel/core.c +4 -0
@@ -2958,6 +2958,10 @@ static unsigned long intel_pmu_free_running_flags(struct perf_event *event)if (event->attr.use_clockid) flags &= ~PERF_SAMPLE_TIME ; +if (!event->attr.exclude_kernel) + flags &= ~PERF_SAMPLE_REGS_USER ; +if (event->attr.sample_regs_user & ~PEBS_REGS ) + flags &= ~(PERF_SAMPLE_REGS_USER |PERF_SAMPLE_REGS_INTR );return flags; }
arch/x86/events/perf_event.h +23 -1
@@ -85,13 +85,15 @@ struct amd_nb {* Flags PEBS can handle without an PMI. * * TID can only be handled by flushing at context switch. +* REGS_USER can be handled for events limited to ring 3. * */ #define PEBS_FREERUNNING_FLAGS \ (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ - PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR) + PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ + PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER)/* * A debug store configuration.
@@ -110,6 +112,26 @@ struct debug_store {u64 pebs_event_reset[MAX_PEBS_EVENTS ]; }; +#define PEBS_REGS \ + (PERF_REG_X86_AX | \ + PERF_REG_X86_BX | \ + PERF_REG_X86_CX | \ + PERF_REG_X86_DX | \ + PERF_REG_X86_DI | \ + PERF_REG_X86_SI | \ + PERF_REG_X86_SP | \ + PERF_REG_X86_BP | \ + PERF_REG_X86_IP | \ + PERF_REG_X86_FLAGS | \ + PERF_REG_X86_R8 | \ + PERF_REG_X86_R9 | \ + PERF_REG_X86_R10 | \ + PERF_REG_X86_R11 | \ + PERF_REG_X86_R12 | \ + PERF_REG_X86_R13 | \ + PERF_REG_X86_R14 | \ + PERF_REG_X86_R15) +/* * Per register state. */