ARM: dts: iwg22d-sodimm: Add Ethernet AVB support

PATCH New Biju Das 4 participants 6 messages Aug 30, 2017 – Sep 1, 2017 Device tree bindings

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Biju Das

author

2017-08-30 15:17 UTC #0 lore raw

PATCH 1/1 ARM: dts: iwg22d-sodimm: Add Ethernet AVB support

Define the iWave RainboW-G22D board dependent part of the Ethernet AVB device node.

On some older versions of the platform (before R4.0) the phy address may be 1 or 3. The address is fixed to 3 for R4.0 onwards (which will be the first mainstream release), hence using 3 in the dts.

Signed-off-by Biju Das <[email protected]>

Signed-off-by Chris Paterson <[email protected]>

---
This patch is tested against renesas-dev tag 20170830-v4.13-rc7

 arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +26 -0

index 442a5cb..aac84c6 100644
@@ -17,9 +17,11 @@
 
 	aliases {
 		serial0 = &scif4;
+		ethernet0 = &avb;
 	};
 
 	chosen {
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
 		stdout-path = "serial0:115200n8";
 	};
 };

@@ -29,6 +31,11 @@
 		groups = "scif4_data_b";
 		function = "scif4";
 	};
+
+	avb_pins: avb {
+		groups = "avb_mdio", "avb_gmii";
+		function = "avb";
+	};
 };
 
 &scif4 {

@@ -37,3 +44,22 @@
 
 	status = "okay";
 };
+
+&avb {
+	pinctrl-0 = <&avb_pins>;
+	pinctrl-names = "default";
+
+	phy-handle = <&phy3>;
+	phy-mode = "gmii";
+	renesas,no-ether-link;
+	status = "okay";
+
+	phy3: ethernet-phy at 3 {
+	/*
+	 * On some older versions of the platform (before R4.0) the phy address
+	 * may be 1 or 3. The address is fixed to 3 for R4.0 onwards.
+	 */
+		reg = <3>;
+		micrel,led-mode = <1>;
+	};
+};

Signature · 1 line

1.9.1

Simon Horman

2017-08-31 08:45 UTC #1 lore raw

PATCH 1/1 ARM: dts: iwg22d-sodimm: Add Ethernet AVB support

Quoted 54 lines · Biju Das

Define the iWave RainboW-G22D board dependent part of the Ethernet AVB device node.
On some older versions of the platform (before R4.0) the phy address may be 1 or 3. The address is fixed to 3 for R4.0 onwards (which will be the first mainstream release), hence using 3 in the dts.
Signed-off-by Biju Das <[email protected]>
Signed-off-by Chris Paterson <[email protected]>
---
This patch is tested against renesas-dev tag 20170830-v4.13-rc7
 arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +14 -0
index 442a5cb..aac84c6 100644
@@ -17,9 +17,11 @@
 
 	aliases {
 		serial0 = &scif4;
+		ethernet0 = &avb;
 	};
 
 	chosen {
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
 		stdout-path = "serial0:115200n8";
 	};
 };
@@ -29,6 +31,11 @@
 		groups = "scif4_data_b";
 		function = "scif4";
 	};
+
+	avb_pins: avb {
+		groups = "avb_mdio", "avb_gmii";
+		function = "avb";
+	};
 };
 
 &scif4 {
@@ -37,3 +44,22 @@
 
 	status = "okay";
 };
+
+&avb {
+	pinctrl-0 = <&avb_pins>;
+	pinctrl-names = "default";
+
+	phy-handle = <&phy3>;
+	phy-mode = "gmii";

arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts line 63

Quoted 10 lines

arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +10 -0

+	renesas,no-ether-link;
+	status = "okay";
+
+	phy3: ethernet-phy at 3 {
+	/*
+	 * On some older versions of the platform (before R4.0) the phy address
+	 * may be 1 or 3. The address is fixed to 3 for R4.0 onwards.
+	 */
+		reg = <3>;
+		micrel,led-mode = <1>;

Does the phy have an interrupt?

Quoted 5 lines

arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +2 -0
+	};
+};
Signature · 1 line
1.9.1

Biju Das

author

2017-08-31 09:24 UTC #2 lore raw

PATCH 1/1 ARM: dts: iwg22d-sodimm: Add Ethernet AVB support

Quoted 77 lines

-----Original Message-----
From: Simon Horman [mailto:horms at verge.net.au]
Sent: 31 August 2017 09:46
To: Biju Das <[email protected]>
Cc: Rob Herring <[email protected]>; Mark Rutland <[email protected]>; Magnus Damm <[email protected]>; Russell King <[email protected]>; Chris Paterson <[email protected]>; devicetree at vger.kernel.org; linux-renesas- soc at vger.kernel.org; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH ] ARM: dts: iwg22d-sodimm: Add Ethernet AVB support
Quoted 52 lines · Biju Das
Define the iWave RainboW-G22D board dependent part of the Ethernet AVB device node.
On some older versions of the platform (before R4.0) the phy address may be 1 or 3. The address is fixed to 3 for R4.0 onwards (which will be the first mainstream release), hence using 3 in the dts.
Signed-off-by Biju Das <[email protected]>
Signed-off-by Chris Paterson <[email protected]>
---
This patch is tested against renesas-dev tag 20170830-v4.13-rc7
 arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 26
++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +10 -0
index 442a5cb..aac84c6 100644
@@ -17,9 +17,11 @@
 
 aliases {
 serial0 = &scif4;
+ethernet0 = &avb;
 };
 
 chosen {
+bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
 stdout-path = "serial0:115200n8";
 };
 };
@@ -29,6 +31,11 @@
 groups = "scif4_data_b";
 function = "scif4";
 };
+
+avb_pins: avb {
+groups = "avb_mdio", "avb_gmii";
+function = "avb";
+};
 };
 
 &scif4 {
@@ -37,3 +44,22 @@
 
 status = "okay";
 };
+
+&avb {
+pinctrl-0 = <&avb_pins>;
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts line 59
Quoted 10 lines
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +10 -0
+pinctrl-names = "default";
+
+phy-handle = <&phy3>;
+phy-mode = "gmii";
+renesas,no-ether-link;
+status = "okay";
+
+phy3: ethernet-phy at 3 {
+/*
+ * On some older versions of the platform (before R4.0) the phy
address

Quoted 6 lines

arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts line 63
Quoted 4 lines
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +4 -0
+ * may be 1 or 3. The address is fixed to 3 for R4.0 onwards.
+ */
+reg = <3>;
+micrel,led-mode = <1>;
Does the phy have an interrupt?

The current board doesn't support interrupt . But there is a plan to support this in future board variants through (GPIO3_28).

Quoted 5 lines

Quoted 5 lines
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +2 -1
+};
+};
--
1.9.1

Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

Chris Paterson

2017-08-31 09:32 UTC #3 lore raw

PATCH 1/1 ARM: dts: iwg22d-sodimm: Add Ethernet AVB support

Hello,

Quoted 5 lines

From: Biju Das
Sent: 31 August 2017 10:24
Quoted 2 lines
From: Simon Horman [mailto:horms at verge.net.au]
Sent: 31 August 2017 09:46

<snip>

Quoted 11 lines

Quoted 10 lines
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
Quoted 3 lines
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +3 -0
+	phy3: ethernet-phy at 3 {
+	/*
+	 * On some older versions of the platform (before R4.0) the phy
address
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts line 63
Quoted 4 lines
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +4 -0
+	 * may be 1 or 3. The address is fixed to 3 for R4.0 onwards.
+	 */
+		reg = <3>;
+		micrel,led-mode = <1>;
Does the phy have an interrupt?

Quoted 2 lines

The current board doesn't support interrupt . But there is a plan to support this in future board variants through (GPIO3_28).

Actually, the plan has recently changed and at the moment interrupt support will not be added in the production version of the board.

If in the end the plan changes again and the actual hardware does add interrupt support we'll submit a new patch accordingly.

Kind regards, Chris

Simon Horman

2017-09-01 08:49 UTC #4 lore raw

PATCH 1/1 ARM: dts: iwg22d-sodimm: Add Ethernet AVB support

Quoted 21 lines · Chris Paterson

Hello,
Quoted 5 lines
From: Biju Das
Sent: 31 August 2017 10:24
Quoted 2 lines
From: Simon Horman [mailto:horms at verge.net.au]
Sent: 31 August 2017 09:46
<snip>
Quoted 11 lines
Quoted 10 lines
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
Quoted 3 lines
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +3 -0
+	phy3: ethernet-phy at 3 {
+	/*
+	 * On some older versions of the platform (before R4.0) the phy
address
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts line 63
Quoted 4 lines
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +4 -0
+	 * may be 1 or 3. The address is fixed to 3 for R4.0 onwards.
+	 */
+		reg = <3>;
+		micrel,led-mode = <1>;
Does the phy have an interrupt?

Quoted 6 lines

Quoted 2 lines
The current board doesn't support interrupt . But there is a plan to support this in future board variants through (GPIO3_28).
Actually, the plan has recently changed and at the moment interrupt support will not be added in the production version of the board.
If in the end the plan changes again and the actual hardware does add interrupt support we'll submit a new patch accordingly.

Thanks for following-up on this. I'm still surprised there is no interrupt
- does link speed renegotiation initiated by the other end of the link work in a timely manner? - but if its not there and my wishful thinking won't make it so.

I have applied this patch for v4.15.

Geert Uytterhoeven

2017-09-01 09:30 UTC #5 lore raw

PATCH 1/1 ARM: dts: iwg22d-sodimm: Add Ethernet AVB support

Hi Simon,

Quoted 17 lines · Simon Horman

Quoted 16 lines · Chris Paterson
Quoted 15 lines
From: Biju Das
Quoted 11 lines
From: Simon Horman [mailto:horms at verge.net.au]
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
Quoted 3 lines
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +3 -0
+       phy3: ethernet-phy at 3 {
+       /*
+        * On some older versions of the platform (before R4.0) the phy
address
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts line 63
Quoted 4 lines
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +4 -0
+        * may be 1 or 3. The address is fixed to 3 for R4.0 onwards.
+        */
+               reg = <3>;
+               micrel,led-mode = <1>;
Does the phy have an interrupt?
The current board doesn't support interrupt . But there is a plan to support this in future board variants through (GPIO3_28).

Quoted 8 lines

Quoted 3 lines
Actually, the plan has recently changed and at the moment interrupt support will not be added in the production version of the board.
If in the end the plan changes again and the actual hardware does add interrupt support we'll submit a new patch accordingly.
Thanks for following-up on this. I'm still surprised there is no interrupt
- does link speed renegotiation initiated by the other end of the link work in a timely manner? - but if its not there and my wishful thinking won't make it so.

I guess it behaves similar to Koelsch using the new CPG/MSSR driver, and without the probe deferral fix for of_mdio, where it also falls back to polling. Cfr. the figures in
https://www.mail-archive.com/linux-renesas-soc at vger.kernel.org/msg17422.html

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds