clk: at91: utmi: Fix to set the main clock
cover clk: at91: utmi: Fix to set the main clock
The source clock of the UTMI PLL is the main clock (MAINCK). The MAINCK must select the fast crystal oscillator to meet the frequency accuracy required by USB.
The crystal frequency selection among 12, 16, 24 MHz must be configured to the correct value in the field SFR_UTMICKTRIM.FREQ, in order to apply the correct multiplier, x40, x30 or x20, respectively. By default, it is assumed that the UTMI clock is generated from a 12 MHz MAINCK.
Wenyou Yang (2):
clk: at91: utmi: Set the reference clock frequency
ARM: dts: at91: sama5: Add the sfr node
arch/arm/dts/sama5d2.dtsi | 6 +++ arch/arm/dts/sama5d3.dtsi | 2 + arch/arm/mach-at91/include/mach/sama5_sfr.h | 5 ++ drivers/clk/at91/Kconfig | 4 ++ drivers/clk/at91/clk-utmi.c | 77 ++++++++++++++++++++++++++++- drivers/clk/at91/pmc.h | 3 ++ 6 files changed, 95 insertions(+), 2 deletions(-)
Signature · 1 line
2.13.0
PATCH 1/2 clk: at91: utmi: Set the reference clock frequency
By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the proper way.
The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz.
The patch is cloned from the patch of mailing-list:
[PATCH v2] clk: at91: utmi: set the mainck rate
---
arch/arm/mach-at91/include/mach/sama5_sfr.h | 5 ++ drivers/clk/at91/Kconfig | 4 ++ drivers/clk/at91/clk-utmi.c | 77 ++++++++++++++++++++++++++++- drivers/clk/at91/pmc.h | 3 ++ 4 files changed, 87 insertions(+), 2 deletions(-)
arch/arm/mach-at91/include/mach/sama5_sfr.h +5 -0
@@ -28,6 +28,9 @@ struct atmel_sfr {u32 l2cc_hramc;/* 0x58 */ }; +/* Register Mapping*/ +#define AT91_SFR_UTMICKTRIM 0x30/* UTMI Clock Trimming Register */ +/* Bit field in DDRCFG */ #define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000
@@ -56,6 +59,8 @@ struct atmel_sfr {#define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12)#define AT91_SFR_EBICFG_SCH1_ON (0x1 << 12) +#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0) +/* Bit field in AICREDIR */ #define ATMEL_SFR_AICREDIR_NSAIC 0x00000001
drivers/clk/at91/Kconfig +4 -0
@@ -15,6 +15,10 @@ config CLK_AT91 config AT91_UTMI bool "Support UTMI PLL Clock" depends on CLK_AT91 + select REGMAP + select SPL_REGMAP + select SYSCON + select SPL_SYSCON help This option is used to enable the AT91 UTMI PLL clock driver. It is the clock provider of USB, and UPLLCK is the
drivers/clk/at91/clk-utmi.c +75 -2
117 lines not on this page · raw message
drivers/clk/at91/pmc.h +3 -0
@@ -8,8 +8,11 @@#ifndef __AT91_PMC_H__#define __AT91_PMC_H__ +#include <regmap.h> +struct pmc_platdata {struct at91_pmc *reg_base; +struct regmap *regmap_sfr; };int at91_pmc_core_probe (struct udevice *dev);
Signature · 1 line
2.13.0
PATCH 1/2 clk: at91: utmi: Set the reference clock frequency
Quoted 50 lines · Wenyou Yang
By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the
SFR_UTMICKTRIMhas to be updated to generate the UTMI clock in the proper way.The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz.
The patch is cloned from the patch of mailing-list:
[PATCH v2] clk: at91: utmi: set the mainck rateSigned-off-by Wenyou Yang <[email protected]>---
arch/arm/mach-at91/include/mach/sama5_sfr.h | 5 ++ drivers/clk/at91/Kconfig | 4 ++ drivers/clk/at91/clk-utmi.c | 77 ++++++++++++++++++++++++++++- drivers/clk/at91/pmc.h | 3 ++ 4 files changed, 87 insertions(+), 2 deletions(-)arch/arm/mach-at91/include/mach/sama5_sfr.h +5
-0@@ -28,6 +28,9 @@ struct atmel_sfr {u32 l2cc_hramc;/* 0x58 */ }; +/* Register Mapping*/ +#define AT91_SFR_UTMICKTRIM 0x30/* UTMI Clock Trimming Register */ +/* Bit field in DDRCFG */ #define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000@@ -56,6 +59,8 @@ struct atmel_sfr {#define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12)#define AT91_SFR_EBICFG_SCH1_ON (0x1 << 12) +#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0) +/* Bit field in AICREDIR */ #define ATMEL_SFR_AICREDIR_NSAIC 0x00000001drivers/clk/at91/Kconfig +0
-0
drivers/clk/at91/Kconfig config CLK_AT91 · line 22
Quoted 8 lines
drivers/clk/at91/Kconfig +4
-0@@ -15,6 +15,10 @@ config CLK_AT91 config AT91_UTMI bool "Support UTMI PLL Clock" depends on CLK_AT91 + select REGMAP + select SPL_REGMAP + select SYSCON + select SPL_SYSCON help
Does this depend on other series in particular? Not all boards that set AT91_UTMI also have SPL_DM enabled, which is required for SPL_REGMAP, thanks!
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PATCH 1/2 clk: at91: utmi: Set the reference clock frequency
In reply to Wenyou YangQuoted 10 lines · Wenyou Yang
By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the
SFR_UTMICKTRIMhas to be updated to generate the UTMI clock in the proper way.The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz.
Quoted 4 lines
The patch is cloned from the patch of mailing-list:
[PATCH v2] clk: at91: utmi: set the mainck rateSigned-off-by Wenyou Yang <[email protected]>
Applied to u-boot/master, thanks!
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PATCH 2/2 ARM: dts: at91: sama5: Add the sfr node
In reply to Wenyou YangFor sama5d2, add the sfr node with syscon support.
In order to access the SFR_UTMICKTRIM register for the utmi clock driver, add the phandle property for the utmi node to point to the sfr node.
---
arch/arm/dts/sama5d2.dtsi | 6 ++++++ arch/arm/dts/sama5d3.dtsi | 2 ++ 2 files changed, 8 insertions(+)
arch/arm/dts/sama5d2.dtsi +6 -0
@@ -122,6 +122,7 @@ compatible = "atmel,at91sam9x5-clk-utmi"; #clock-cells = <0>; clocks = <&main>; + regmap-sfr = <&sfr>; u-boot,dm-pre-reloc; };
@@ -660,6 +661,11 @@ status = "disabled"; }; + sfr: sfr at f8030000 { + compatible = "atmel,sama5d2-sfr", "syscon"; + reg = <0xf8030000 0x98>; + }; + sckc at f8048050 { compatible = "atmel,at91sam9x5-sckc"; reg = <0xf8048050 0x4>;
arch/arm/dts/sama5d3.dtsi +2 -0
@@ -998,6 +998,8 @@ interrupt-parent = <&pmc>; interrupts = <AT91_PMC_LOCKU>; clocks = <&main>; + regmap-sfr = <&sfr>; + u-boot,dm-pre-reloc; }; mck: masterck {
Signature · 1 line
2.13.0
PATCH 2/2 ARM: dts: at91: sama5: Add the sfr node
Quoted 7 lines · Wenyou Yang
For sama5d2, add the sfr node with syscon support.
In order to access the
SFR_UTMICKTRIMregister for the utmi clock driver, add the phandle property for the utmi node to point to the sfr node.Signed-off-by Wenyou Yang <[email protected]>
Applied to u-boot/master, thanks!
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