A few vega10 powerplay cleanups
Subsystems (2)
Started looking at tidying up the powerplay code a bit. I stopped to send these out because I want to get feedback on the new CGS macros before I go too far down this path.
Thanks,
Tom
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PATCH 1/4 drm/amd/powerplay: Simplify vega10_patch_voltage_dependency_tables_with_lookup_table()
Signed-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 75 +++++++--------------- 1 file changed, 23 insertions(+), 52 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +23 -52
@@ -590,61 +590,37 @@ static int vega10_patch_clock_voltage_limits_with_vddc_leakage(static int vega10_patch_voltage_dependency_tables_with_lookup_table (struct pp_hwmgr *hwmgr) { -uint8_t entry_id; -uint8_t voltage_id; +uint8_t entry_id, voltage_id; +unsigned i;struct phm_ppt_v2_information *table_info = (struct phm_ppt_v2_information *)(hwmgr->pptable); -struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table = - table_info->vdd_dep_on_socclk; -struct phm_ppt_v1_clock_voltage_dependency_table *gfxclk_table = - table_info->vdd_dep_on_sclk; -struct phm_ppt_v1_clock_voltage_dependency_table *dcefclk_table = - table_info->vdd_dep_on_dcefclk; -struct phm_ppt_v1_clock_voltage_dependency_table *pixclk_table = - table_info->vdd_dep_on_pixclk; -struct phm_ppt_v1_clock_voltage_dependency_table *dspclk_table = - table_info->vdd_dep_on_dispclk; -struct phm_ppt_v1_clock_voltage_dependency_table *phyclk_table = - table_info->vdd_dep_on_phyclk; -struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = - table_info->vdd_dep_on_mclk;struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = table_info->mm_dep_table; +struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = + table_info->vdd_dep_on_mclk; -for (entry_id =0 ; entry_id < socclk_table->count; entry_id++) { - voltage_id = socclk_table->entries[entry_id].vddInd; - socclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - } - -for (entry_id =0 ; entry_id < gfxclk_table->count; entry_id++) { - voltage_id = gfxclk_table->entries[entry_id].vddInd; - gfxclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - } - -for (entry_id =0 ; entry_id < dcefclk_table->count; entry_id++) { - voltage_id = dcefclk_table->entries[entry_id].vddInd; - dcefclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - } - -for (entry_id =0 ; entry_id < pixclk_table->count; entry_id++) { - voltage_id = pixclk_table->entries[entry_id].vddInd; - pixclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - } +for (i =0 ; i <6 ; i++) { +struct phm_ppt_v1_clock_voltage_dependency_table *vdt; +switch (i) { +case 0 : vdt = table_info->vdd_dep_on_socclk;break ; +case 1 : vdt = table_info->vdd_dep_on_sclk;break ; +case 2 : vdt = table_info->vdd_dep_on_dcefclk;break ; +case 3 : vdt = table_info->vdd_dep_on_pixclk;break ; +case 4 : vdt = table_info->vdd_dep_on_dispclk;break ; +case 5 : vdt = table_info->vdd_dep_on_phyclk;break ; + } -for (entry_id =0 ; entry_id < dspclk_table->count; entry_id++) { - voltage_id = dspclk_table->entries[entry_id].vddInd; - dspclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; +for (entry_id =0 ; entry_id < vdt->count; entry_id++) { + voltage_id = vdt->entries[entry_id].vddInd; + vdt->entries[entry_id].vddc = + table_info->vddc_lookup_table->entries[voltage_id].us_vdd; + } } -for (entry_id =0 ; entry_id < phyclk_table->count; entry_id++) { - voltage_id = phyclk_table->entries[entry_id].vddInd; - phyclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; +for (entry_id =0 ; entry_id < mm_table->count; ++entry_id) { + voltage_id = mm_table->entries[entry_id].vddcInd; + mm_table->entries[entry_id].vddc = + table_info->vddc_lookup_table->entries[voltage_id].us_vdd; }for (entry_id =0 ; entry_id < mclk_table->count; ++entry_id) {
@@ -659,11 +635,6 @@ static int vega10_patch_voltage_dependency_tables_with_lookup_table( table_info->vddmem_lookup_table->entries[voltage_id].us_vdd; } -for (entry_id =0 ; entry_id < mm_table->count; ++entry_id) { - voltage_id = mm_table->entries[entry_id].vddcInd; - mm_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - }return 0 ;
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PATCH 2/4 drm/amd/powerplay: Simplify vega10_acg_disable()
In reply to a message not in the archiveSigned-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +4 -6
@@ -2312,13 +2312,11 @@ static int vega10_acg_disable(struct pp_hwmgr *hwmgr)struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); -if (data->smu_features[GNLD_ACG ].supported) { -if (data->smu_features[GNLD_ACG ].enabled) { -if (0 ==vega10_enable_smc_features (hwmgr->smumgr, false, - data->smu_features[GNLD_ACG ].smu_feature_bitmap)) +if (data->smu_features[GNLD_ACG ].supported && + data->smu_features[GNLD_ACG ].enabled) +if (!vega10_enable_smc_features (hwmgr->smumgr, false, + data->smu_features[GNLD_ACG ].smu_feature_bitmap)) data->smu_features[GNLD_ACG ].enabled = false; - } - }return 0 ; }
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PATCH 3/4 drm/amd/powerplay: Introduction of bitmask macros for registers
In reply to a message not in the archiveSigned-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/include/cgs_common.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
drivers/gpu/drm/amd/include/cgs_common.h +16 -0
@@ -310,6 +310,22 @@ typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enumtypedef void (*cgs_write_ind_register_t )(struct cgs_device *cgs_device,enum cgs_ind_reg space,unsigned index,uint32_t value); +#define CGS_REG_FIELD_SHIFT (reg, field) reg##__##field##__SHIFT +#define CGS_REG_FIELD_MASK (reg, field) reg##__##field##_MASK + +#define CGS_REG_SET_FIELD (orig_val, reg, field, field_val) \ + (((orig_val) & ~CGS_REG_FIELD_MASK(reg, field)) | \ + (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field)))) + +#define CGS_REG_GET_FIELD (value, reg, field) \ + (((value) & CGS_REG_FIELD_MASK(reg, field)) >> CGS_REG_FIELD_SHIFT(reg, field)) + +#define CGS_WREG32_FIELD (device, reg, field, val) \ + cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field)) + +#define CGS_WREG32_FIELD_IND (device, space, reg, field, val) \ + cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field)) +/** * cgs_get_pci_resource() - provide access to a device resource (PCI BAR) * @cgs_device: opaque device handle
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PATCH 4/4 drm/amd/powerplay: Port vega10_didt_set_mask() to new macros
In reply to a message not in the archiveStart using new CGS bitmask macros.
Signed-off-by Tom St Denis <[email protected]>
--- .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 60 ++++++++-------------- 1 file changed, 20 insertions(+), 40 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c +20 -40
@@ -855,91 +855,71 @@ static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)uint32_t didt_block_info =SQ_IR_MASK |TCP_IR_MASK |TD_PCC_MASK ;if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) { - data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_SQ_CTRL0); - data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK ; - data |= ((en <<DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT ) &DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK ); -cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_SQ_CTRL0, data); +CGS_WREG32_FIELD_IND (hwmgr->device,CGS_IND_REG__DIDT , +DIDT_SQ_CTRL0 ,DIDT_CTRL_EN , en); didt_block_info &= ~SQ_Enable_MASK; didt_block_info |= en << SQ_Enable_SHIFT; }if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) { - data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DB_CTRL0); - data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK ; - data |= ((en <<DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT ) &DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK ); -cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DB_CTRL0, data); +CGS_WREG32_FIELD_IND (hwmgr->device,CGS_IND_REG__DIDT , +DIDT_DB_CTRL0 ,DIDT_CTRL_EN , en); didt_block_info &= ~DB_Enable_MASK; didt_block_info |= en << DB_Enable_SHIFT; }if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) { - data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TD_CTRL0); - data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK ; - data |= ((en <<DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT ) &DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK ); -cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TD_CTRL0, data); +CGS_WREG32_FIELD_IND (hwmgr->device,CGS_IND_REG__DIDT , +DIDT_TD_CTRL0 ,DIDT_CTRL_EN , en); didt_block_info &= ~TD_Enable_MASK; didt_block_info |= en << TD_Enable_SHIFT; }if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) { - data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TCP_CTRL0); - data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK ; - data |= ((en <<DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT ) &DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK ); -cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TCP_CTRL0, data); +CGS_WREG32_FIELD_IND (hwmgr->device,CGS_IND_REG__DIDT , +DIDT_TCP_CTRL0 ,DIDT_CTRL_EN , en); didt_block_info &= ~TCP_Enable_MASK; didt_block_info |= en << TCP_Enable_SHIFT; }if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping)) { - data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DBR_CTRL0); - data &= ~DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK ; - data |= ((en <<DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT ) &DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK ); -cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DBR_CTRL0, data); +CGS_WREG32_FIELD_IND (hwmgr->device,CGS_IND_REG__DIDT , +DIDT_DBR_CTRL0 ,DIDT_CTRL_EN , en); }if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable)) {if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) { data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_SQ_EDC_CTRL); - data &= ~DIDT_SQ_EDC_CTRL__EDC_EN_MASK ; - data |= ((en <<DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT ) &DIDT_SQ_EDC_CTRL__EDC_EN_MASK ); - data &= ~DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK ; - data |= ((~en <<DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT ) &DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK ); + data =CGS_REG_SET_FIELD (data,DIDT_SQ_EDC_CTRL ,EDC_EN , en); + data =CGS_REG_SET_FIELD (data,DIDT_SQ_EDC_CTRL ,EDC_SW_RST , ~en);cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_SQ_EDC_CTRL, data); }if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) { data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DB_EDC_CTRL); - data &= ~DIDT_DB_EDC_CTRL__EDC_EN_MASK ; - data |= ((en <<DIDT_DB_EDC_CTRL__EDC_EN__SHIFT ) &DIDT_DB_EDC_CTRL__EDC_EN_MASK ); - data &= ~DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK ; - data |= ((~en <<DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT ) &DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK ); + data =CGS_REG_SET_FIELD (data,DIDT_DB_EDC_CTRL ,EDC_EN , en); + data =CGS_REG_SET_FIELD (data,DIDT_DB_EDC_CTRL ,EDC_SW_RST , ~en);cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DB_EDC_CTRL, data); }if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) { data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TD_EDC_CTRL); - data &= ~DIDT_TD_EDC_CTRL__EDC_EN_MASK ; - data |= ((en <<DIDT_TD_EDC_CTRL__EDC_EN__SHIFT ) &DIDT_TD_EDC_CTRL__EDC_EN_MASK ); - data &= ~DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK ; - data |= ((~en <<DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT ) &DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK ); + data =CGS_REG_SET_FIELD (data,DIDT_TD_EDC_CTRL ,EDC_EN , en); + data =CGS_REG_SET_FIELD (data,DIDT_TD_EDC_CTRL ,EDC_SW_RST , ~en);cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TD_EDC_CTRL, data); }if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) { data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TCP_EDC_CTRL); - data &= ~DIDT_TCP_EDC_CTRL__EDC_EN_MASK ; - data |= ((en <<DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT ) &DIDT_TCP_EDC_CTRL__EDC_EN_MASK ); - data &= ~DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK ; - data |= ((~en <<DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT ) &DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK ); + data =CGS_REG_SET_FIELD (data,DIDT_TCP_EDC_CTRL ,EDC_EN , en); + data =CGS_REG_SET_FIELD (data,DIDT_TCP_EDC_CTRL ,EDC_SW_RST , ~en);cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TCP_EDC_CTRL, data); }if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping)) { data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DBR_EDC_CTRL); - data &= ~DIDT_DBR_EDC_CTRL__EDC_EN_MASK ; - data |= ((en <<DIDT_DBR_EDC_CTRL__EDC_EN__SHIFT ) &DIDT_DBR_EDC_CTRL__EDC_EN_MASK ); - data &= ~DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK ; - data |= ((~en <<DIDT_DBR_EDC_CTRL__EDC_SW_RST__SHIFT ) &DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK ); + data =CGS_REG_SET_FIELD (data,DIDT_DBR_EDC_CTRL ,EDC_EN , en); + data =CGS_REG_SET_FIELD (data,DIDT_DBR_EDC_CTRL ,EDC_SW_RST , ~en);cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DBR_EDC_CTRL, data); } }
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2.12.0 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Quoted 10 lines
-----Original Message-----
From: amd-gfx [mailto:[email protected]] On Behalf Of Tom St Denis
Sent: Wednesday, September 06, 2017 8:07 AM
To: [email protected]
Subject: A few vega10 powerplay cleanupsStarted looking at tidying up the powerplay code a bit. I stopped to send these out because I want to get feedback on the new CGS macros before I go too far down this path.
Looks good to me, but please let Rex take a look.
Alex
Quoted 8 lines
Thanks,
Tom_______________________________________________
amd-gfx mailing list
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_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
A message that is not in the archive (sent off-list or not yet received): BN6PR12MB16522E1DA354D44FA2A47628F7970-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org
Quoted 7 lines · Alexander
Quoted 7 lines
-----Original Message-----
From: amd-gfx [mailto:[email protected]] On Behalf Of Tom St Denis
Sent: Wednesday, September 06, 2017 8:07 AM
To: [email protected]
Subject: A few vega10 powerplay cleanups
Quoted 5 lines
Quoted 3 lines
Started looking at tidying up the powerplay code a bit. I stopped to send these out because I want to get feedback on the new CGS macros before I go too far down this path.
Looks good to me, but please let Rex take a look.
Hi Alex,
Yup, I suspect he's in a phase shifted time zone so I'll hopefully see a reply tomorrow.
Thanks,
Tom
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