Various vega10 hwmgr cleanups
Subsystems (2)
These patches introduce a couple of new macro sets to help and tidy up the hwmgr code for powerplay. Applied only to the vega10 drivers so far. Should be no functional changes but there are a few re-arrangements of existing code.
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PATCH 1/16 drm/amd/powerplay: Simplify vega10_patch_voltage_dependency_tables_with_lookup_table()
Signed-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 75 +++++++--------------- 1 file changed, 23 insertions(+), 52 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +23 -52
@@ -590,61 +590,37 @@ static int vega10_patch_clock_voltage_limits_with_vddc_leakage(static int vega10_patch_voltage_dependency_tables_with_lookup_table (struct pp_hwmgr *hwmgr) { -uint8_t entry_id; -uint8_t voltage_id; +uint8_t entry_id, voltage_id; +unsigned i;struct phm_ppt_v2_information *table_info = (struct phm_ppt_v2_information *)(hwmgr->pptable); -struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table = - table_info->vdd_dep_on_socclk; -struct phm_ppt_v1_clock_voltage_dependency_table *gfxclk_table = - table_info->vdd_dep_on_sclk; -struct phm_ppt_v1_clock_voltage_dependency_table *dcefclk_table = - table_info->vdd_dep_on_dcefclk; -struct phm_ppt_v1_clock_voltage_dependency_table *pixclk_table = - table_info->vdd_dep_on_pixclk; -struct phm_ppt_v1_clock_voltage_dependency_table *dspclk_table = - table_info->vdd_dep_on_dispclk; -struct phm_ppt_v1_clock_voltage_dependency_table *phyclk_table = - table_info->vdd_dep_on_phyclk; -struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = - table_info->vdd_dep_on_mclk;struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = table_info->mm_dep_table; +struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = + table_info->vdd_dep_on_mclk; -for (entry_id =0 ; entry_id < socclk_table->count; entry_id++) { - voltage_id = socclk_table->entries[entry_id].vddInd; - socclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - } - -for (entry_id =0 ; entry_id < gfxclk_table->count; entry_id++) { - voltage_id = gfxclk_table->entries[entry_id].vddInd; - gfxclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - } - -for (entry_id =0 ; entry_id < dcefclk_table->count; entry_id++) { - voltage_id = dcefclk_table->entries[entry_id].vddInd; - dcefclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - } - -for (entry_id =0 ; entry_id < pixclk_table->count; entry_id++) { - voltage_id = pixclk_table->entries[entry_id].vddInd; - pixclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - } +for (i =0 ; i <6 ; i++) { +struct phm_ppt_v1_clock_voltage_dependency_table *vdt; +switch (i) { +case 0 : vdt = table_info->vdd_dep_on_socclk;break ; +case 1 : vdt = table_info->vdd_dep_on_sclk;break ; +case 2 : vdt = table_info->vdd_dep_on_dcefclk;break ; +case 3 : vdt = table_info->vdd_dep_on_pixclk;break ; +case 4 : vdt = table_info->vdd_dep_on_dispclk;break ; +case 5 : vdt = table_info->vdd_dep_on_phyclk;break ; + } -for (entry_id =0 ; entry_id < dspclk_table->count; entry_id++) { - voltage_id = dspclk_table->entries[entry_id].vddInd; - dspclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; +for (entry_id =0 ; entry_id < vdt->count; entry_id++) { + voltage_id = vdt->entries[entry_id].vddInd; + vdt->entries[entry_id].vddc = + table_info->vddc_lookup_table->entries[voltage_id].us_vdd; + } } -for (entry_id =0 ; entry_id < phyclk_table->count; entry_id++) { - voltage_id = phyclk_table->entries[entry_id].vddInd; - phyclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; +for (entry_id =0 ; entry_id < mm_table->count; ++entry_id) { + voltage_id = mm_table->entries[entry_id].vddcInd; + mm_table->entries[entry_id].vddc = + table_info->vddc_lookup_table->entries[voltage_id].us_vdd; }for (entry_id =0 ; entry_id < mclk_table->count; ++entry_id) {
@@ -659,11 +635,6 @@ static int vega10_patch_voltage_dependency_tables_with_lookup_table( table_info->vddmem_lookup_table->entries[voltage_id].us_vdd; } -for (entry_id =0 ; entry_id < mm_table->count; ++entry_id) { - voltage_id = mm_table->entries[entry_id].vddcInd; - mm_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - }return 0 ;
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PATCH 2/16 drm/amd/powerplay: Simplify vega10_acg_disable()
In reply to a message not in the archiveSigned-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +4 -6
@@ -2312,13 +2312,11 @@ static int vega10_acg_disable(struct pp_hwmgr *hwmgr)struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); -if (data->smu_features[GNLD_ACG ].supported) { -if (data->smu_features[GNLD_ACG ].enabled) { -if (0 ==vega10_enable_smc_features (hwmgr->smumgr, false, - data->smu_features[GNLD_ACG ].smu_feature_bitmap)) +if (data->smu_features[GNLD_ACG ].supported && + data->smu_features[GNLD_ACG ].enabled) +if (!vega10_enable_smc_features (hwmgr->smumgr, false, + data->smu_features[GNLD_ACG ].smu_feature_bitmap)) data->smu_features[GNLD_ACG ].enabled = false; - } - }return 0 ; }
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PATCH 3/16 drm/amd/powerplay: Introduction of bitmask macros for registers
In reply to a message not in the archiveSigned-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/include/cgs_common.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
drivers/gpu/drm/amd/include/cgs_common.h +16 -0
@@ -310,6 +310,22 @@ typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enumtypedef void (*cgs_write_ind_register_t )(struct cgs_device *cgs_device,enum cgs_ind_reg space,unsigned index,uint32_t value); +#define CGS_REG_FIELD_SHIFT (reg, field) reg##__##field##__SHIFT +#define CGS_REG_FIELD_MASK (reg, field) reg##__##field##_MASK + +#define CGS_REG_SET_FIELD (orig_val, reg, field, field_val) \ + (((orig_val) & ~CGS_REG_FIELD_MASK(reg, field)) | \ + (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field)))) + +#define CGS_REG_GET_FIELD (value, reg, field) \ + (((value) & CGS_REG_FIELD_MASK(reg, field)) >> CGS_REG_FIELD_SHIFT(reg, field)) + +#define CGS_WREG32_FIELD (device, reg, field, val) \ + cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field)) + +#define CGS_WREG32_FIELD_IND (device, space, reg, field, val) \ + cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field)) +/** * cgs_get_pci_resource() - provide access to a device resource (PCI BAR) * @cgs_device: opaque device handle
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PATCH 4/16 drm/amd/powerplay: Port vega10_didt_set_mask() to new macros
In reply to a message not in the archiveStart using new CGS bitmask macros.
Signed-off-by Tom St Denis <[email protected]>
--- .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 60 ++++++++-------------- 1 file changed, 20 insertions(+), 40 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c +20 -40
@@ -855,91 +855,71 @@ static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)uint32_t didt_block_info =SQ_IR_MASK |TCP_IR_MASK |TD_PCC_MASK ;if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) { - data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_SQ_CTRL0); - data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK ; - data |= ((en <<DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT ) &DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK ); -cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_SQ_CTRL0, data); +CGS_WREG32_FIELD_IND (hwmgr->device,CGS_IND_REG__DIDT , +DIDT_SQ_CTRL0 ,DIDT_CTRL_EN , en); didt_block_info &= ~SQ_Enable_MASK; didt_block_info |= en << SQ_Enable_SHIFT; }if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) { - data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DB_CTRL0); - data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK ; - data |= ((en <<DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT ) &DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK ); -cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DB_CTRL0, data); +CGS_WREG32_FIELD_IND (hwmgr->device,CGS_IND_REG__DIDT , +DIDT_DB_CTRL0 ,DIDT_CTRL_EN , en); didt_block_info &= ~DB_Enable_MASK; didt_block_info |= en << DB_Enable_SHIFT; }if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) { - data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TD_CTRL0); - data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK ; - data |= ((en <<DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT ) &DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK ); -cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TD_CTRL0, data); +CGS_WREG32_FIELD_IND (hwmgr->device,CGS_IND_REG__DIDT , +DIDT_TD_CTRL0 ,DIDT_CTRL_EN , en); didt_block_info &= ~TD_Enable_MASK; didt_block_info |= en << TD_Enable_SHIFT; }if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) { - data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TCP_CTRL0); - data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK ; - data |= ((en <<DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT ) &DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK ); -cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TCP_CTRL0, data); +CGS_WREG32_FIELD_IND (hwmgr->device,CGS_IND_REG__DIDT , +DIDT_TCP_CTRL0 ,DIDT_CTRL_EN , en); didt_block_info &= ~TCP_Enable_MASK; didt_block_info |= en << TCP_Enable_SHIFT; }if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping)) { - data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DBR_CTRL0); - data &= ~DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK ; - data |= ((en <<DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT ) &DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK ); -cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DBR_CTRL0, data); +CGS_WREG32_FIELD_IND (hwmgr->device,CGS_IND_REG__DIDT , +DIDT_DBR_CTRL0 ,DIDT_CTRL_EN , en); }if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable)) {if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) { data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_SQ_EDC_CTRL); - data &= ~DIDT_SQ_EDC_CTRL__EDC_EN_MASK ; - data |= ((en <<DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT ) &DIDT_SQ_EDC_CTRL__EDC_EN_MASK ); - data &= ~DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK ; - data |= ((~en <<DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT ) &DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK ); + data =CGS_REG_SET_FIELD (data,DIDT_SQ_EDC_CTRL ,EDC_EN , en); + data =CGS_REG_SET_FIELD (data,DIDT_SQ_EDC_CTRL ,EDC_SW_RST , ~en);cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_SQ_EDC_CTRL, data); }if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) { data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DB_EDC_CTRL); - data &= ~DIDT_DB_EDC_CTRL__EDC_EN_MASK ; - data |= ((en <<DIDT_DB_EDC_CTRL__EDC_EN__SHIFT ) &DIDT_DB_EDC_CTRL__EDC_EN_MASK ); - data &= ~DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK ; - data |= ((~en <<DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT ) &DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK ); + data =CGS_REG_SET_FIELD (data,DIDT_DB_EDC_CTRL ,EDC_EN , en); + data =CGS_REG_SET_FIELD (data,DIDT_DB_EDC_CTRL ,EDC_SW_RST , ~en);cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DB_EDC_CTRL, data); }if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) { data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TD_EDC_CTRL); - data &= ~DIDT_TD_EDC_CTRL__EDC_EN_MASK ; - data |= ((en <<DIDT_TD_EDC_CTRL__EDC_EN__SHIFT ) &DIDT_TD_EDC_CTRL__EDC_EN_MASK ); - data &= ~DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK ; - data |= ((~en <<DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT ) &DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK ); + data =CGS_REG_SET_FIELD (data,DIDT_TD_EDC_CTRL ,EDC_EN , en); + data =CGS_REG_SET_FIELD (data,DIDT_TD_EDC_CTRL ,EDC_SW_RST , ~en);cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TD_EDC_CTRL, data); }if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) { data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TCP_EDC_CTRL); - data &= ~DIDT_TCP_EDC_CTRL__EDC_EN_MASK ; - data |= ((en <<DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT ) &DIDT_TCP_EDC_CTRL__EDC_EN_MASK ); - data &= ~DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK ; - data |= ((~en <<DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT ) &DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK ); + data =CGS_REG_SET_FIELD (data,DIDT_TCP_EDC_CTRL ,EDC_EN , en); + data =CGS_REG_SET_FIELD (data,DIDT_TCP_EDC_CTRL ,EDC_SW_RST , ~en);cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TCP_EDC_CTRL, data); }if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping)) { data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DBR_EDC_CTRL); - data &= ~DIDT_DBR_EDC_CTRL__EDC_EN_MASK ; - data |= ((en <<DIDT_DBR_EDC_CTRL__EDC_EN__SHIFT ) &DIDT_DBR_EDC_CTRL__EDC_EN_MASK ); - data &= ~DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK ; - data |= ((~en <<DIDT_DBR_EDC_CTRL__EDC_SW_RST__SHIFT ) &DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK ); + data =CGS_REG_SET_FIELD (data,DIDT_DBR_EDC_CTRL ,EDC_EN , en); + data =CGS_REG_SET_FIELD (data,DIDT_DBR_EDC_CTRL ,EDC_SW_RST , ~en);cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DBR_EDC_CTRL, data); } }
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PATCH 5/16 drm/amd/powerplay: Add PP_CAP() macro
In reply to a message not in the archiveTo replace common lengthy sequence that would create really long lines all over.
Signed-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h | 2 ++ 1 file changed, 2 insertions(+)
drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h +2 -0
@@ -283,6 +283,8 @@ static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))))); } +#define PP_CAP (c) phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (c)) +#define PP_PCIEGenInvalid 0xffffenum PP_PCIEGen { PP_PCIEGen1 =0 ,/* PCIE 1.0 - Transfer rate of 2.5 GT/s */
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2.12.0 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 6/16 drm/amd/powerplay: Port vega10_hwmgr.c over to PP_CAP
In reply to a message not in the archiveReplace and cleanup lengthy phm_cap_enabled() sequences with PP_CAP.
Signed-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 91 ++++++++-------------- 1 file changed, 32 insertions(+), 59 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +32 -59
@@ -380,12 +380,10 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)if (!data->registry_data.socclk_dpm_key_disabled) data->smu_features[GNLD_DPM_SOCCLK ].supported = true; -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UVDDPM)) +if (PP_CAP (PHM_PlatformCaps_UVDDPM)) data->smu_features[GNLD_DPM_UVD ].supported = true; -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_VCEDPM)) +if (PP_CAP (PHM_PlatformCaps_VCEDPM)) data->smu_features[GNLD_DPM_VCE ].supported = true;if (!data->registry_data.pcie_dpm_key_disabled)
@@ -394,9 +392,8 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)if (!data->registry_data.dcefclk_dpm_key_disabled) data->smu_features[GNLD_DPM_DCEFCLK ].supported = true; -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkDeepSleep) && - data->registry_data.sclk_deep_sleep_support) { +if (PP_CAP (PHM_PlatformCaps_SclkDeepSleep) && + data->registry_data.sclk_deep_sleep_support) { data->smu_features[GNLD_DS_GFXCLK ].supported = true; data->smu_features[GNLD_DS_SOCCLK ].supported = true; data->smu_features[GNLD_DS_LCLK ].supported = true;
@@ -496,8 +493,7 @@ static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)if (!vega10_get_socclk_for_voltage_evv (hwmgr, table_info->vddc_lookup_table, vv_id, &sclk)) { -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ClockStretcher)) { +if (PP_CAP (PHM_PlatformCaps_ClockStretcher)) {for (j =1 ; j < socclk_table->count; j++) {if (socclk_table->entries[j].clk == sclk && socclk_table->entries[j].cks_enable ==0 ) {
@@ -808,8 +804,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) }/* VDDCI_MEM */ -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ControlVDDCI)) { +if (PP_CAP (PHM_PlatformCaps_ControlVDDCI)) {if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4 (hwmgr,VOLTAGE_TYPE_VDDCI ,VOLTAGE_OBJ_GPIO_LUT )) data->vddci_control =VEGA10_VOLTAGE_CONTROL_BY_GPIO ;
@@ -1381,10 +1376,8 @@ static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)memcpy (&(data->golden_dpm_table), &(data->dpm_table),sizeof (struct vega10_dpm_table )); -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODNinACSupport) || -phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODNinDCSupport)) { +if (PP_CAP (PHM_PlatformCaps_ODNinACSupport) || +PP_CAP (PHM_PlatformCaps_ODNinDCSupport)) { data->odn_dpm_table.odn_core_clock_dpm_levels. number_of_performance_levels = data->dpm_table.gfx_table.count;for (i =0 ; i < data->dpm_table.gfx_table.count; i++) {
@@ -2331,9 +2324,8 @@ static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr) result =pp_atomfwctrl_get_gpio_information (hwmgr, &gpio_params);if (!result) { -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_RegulatorHot) && - (data->registry_data.regulator_hot_gpio_support)) { +if (PP_CAP (PHM_PlatformCaps_RegulatorHot) && + data->registry_data.regulator_hot_gpio_support) { pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio; pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity; pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio;
@@ -2345,9 +2337,8 @@ static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr) pp_table->VR1HotPolarity =0 ; } -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_AutomaticDCTransition) && - (data->registry_data.ac_dc_switch_gpio_support)) { +if (PP_CAP (PHM_PlatformCaps_AutomaticDCTransition) && + data->registry_data.ac_dc_switch_gpio_support) { pp_table->AcDcGpio = gpio_params.ucAcDcGpio; pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity; }else {
@@ -2645,8 +2636,7 @@ static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_RegulatorHot)) { + if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) { if (data->smu_features[GNLD_VR0HOT].supported) { PP_ASSERT_WITH_CODE( !vega10_enable_smc_features(hwmgr->smumgr,
@@ -2860,8 +2850,7 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) data->vbios_boot_state.bsoc_vddc_lock = false; } -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_Falcon_QuickTransition)) { +if (PP_CAP (PHM_PlatformCaps_Falcon_QuickTransition)) {if (data->smu_features[GNLD_ACDC ].supported) { PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, true, data->smu_features[GNLD_ACDC].smu_feature_bitmap),
@@ -2904,8 +2893,7 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)"Failed to initialize SMC table!" , result = tmp_result); -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ThermalController)) { +if (PP_CAP (PHM_PlatformCaps_ThermalController)) { tmp_result =vega10_enable_thermal_protection (hwmgr); PP_ASSERT_WITH_CODE(!tmp_result, "Failed to enable thermal protection!",
@@ -3139,8 +3127,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock; minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_StablePState)) { +if (PP_CAP (PHM_PlatformCaps_StablePState)) { PP_ASSERT_WITH_CODE( data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 && data->registry_data.stable_pstate_sclk_dpm_percentage <= 100,
@@ -3205,10 +3192,8 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, disable_mclk_switching_for_frame_lock =phm_cap_enabled ( hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); - disable_mclk_switching_for_vr =phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DisableMclkSwitchForVR); - force_mclk_high =phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ForceMclkHigh); + disable_mclk_switching_for_vr =PP_CAP (PHM_PlatformCaps_DisableMclkSwitchForVR); + force_mclk_high =PP_CAP (PHM_PlatformCaps_ForceMclkHigh); disable_mclk_switching = (info.display_count >1 ) || disable_mclk_switching_for_frame_lock ||
@@ -3259,8 +3244,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, vega10_ps->performance_levels[1 ].mem_clock; } -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_StablePState)) { +if (PP_CAP (PHM_PlatformCaps_StablePState)) {for (i =0 ; i < vega10_ps->performance_level_count; i++) { vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk; vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk;
@@ -3292,10 +3276,8 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co data->need_update_dpm_table =0 ; -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODNinACSupport) || -phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODNinDCSupport)) { +if (PP_CAP (PHM_PlatformCaps_ODNinACSupport) || +PP_CAP (PHM_PlatformCaps_ODNinDCSupport)) {for (i =0 ; i < sclk_table->count; i++) {if (sclk == sclk_table->dpm_levels[i].value)break ;
@@ -3379,10 +3361,8 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(uint32_t dpm_count, clock_percent;uint32_t i; -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODNinACSupport) || -phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODNinDCSupport)) { +if (PP_CAP (PHM_PlatformCaps_ODNinACSupport) || +PP_CAP (PHM_PlatformCaps_ODNinDCSupport)) { if (!data->need_update_dpm_table && !data->apply_optimized_settings &&
@@ -3447,10 +3427,8 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( dpm_table-> gfx_table.dpm_levels[dpm_table->gfx_table.count -1 ]. value = sclk; -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_OD6PlusinACSupport) || -phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_OD6PlusinDCSupport)) { +if (PP_CAP (PHM_PlatformCaps_OD6PlusinACSupport) || +PP_CAP (PHM_PlatformCaps_OD6PlusinDCSupport)) {/* Need to do calculation based on the golden DPM table * as the Heatmap GPU Clock axis is also based on * the default values
@@ -3504,10 +3482,8 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( mem_table.dpm_levels[dpm_table->mem_table.count -1 ]. value = mclk; -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_OD6PlusinACSupport) || -phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_OD6PlusinDCSupport)) { +if (PP_CAP (PHM_PlatformCaps_OD6PlusinACSupport) || +PP_CAP (PHM_PlatformCaps_OD6PlusinDCSupport)) {PP_ASSERT_WITH_CODE ( golden_dpm_table->mem_table.dpm_levels
@@ -3838,9 +3814,8 @@ static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)int result =0 ;uint32_t low_sclk_interrupt_threshold =0 ; -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkThrottleLowNotification) - && (hwmgr->gfx_arbiter.sclk_threshold != +if (PP_CAP (PHM_PlatformCaps_SclkThrottleLowNotification) && + (hwmgr->gfx_arbiter.sclk_threshold != data->low_sclk_interrupt_threshold)) { data->low_sclk_interrupt_threshold = hwmgr->gfx_arbiter.sclk_threshold;
@@ -4251,8 +4226,7 @@ static int vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) result =vega10_fan_ctrl_set_fan_speed_percent (hwmgr,100 );break ;case AMD_FAN_CTRL_MANUAL : -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) +if (PP_CAP (PHM_PlatformCaps_MicrocodeFanControl)) result =vega10_fan_ctrl_stop_smc_fan_control (hwmgr);break ;case AMD_FAN_CTRL_AUTO :
@@ -4796,7 +4770,7 @@ vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgif (data->display_timing.num_existing_displays != info.display_count) is_update_required = true; -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { +if (PP_CAP (PHM_PlatformCaps_SclkDeepSleep)) {if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr) is_update_required = true; }
@@ -4813,8 +4787,7 @@ static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)"DPM is not running right now, no need to disable DPM!" , return 0); -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ThermalController)) +if (PP_CAP (PHM_PlatformCaps_ThermalController))vega10_disable_thermal_protection (hwmgr); tmp_result =vega10_disable_power_containment (hwmgr);
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2.12.0 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 7/16 drm/amd/powerplay: Port vega10_powertune.c over to PP_CAP
In reply to a message not in the archiveSigned-off-by Tom St Denis <[email protected]>
--- .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 47 ++++++++++------------ 1 file changed, 22 insertions(+), 25 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c +22 -25
@@ -854,69 +854,69 @@ static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)uint32_t en = (enable ?1 :0 );uint32_t didt_block_info =SQ_IR_MASK |TCP_IR_MASK |TD_PCC_MASK ; -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) { +if (PP_CAP (PHM_PlatformCaps_SQRamping)) {CGS_WREG32_FIELD_IND (hwmgr->device,CGS_IND_REG__DIDT ,DIDT_SQ_CTRL0 ,DIDT_CTRL_EN , en); didt_block_info &= ~SQ_Enable_MASK; didt_block_info |= en << SQ_Enable_SHIFT; } -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) { +if (PP_CAP (PHM_PlatformCaps_DBRamping)) {CGS_WREG32_FIELD_IND (hwmgr->device,CGS_IND_REG__DIDT ,DIDT_DB_CTRL0 ,DIDT_CTRL_EN , en); didt_block_info &= ~DB_Enable_MASK; didt_block_info |= en << DB_Enable_SHIFT; } -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) { +if (PP_CAP (PHM_PlatformCaps_TDRamping)) {CGS_WREG32_FIELD_IND (hwmgr->device,CGS_IND_REG__DIDT ,DIDT_TD_CTRL0 ,DIDT_CTRL_EN , en); didt_block_info &= ~TD_Enable_MASK; didt_block_info |= en << TD_Enable_SHIFT; } -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) { +if (PP_CAP (PHM_PlatformCaps_TCPRamping)) {CGS_WREG32_FIELD_IND (hwmgr->device,CGS_IND_REG__DIDT ,DIDT_TCP_CTRL0 ,DIDT_CTRL_EN , en); didt_block_info &= ~TCP_Enable_MASK; didt_block_info |= en << TCP_Enable_SHIFT; } -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping)) { +if (PP_CAP (PHM_PlatformCaps_DBRRamping)) {CGS_WREG32_FIELD_IND (hwmgr->device,CGS_IND_REG__DIDT ,DIDT_DBR_CTRL0 ,DIDT_CTRL_EN , en); } -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable)) { -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) { +if (PP_CAP (PHM_PlatformCaps_DiDtEDCEnable)) { +if (PP_CAP (PHM_PlatformCaps_SQRamping)) { data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_SQ_EDC_CTRL); data =CGS_REG_SET_FIELD (data,DIDT_SQ_EDC_CTRL ,EDC_EN , en); data =CGS_REG_SET_FIELD (data,DIDT_SQ_EDC_CTRL ,EDC_SW_RST , ~en);cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_SQ_EDC_CTRL, data); } -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) { +if (PP_CAP (PHM_PlatformCaps_DBRamping)) { data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DB_EDC_CTRL); data =CGS_REG_SET_FIELD (data,DIDT_DB_EDC_CTRL ,EDC_EN , en); data =CGS_REG_SET_FIELD (data,DIDT_DB_EDC_CTRL ,EDC_SW_RST , ~en);cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DB_EDC_CTRL, data); } -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) { +if (PP_CAP (PHM_PlatformCaps_TDRamping)) { data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TD_EDC_CTRL); data =CGS_REG_SET_FIELD (data,DIDT_TD_EDC_CTRL ,EDC_EN , en); data =CGS_REG_SET_FIELD (data,DIDT_TD_EDC_CTRL ,EDC_SW_RST , ~en);cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TD_EDC_CTRL, data); } -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) { +if (PP_CAP (PHM_PlatformCaps_TCPRamping)) { data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TCP_EDC_CTRL); data =CGS_REG_SET_FIELD (data,DIDT_TCP_EDC_CTRL ,EDC_EN , en); data =CGS_REG_SET_FIELD (data,DIDT_TCP_EDC_CTRL ,EDC_SW_RST , ~en);cgs_write_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_TCP_EDC_CTRL, data); } -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping)) { +if (PP_CAP (PHM_PlatformCaps_DBRRamping)) { data =cgs_read_ind_register (hwmgr->device,CGS_IND_REG__DIDT , ixDIDT_DBR_EDC_CTRL); data =CGS_REG_SET_FIELD (data,DIDT_DBR_EDC_CTRL ,EDC_EN , en); data =CGS_REG_SET_FIELD (data,DIDT_DBR_EDC_CTRL ,EDC_SW_RST , ~en);
@@ -1020,10 +1020,10 @@ static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)cgs_enter_safe_mode (hwmgr->device, false);vega10_program_gc_didt_config_registers (hwmgr, GCDiDtDroopCtrlConfig_vega10); -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC)) +if (PP_CAP (PHM_PlatformCaps_GCEDC))vega10_program_gc_didt_config_registers (hwmgr, GCDiDtCtrl0Config_vega10); -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM)) +if (PP_CAP (PHM_PlatformCaps_PSM))vega10_program_gc_didt_config_registers (hwmgr, AvfsPSMInitConfig_vega10);return 0 ;
@@ -1039,12 +1039,12 @@ static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)cgs_enter_safe_mode (hwmgr->device, false); -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC)) { +if (PP_CAP (PHM_PlatformCaps_GCEDC)) { data =0x00000000 ;cgs_write_register (hwmgr->device, mmGC_DIDT_CTRL0, data); } -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM)) +if (PP_CAP (PHM_PlatformCaps_PSM))vega10_program_gc_didt_config_registers (hwmgr, AvfsPSMResetConfig_vega10);return 0 ;
@@ -1139,12 +1139,12 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)vega10_program_gc_didt_config_registers (hwmgr, PSMGCEDCDroopCtrlConfig_vega10); -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC)) { +if (PP_CAP (PHM_PlatformCaps_GCEDC)) {vega10_program_gc_didt_config_registers (hwmgr, PSMGCEDCCtrlResetConfig_vega10);vega10_program_gc_didt_config_registers (hwmgr, PSMGCEDCCtrlConfig_vega10); } -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM)) +if (PP_CAP (PHM_PlatformCaps_PSM))vega10_program_gc_didt_config_registers (hwmgr, AvfsPSMInitConfig_vega10);return 0 ;
@@ -1160,12 +1160,12 @@ static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)cgs_enter_safe_mode (hwmgr->device, false); -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC)) { +if (PP_CAP (PHM_PlatformCaps_GCEDC)) { data =0x00000000 ;cgs_write_register (hwmgr->device, mmGC_EDC_CTRL, data); } -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM)) +if (PP_CAP (PHM_PlatformCaps_PSM))vega10_program_gc_didt_config_registers (hwmgr, AvfsPSMResetConfig_vega10);return 0 ;
@@ -1361,8 +1361,7 @@ int vega10_enable_power_containment(struct pp_hwmgr *hwmgr) (uint32_t )(tdp_table->usMaximumPowerDeliveryLimit);int result =0 ; -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment)) { +if (PP_CAP (PHM_PlatformCaps_PowerContainment)) {if (data->smu_features[GNLD_PPT ].supported) PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, true, data->smu_features[GNLD_PPT].smu_feature_bitmap),
@@ -1389,8 +1388,7 @@ int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment)) { +if (PP_CAP (PHM_PlatformCaps_PowerContainment)) {if (data->smu_features[GNLD_PPT ].supported) PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, false, data->smu_features[GNLD_PPT].smu_feature_bitmap),
@@ -1418,8 +1416,7 @@ int vega10_power_control_set_level(struct pp_hwmgr *hwmgr) {int adjust_percent, result =0 ; -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment)) { +if (PP_CAP (PHM_PlatformCaps_PowerContainment)) { adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ? hwmgr->platform_descriptor.TDPAdjustment :
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2.12.0 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 8/16 drm/amd/powerplay: Port vega10_thermal.c over to PP_CAP
In reply to a message not in the archiveSigned-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +5 -11
@@ -54,8 +54,7 @@ int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, fan_speed_info->min_percent =0 ; fan_speed_info->max_percent =100 ; -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_FanSpeedInTableIsRPM) && +if (PP_CAP (PHM_PlatformCaps_FanSpeedInTableIsRPM) && hwmgr->thermal_controller.fanInfo. ucTachometerPulsesPerRevolution) { fan_speed_info->supports_rpm_read = true;
@@ -279,8 +278,7 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,if (speed >100 ) speed =100 ; -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) +if (PP_CAP (PHM_PlatformCaps_MicrocodeFanControl))vega10_fan_ctrl_stop_smc_fan_control (hwmgr); reg = soc15_get_register_offset(THM_HWID, 0,
@@ -319,8 +317,7 @@ int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)if (hwmgr->thermal_controller.fanInfo.bNoFan)return 0 ; -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) { +if (PP_CAP (PHM_PlatformCaps_MicrocodeFanControl)) { result =vega10_fan_ctrl_start_smc_fan_control (hwmgr); }else result =vega10_fan_ctrl_set_default_mode (hwmgr);
@@ -346,8 +343,7 @@ int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))return -1 ; -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) +if (PP_CAP (PHM_PlatformCaps_MicrocodeFanControl)) result =vega10_fan_ctrl_stop_smc_fan_control (hwmgr);if (!result) {
@@ -627,10 +623,8 @@ int tf_vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,* this function was included in the table. * Make sure that we still think controlling the fan is OK. */ -if (phm_cap_enabled (hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) { +if (PP_CAP (PHM_PlatformCaps_MicrocodeFanControl))vega10_fan_ctrl_start_smc_fan_control (hwmgr); - }return 0 ; }
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2.12.0 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 9/16 drm/amd/powerplay: Tidy up vega10_fan_ctrl_get_fan_speed_rpm()
In reply to a message not in the archiveSigned-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +6 -5
@@ -104,14 +104,15 @@ int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)if (hwmgr->thermal_controller.fanInfo.bNoFan)return -1 ; -if (data->smu_features[GNLD_FAN_CONTROL ].supported) +if (data->smu_features[GNLD_FAN_CONTROL ].supported) { result =vega10_get_current_rpm (hwmgr, speed); -else { + }else {uint32_t reg =soc15_get_register_offset (THM_HWID ,0 , mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS); - tach_period = (cgs_read_register (hwmgr->device, - reg) &CG_TACH_STATUS__TACH_PERIOD_MASK ) >> -CG_TACH_STATUS__TACH_PERIOD__SHIFT ; + tach_period = +CGS_REG_GET_FIELD (cgs_read_register (hwmgr->device, reg), +CG_TACH_STATUS , +TACH_PERIOD );if (tach_period ==0 )return -EINVAL ;
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2.12.0 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 10/16 drm/amd/powerplay: Tidy up vega10_fan_ctrl_set_static_mode()
In reply to a message not in the archiveSigned-off-by Tom St Denis <[email protected]>
--- .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +9 -12
@@ -141,23 +141,20 @@ int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)if (hwmgr->fan_ctrl_is_in_default_mode) { hwmgr->fan_ctrl_default_mode = - (cgs_read_register (hwmgr->device, reg) & -CG_FDO_CTRL2__FDO_PWM_MODE_MASK ) >> -CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT ; - hwmgr->tmin = (cgs_read_register (hwmgr->device, reg) & -CG_FDO_CTRL2__TMIN_MASK ) >> -CG_FDO_CTRL2__TMIN__SHIFT ; +CGS_REG_GET_FIELD (cgs_read_register (hwmgr->device, reg), +CG_FDO_CTRL2 ,FDO_PWM_MODE ); + hwmgr->tmin = +CGS_REG_GET_FIELD (cgs_read_register (hwmgr->device, reg), +CG_FDO_CTRL2 ,TMIN ); hwmgr->fan_ctrl_is_in_default_mode = false; }cgs_write_register (hwmgr->device, reg, - (cgs_read_register (hwmgr->device, reg) & - ~CG_FDO_CTRL2__TMIN_MASK ) | - (0 <<CG_FDO_CTRL2__TMIN__SHIFT )); +CGS_REG_SET_FIELD (cgs_read_register (hwmgr->device, reg), +CG_FDO_CTRL2 ,TMIN ,0 ));cgs_write_register (hwmgr->device, reg, - (cgs_read_register (hwmgr->device, reg) & - ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK ) | - (mode <<CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT )); +CGS_REG_SET_FIELD (cgs_read_register (hwmgr->device, reg), +CG_FDO_CTRL2 ,FDO_PWM_MODE , mode));return 0 ; }
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PATCH 11/16 drm/amd/powerplay: Tidy up vega10_fan_ctrl_set_default_mode()
In reply to a message not in the archiveSigned-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +6 -7
@@ -173,14 +173,13 @@ int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)if (!hwmgr->fan_ctrl_is_in_default_mode) {cgs_write_register (hwmgr->device, reg, - (cgs_read_register (hwmgr->device, reg) & - ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK ) | - (hwmgr->fan_ctrl_default_mode << -CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT )); +CGS_REG_SET_FIELD (cgs_read_register (hwmgr->device, reg), +CG_FDO_CTRL2 ,FDO_PWM_MODE , + hwmgr->fan_ctrl_default_mode));cgs_write_register (hwmgr->device, reg, - (cgs_read_register (hwmgr->device, reg) & - ~CG_FDO_CTRL2__TMIN_MASK ) | - (hwmgr->tmin <<CG_FDO_CTRL2__TMIN__SHIFT )); +CGS_REG_SET_FIELD (cgs_read_register (hwmgr->device, reg), +CG_FDO_CTRL2 ,TMIN , + hwmgr->tmin <<CG_FDO_CTRL2__TMIN__SHIFT )); hwmgr->fan_ctrl_is_in_default_mode = true; }
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PATCH 12/16 drm/amd/powerplay: Tidy up vega10_fan_ctrl_set_fan_speed_percent()
In reply to a message not in the archiveSigned-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +4 -6
@@ -281,9 +281,8 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, reg =soc15_get_register_offset (THM_HWID ,0 , mmCG_FDO_CTRL1_BASE_IDX, mmCG_FDO_CTRL1); - duty100 = (cgs_read_register (hwmgr->device, reg) & -CG_FDO_CTRL1__FMAX_DUTY100_MASK ) >> -CG_FDO_CTRL1__FMAX_DUTY100__SHIFT ; + duty100 =CGS_REG_GET_FIELD (cgs_read_register (hwmgr->device, reg), +CG_FDO_CTRL1 ,FMAX_DUTY100 );if (duty100 ==0 )return -EINVAL ;
@@ -295,9 +294,8 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, reg =soc15_get_register_offset (THM_HWID ,0 , mmCG_FDO_CTRL0_BASE_IDX, mmCG_FDO_CTRL0);cgs_write_register (hwmgr->device, reg, - (cgs_read_register (hwmgr->device, reg) & - ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK ) | - (duty <<CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT )); +CGS_REG_SET_FIELD (cgs_read_register (hwmgr->device, reg), +CG_FDO_CTRL0 ,FDO_STATIC_DUTY , duty));return vega10_fan_ctrl_set_static_mode (hwmgr,FDO_PWM_MODE_STATIC ); }
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PATCH 13/16 drm/amd/powerplay: Fix indentation in vega10_fan_ctrl_reset_fan_speed_to_default()
In reply to a message not in the archiveSigned-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +4 -8
@@ -307,17 +307,13 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,*/ int vega10_fan_ctrl_reset_fan_speed_to_default (struct pp_hwmgr *hwmgr) { -int result; -if (hwmgr->thermal_controller.fanInfo.bNoFan)return 0 ; -if (PP_CAP (PHM_PlatformCaps_MicrocodeFanControl)) { - result =vega10_fan_ctrl_start_smc_fan_control (hwmgr); - }else - result =vega10_fan_ctrl_set_default_mode (hwmgr); - -return result; +if (PP_CAP (PHM_PlatformCaps_MicrocodeFanControl)) +return vega10_fan_ctrl_start_smc_fan_control (hwmgr); +else +return vega10_fan_ctrl_set_default_mode (hwmgr); }/**
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PATCH 14/16 drm/amd/powerplay: Tidy up vega10_fan_ctrl_set_fan_speed_rpm()
In reply to a message not in the archiveSigned-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +5 -5
@@ -330,8 +330,8 @@ int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)uint32_t reg;if (hwmgr->thermal_controller.fanInfo.bNoFan || - (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) || - (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM)) + (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) || + (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))return -1 ;if (PP_CAP (PHM_PlatformCaps_MicrocodeFanControl))
@@ -343,9 +343,9 @@ int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) reg =soc15_get_register_offset (THM_HWID ,0 , mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);cgs_write_register (hwmgr->device, reg, - (cgs_read_register (hwmgr->device, reg) & - ~CG_TACH_STATUS__TACH_PERIOD_MASK ) | - (tach_period <<CG_TACH_STATUS__TACH_PERIOD__SHIFT )); +CGS_REG_SET_FIELD (cgs_read_register (hwmgr->device, reg), +CG_TACH_STATUS ,TACH_PERIOD , + tach_period)); }return vega10_fan_ctrl_set_static_mode (hwmgr,FDO_PWM_MODE_STATIC_RPM ); }
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PATCH 15/16 drm/amd/powerplay: Tidy up vega10_thermal_set_temperature_range()
In reply to a message not in the archiveSigned-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +4 -14
@@ -405,20 +405,10 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, val =cgs_read_register (hwmgr->device, reg); - val &= (~THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK ); - val |= (5 <<THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT ); - - val &= (~THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK ); - val |= (1 <<THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT ); - - val &= (~THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK ); - val |= ((high /PP_TEMPERATURE_UNITS_PER_CENTIGRADES ) - <<THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT ); - - val &= (~THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK ); - val |= ((low /PP_TEMPERATURE_UNITS_PER_CENTIGRADES ) - <<THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT ); - + val =CGS_REG_SET_FIELD (val,THM_THERMAL_INT_CTRL ,MAX_IH_CREDIT ,5 ); + val =CGS_REG_SET_FIELD (val,THM_THERMAL_INT_CTRL ,THERM_IH_HW_ENA ,1 ); + val =CGS_REG_SET_FIELD (val,THM_THERMAL_INT_CTRL ,DIG_THERM_INTH , (high /PP_TEMPERATURE_UNITS_PER_CENTIGRADES )); + val =CGS_REG_SET_FIELD (val,THM_THERMAL_INT_CTRL ,DIG_THERM_INTL , (low /PP_TEMPERATURE_UNITS_PER_CENTIGRADES )); val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK );cgs_write_register (hwmgr->device, reg, val);
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PATCH 16/16 drm/amd/powerplay: Tidy up vega10_thermal_initialize()
In reply to a message not in the archiveSigned-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +5 -8
@@ -429,19 +429,16 @@ static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr) reg =soc15_get_register_offset (THM_HWID ,0 , mmCG_TACH_CTRL_BASE_IDX, mmCG_TACH_CTRL);cgs_write_register (hwmgr->device, reg, - (cgs_read_register (hwmgr->device, reg) & - ~CG_TACH_CTRL__EDGE_PER_REV_MASK ) | - ((hwmgr->thermal_controller.fanInfo. - ucTachometerPulsesPerRevolution -1 ) << -CG_TACH_CTRL__EDGE_PER_REV__SHIFT )); +CGS_REG_SET_FIELD (cgs_read_register (hwmgr->device, reg), +CG_TACH_CTRL ,EDGE_PER_REV , + hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution -1 )); } reg =soc15_get_register_offset (THM_HWID ,0 , mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);cgs_write_register (hwmgr->device, reg, - (cgs_read_register (hwmgr->device, reg) & - ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK ) | - (0x28 <<CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT )); +CGS_REG_SET_FIELD (cgs_read_register (hwmgr->device, reg), +CG_FDO_CTRL2 ,TACH_PWM_RESP_RATE ,0x28 ));return 0 ; }
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2.12.0 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
A message that is not in the archive (sent off-list or not yet received): [email protected]
Zhu, Rex
Reviewed-byRe: [PATCH 16/16] drm/amd/powerplay: Tidy up vega10_thermal_initialize()
Series is:
Reviewed-by Rex Zhu <[email protected]>
Best Regards
Rex
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Tom St Denis <[email protected]>
Sent: Saturday, September 9, 2017 12:01 AM
To: [email protected]
Cc: StDenis, Tom
Subject: [PATCH 16/16] drm/amd/powerplay: Tidy up vega10_thermal_initialize()
Signed-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +5 -8
@@ -429,19 +429,16 @@ static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr) reg =soc15_get_register_offset (THM_HWID ,0 , mmCG_TACH_CTRL_BASE_IDX, mmCG_TACH_CTRL);cgs_write_register (hwmgr->device, reg, - (cgs_read_register (hwmgr->device, reg) & - ~CG_TACH_CTRL__EDGE_PER_REV_MASK ) | - ((hwmgr->thermal_controller.fanInfo. - ucTachometerPulsesPerRevolution -1 ) << -CG_TACH_CTRL__EDGE_PER_REV__SHIFT )); +CGS_REG_SET_FIELD (cgs_read_register (hwmgr->device, reg), +CG_TACH_CTRL ,EDGE_PER_REV , + hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution -1 )); } reg =soc15_get_register_offset (THM_HWID ,0 , mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);cgs_write_register (hwmgr->device, reg, - (cgs_read_register (hwmgr->device, reg) & - ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK ) | - (0x28 <<CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT )); +CGS_REG_SET_FIELD (cgs_read_register (hwmgr->device, reg), +CG_FDO_CTRL2 ,TACH_PWM_RESP_RATE ,0x28 ));return 0 ; }
--
2.12.0
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