perf/x86/intel/cstate: add missing CPU IDs

PATCH New [email protected] 2 participants 6 messages Sep 8, 2017 – Sep 25, 2017

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2017-09-08 21:35 UTC #0 lore raw

PATCH 1/3 perf/x86/intel/cstate: add missing CPU IDs

From: Kan Liang <[email protected]>

Skylake server uses the same C-state residency events as Sandy Bridge.

Denverton and Gemini lake use the same C-state residency events as Apollo Lake.

Signed-off-by Kan Liang <[email protected]>

---
 arch/x86/events/intel/cstate.c | 4 ++++
 1 file changed, 4 insertions(+)

arch/x86/events/intel/cstate.c +4 -0

index 4cf100f..72db066 100644
@@ -552,6 +552,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 
 	X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_MOBILE,  snb_cstates),
 	X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_DESKTOP, snb_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_X, snb_cstates),
 
 	X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE,  snb_cstates),
 	X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates),

@@ -560,6 +561,9 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 	X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),
 
 	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT, glm_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_DENVERTON, glm_cstates),
+
+	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GEMINI_LAKE, glm_cstates),
 	{ },
 };
 MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);

Signature · 1 line

2.9.4

[email protected]

author

2017-09-08 21:35 UTC #1 lore raw

PATCH 2/3 perf/x86/msr: add missing CPU IDs

From: Kan Liang <[email protected]>

Goldmont, Glodmont plus and Xeon Phi have MSR_SMI_COUNT as well.

Signed-off-by Kan Liang <[email protected]>

---
 arch/x86/events/msr.c | 8 ++++++++
 1 file changed, 8 insertions(+)

arch/x86/events/msr.c +8 -0

index 4bb3ec6..0672367 100644
@@ -63,6 +63,14 @@ static bool test_intel(int idx)
 	case INTEL_FAM6_ATOM_SILVERMONT1:
 	case INTEL_FAM6_ATOM_SILVERMONT2:
 	case INTEL_FAM6_ATOM_AIRMONT:
+
+	case INTEL_FAM6_ATOM_GOLDMONT:
+	case INTEL_FAM6_ATOM_DENVERTON:
+
+	case INTEL_FAM6_ATOM_GEMINI_LAKE:
+
+	case INTEL_FAM6_XEON_PHI_KNL:
+	case INTEL_FAM6_XEON_PHI_KNM:
 		if (idx == PERF_MSR_SMI)
 			return true;
 		break;

Signature · 1 line

2.9.4

tip-bot for Kan Liang

merge bot

2017-09-25 10:10 UTC #2 lore raw

[tip:x86/urgent] perf/x86/msr: Add missing CPU IDs

perf/x86/msr: Add missing CPU IDs

Commit-ID:  1aaccc40a1864053da26605b0297be16dd52641e
Gitweb:     http://git.kernel.org/tip/1aaccc40a1864053da26605b0297be16dd52641e
Author:     Kan Liang <[email protected]>
AuthorDate: Fri, 8 Sep 2017 17:34:48 -0400
Committer:  Thomas Gleixner <[email protected]>
CommitDate: Mon, 25 Sep 2017 09:36:17 +0200

perf/x86/msr: Add missing CPU IDs

Goldmont, Glodmont plus and Xeon Phi have MSR_SMI_COUNT as well.

Signed-off-by Kan Liang <[email protected]>

Signed-off-by Thomas Gleixner <[email protected]>

Cc [email protected]

Link http://lkml.kernel.org/r/[email protected] open here

---
 arch/x86/events/msr.c | 8 ++++++++
 1 file changed, 8 insertions(+)

arch/x86/events/msr.c +8 -0

index 4bb3ec6..0672367 100644
@@ -63,6 +63,14 @@ static bool test_intel(int idx)
 	case INTEL_FAM6_ATOM_SILVERMONT1:
 	case INTEL_FAM6_ATOM_SILVERMONT2:
 	case INTEL_FAM6_ATOM_AIRMONT:
+
+	case INTEL_FAM6_ATOM_GOLDMONT:
+	case INTEL_FAM6_ATOM_DENVERTON:
+
+	case INTEL_FAM6_ATOM_GEMINI_LAKE:
+
+	case INTEL_FAM6_XEON_PHI_KNL:
+	case INTEL_FAM6_XEON_PHI_KNM:
 		if (idx == PERF_MSR_SMI)
 			return true;
 		break;

[email protected]

author

2017-09-08 21:35 UTC #3 lore raw

PATCH 3/3 perf/x86/intel/rapl: add missing CPU IDs

In reply to [email protected]

From: Kan Liang <[email protected]>

DENVERTON and GEMINI_LAKE support same RAPL counters as Apollo Lake.

Signed-off-by Kan Liang <[email protected]>

---
 arch/x86/events/intel/rapl.c | 3 +++
 1 file changed, 3 insertions(+)

arch/x86/events/intel/rapl.c +3 -0

index 8e2457c..005908e 100644
@@ -775,6 +775,9 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = {
 	X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_rapl_init),
 
 	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init),
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_DENVERTON, hsw_rapl_init),
+
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GEMINI_LAKE, hsw_rapl_init),
 	{},
 };

Signature · 1 line

2.9.4

tip-bot for Kan Liang

merge bot

2017-09-25 10:10 UTC #4 lore raw

[tip:x86/urgent] perf/x86/intel/rapl: Add missing CPU IDs

perf/x86/intel/rapl: Add missing CPU IDs

Commit-ID:  450a97893559354b927c935f39ee11126f01f520
Gitweb:     http://git.kernel.org/tip/450a97893559354b927c935f39ee11126f01f520
Author:     Kan Liang <[email protected]>
AuthorDate: Fri, 8 Sep 2017 17:34:49 -0400
Committer:  Thomas Gleixner <[email protected]>
CommitDate: Mon, 25 Sep 2017 09:36:17 +0200

perf/x86/intel/rapl: Add missing CPU IDs

DENVERTON and GEMINI_LAKE support same RAPL counters as Apollo Lake.

Signed-off-by Kan Liang <[email protected]>

Signed-off-by Thomas Gleixner <[email protected]>

Cc [email protected]

Link http://lkml.kernel.org/r/[email protected] open here

---
 arch/x86/events/intel/rapl.c | 3 +++
 1 file changed, 3 insertions(+)

arch/x86/events/intel/rapl.c +3 -0

index 8e2457c..005908e 100644
@@ -775,6 +775,9 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = {
 	X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_rapl_init),
 
 	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init),
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_DENVERTON, hsw_rapl_init),
+
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GEMINI_LAKE, hsw_rapl_init),
 	{},
 };

tip-bot for Kan Liang

merge bot

2017-09-25 10:10 UTC #5 lore raw

[tip:x86/urgent] perf/x86/intel/cstate: Add missing CPU IDs

In reply to [email protected]

perf/x86/intel/cstate: Add missing CPU IDs

Commit-ID:  b09c146f8f63c0e03adba74df76bf9c2be466fec
Gitweb:     http://git.kernel.org/tip/b09c146f8f63c0e03adba74df76bf9c2be466fec
Author:     Kan Liang <[email protected]>
AuthorDate: Fri, 8 Sep 2017 17:34:47 -0400
Committer:  Thomas Gleixner <[email protected]>
CommitDate: Mon, 25 Sep 2017 09:36:17 +0200

perf/x86/intel/cstate: Add missing CPU IDs

Skylake server uses the same C-state residency events as Sandy Bridge.

Denverton and Gemini lake use the same C-state residency events as Apollo Lake.

Signed-off-by Kan Liang <[email protected]>

Signed-off-by Thomas Gleixner <[email protected]>

Cc [email protected]

Link http://lkml.kernel.org/r/[email protected] open here

---
 arch/x86/events/intel/cstate.c | 4 ++++
 1 file changed, 4 insertions(+)

arch/x86/events/intel/cstate.c +4 -0

index 4cf100f..72db066 100644
@@ -552,6 +552,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 
 	X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_MOBILE,  snb_cstates),
 	X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_DESKTOP, snb_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_X, snb_cstates),
 
 	X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE,  snb_cstates),
 	X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates),

@@ -560,6 +561,9 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 	X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),
 
 	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT, glm_cstates),
+	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_DENVERTON, glm_cstates),
+
+	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GEMINI_LAKE, glm_cstates),
 	{ },
 };
 MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);