RISC-V Linux Port v8
Subsystems (15)
Palmer Dabbelt
maintainerI know it may not be the ideal time to submit a patch set right now, as it's the middle of the merge window, but things have calmed down quite a bit in the last month so I thought it would be good to get everyone on the same page. There's been a handful of changes since the last patch set, but most of them are fairly minor:
* We changed PAGE_OFFSET to allowing mapping more physical memory on 64-bit systems. This is user configurable, as it triggers a different code model that generates slightly less efficient code.
* The device tree binding documentation is back, I'd managed to lose it at some point.
* We now pass the atomic64 test suite.
* The SBI timer driver has been refactored.
To the best of by knowledge, all the feedback we've gotten so far has been taken into account for this patch set. If I've missed anyone's feedback I'm sorry, just point it out and I'll try to dig it up.
Just to be clear on timelines: we're not pushing to get into 4.14, but we are hoping we can make it in for 4.15. If I understand the process correctly, we should aim to get into linux-next some time in the next month so we can be merged during the next merge window.
As usual, we've make this patch set availiable Online in addition to via this submission. There are a handful of additional patches there, but those should all be going upstream either in other trees (though frequently in a heavily modified form, as there was already a fix floating around).
https://github.com/riscv/riscv-linux/tree/riscv-for-submission-v8
Here's a summary, in case something gets lost
[PATCH v8 01/18] MAINTAINERS: Add RISC-V
[PATCH v8 02/18] lib: Add shared copies of some GCC library routines [PATCH v8 03/18] dt-bindings: interrupt-controller: RISC-V local [PATCH v8 04/18] dt-bindings: interrupt-controller: RISC-V PLIC [PATCH v8 05/18] dt-bindings: RISC-V CPU Bindings
[PATCH v8 06/18] clocksource: New RISC-V SBI timer driver [PATCH v8 07/18] irqchip: RISC-V Local Interrupt Controller Driver [PATCH v8 08/18] irqchip: New RISC-V PLIC Driver
[PATCH v8 09/18] tty: New RISC-V SBI console driver [PATCH v8 10/18] RISC-V: Init and Halt Code
[PATCH v8 11/18] RISC-V: Atomic and Locking Code
[PATCH v8 12/18] RISC-V: Generic library routines and assembly [PATCH v8 13/18] RISC-V: ELF and module implementation [PATCH v8 14/18] RISC-V: Task implementation
[PATCH v8 15/18] RISC-V: Device, timer, IRQs, and the SBI [PATCH v8 16/18] RISC-V: Paging and MMU
[PATCH v8 17/18] RISC-V: User-facing API
[PATCH v8 18/18] RISC-V: Build Infastructure
Here's the change highlights from the whole patch set
(v7) It's been a while since my last patch set, but the changes han been fairly minimal:
* The PCI cleanup patches have been dropped, we'll do them as a separate patch set later.
* We've the Kconfig entries from CONFIG_ISA_* to CONFIG_RISCV_ISA_*, to make grep easier.
* There have been a handful of memory model related tweaks in I/O land, particularly relating the PCI and the upcoming platform specification. There are significant comments in the relevant files. This is still a WIP, but I think we're close to getting as good as we're going to get until we end up with some more specifications.
(v6) As it's been only a day since the v5 patch set, the changes are pretty minimal:
* The patch set is now based on linux-next/master, which I believe is a better base now that we're getting closer to upstream.
* EARLY_PRINTK is no longer an option. Since the SBI console is reasonable, there's no penalty to enabling it (and thus no benefit to disabling it).
* The mmap syscalls were refactored a bit.
(v5) Things have really started to calm down, so this is fairly similar to the v4 patch set. The most interesting changes include:
* We've moved back to a single patch set.
* SMP support has been fixed, I was accidentally running on a non-SMP configuration. There were various mistakes all over the tree as a result of this.
* The cmpxchg syscalls have been removed, as they were deemed a bad idea. As a result, RISC-V Linux systems mandate the A extension. The corresponding Kconfig entry to enable builds on non-A systems has been removed.
* A few more atomic fixes: mostly fence changes, but those resulted in a handful of additional macros that were no longer necessary.
* riscv_early_sie has been removed.
(v4) There have only been a few changes since the v3 patch set:
* The cmpxchg64 syscall is no longer enabled on 32-bit systems. It's not possible to provide this on SMP systems, and it's not necessary as glibc knows not to call it.
* We provide a ELF_HWCAP so users can determine the ISA of the machine the kernel is running on.
* The multi-line comments are in a better form.
* There were a handful of headers that could be replaced with the asm-generic versions, and a few unnecessary definitions.
* We no longer use printk, but instead use pr_*.
* A few Kconfig and defconfig entries have been cleaned up.
(v3) A highlight of the changes since the v2 patch set includes:
* We've split out all our drivers into separate patch sets, which I've already sent out to the relevant maintainers. I haven't included those patches in this patch set, but some of them are necessary to build our port. A git tree that contains all our patch sets merged together lives at
<https://github.com/riscv/riscv-linux/tree/riscv-for-submission-v3>.
* The patch set is now split up differently: rather than being split per directory it is split per topic. Hopefully this will make it easier to review the port on the mailing list. The split is a bit rough, so you probably still want to look at the patch set as a whole.
* atomic.h has been completely rewritten and is hopefully now correct. I've attempted to sanitize the various other memory model related code as well, and I think it should all be sane now aside from a handful of FIXMEs commented in the code.
* We've changed the cmpexchg syscall to always exist and to not be multiplexed. There is also a VDSO entry for compare and exchange, which allows kernels with the A extension to execute user code without the A extension reasonably fast.
* Our user-visible register state now contains enough space for the Q extension for 128-bit floating point, as well as a few words to allow extensibility to future ISA extensions like the eventual V extension for vectors.
* A handful of driver cleanups, but these have been split into separate patch sets now so I won't duplicate them here.
(v2) A highlight of the changes since the v1 patch set includes:
* We've split out our drivers into the right places, which means now there's a lot more patches. I'll be submitting these patches to various subsystem maintainers and including them in any future RISC-V patch sets until they've been merged.
* The SBI console driver has been completely rewritten to use the HVC helpers and is now significantly smaller.
* We've begun to use weaker barriers as opposed to just the big "fence". There's still some work to do here, specifically:
- We need fences in the relaxed MMIO functions.
- The non-relaxed MMIO functions are missing R/W bits on their fences.
- Many AMOs need the aq and rl bits set.
* We now have thread_info in task_struct. As a result, sscratch now contains TP instead of SP. This was necessary because thread_info is no longer on the stack.
* A few shared routines have been added that we use instead of creating another arch copy.
Palmer Dabbelt
maintainerPATCH v8 1/18 MAINTAINERS: Add RISC-V
From: Jonathan Neuschäfer <[email protected]>
RISC-V needs a MAINTAINERS entry. Let's add one.
Signed-off-by Jonathan Neuschäfer <[email protected]>
Signed-off-by Palmer Dabbelt <[email protected]>
--- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+)
MAINTAINERS +9 -0
@@ -11253,6 +11253,15 @@ S: Maintained F: drivers/mtd/nand/r852.c F: drivers/mtd/nand/r852.h +RISC-V ARCHITECTURE +M: Palmer Dabbelt <[email protected]> +M: Albert Ou <[email protected]> +L: [email protected] +T: git https://github.com/riscv/riscv-linux +S: Supported +F: arch/riscv/ +K: riscv + ROCCAT DRIVERS M: Stefan Achatz <[email protected]> W: http://sourceforge.net/projects/roccat/
Signature · 1 line
2.13.5
Re: [PATCH v8 01/18] MAINTAINERS: Add RISC-V
Quoted 1 line · Palmer Dabbelt
RISC-V needs a
MAINTAINERSentry. Let's add one.
[]
MAINTAINERS
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MAINTAINERS +0
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[]
MAINTAINERS S: Maintained · line 11263
Quoted 12 lines
MAINTAINERS +8
-0@@ -11253,6 +11253,15 @@ S: Maintained F: drivers/mtd/nand/r852.c F: drivers/mtd/nand/r852.h +RISC-V ARCHITECTURE +M: Palmer Dabbelt <[email protected]> +M: Albert Ou <[email protected]> +L: [email protected] +T: git https://github.com/riscv/riscv-linux +S: Supported +F: arch/riscv/ +K: riscv
perhaps add
N: riscv
Palmer Dabbelt
maintainerRe: [PATCH v8 01/18] MAINTAINERS: Add RISC-V
Quoted 20 lines · On Wed, 13 Sep 2017 07:39:05 PDT (-0700), [email protected] wrote:
Quoted 1 line · Palmer Dabbelt
RISC-V needs a
MAINTAINERSentry. Let's add one.[]
MAINTAINERS
Quoted 1 line
MAINTAINERS +0
-0[]
MAINTAINERS S: Maintained · line 11263
Quoted 12 lines
MAINTAINERS +8
-0@@ -11253,6 +11253,15 @@ S: Maintained F: drivers/mtd/nand/r852.c F: drivers/mtd/nand/r852.h +RISC-V ARCHITECTURE +M: Palmer Dabbelt <[email protected]> +M: Albert Ou <[email protected]> +L: [email protected] +T: git https://github.com/riscv/riscv-linux +S: Supported +F: arch/riscv/ +K: riscvperhaps add
Quoted 1 line
N: riscv
OK. I'm assuming we'll submit a v9 that's based on linux-next, so I'll just squash this in.
MAINTAINERS +1 -0
@@ -11261,6 +11261,7 @@ T: git https://github.com/riscv/riscv-linux S: Supported F: arch/riscv/ K: riscv +N: riscv ROCCAT DRIVERS M: Stefan Achatz <[email protected]>
Palmer Dabbelt
maintainerPATCH v8 2/18 lib: Add shared copies of some GCC library routines
In reply to Palmer DabbeltMany ports (m32r, microblaze, mips, parisc, score, and sparc) use functionally identical copies of various GCC library routine files, which came up as we were submitting the RISC-V port (which also uses some of these).
This patch adds a new copy of these library routine files, which are functionally identical to the various other copies. These are availiable via Kconfig as CONFIG_GENERIC_$ROUTINE, which currently isn't used anywhere.
Reviewed-by Geert Uytterhoeven <[email protected]>
Signed-off-by Palmer Dabbelt <[email protected]>
--- include/lib/libgcc.h | 43 +++++++++++++++++++++++++++++++ lib/Kconfig | 18 +++++++++++++ lib/Makefile | 8 ++++++ lib/ashldi3.c | 44 ++++++++++++++++++++++++++++++++ lib/ashrdi3.c | 46 +++++++++++++++++++++++++++++++++ lib/cmpdi2.c | 42 ++++++++++++++++++++++++++++++ lib/lshrdi3.c | 45 ++++++++++++++++++++++++++++++++ lib/muldi3.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++ lib/ucmpdi2.c | 35 +++++++++++++++++++++++++ 9 files changed, 353 insertions(+) create mode 100644 include/lib/libgcc.h create mode 100644 lib/ashldi3.c create mode 100644 lib/ashrdi3.c create mode 100644 lib/cmpdi2.c create mode 100644 lib/lshrdi3.c create mode 100644 lib/muldi3.c create mode 100644 lib/ucmpdi2.c
include/lib/libgcc.h new file +43 -0
@@ -0,0 +1,43 @@ +/* +* include/lib/libgcc.h +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, see the file COPYING, or write +* to the Free Software Foundation, Inc. +*/ + +#ifndef __LIB_LIBGCC_H +#define __LIB_LIBGCC_H + +#include <asm/byteorder.h> + +typedef int word_type __attribute__ ((mode (__word__))); + +#ifdef __BIG_ENDIAN +struct DWstruct { +int high, low; +}; +#elif defined(__LITTLE_ENDIAN) +struct DWstruct { +int low, high; +}; +#else +#error I feel sick. +#endif + +typedef union { +struct DWstruct s; +long long ll; +}DWunion ; + +#endif /* __ASM_LIBGCC_H */
lib/Kconfig +18 -0
@@ -576,3 +576,21 @@ config PRIME_NUMBERS tristate endmenu + +config GENERIC_ASHLDI3 + bool + +config GENERIC_ASHRDI3 + bool + +config GENERIC_LSHRDI3 + bool + +config GENERIC_MULDI3 + bool + +config GENERIC_CMPDI2 + bool + +config GENERIC_UCMPDI2 + bool
lib/Makefile +8 -0
@@ -243,3 +243,11 @@ UBSAN_SANITIZE_ubsan.o := n obj-$(CONFIG_SBITMAP) += sbitmap.o obj-$(CONFIG_PARMAN) += parman.o + +# GCC library routines +obj-$(CONFIG_GENERIC_ASHLDI3) += ashldi3.o +obj-$(CONFIG_GENERIC_ASHRDI3) += ashrdi3.o +obj-$(CONFIG_GENERIC_LSHRDI3) += lshrdi3.o +obj-$(CONFIG_GENERIC_MULDI3) += muldi3.o +obj-$(CONFIG_GENERIC_CMPDI2) += cmpdi2.o +obj-$(CONFIG_GENERIC_UCMPDI2) += ucmpdi2.o
lib/ashldi3.c new file +44 -0
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lib/ashrdi3.c new file +46 -0
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lib/cmpdi2.c new file +42 -0
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lib/lshrdi3.c new file +45 -0
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lib/muldi3.c new file +72 -0
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lib/ucmpdi2.c new file +35 -0
@@ -0,0 +1,35 @@ +/* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, see the file COPYING, or write +* to the Free Software Foundation, Inc. +*/ + +#include <linux/module.h> +#include <lib/libgcc.h> + +word_type __ucmpdi2 (unsigned long long a,unsigned long long b) +{ +const DWunion au = {.ll = a}; +const DWunion bu = {.ll = b}; + +if ((unsigned int ) au.s.high < (unsigned int ) bu.s.high) +return 0 ; +else if ((unsigned int ) au.s.high > (unsigned int ) bu.s.high) +return 2 ; +if ((unsigned int ) au.s.low < (unsigned int ) bu.s.low) +return 0 ; +else if ((unsigned int ) au.s.low > (unsigned int ) bu.s.low) +return 2 ; +return 1 ; +} +EXPORT_SYMBOL (__ucmpdi2);
Signature · 1 line
2.13.5
Palmer Dabbelt
maintainerPATCH v8 3/18 dt-bindings: interrupt-controller: RISC-V local interrupt controller docs
In reply to Palmer DabbeltThis patch adds documentation on the RISC-V local interrupt controller, which is a per-hart interrupt controller that manages all interrupts entering a RISC-V hart. This interrupt controller is present on all RISC-V systems.
Signed-off-by Palmer Dabbelt <[email protected]>
--- .../interrupt-controller/riscv,cpu-intc.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt new file +41 -0
@@ -0,0 +1,41 @@ +RISC-V Hart-Level Interrupt Controller (HLIC) +--------------------------------------------- + +RISC-V cores include Control Status Registers (CSRs) which are local to each +hart and can be read or written by software. Some of these CSRs are used to +control local interrupts connected to the core. Every interrupt is ultimately +routed through a hart's HLIC before it interrupts that hart. + +The RISC-V supervisor ISA manual specifies three interrupt sources that are +attached to every HLIC: software interrupts, the timer interrupt, and external +interrupts. Software interrupts are used to send IPIs between cores. The +timer interrupt comes from an architecturally mandated real-time timer that is +controller via SBI calls and CSR reads. External interrupts connect all other +device interrupts to the HLIC, which are routed via the platform-level +interrupt controller (PLIC). + +All RISC-V systems that conform to the supervisor ISA specification are +required to have a HLIC with these three interrupt sources present. Since the +interrupt map is defined by the ISA it's not listed in the HLIC's device tree +entry, though external interrupt controllers (like the PLIC, for example) will +need to define how their interrupts map to the relevant HLICs. + +Required properties: +- compatible : "riscv,cpu-intc" +- #interrupt-cells : should be <1> +- interrupt-controller : Identifies the node as an interrupt controller + +Furthermore, this interrupt-controller MUST be embedded inside the cpu +definition of the hart whose CSRs control these local interrupts. + +An example device tree entry for a HLIC is show below. + + cpu1: cpu@1 { + compatible = "riscv"; + ... + cpu1-intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + };
Signature · 1 line
2.13.5
Palmer Dabbelt
maintainerPATCH v8 4/18 dt-bindings: interrupt-controller: RISC-V PLIC documentation
In reply to Palmer DabbeltThis patch adds documentation for the platform-level interrupt controller (PLIC) found in all RISC-V systems. This interrupt controller routes interrupts from all the devices in the system to each hart-local interrupt controller.
Note: the DTS bindings for the PLIC aren't set in stone yet, as we might want to change how we're specifying holes in the hart list.
Signed-off-by Palmer Dabbelt <[email protected]>
--- .../bindings/interrupt-controller/riscv,plic0.txt | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,plic0.txt
Documentation/devicetree/bindings/interrupt-controller/riscv,plic0.txt new file +55 -0
@@ -0,0 +1,55 @@ +RISC-V Platform-Level Interrupt Controller (PLIC) +------------------------------------------------- + +The RISC-V supervisor ISA specification allows for the presence of a +platform-level interrupt controller (PLIC). The PLIC connects all external +interrupts in the system to all hart contexts in the system, via the external +interrupt source in each hart's hart-local interrupt controller (HLIC). A hart +context is a privilege mode in a hardware execution thread. For example, in +an 4 core system with 2-way SMT, you have 8 harts and probably at least two +privilege modes per hart; machine mode and supervisor mode. + +Each interrupt can be enabled on per-context basis. Any context can claim +a pending enabled interrupt and then release it once it has been handled. + +Each interrupt has a configurable priority. Higher priority interrupts are +serviced firs. Each context can specify a priority threshold. Interrupts +with priority below this threshold will not cause the PLIC to raise its +interrupt line leading to the context. + +While the PLIC supports both edge-triggered and level-triggered interrupts, +interrupt handlers are oblivious to this distinction and therefor it is not +specific in the PLIC device-tree binding. + +While the RISC-V ISA doesn't specify a memory layout for the PLIC, the +"riscv,plic0" device is a concrete implementation of the PLIC that contains a +specific memory layout. More details about the memory layout of the +"riscv,plic0" device can be found as a comment in the device driver, or as part +of the SiFive U5 Coreplex Series Manual (page 22 of the PDF of version 1.0) +<https://www.sifive.com/documentation/coreplex/u5-coreplex-series-manual/> + +Required properties: +- compatible : "riscv,plic0" +- #address-cells : should be <0> +- #interrupt-cells : should be <1> +- interrupt-controller : Identifies the node as an interrupt controller +- reg : Should contain 1 register range (address and length) +- interrupts-extended : Specifies which contexts are connected to the PLIC, + with "-1" specifying that a context is not present. + +Example: + + plic: interrupt-controller@c000000 { + #address-cells = <0>; + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = < + &cpu0-intc 11 + &cpu1-intc 11 &cpu1-intc 9 + &cpu2-intc 11 &cpu2-intc 9 + &cpu3-intc 11 &cpu3-intc 9 + &cpu4-intc 11 &cpu4-intc 9>; + reg = <0xc000000 0x4000000>; + riscv,ndev = <10>; + };
Signature · 1 line
2.13.5
Rob Herring
maintainerRe: [PATCH v8 04/18] dt-bindings: interrupt-controller: RISC-V PLIC documentation
Quoted 4 lines · Palmer Dabbelt
This patch adds documentation for the platform-level interrupt controller (PLIC) found in all RISC-V systems. This interrupt controller routes interrupts from all the devices in the system to each hart-local interrupt controller.
It has been mentioned before, but please copy the right people and lists. IOW, use scripts/get_maintainers.pl. You've got a whole bunch of people CCed and probably most don't care about DT bindings at all.
Rob
Palmer Dabbelt
maintainerRe: [PATCH v8 04/18] dt-bindings: interrupt-controller: RISC-V PLIC documentation
Quoted 9 lines · On Fri, 15 Sep 2017 07:34:33 PDT (-0700), [email protected] wrote:
Quoted 4 lines · Palmer Dabbelt
This patch adds documentation for the platform-level interrupt controller (PLIC) found in all RISC-V systems. This interrupt controller routes interrupts from all the devices in the system to each hart-local interrupt controller.
It has been mentioned before, but please copy the right people and lists. IOW, use
scripts/get_maintainers.pl. You've got a whole bunch of people CCed and probably most don't care about DT bindings at all.
Sorry about that -- I'd just been CCing everyone on the entire patch set so everyone's on the same page. It was suggested we start splitting up the patches again, so if you think it's better I can submit just the binding patches as another patch set right now? Then they'll only go to the people from get_maintainers.
Palmer Dabbelt
maintainerPATCH v8 5/18 dt-bindings: RISC-V CPU Bindings
In reply to Palmer DabbeltThis patch adds device tree bindings for RISC-V CPUs, patterned after the ARM device tree CPU bindings.
Signed-off-by Palmer Dabbelt <[email protected]>
--- Documentation/devicetree/bindings/riscv/cpus.txt | 162 +++++++++++++++++++++++ 1 file changed, 162 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/cpus.txt
Documentation/devicetree/bindings/riscv/cpus.txt new file +162 -0
@@ -0,0 +1,162 @@ +=================== +RISC-V CPU Bindings +=================== + +The device tree allows to describe the layout of CPUs in a system through +the "cpus" node, which in turn contains a number of subnodes (ie "cpu") +defining properties for every cpu. + +Bindings for CPU nodes follow the Devicetree Specification, available from: + +https://www.devicetree.org/specifications/ + +with updates for 32-bit and 64-bit RISC-V systems provided in this document. + +=========== +Terminology +=========== + +This document uses some terminology common to the RISC-V community that is not +widely used, the definitions of which are listed here: + +* hart: A hardware execution context, which contains all the state mandated by + the RISC-V ISA: a PC and some registers. This terminology is designed to + disambiguate software's view of execution contexts from any particular + microarchitectural implementation strategy. For example, my Intel laptop is + described as having one socket with two cores, each of which has two hyper + threads. Therefore this system has four harts. + +===================================== +cpus and cpu node bindings definition +===================================== + +The RISC-V architecture, in accordance with the Devicetree Specification, +requires the cpus and cpu nodes to be present and contain the properties +described below. + +- cpus node + + Description: Container of cpu nodes + + The node name must be "cpus". + + A cpus node must define the following properties: + + - #address-cells + Usage: required + Value type: <u32> + Definition: must be set to 1 + - #size-cells + Usage: required + Value type: <u32> + Definition: must be set to 0 + +- cpu node + + Description: Describes a hart context + + PROPERTIES + + - device_type + Usage: required + Value type: <string> + Definition: must be "cpu" + - reg + Usage: required + Value type: <u32> + Definition: The hart ID of this CPU node + - compatible: + Usage: required + Value type: <stringlist> + Definition: must contain "riscv", may contain one of + "sifive,rocket0" + - mmu-type: + Usage: optional + Value type: <string> + Definition: Specifies the CPU's MMU type. Possible values are + "riscv,sv32" + "riscv,sv39" + "riscv,sv48" + - riscv,isa: + Usage: required + Value type: <string> + Definition: Contains the RISC-V ISA string of this hart. These + ISA strings are defined by the RISC-V ISA manual. + +Example: SiFive Freedom U540G Development Kit +--------------------------------------------- + +This system contains two harts: a hart marked as disabled that's used for +low-level system tasks and should be ignored by Linux, and a second hart that +Linux is allowed to run on. + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + cpu@0 { + clock-frequency = <1600000000>; + compatible = "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + next-level-cache = <&L15 &L0>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + L10: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu@1 { + clock-frequency = <1600000000>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L15 &L0>; + reg = <1>; + riscv,isa = "rv64imafdc"; + status = "okay"; + tlb-split; + L13: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + +Example: Spike ISA Simulator with 1 Hart +---------------------------------------- + +This device tree matches the Spike ISA golden model as run with `spike -p1`. + + cpus { + cpu@0 { + device_type = "cpu"; + reg = <0x00000000>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv48"; + clock-frequency = <0x3b9aca00>; + interrupt-controller { + #interrupt-cells = <0x00000001>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + } + } + }
Signature · 1 line
2.13.5
Palmer Dabbelt
maintainerPATCH v8 6/18 clocksource: New RISC-V SBI timer driver
In reply to Palmer DabbeltThe RISC-V ISA defines a per-hart real-time clock and timer, which is present on all systems. The clock is accessed via the 'rdtime' pseudo-instruction (which reads a CSR), and the timer is set via an SBI call.
This driver attempts to split out the RISC-V ISA specific mechanisms of accessing the hardware from the clocksource driver by taking a pair of function pointers to issue the actual RISC-V specific instructions.
Signed-off-by Dmitriy Cherkasov <[email protected]>
Signed-off-by Palmer Dabbelt <[email protected]>
--- drivers/clocksource/Kconfig | 8 ++++++ drivers/clocksource/Makefile | 1 + drivers/clocksource/riscv_timer.c | 58 +++++++++++++++++++++++++++++++++++++++ include/linux/timer_riscv.h | 34 +++++++++++++++++++++++ 4 files changed, 101 insertions(+) create mode 100644 drivers/clocksource/riscv_timer.c create mode 100644 include/linux/timer_riscv.h
drivers/clocksource/Kconfig +8 -0
@@ -607,4 +607,12 @@ config CLKSRC_ST_LPC Enable this option to use the Low Power controller timer as clocksource. +config RISCV_TIMER + bool "Timer for the RISC-V platform" if COMPILE_TEST + depends on RISCV + help + This enables the per-hart timer built into all RISC-V systems, which + is accessed via both the SBI and the rdcycle instruction. This is + required for all RISC-V systems. + endmenu
drivers/clocksource/Makefile +1 -0
@@ -73,3 +73,4 @@ obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o obj-$(CONFIG_H8300_TPU) += h8300_tpu.o obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o obj-$(CONFIG_X86_NUMACHIP) += numachip.o +obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
drivers/clocksource/riscv_timer.c new file +58 -0
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include/linux/timer_riscv.h new file +34 -0
@@ -0,0 +1,34 @@ +/* +* Copyright (C) 2017 SiFive +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef _LINUX_TIMER_RISCV_H +#define _LINUX_TIMER_RISCV_H + +/* +* All RISC-V systems have a timer attached to every hart. These timers can be +* read by the 'rdcycle' pseudo instruction, and can use the SBI to setup +* events. In order to abstract the architecture-specific timer reading and +* setting functions away from the clock event insertion code, we provide +* function pointers to the clockevent subsystem that perform two basic operations: +* rdtime() reads the timer on the current CPU, and next_event(delta) sets the +* next timer event to 'delta' cycles in the future. As the timers are +* inherently a per-cpu resource, these callbacks perform operations on the +* current hart. There is guaranteed to be exactly one timer per hart on all +* RISC-V systems. +*/ +void timer_riscv_init (int cpu_id, +unsigned long riscv_timebase, +int (*next_event)(unsigned long ,struct clock_event_device *)); + +void clocksource_riscv_init (unsigned long long (*rdtime)(struct clocksource *)); +#endif
Signature · 1 line
2.13.5
Palmer Dabbelt
maintainerPATCH v8 7/18 irqchip: RISC-V Local Interrupt Controller Driver
In reply to Palmer DabbeltThis patch adds a driver that manages the local interrupts on each RISC-V hart, as specifiec by the RISC-V supervisor level ISA manual. The local interrupt controller manages software interrupts, timer interrupts, and hardware interrupts (which are routed via the platform level interrupt controller). Per-hart local interrupt controllers are found on all RISC-V systems.
Signed-off-by Palmer Dabbelt <[email protected]>
--- drivers/irqchip/Kconfig | 14 +++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-intc.c | 210 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 225 insertions(+) create mode 100644 drivers/irqchip/irq-riscv-intc.c
drivers/irqchip/Kconfig +14 -0
@@ -306,3 +306,17 @@ config QCOM_IRQ_COMBINER help Say yes here to add support for the IRQ combiner devices embedded in Qualcomm Technologies chips. + +config RISCV_INTC + def_bool y if RISCV + #bool "RISC-V Interrupt Controller" + depends on RISCV + default y + help + This enables support for the local interrupt controller found in + standard RISC-V systems. The local interrupt controller handles + timer interrupts, software interrupts, and hardware interrupts. + Without a local interrupt controller the system will be unable to + handle any interrupts, including those passed via the PLIC. + + If you don't know what to do here, say Y.
drivers/irqchip/Makefile +1 -0
@@ -78,3 +78,4 @@ obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o +obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o
drivers/irqchip/irq-riscv-intc.c new file +210 -0
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Signature · 1 line
2.13.5
Palmer Dabbelt
maintainerPATCH v8 8/18 irqchip: New RISC-V PLIC Driver
In reply to Palmer DabbeltThis patch adds a driver for the Platform Level Interrupt Controller (PLIC) specified as part of the RISC-V supervisor level ISA manual. The PLIC connocts global interrupt sources to the local interrupt controller on each hart. A PLIC is present on all RISC-V systems.
Signed-off-by Palmer Dabbelt <[email protected]>
--- drivers/irqchip/Kconfig | 13 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-plic.c | 379 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 393 insertions(+) create mode 100644 drivers/irqchip/irq-riscv-plic.c
drivers/irqchip/Kconfig +13 -0
@@ -307,6 +307,19 @@ config QCOM_IRQ_COMBINER Say yes here to add support for the IRQ combiner devices embedded in Qualcomm Technologies chips. +config RISCV_PLIC + bool "Platform-Level Interrupt Controller" + depends on RISCV + default y + help + This enables support for the PLIC chip found in standard RISC-V + systems. The PLIC controls devices interrupts and connects them to + each core's local interrupt controller. Aside from timer and + software interrupts, all other interrupt sources (MSI, GPIO, etc) + are subordinate to the PLIC. + + If you don't know what to do here, say Y. + config RISCV_INTC def_bool y if RISCV #bool "RISC-V Interrupt Controller"
drivers/irqchip/Makefile +1 -0
@@ -78,4 +78,5 @@ obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o +obj-$(CONFIG_RISCV_PLIC) += irq-riscv-plic.o obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o
drivers/irqchip/irq-riscv-plic.c new file +379 -0
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Signature · 1 line
2.13.5
Re: [patches] [PATCH v8 08/18] irqchip: New RISC-V PLIC Driver
Hi,
Quoted 3 lines · Palmer Dabbelt
This patch adds a driver for the Platform Level Interrupt Controller (PLIC) specified as part of the RISC-V supervisor level ISA manual. The PLIC connocts global interrupt sources to the local interrupt
s/connocts/connects/?
Quoted 4 lines
controller on each hart. A PLIC is present on all RISC-V systems.
Signed-off-by Palmer Dabbelt <[email protected]>---
[...]
Quoted 3 lines
+/*
+ * The PLIC consists of memory-mapped control registers, with a memory map as
+ * follows:
This memory map is mostly still as confusing as before (see my email in the v7 thread).
Quoted 27 lines
+ *
+ * base +0x000000: Reserved (interrupt source 0 does not exist)
+ * base +0x000004: Interrupt source 1 priority
+ * base +0x000008: Interrupt source 2 priority
+ * ...
+ * base +0x000FFC: Interrupt source 1023 priority
+ * base +0x001000: Pending 0
+ * base +0x001FFF: Pending
+ * base +0x002000: Enable bits for sources 0-31 on context 0
+ * base +0x002004: Enable bits for sources 32-63 on context 0
+ * ...
+ * base +0x0020FC: Enable bits for sources 992-1023 on context 0
+ * base +0x002080: Enable bits for sources 0-31 on context 1
+ * ...
+ * base +0x002100: Enable bits for sources 0-31 on context 2
+ * ...
+ * base +0x1F1F80: Enable bits for sources 992-1023 on context 15871
+ * base +0x1F1F84: Reserved
+ * ... (higher context IDs would fit here, but wouldn't fit
+ * inside the per-context priority vector)
+ * base +0x1FFFFC: Reserved
+ * base +0x200000: Priority threshold for context 0
+ * base +0x200004: Claim/complete for context 0
+ * base +0x200008: Reserved
+ * ...
+ * base +0x200FFC: Reserved
+ * base +0x201000: Priority threshold for context 1
Quoted 8 lines
+ * base +
0x201004: Claim/complete for context 1
+ * ...
+ * base +0xFFE000: Priority threshold for context 15871
+ * base +0xFFE004: Claim/complete for context 15871
+ * base +0xFFE008: Reserved
+ * ...
+ * base +0xFFFFFC: Reserved
+ */
Jonathan Neuschäfer
Palmer Dabbelt
maintainerPATCH v8 9/18 tty: New RISC-V SBI console driver
In reply to Palmer DabbeltThe RISC-V ISA defines a simple console that is availiable via SBI calls on all systems. This patch adds a driver for this console interface that can act as both a target for early printk and as the system console.
Signed-off-by Palmer Dabbelt <[email protected]>
--- arch/riscv/include/asm/hvc_riscv_sbi.h | 25 ++++++++++ drivers/tty/hvc/Kconfig | 11 +++++ drivers/tty/hvc/Makefile | 1 + drivers/tty/hvc/hvc_riscv_sbi.c | 90 ++++++++++++++++++++++++++++++++++ 4 files changed, 127 insertions(+) create mode 100644 arch/riscv/include/asm/hvc_riscv_sbi.h create mode 100644 drivers/tty/hvc/hvc_riscv_sbi.c
arch/riscv/include/asm/hvc_riscv_sbi.h new file +25 -0
@@ -0,0 +1,25 @@ +/* +* RISC-V SBI console interface +* +* Copyright (C) 2017 SiFive +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef _ASM_RISCV_HVC_RISCV_SBI_H +#define _ASM_RISCV_HVC_RISCV_SBI_H + +/* +* We always support CONFIG_EARLY_PRINTK via the SBI console driver because it +* works well enough that there's no penalty to doing so. +*/ +extern struct console riscv_sbi_early_console_dev__initdata ; + +#endif
drivers/tty/hvc/Kconfig +11 -0
@@ -97,6 +97,17 @@ config HVC_BFIN_JTAG the HVC driver. If you don't have JTAG, then you probably don't want this option. +config HVC_RISCV_SBI + bool "RISC-V SBI console support" + depends on RISCV + select HVC_DRIVER + default y + help + This enables support for console output via RISC-V SBI calls, which + is normally used only during boot to output printk. + + If you don't know what do to here, say Y. + config HVCS tristate "IBM Hypervisor Virtual Console Server support" depends on PPC_PSERIES && HVC_CONSOLE
drivers/tty/hvc/Makefile +1 -0
@@ -11,3 +11,4 @@ obj-$(CONFIG_HVC_IUCV) += hvc_iucv.o obj-$(CONFIG_HVC_UDBG) += hvc_udbg.o obj-$(CONFIG_HVC_BFIN_JTAG) += hvc_bfin_jtag.o obj-$(CONFIG_HVCS) += hvcs.o +obj-$(CONFIG_HVC_RISCV_SBI) += hvc_riscv_sbi.o
drivers/tty/hvc/hvc_riscv_sbi.c new file +90 -0
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Signature · 1 line
2.13.5
Palmer Dabbelt
maintainerPATCH v8 10/18 RISC-V: Init and Halt Code
In reply to Palmer DabbeltThis contains the various __init C functions, the initial assembly kernel entry point, and the code to reset the system. When a file was init-related this patch contains the entire file.
Signed-off-by Palmer Dabbelt <[email protected]>
--- arch/riscv/include/asm/bug.h | 88 ++++++++++++++ arch/riscv/include/asm/cache.h | 22 ++++ arch/riscv/include/asm/smp.h | 52 +++++++++ arch/riscv/kernel/cacheinfo.c | 105 +++++++++++++++++ arch/riscv/kernel/cpu.c | 108 ++++++++++++++++++ arch/riscv/kernel/head.S | 156 +++++++++++++++++++++++++ arch/riscv/kernel/irq.c | 20 ++++ arch/riscv/kernel/reset.c | 36 ++++++ arch/riscv/kernel/setup.c | 254 +++++++++++++++++++++++++++++++++++++++++ arch/riscv/kernel/smp.c | 110 ++++++++++++++++++ arch/riscv/kernel/smpboot.c | 114 ++++++++++++++++++ arch/riscv/kernel/time.c | 78 +++++++++++++ arch/riscv/kernel/traps.c | 180 +++++++++++++++++++++++++++++ arch/riscv/kernel/vdso.c | 125 ++++++++++++++++++++ arch/riscv/mm/init.c | 70 ++++++++++++ 15 files changed, 1518 insertions(+) create mode 100644 arch/riscv/include/asm/bug.h create mode 100644 arch/riscv/include/asm/cache.h create mode 100644 arch/riscv/include/asm/smp.h create mode 100644 arch/riscv/kernel/cacheinfo.c create mode 100644 arch/riscv/kernel/cpu.c create mode 100644 arch/riscv/kernel/head.S create mode 100644 arch/riscv/kernel/irq.c create mode 100644 arch/riscv/kernel/reset.c create mode 100644 arch/riscv/kernel/setup.c create mode 100644 arch/riscv/kernel/smp.c create mode 100644 arch/riscv/kernel/smpboot.c create mode 100644 arch/riscv/kernel/time.c create mode 100644 arch/riscv/kernel/traps.c create mode 100644 arch/riscv/kernel/vdso.c create mode 100644 arch/riscv/mm/init.c
arch/riscv/include/asm/bug.h new file +88 -0
@@ -0,0 +1,88 @@ +/* +* Copyright (C) 2012 Regents of the University of California +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef _ASM_RISCV_BUG_H +#define _ASM_RISCV_BUG_H + +#include <linux/compiler.h> +#include <linux/const.h> +#include <linux/types.h> + +#include <asm/asm.h> + +#ifdef CONFIG_GENERIC_BUG +#define __BUG_INSN _AC(0x00100073, UL)/* ebreak */ + +#ifndef __ASSEMBLY__ +typedef u32 bug_insn_t ; + +#ifdef CONFIG_GENERIC_BUG_RELATIVE_POINTERS +#define __BUG_ENTRY_ADDR INT " 1b - 2b" +#define __BUG_ENTRY_FILE INT " %0 - 2b" +#else +#define __BUG_ENTRY_ADDR RISCV_PTR " 1b" +#define __BUG_ENTRY_FILE RISCV_PTR " %0" +#endif + +#ifdef CONFIG_DEBUG_BUGVERBOSE +#define __BUG_ENTRY \ + __BUG_ENTRY_ADDR "\n\t" \ + __BUG_ENTRY_FILE "\n\t" \ + SHORT " %1" +#else +#define __BUG_ENTRY \ + __BUG_ENTRY_ADDR +#endif + +#define BUG () \ +do { \ + __asm__ __volatile__ ( \ + "1:\n\t" \ + "ebreak\n" \ + ".pushsection __bug_table,\"a\"\n\t" \ + "2:\n\t" \ + __BUG_ENTRY "\n\t" \ + ".org 2b + %2\n\t" \ + ".popsection" \ + : \ + : "i" (__FILE__), "i" (__LINE__), \ + "i" (sizeof(struct bug_entry))); \ + unreachable(); \ +} while (0) +#endif /* !__ASSEMBLY__ */ +#else /* CONFIG_GENERIC_BUG */ +#ifndef __ASSEMBLY__ +#define BUG () \ +do { \ + __asm__ __volatile__ ("ebreak\n"); \ + unreachable(); \ +} while (0) +#endif /* !__ASSEMBLY__ */ +#endif /* CONFIG_GENERIC_BUG */ + +#define HAVE_ARCH_BUG + +#include <asm-generic/bug.h> + +#ifndef __ASSEMBLY__ + +struct pt_regs ; +struct task_struct ; + +extern void die (struct pt_regs *regs,const char *str); +extern void do_trap (struct pt_regs *regs,int signo,int code, +unsigned long addr,struct task_struct *tsk); + +#endif /* !__ASSEMBLY__ */ + +#endif /* _ASM_RISCV_BUG_H */
arch/riscv/include/asm/cache.h new file +22 -0
@@ -0,0 +1,22 @@ +/* +* Copyright (C) 2017 Chen Liqin <[email protected]> +* Copyright (C) 2012 Regents of the University of California +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef _ASM_RISCV_CACHE_H +#define _ASM_RISCV_CACHE_H + +#define L1_CACHE_SHIFT 6 + +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +#endif /* _ASM_RISCV_CACHE_H */
arch/riscv/include/asm/smp.h new file +52 -0
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arch/riscv/kernel/cacheinfo.c new file +105 -0
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arch/riscv/kernel/cpu.c new file +108 -0
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arch/riscv/kernel/head.S new file +156 -0
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arch/riscv/kernel/irq.c new file +20 -0
@@ -0,0 +1,20 @@ +/* +* Copyright (C) 2012 Regents of the University of California +* Copyright (C) 2017 SiFive +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <linux/irqchip.h> + +void __init init_IRQ (void ) +{ +irqchip_init (); +}
arch/riscv/kernel/reset.c new file +36 -0
@@ -0,0 +1,36 @@ +/* +* Copyright (C) 2012 Regents of the University of California +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <linux/reboot.h> +#include <linux/export.h> +#include <asm/sbi.h> + +void (*pm_power_off)(void ) = machine_power_off; +EXPORT_SYMBOL (pm_power_off); + +void machine_restart (char *cmd) +{ +do_kernel_restart (cmd); +while (1 ); +} + +void machine_halt (void ) +{ +machine_power_off (); +} + +void machine_power_off (void ) +{ +sbi_shutdown (); +while (1 ); +}
arch/riscv/kernel/setup.c new file +254 -0
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arch/riscv/kernel/smp.c new file +110 -0
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arch/riscv/kernel/smpboot.c new file +114 -0
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arch/riscv/kernel/time.c new file +78 -0
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arch/riscv/kernel/traps.c new file +180 -0
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arch/riscv/kernel/vdso.c new file +125 -0
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arch/riscv/mm/init.c new file +70 -0
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Signature · 1 line
2.13.5
Re: [PATCH v8 10/18] RISC-V: Init and Halt Code
Quoted 6 lines · Palmer Dabbelt
This contains the various
__initC functions, the initial assembly kernel entry point, and the code to reset the system. When a file was init-related this patch contains the entire file.Signed-off-by Palmer Dabbelt <[email protected]>---
[ ... ]
Quoted 74 lines
arch/riscv/kernel/time.c new file +68
-0@@ -0,0 +1,78 @@ +/* +* Copyright (C) 2012 Regents of the University of California +* Copyright (C) 2017 SiFive +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <linux/clocksource.h> +#include <linux/clockchips.h> +#include <linux/delay.h> +#include <linux/timer_riscv.h> + +#include <asm/sbi.h> + +unsigned long riscv_timebase; + +DECLARE_PER_CPU(struct clock_event_device, riscv_clock_event); + +static int next_event (unsigned long delta,struct clock_event_device *ce) +{ +/* +* time_init() allocates a timer for each CPU. Since we're writing the +* timer comparison register here we can't allow the timers to cross +* harts. +*/ +BUG_ON (ce !=this_cpu_ptr (&riscv_clock_event)); +sbi_set_timer (get_cycles64 () + delta); +return 0 ; +} + +static unsigned long long rdtime (struct clocksource *cs) +{ +/* +* It's guarnteed that all the timers across all the harts are +* synchronized within one tick of each other, so while this could +* technically go backwards when hopping between CPUs, practically it +* won't happen. +*/ +return get_cycles64 (); +} + +void riscv_timer_interrupt (void ) +{ +struct clock_event_device *evdev =this_cpu_ptr (&riscv_clock_event); + + evdev->event_handler (evdev); +} + +void __init init_clockevent (void ) +{ +int cpu_id =smp_processor_id (); + +timer_riscv_init (cpu_id, riscv_timebase, &next_event); +csr_set (sie,SIE_STIE ); +} + +void __init time_init (void ) +{ +struct device_node *cpu; +u32 prop; +
arch/riscv/kernel/time.c line 78
Quoted 10 lines
arch/riscv/kernel/time.c new file +10
-0+ cpu =of_find_node_by_path ("/cpus" ); +if (!cpu ||of_property_read_u32 (cpu,"timebase-frequency" , &prop)) +panic (KERN_WARNING "RISC-V system with no 'timebase-frequency' in DTS\n" ); + riscv_timebase = prop; + + lpj_fine = riscv_timebase /HZ ; + +clocksource_riscv_init (&rdtime); +init_clockevent (); +}
All this code must go in the timer side and use the TIMER_OF_DECLARE macro with the proper wrappers.
Where is the request_per_cpu_interrupt()?
What is this riscv_timer_interrupt() signature?
Where is get_cycles64() ?
The timer driver should be self-contained and not spread across different places, it is very difficult to review it.
[ ... ]
Signature · 5 lines
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog
Re: [PATCH v8 10/18] RISC-V: Init and Halt Code
Quoted 3 lines · Daniel Lezcano
All this code must go in the timer side and use the
TIMER_OF_DECLAREmacro with the proper wrappers.
Hi, thanks for the feedback.
Agreed. I'll clean this up.
Quoted 4 lines
Where is the
request_per_cpu_interrupt()?What is this
riscv_timer_interrupt()signature?
This arch defines a separate exception type for local timer interrupts. Currently the interrupt controller driver checks the trap cause register, determines that it's a timer, and calls the handler directly. To make this go through the interrupt subsystem, this driver would need to be reworked.
Quoted 2 lines
Where is
get_cycles64()?
This is in asm/timex.h. Should this be split into a separate asm header ala arm64?
Quoted 6 lines
The timer driver should be self-contained and not spread across different places, it is very difficult to review it.
[ ... ]
Agreed, thanks again for reviewing it anyway :)
Re: [PATCH v8 10/18] RISC-V: Init and Halt Code
Quoted 21 lines · Dmitriy Cherkasov
Quoted 3 lines · Daniel Lezcano
All this code must go in the timer side and use the
TIMER_OF_DECLAREmacro with the proper wrappers.Hi, thanks for the feedback.
Agreed. I'll clean this up.
Quoted 4 lines
Where is the
request_per_cpu_interrupt()?What is this
riscv_timer_interrupt()signature?This arch defines a separate exception type for local timer interrupts. Currently the interrupt controller driver checks the trap cause register, determines that it's a timer, and calls the handler directly. To make this go through the interrupt subsystem, this driver would need to be reworked.
Quoted 1 line
Quoted 4 lines
Quoted 1 line
Where is
get_cycles64()?This is in
asm/timex.h. Should this be split into a separate asm header ala arm64?
No, it is fine but may be it is get_cycles(), no get_cycles64(), right?
Quoted 7 lines
Quoted 5 lines
The timer driver should be self-contained and not spread across different places, it is very difficult to review it.
[ ... ]
Agreed, thanks again for reviewing it anyway :)
Ok, thanks.
-- Daniel
Signature · 5 lines
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog
Re: [PATCH v8 10/18] RISC-V: Init and Halt Code
Quoted 11 lines · Daniel Lezcano
Quoted 7 lines · Dmitriy Cherkasov
Quoted 2 lines · Daniel Lezcano
Where is
get_cycles64()?This is in
asm/timex.h. Should this be split into a separate asm header ala arm64?No, it is fine but may be it is
get_cycles(), noget_cycles64(), right?
get_cycles() returns a 32 or 64-bit value depending on machine register width, using one assembly instruction to retrieve it.
get_cycles64() always returns a 64-bit value at the expense of a few more instructions on 32-bit systems.
Palmer Dabbelt
maintainerPATCH v8 11/18 RISC-V: Atomic and Locking Code
In reply to Palmer DabbeltThis contains all the code that directly interfaces with the RISC-V memory model. While this code corforms to the current RISC-V ISA specifications (user 2.2 and priv 1.10), the memory model is somewhat underspecified in those documents. There is a working group that hopes to produce a formal memory model by the end of the year, but my understanding is that the basic definitions we're relying on here won't change significantly.
Signed-off-by Palmer Dabbelt <[email protected]>
--- arch/riscv/include/asm/atomic.h | 375 ++++++++++++++++++++++++++++++++ arch/riscv/include/asm/barrier.h | 68 ++++++ arch/riscv/include/asm/bitops.h | 218 +++++++++++++++++++ arch/riscv/include/asm/cacheflush.h | 39 ++++ arch/riscv/include/asm/cmpxchg.h | 134 ++++++++++++ arch/riscv/include/asm/io.h | 303 ++++++++++++++++++++++++++ arch/riscv/include/asm/spinlock.h | 165 ++++++++++++++ arch/riscv/include/asm/spinlock_types.h | 33 +++ arch/riscv/include/asm/tlb.h | 24 ++ arch/riscv/include/asm/tlbflush.h | 64 ++++++ 10 files changed, 1423 insertions(+) create mode 100644 arch/riscv/include/asm/atomic.h create mode 100644 arch/riscv/include/asm/barrier.h create mode 100644 arch/riscv/include/asm/bitops.h create mode 100644 arch/riscv/include/asm/cacheflush.h create mode 100644 arch/riscv/include/asm/cmpxchg.h create mode 100644 arch/riscv/include/asm/io.h create mode 100644 arch/riscv/include/asm/spinlock.h create mode 100644 arch/riscv/include/asm/spinlock_types.h create mode 100644 arch/riscv/include/asm/tlb.h create mode 100644 arch/riscv/include/asm/tlbflush.h
arch/riscv/include/asm/atomic.h new file +375 -0
@@ -0,0 +1,375 @@ +/* +* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. +* Copyright (C) 2012 Regents of the University of California +* Copyright (C) 2017 SiFive +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public Licence +* as published by the Free Software Foundation; either version +* 2 of the Licence, or (at your option) any later version. +*/ + +#ifndef _ASM_RISCV_ATOMIC_H +#define _ASM_RISCV_ATOMIC_H + +#ifdef CONFIG_GENERIC_ATOMIC64 +# include <asm-generic/atomic64.h> +#else +# if (__riscv_xlen <64 ) +# error "64-bit atomics require XLEN to be at least 64" +# endif +#endif + +#include <asm/cmpxchg.h> +#include <asm/barrier.h> + +#define ATOMIC_INIT (i) { (i) } +static __always_inline int atomic_read(const atomic_t *v) +{ +return READ_ONCE (v->counter); +} +static __always_inline void atomic_set(atomic_t *v, int i) +{ +WRITE_ONCE (v->counter, i); +} + +#ifndef CONFIG_GENERIC_ATOMIC64 +#define ATOMIC64_INIT (i) { (i) } +static __always_inline long atomic64_read (const atomic64_t *v) +{ +return READ_ONCE (v->counter); +} +static __always_inline void atomic64_set(atomic64_t *v, long i) +{ +WRITE_ONCE (v->counter, i); +} +#endif + +/* +* First, the atomic ops that have no ordering constraints and therefor don't +* have the AQ or RL bits set. These don't return anything, so there's only +* one version to worry about. +*/ +#define ATOMIC_OP (op, asm_op, c_op,I , asm_type, c_type, prefix) \ +static __always_inline void atomic##prefix##_##op(c_type i, atomic##prefix##_t *v) \ +{ \ + __asm__ __volatile__ ( \ + "amo" #asm_op "." #asm_type " zero, %1, %0" \ + : "+A" (v->counter) \ + : "r" (I) \ + : "memory"); \ +} + +#ifdef CONFIG_GENERIC_ATOMIC64 +#define ATOMIC_OPS (op, asm_op, c_op,I ) \ + ATOMIC_OP (op, asm_op, c_op, I, w, int, ) +#else +#define ATOMIC_OPS (op, asm_op, c_op,I ) \ + ATOMIC_OP (op, asm_op, c_op, I, w, int, ) \ + ATOMIC_OP (op, asm_op, c_op, I, d, long, 64) +#endif + +ATOMIC_OPS(add, add, +, i) +ATOMIC_OPS(sub, add, +, -i) +ATOMIC_OPS(and, and, &, i) +ATOMIC_OPS( or, or, |, i) +ATOMIC_OPS(xor, xor, ^, i) + +#undef ATOMIC_OP +#undef ATOMIC_OPS + +/* +* Atomic ops that have ordered, relaxed, acquire, and relese variants. +* There's two flavors of these: the arithmatic ops have both fetch and return +* versions, while the logical ops only have fetch versions. +*/ +#define ATOMIC_FETCH_OP (op, asm_op, c_op,I , asm_or, c_or, asm_type, c_type, prefix) \ +static __always_inline c_type atomic##prefix##_fetch_##op##c_or(c_type i, atomic##prefix##_t *v) \ +{ \ + register c_type ret; \ + __asm__ __volatile__ ( \ + "amo" #asm_op "." #asm_type #asm_or " %1, %2, %0" \ + : "+A" (v->counter), "=r" (ret) \ + : "r" (I) \ + : "memory"); \ + return ret; \ +} + +#define ATOMIC_OP_RETURN (op, asm_op, c_op,I , asm_or, c_or, asm_type, c_type, prefix) \ +static __always_inline c_type atomic##prefix##_##op##_return##c_or(c_type i, atomic##prefix##_t *v) \ +{ \ + return atomic##prefix##_fetch_##op##c_or(i, v) c_op I; \ +} + +#ifdef CONFIG_GENERIC_ATOMIC64 +#define ATOMIC_OPS (op, asm_op, c_op,I , asm_or, c_or) \ + ATOMIC_FETCH_OP (op, asm_op, c_op, I, asm_or, c_or, w, int, ) \ + ATOMIC_OP_RETURN(op, asm_op, c_op, I, asm_or, c_or, w, int, ) +#else +#define ATOMIC_OPS (op, asm_op, c_op,I , asm_or, c_or) \ + ATOMIC_FETCH_OP (op, asm_op, c_op, I, asm_or, c_or, w, int, ) \ + ATOMIC_OP_RETURN(op, asm_op, c_op, I, asm_or, c_or, w, int, ) \ + ATOMIC_FETCH_OP (op, asm_op, c_op, I, asm_or, c_or, d, long, 64) \ + ATOMIC_OP_RETURN(op, asm_op, c_op, I, asm_or, c_or, d, long, 64) +#endif + +ATOMIC_OPS(add, add, +, i, , _relaxed) +ATOMIC_OPS(add, add, +, i, .aq , _acquire) +ATOMIC_OPS(add, add, +, i, .rl , _release) +ATOMIC_OPS(add, add, +, i, .aqrl, ) + +ATOMIC_OPS(sub, add, +, -i, , _relaxed) +ATOMIC_OPS(sub, add, +, -i, .aq , _acquire) +ATOMIC_OPS(sub, add, +, -i, .rl , _release) +ATOMIC_OPS(sub, add, +, -i, .aqrl, ) + +#undef ATOMIC_OPS + +#ifdef CONFIG_GENERIC_ATOMIC64 +#define ATOMIC_OPS(op, asm_op, c_op, I, asm_or, c_or) \ + ATOMIC_FETCH_OP(op, asm_op, c_op, I, asm_or, c_or, w, int, ) +#else +#define ATOMIC_OPS(op, asm_op, c_op, I, asm_or, c_or) \ + ATOMIC_FETCH_OP(op, asm_op, c_op, I, asm_or, c_or, w, int, ) \ + ATOMIC_FETCH_OP(op, asm_op, c_op, I, asm_or, c_or, d, long, 64) +#endif + +ATOMIC_OPS(and, and, &, i, , _relaxed) +ATOMIC_OPS(and, and, &, i, .aq , _acquire) +ATOMIC_OPS(and, and, &, i, .rl , _release) +ATOMIC_OPS(and, and, &, i, .aqrl, ) + +ATOMIC_OPS( or, or, |, i, , _relaxed) +ATOMIC_OPS( or, or, |, i, .aq , _acquire) +ATOMIC_OPS( or, or, |, i, .rl , _release) +ATOMIC_OPS( or, or, |, i, .aqrl, ) + +ATOMIC_OPS(xor, xor, ^, i, , _relaxed) +ATOMIC_OPS(xor, xor, ^, i, .aq , _acquire) +ATOMIC_OPS(xor, xor, ^, i, .rl , _release) +ATOMIC_OPS(xor, xor, ^, i, .aqrl, ) + +#undef ATOMIC_OPS + +#undef ATOMIC_FETCH_OP +#undef ATOMIC_OP_RETURN + +/* + * The extra atomic operations that are constructed from one of the core + * AMO-based operations above (aside from sub, which is easier to fit above). + * These are required to perform a barrier, but they're OK this way because + * atomic_*_return is also required to perform a barrier. + */ +#define ATOMIC_OP(op, func_op, comp_op, I, c_type, prefix) \ +static __always_inline bool atomic##prefix##_##op(c_type i, atomic##prefix##_t *v) \ +{ \ + return atomic##prefix##_##func_op##_return(i, v) comp_op I; \ +} + +#ifdef CONFIG_GENERIC_ATOMIC64 +#define ATOMIC_OPS(op, func_op, comp_op, I) \ + ATOMIC_OP (op, func_op, comp_op, I, int, ) +#else +#define ATOMIC_OPS(op, func_op, comp_op, I) \ + ATOMIC_OP (op, func_op, comp_op, I, int, ) \ + ATOMIC_OP (op, func_op, comp_op, I, long, 64) +#endif + +ATOMIC_OPS(add_and_test, add, ==, 0) +ATOMIC_OPS(sub_and_test, sub, ==, 0) +ATOMIC_OPS(add_negative, add, <, 0) + +#undef ATOMIC_OP +#undef ATOMIC_OPS + +#define ATOMIC_OP(op, func_op, c_op, I, c_type, prefix) \ +static __always_inline void atomic##prefix##_##op(atomic##prefix##_t *v) \ +{ \ + atomic##prefix##_##func_op(I, v); \ +} + +#define ATOMIC_FETCH_OP(op, func_op, c_op, I, c_type, prefix) \ +static __always_inline c_type atomic##prefix##_fetch_##op(atomic##prefix##_t *v) \ +{ \ + return atomic##prefix##_fetch_##func_op(I, v); \ +} + +#define ATOMIC_OP_RETURN (op, asm_op, c_op,I , c_type, prefix) \ +static __always_inline c_type atomic##prefix##_##op##_return(atomic##prefix##_t *v) \ +{ \ + return atomic##prefix##_fetch_##op(v) c_op I; \ +} + +#ifdef CONFIG_GENERIC_ATOMIC64 +#define ATOMIC_OPS (op, asm_op, c_op,I ) \ + ATOMIC_OP (op, asm_op, c_op, I, int, ) \ + ATOMIC_FETCH_OP (op, asm_op, c_op, I, int, ) \ + ATOMIC_OP_RETURN(op, asm_op, c_op, I, int, ) +#else +#define ATOMIC_OPS (op, asm_op, c_op,I ) \ + ATOMIC_OP (op, asm_op, c_op, I, int, ) \ + ATOMIC_FETCH_OP (op, asm_op, c_op, I, int, ) \ + ATOMIC_OP_RETURN(op, asm_op, c_op, I, int, ) \ + ATOMIC_OP (op, asm_op, c_op, I, long, 64) \ + ATOMIC_FETCH_OP (op, asm_op, c_op, I, long, 64) \ + ATOMIC_OP_RETURN(op, asm_op, c_op, I, long, 64) +#endif + +ATOMIC_OPS(inc, add, +, 1) +ATOMIC_OPS(dec, add, +, -1) + +#undef ATOMIC_OPS +#undef ATOMIC_OP +#undef ATOMIC_FETCH_OP +#undef ATOMIC_OP_RETURN + +#define ATOMIC_OP (op, func_op, comp_op,I , prefix) \ +static __always_inline bool atomic##prefix##_##op(atomic##prefix##_t *v) \ +{ \ + return atomic##prefix##_##func_op##_return(v) comp_op I; \ +} + +ATOMIC_OP(inc_and_test, inc, ==, 0, ) +ATOMIC_OP(dec_and_test, dec, ==, 0, ) +#ifndef CONFIG_GENERIC_ATOMIC64 +ATOMIC_OP(inc_and_test, inc, ==, 0, 64) +ATOMIC_OP(dec_and_test, dec, ==, 0, 64) +#endif + +#undef ATOMIC_OP + +/* This is required to provide a barrier on success. */ +static __always_inline int __atomic_add_unless(atomic_t *v, int a, int u) +{ +int prev, rc; + + __asm__ __volatile__ ( +"0:\n\t" +"lr.w.aqrl %[p], %[c]\n\t" +"beq %[p], %[u], 1f\n\t" +"add %[rc], %[p], %[a]\n\t" +"sc.w.aqrl %[rc], %[rc], %[c]\n\t" +"bnez %[rc], 0b\n\t" +"1:" + : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) + : [a]"r" (a), [u]"r" (u) + :"memory" ); +return prev; +} + +#ifndef CONFIG_GENERIC_ATOMIC64 +static __always_inline long __atomic64_add_unless(atomic64_t *v, long a, long u) +{ + long prev, rc; + + __asm__ __volatile__ ( +"0:\n\t" +"lr.d.aqrl %[p], %[c]\n\t" +"beq %[p], %[u], 1f\n\t" +"add %[rc], %[p], %[a]\n\t" +"sc.d.aqrl %[rc], %[rc], %[c]\n\t" +"bnez %[rc], 0b\n\t" +"1:" + : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) + : [a]"r" (a), [u]"r" (u) + :"memory" ); +return prev; +} + +static __always_inline int atomic64_add_unless(atomic64_t *v, long a, long u) +{ +return __atomic64_add_unless (v, a, u) != u; +} +#endif + +/* +* The extra atomic operations that are constructed from one of the core +* LR/SC-based operations above. +*/ +static __always_inline int atomic_inc_not_zero(atomic_t *v) +{ +return __atomic_add_unless (v,1 ,0 ); +} + +#ifndef CONFIG_GENERIC_ATOMIC64 +static __always_inline long atomic64_inc_not_zero (atomic64_t *v) +{ +return atomic64_add_unless (v,1 ,0 ); +} +#endif + +/* +* atomic_{cmp,}xchg is required to have exactly the same ordering semantics as +* {cmp,}xchg and the operations that return, so they need a barrier. We just +* use the other implementations directly. +*/ +#define ATOMIC_OP (c_t, prefix, c_or, size, asm_or) \ +static __always_inline c_t atomic##prefix##_cmpxchg##c_or(atomic##prefix##_t *v, c_t o, c_t n) \ +{ \ + return __cmpxchg(&(v->counter), o, n, size, asm_or, asm_or); \ +} \ +static __always_inline c_t atomic##prefix##_xchg##c_or(atomic##prefix##_t *v, c_t n) \ +{ \ + return __xchg(n, &(v->counter), size, asm_or); \ +} + +#ifdef CONFIG_GENERIC_ATOMIC64 +#define ATOMIC_OPS (c_or, asm_or) \ + ATOMIC_OP( int, , c_or, 4, asm_or) +#else +#define ATOMIC_OPS (c_or, asm_or) \ + ATOMIC_OP( int, , c_or, 4, asm_or) \ + ATOMIC_OP(long, 64, c_or, 8, asm_or) +#endif + +ATOMIC_OPS( , .aqrl) +ATOMIC_OPS(_acquire, .aq) +ATOMIC_OPS(_release, .rl) +ATOMIC_OPS(_relaxed, ) + +#undef ATOMIC_OPS +#undef ATOMIC_OP + +static __always_inline int atomic_sub_if_positive(atomic_t *v, int offset) +{ + int prev, rc; + + __asm__ __volatile__ ( + "0:\n\t" + "lr.w.aqrl %[p], %[c]\n\t" + "sub %[rc], %[p], %[o]\n\t" + "bltz %[rc], 1f\n\t" + "sc.w.aqrl %[rc], %[rc], %[c]\n\t" + "bnez %[rc], 0b\n\t" + "1:" + : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) + : [o]"r" (offset) + : "memory"); +return prev - offset; +} + +#define atomic_dec_if_positive (v) atomic_sub_if_positive(v, 1) + +#ifndef CONFIG_GENERIC_ATOMIC64 +static __always_inline long atomic64_sub_if_positive (atomic64_t *v,int offset) +{ +long prev, rc; + + __asm__ __volatile__ ( +"0:\n\t" +"lr.d.aqrl %[p], %[c]\n\t" +"sub %[rc], %[p], %[o]\n\t" +"bltz %[rc], 1f\n\t" +"sc.d.aqrl %[rc], %[rc], %[c]\n\t" +"bnez %[rc], 0b\n\t" +"1:" + : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) + : [o]"r" (offset) + :"memory" ); +return prev - offset; +} + +#define atomic64_dec_if_positive (v) atomic64_sub_if_positive(v, 1) +#endif + +#endif /* _ASM_RISCV_ATOMIC_H */
arch/riscv/include/asm/barrier.h new file +68 -0
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arch/riscv/include/asm/bitops.h new file +218 -0
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arch/riscv/include/asm/cacheflush.h new file +39 -0
@@ -0,0 +1,39 @@ +/* +* Copyright (C) 2015 Regents of the University of California +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef _ASM_RISCV_CACHEFLUSH_H +#define _ASM_RISCV_CACHEFLUSH_H + +#include <asm-generic/cacheflush.h> + +#undef flush_icache_range +#undef flush_icache_user_range + +static inline void local_flush_icache_all (void ) +{ + asmvolatile ("fence.i" :::"memory" ); +} + +#ifndef CONFIG_SMP + +#define flush_icache_range (start, end) local_flush_icache_all() +#define flush_icache_user_range (vma, pg, addr, len) local_flush_icache_all() + +#else /* CONFIG_SMP */ + +#define flush_icache_range (start, end) sbi_remote_fence_i(0) +#define flush_icache_user_range (vma, pg, addr, len) sbi_remote_fence_i(0) + +#endif /* CONFIG_SMP */ + +#endif /* _ASM_RISCV_CACHEFLUSH_H */
arch/riscv/include/asm/cmpxchg.h new file +134 -0
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arch/riscv/include/asm/io.h new file +303 -0
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arch/riscv/include/asm/spinlock.h new file +165 -0
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arch/riscv/include/asm/spinlock_types.h new file +33 -0
@@ -0,0 +1,33 @@ +/* +* Copyright (C) 2015 Regents of the University of California +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef _ASM_RISCV_SPINLOCK_TYPES_H +#define _ASM_RISCV_SPINLOCK_TYPES_H + +#ifndef __LINUX_SPINLOCK_TYPES_H +# error "please don't include this file directly" +#endif + +typedef struct { +volatile unsigned int lock; +}arch_spinlock_t ; + +#define __ARCH_SPIN_LOCK_UNLOCKED { 0 } + +typedef struct { +volatile unsigned int lock; +}arch_rwlock_t ; + +#define __ARCH_RW_LOCK_UNLOCKED { 0 } + +#endif
arch/riscv/include/asm/tlb.h new file +24 -0
@@ -0,0 +1,24 @@ +/* +* Copyright (C) 2012 Regents of the University of California +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef _ASM_RISCV_TLB_H +#define _ASM_RISCV_TLB_H + +#include <asm-generic/tlb.h> + +static inline void tlb_flush (struct mmu_gather *tlb) +{ +flush_tlb_mm (tlb->mm); +} + +#endif /* _ASM_RISCV_TLB_H */
arch/riscv/include/asm/tlbflush.h new file +64 -0
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Signature · 1 line
2.13.5
Palmer Dabbelt
maintainerPATCH v8 12/18 RISC-V: Generic library routines and assembly
In reply to Palmer DabbeltThis patch contains code that is more specific to the RISC-V ISA than it is to Linux. It contains string and math operations, C wrappers for various assembly instructions, stack walking code, and uaccess.
Signed-off-by Palmer Dabbelt <[email protected]>
--- arch/riscv/include/asm/asm.h | 76 +++++ arch/riscv/include/asm/csr.h | 132 ++++++++ arch/riscv/include/asm/linkage.h | 20 ++ arch/riscv/include/asm/string.h | 26 ++ arch/riscv/include/asm/uaccess.h | 513 ++++++++++++++++++++++++++++++++ arch/riscv/include/asm/word-at-a-time.h | 55 ++++ arch/riscv/kernel/stacktrace.c | 177 +++++++++++ arch/riscv/lib/memcpy.S | 115 +++++++ arch/riscv/lib/memset.S | 120 ++++++++ arch/riscv/lib/uaccess.S | 117 ++++++++ arch/riscv/lib/udivdi3.S | 38 +++ 11 files changed, 1389 insertions(+) create mode 100644 arch/riscv/include/asm/asm.h create mode 100644 arch/riscv/include/asm/csr.h create mode 100644 arch/riscv/include/asm/linkage.h create mode 100644 arch/riscv/include/asm/string.h create mode 100644 arch/riscv/include/asm/uaccess.h create mode 100644 arch/riscv/include/asm/word-at-a-time.h create mode 100644 arch/riscv/kernel/stacktrace.c create mode 100644 arch/riscv/lib/memcpy.S create mode 100644 arch/riscv/lib/memset.S create mode 100644 arch/riscv/lib/uaccess.S create mode 100644 arch/riscv/lib/udivdi3.S
arch/riscv/include/asm/asm.h new file +76 -0
@@ -0,0 +1,76 @@ +/* +* Copyright (C) 2015 Regents of the University of California +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef _ASM_RISCV_ASM_H +#define _ASM_RISCV_ASM_H + +#ifdef __ASSEMBLY__ +#define __ASM_STR (x) x +#else +#define __ASM_STR (x) #x +#endif + +#if __riscv_xlen ==64 +#define __REG_SEL (a, b) __ASM_STR(a) +#elif __riscv_xlen ==32 +#define __REG_SEL (a, b) __ASM_STR(b) +#else +#error "Unexpected __riscv_xlen" +#endif + +#define REG_L __REG_SEL(ld, lw) +#define REG_S __REG_SEL(sd, sw) +#define SZREG __REG_SEL(8, 4) +#define LGREG __REG_SEL(3, 2) + +#if __SIZEOF_POINTER__ ==8 +#ifdef __ASSEMBLY__ +#define RISCV_PTR .dword +#define RISCV_SZPTR 8 +#define RISCV_LGPTR 3 +#else +#define RISCV_PTR ".dword" +#define RISCV_SZPTR "8" +#define RISCV_LGPTR "3" +#endif +#elif __SIZEOF_POINTER__ ==4 +#ifdef __ASSEMBLY__ +#define RISCV_PTR .word +#define RISCV_SZPTR 4 +#define RISCV_LGPTR 2 +#else +#define RISCV_PTR ".word" +#define RISCV_SZPTR "4" +#define RISCV_LGPTR "2" +#endif +#else +#error "Unexpected __SIZEOF_POINTER__" +#endif + +#if (__SIZEOF_INT__ ==4 ) +#define INT __ASM_STR(.word) +#define SZINT __ASM_STR(4) +#define LGINT __ASM_STR(2) +#else +#error "Unexpected __SIZEOF_INT__" +#endif + +#if (__SIZEOF_SHORT__ ==2 ) +#define SHORT __ASM_STR(.half) +#define SZSHORT __ASM_STR(2) +#define LGSHORT __ASM_STR(1) +#else +#error "Unexpected __SIZEOF_SHORT__" +#endif + +#endif /* _ASM_RISCV_ASM_H */
arch/riscv/include/asm/csr.h new file +132 -0
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arch/riscv/include/asm/linkage.h new file +20 -0
@@ -0,0 +1,20 @@ +/* +* Copyright (C) 2015 Regents of the University of California +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef _ASM_RISCV_LINKAGE_H +#define _ASM_RISCV_LINKAGE_H + +#define __ALIGN .balign 4 +#define __ALIGN_STR ".balign 4" + +#endif /* _ASM_RISCV_LINKAGE_H */
arch/riscv/include/asm/string.h new file +26 -0
@@ -0,0 +1,26 @@ +/* +* Copyright (C) 2013 Regents of the University of California +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef _ASM_RISCV_STRING_H +#define _ASM_RISCV_STRING_H + +#include <linux/types.h> +#include <linux/linkage.h> + +#define __HAVE_ARCH_MEMSET +extern asmlinkage void *memset(void *, int, size_t); + +#define __HAVE_ARCH_MEMCPY +extern asmlinkage void *memcpy(void *, const void *, size_t); + +#endif /* _ASM_RISCV_STRING_H */
arch/riscv/include/asm/uaccess.h new file +513 -0
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arch/riscv/include/asm/word-at-a-time.h new file +55 -0
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arch/riscv/kernel/stacktrace.c new file +177 -0
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arch/riscv/lib/memcpy.S new file +115 -0
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arch/riscv/lib/memset.S new file +120 -0
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arch/riscv/lib/uaccess.S new file +117 -0
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arch/riscv/lib/udivdi3.S new file +38 -0
@@ -0,0 +1,38 @@ +/* + * Copyright (C) 2016-2017 Free Software Foundation, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + .globl __udivdi3 +__udivdi3: + mv a2, a1 + mv a1, a0 + li a0, -1 + beqz a2, .L5 + li a3, 1 + bgeu a2, a1, .L2 +.L1: + blez a2, .L2 + slli a2, a2, 1 + slli a3, a3, 1 + bgtu a1, a2, .L1 +.L2: + li a0, 0 +.L3: + bltu a1, a2, .L4 + sub a1, a1, a2 + or a0, a0, a3 +.L4: + srli a3, a3, 1 + srli a2, a2, 1 + bnez a3, .L3 +.L5: + ret
Signature · 1 line
2.13.5
Palmer Dabbelt
maintainerPATCH v8 13/18 RISC-V: ELF and module implementation
In reply to Palmer DabbeltThis patch contains the code that interfaces with ELF objects on RISC-V systems, the vast majority of which is present to load kernel modules.
Signed-off-by Palmer Dabbelt <[email protected]>
--- arch/riscv/include/asm/compat.h | 29 ++++++++++++++ arch/riscv/include/asm/elf.h | 84 +++++++++++++++++++++++++++++++++++++++++ arch/riscv/include/asm/hwcap.h | 37 ++++++++++++++++++ arch/riscv/mm/extable.c | 37 ++++++++++++++++++ 4 files changed, 187 insertions(+) create mode 100644 arch/riscv/include/asm/compat.h create mode 100644 arch/riscv/include/asm/elf.h create mode 100644 arch/riscv/include/asm/hwcap.h create mode 100644 arch/riscv/mm/extable.c
arch/riscv/include/asm/compat.h new file +29 -0
@@ -0,0 +1,29 @@ +/* +* Copyright (C) 2012 ARM Ltd. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ +#ifndef __ASM_COMPAT_H +#define __ASM_COMPAT_H +#ifdef CONFIG_COMPAT + +#if defined(CONFIG_64BIT ) +#define COMPAT_UTS_MACHINE "riscv64\0\0" +#elif defined(CONFIG_32BIT ) +#define COMPAT_UTS_MACHINE "riscv32\0\0" +#else +#error "Unknown RISC-V base ISA" +#endif + +#endif /*CONFIG_COMPAT*/ +#endif /*__ASM_COMPAT_H*/
arch/riscv/include/asm/elf.h new file +84 -0
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arch/riscv/include/asm/hwcap.h new file +37 -0
@@ -0,0 +1,37 @@ +/* +* Copied from arch/arm64/include/asm/hwcap.h +* +* Copyright (C) 2012 ARM Ltd. +* Copyright (C) 2017 SiFive +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ +#ifndef __ASM_HWCAP_H +#define __ASM_HWCAP_H + +#include <uapi/asm/hwcap.h> + +#ifndef __ASSEMBLY__ +/* +* This yields a mask that user programs can use to figure out what +* instruction set this cpu supports. +*/ +#define ELF_HWCAP (elf_hwcap) + +enum { +CAP_HWCAP =1 , +}; + +extern unsigned long elf_hwcap; +#endif +#endif
arch/riscv/mm/extable.c new file +37 -0
@@ -0,0 +1,37 @@ +/* +* Copyright (C) 2009 Sunplus Core Technology Co., Ltd. +* Lennox Wu <[email protected]> +* Chen Liqin <[email protected]> +* Copyright (C) 2013 Regents of the University of California +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, see the file COPYING, or write +* to the Free Software Foundation, Inc., +*/ + + +#include <linux/extable.h> +#include <linux/module.h> +#include <linux/uaccess.h> + +int fixup_exception (struct pt_regs *regs) +{ +const struct exception_table_entry *fixup; + + fixup =search_exception_tables (regs->sepc); +if (fixup) { + regs->sepc = fixup->fixup; +return 1 ; + } +return 0 ; +}
Signature · 1 line
2.13.5
Palmer Dabbelt
maintainerPATCH v8 14/18 RISC-V: Task implementation
In reply to Palmer DabbeltThis patch contains the implementation of tasks on RISC-V, most of which is involved in task switching.
Signed-off-by Palmer Dabbelt <[email protected]>
--- arch/riscv/include/asm/asm-offsets.h | 1 + arch/riscv/include/asm/current.h | 45 ++++ arch/riscv/include/asm/kprobes.h | 22 ++ arch/riscv/include/asm/processor.h | 97 ++++++++ arch/riscv/include/asm/switch_to.h | 69 ++++++ arch/riscv/include/asm/thread_info.h | 94 +++++++ arch/riscv/kernel/asm-offsets.c | 322 ++++++++++++++++++++++++ arch/riscv/kernel/entry.S | 464 +++++++++++++++++++++++++++++++++++ arch/riscv/kernel/process.c | 129 ++++++++++ 9 files changed, 1243 insertions(+) create mode 100644 arch/riscv/include/asm/asm-offsets.h create mode 100644 arch/riscv/include/asm/current.h create mode 100644 arch/riscv/include/asm/kprobes.h create mode 100644 arch/riscv/include/asm/processor.h create mode 100644 arch/riscv/include/asm/switch_to.h create mode 100644 arch/riscv/include/asm/thread_info.h create mode 100644 arch/riscv/kernel/asm-offsets.c create mode 100644 arch/riscv/kernel/entry.S create mode 100644 arch/riscv/kernel/process.c
arch/riscv/include/asm/asm-offsets.h new file +1 -0
@@ -0,0 +1 @@ +#include <generated/asm-offsets.h>
arch/riscv/include/asm/current.h new file +45 -0
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arch/riscv/include/asm/kprobes.h new file +22 -0
@@ -0,0 +1,22 @@ +/* +* Copied from arch/arm64/include/asm/kprobes.h +* +* Copyright (C) 2013 Linaro Limited +* Copyright (C) 2017 SiFive +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* General Public License for more details. +*/ + +#ifndef _RISCV_KPROBES_H +#define _RISCV_KPROBES_H + +#include <asm-generic/kprobes.h> + +#endif /* _RISCV_KPROBES_H */
arch/riscv/include/asm/processor.h new file +97 -0
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arch/riscv/include/asm/switch_to.h new file +69 -0
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arch/riscv/include/asm/thread_info.h new file +94 -0
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arch/riscv/kernel/asm-offsets.c new file +322 -0
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arch/riscv/kernel/entry.S new file +464 -0
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arch/riscv/kernel/process.c new file +129 -0
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Signature · 1 line
2.13.5
Palmer Dabbelt
maintainerPATCH v8 15/18 RISC-V: Device, timer, IRQs, and the SBI
In reply to Palmer DabbeltThis patch contains code that interfaces with devices that are mandated by the RISC-V supervisor specification and that don't have explicit drivers anywhere else in the tree. This includes the staticly defined interrupts, the CSR-mapped timer, and virtualized SBI devices.
Signed-off-by Palmer Dabbelt <[email protected]>
--- arch/riscv/include/asm/delay.h | 28 +++++++++ arch/riscv/include/asm/dma-mapping.h | 38 ++++++++++++ arch/riscv/include/asm/irq.h | 28 +++++++++ arch/riscv/include/asm/irqflags.h | 63 ++++++++++++++++++++ arch/riscv/include/asm/pci.h | 48 +++++++++++++++ arch/riscv/include/asm/sbi.h | 100 +++++++++++++++++++++++++++++++ arch/riscv/include/asm/timex.h | 59 +++++++++++++++++++ arch/riscv/lib/delay.c | 110 +++++++++++++++++++++++++++++++++++ arch/riscv/mm/ioremap.c | 92 +++++++++++++++++++++++++++++ 9 files changed, 566 insertions(+) create mode 100644 arch/riscv/include/asm/delay.h create mode 100644 arch/riscv/include/asm/dma-mapping.h create mode 100644 arch/riscv/include/asm/irq.h create mode 100644 arch/riscv/include/asm/irqflags.h create mode 100644 arch/riscv/include/asm/pci.h create mode 100644 arch/riscv/include/asm/sbi.h create mode 100644 arch/riscv/include/asm/timex.h create mode 100644 arch/riscv/lib/delay.c create mode 100644 arch/riscv/mm/ioremap.c
arch/riscv/include/asm/delay.h new file +28 -0
@@ -0,0 +1,28 @@ +/* +* Copyright (C) 2009 Chen Liqin <[email protected]> +* Copyright (C) 2016 Regents of the University of California +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef _ASM_RISCV_DELAY_H +#define _ASM_RISCV_DELAY_H + +extern unsigned long riscv_timebase; + +#define udelay udelay +extern void udelay (unsigned long usecs); + +#define ndelay ndelay +extern void ndelay (unsigned long nsecs); + +extern void __delay (unsigned long cycles); + +#endif /* _ASM_RISCV_DELAY_H */
arch/riscv/include/asm/dma-mapping.h new file +38 -0
@@ -0,0 +1,38 @@ +/* +* Copyright (C) 2003-2004 Hewlett-Packard Co +* David Mosberger-Tang <[email protected]> +* Copyright (C) 2012 ARM Ltd. +* Copyright (C) 2016 SiFive, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ +#ifndef __ASM_RISCV_DMA_MAPPING_H +#define __ASM_RISCV_DMA_MAPPING_H + +/* Use ops->dma_mapping_error (if it exists) or assume success */ +// #undef DMA_ERROR_CODE + +static inline const struct dma_map_ops *get_arch_dma_ops (struct bus_type *bus) +{ +return &dma_noop_ops; +} + +static inline bool dma_capable (struct device *dev,dma_addr_t addr,size_t size) +{ +if (!dev->dma_mask) +return false; + +return addr + size -1 <= *dev->dma_mask; +} + +#endif /* __ASM_RISCV_DMA_MAPPING_H */
arch/riscv/include/asm/irq.h new file +28 -0
@@ -0,0 +1,28 @@ +/* +* Copyright (C) 2012 Regents of the University of California +* Copyright (C) 2017 SiFive +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef _ASM_RISCV_IRQ_H +#define _ASM_RISCV_IRQ_H + +#define NR_IRQS 0 + +#define INTERRUPT_CAUSE_SOFTWARE 1 +#define INTERRUPT_CAUSE_TIMER 5 +#define INTERRUPT_CAUSE_EXTERNAL 9 + +void riscv_timer_interrupt (void ); + +#include <asm-generic/irq.h> + +#endif /* _ASM_RISCV_IRQ_H */
arch/riscv/include/asm/irqflags.h new file +63 -0
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arch/riscv/include/asm/pci.h new file +48 -0
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arch/riscv/include/asm/sbi.h new file +100 -0
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arch/riscv/include/asm/timex.h new file +59 -0
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arch/riscv/lib/delay.c new file +110 -0
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arch/riscv/mm/ioremap.c new file +92 -0
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Signature · 1 line
2.13.5
Palmer Dabbelt
maintainerPATCH v8 16/18 RISC-V: Paging and MMU
In reply to Palmer DabbeltThis patch contains code to manage the RISC-V MMU, including definitions of the page tables and the page walking code.
Signed-off-by Palmer Dabbelt <[email protected]>
--- arch/riscv/include/asm/mmu_context.h | 69 ++++++ arch/riscv/include/asm/page.h | 130 ++++++++++ arch/riscv/include/asm/pgalloc.h | 124 ++++++++++ arch/riscv/include/asm/pgtable-32.h | 25 ++ arch/riscv/include/asm/pgtable-64.h | 84 +++++++ arch/riscv/include/asm/pgtable-bits.h | 48 ++++ arch/riscv/include/asm/pgtable.h | 430 ++++++++++++++++++++++++++++++++++ arch/riscv/mm/fault.c | 282 ++++++++++++++++++++++ 8 files changed, 1192 insertions(+) create mode 100644 arch/riscv/include/asm/mmu_context.h create mode 100644 arch/riscv/include/asm/page.h create mode 100644 arch/riscv/include/asm/pgalloc.h create mode 100644 arch/riscv/include/asm/pgtable-32.h create mode 100644 arch/riscv/include/asm/pgtable-64.h create mode 100644 arch/riscv/include/asm/pgtable-bits.h create mode 100644 arch/riscv/include/asm/pgtable.h create mode 100644 arch/riscv/mm/fault.c
arch/riscv/include/asm/mmu_context.h new file +69 -0
@@ -0,0 +1,69 @@ +/* +* Copyright (C) 2012 Regents of the University of California +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef _ASM_RISCV_MMU_CONTEXT_H +#define _ASM_RISCV_MMU_CONTEXT_H + +#include <asm-generic/mm_hooks.h> + +#include <linux/mm.h> +#include <linux/sched.h> +#include <asm/tlbflush.h> + +static inline void enter_lazy_tlb (struct mm_struct *mm, +struct task_struct *task) +{ +} + +/* Initialize context-related info for a new mm_struct */ +static inline int init_new_context (struct task_struct *task, +struct mm_struct *mm) +{ +return 0 ; +} + +static inline void destroy_context (struct mm_struct *mm) +{ +} + +static inline pgd_t *current_pgdir (void ) +{ +return pfn_to_virt (csr_read (sptbr) &SPTBR_PPN ); +} + +static inline void set_pgdir (pgd_t *pgd) +{ +csr_write (sptbr,virt_to_pfn (pgd) |SPTBR_MODE ); +} + +static inline void switch_mm (struct mm_struct *prev, +struct mm_struct *next,struct task_struct *task) +{ +if (likely (prev != next)) { +set_pgdir (next->pgd); +local_flush_tlb_all (); + } +} + +static inline void activate_mm (struct mm_struct *prev, +struct mm_struct *next) +{ +switch_mm (prev, next,NULL ); +} + +static inline void deactivate_mm (struct task_struct *task, +struct mm_struct *mm) +{ +} + +#endif /* _ASM_RISCV_MMU_CONTEXT_H */
arch/riscv/include/asm/page.h new file +130 -0
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arch/riscv/include/asm/pgalloc.h new file +124 -0
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arch/riscv/include/asm/pgtable-32.h new file +25 -0
@@ -0,0 +1,25 @@ +/* +* Copyright (C) 2012 Regents of the University of California +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef _ASM_RISCV_PGTABLE_32_H +#define _ASM_RISCV_PGTABLE_32_H + +#include <asm-generic/pgtable-nopmd.h> +#include <linux/const.h> + +/* Size of region mapped by a page global directory */ +#define PGDIR_SHIFT 22 +#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE - 1)) + +#endif /* _ASM_RISCV_PGTABLE_32_H */
arch/riscv/include/asm/pgtable-64.h new file +84 -0
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arch/riscv/include/asm/pgtable-bits.h new file +48 -0
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arch/riscv/include/asm/pgtable.h new file +430 -0
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arch/riscv/mm/fault.c new file +282 -0
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Signature · 1 line
2.13.5
Palmer Dabbelt
maintainerPATCH v8 17/18 RISC-V: User-facing API
In reply to Palmer DabbeltThis patch contains code that is in some way visible to the user:
including via system calls, the VDSO, module loading and signal handling. It also contains some generic code that is ABI visible.
Signed-off-by Palmer Dabbelt <[email protected]>
--- arch/riscv/include/asm/mmu.h | 26 +++ arch/riscv/include/asm/ptrace.h | 118 ++++++++++++ arch/riscv/include/asm/syscall.h | 102 +++++++++++ arch/riscv/include/asm/unistd.h | 16 ++ arch/riscv/include/asm/vdso.h | 41 +++++ arch/riscv/include/uapi/asm/Kbuild | 27 +++ arch/riscv/include/uapi/asm/auxvec.h | 24 +++ arch/riscv/include/uapi/asm/bitsperlong.h | 25 +++ arch/riscv/include/uapi/asm/byteorder.h | 23 +++ arch/riscv/include/uapi/asm/elf.h | 83 +++++++++ arch/riscv/include/uapi/asm/hwcap.h | 36 ++++ arch/riscv/include/uapi/asm/ptrace.h | 90 +++++++++ arch/riscv/include/uapi/asm/sigcontext.h | 30 +++ arch/riscv/include/uapi/asm/siginfo.h | 24 +++ arch/riscv/include/uapi/asm/ucontext.h | 35 ++++ arch/riscv/kernel/cpufeature.c | 61 +++++++ arch/riscv/kernel/module.c | 217 ++++++++++++++++++++++ arch/riscv/kernel/ptrace.c | 125 +++++++++++++ arch/riscv/kernel/riscv_ksyms.c | 15 ++ arch/riscv/kernel/signal.c | 292 ++++++++++++++++++++++++++++++ arch/riscv/kernel/sys_riscv.c | 49 +++++ arch/riscv/kernel/syscall_table.c | 25 +++ arch/riscv/kernel/vdso/.gitignore | 2 + arch/riscv/kernel/vdso/Makefile | 63 +++++++ arch/riscv/kernel/vdso/rt_sigreturn.S | 24 +++ arch/riscv/kernel/vdso/vdso.S | 27 +++ arch/riscv/kernel/vdso/vdso.lds.S | 77 ++++++++ 27 files changed, 1677 insertions(+) create mode 100644 arch/riscv/include/asm/mmu.h create mode 100644 arch/riscv/include/asm/ptrace.h create mode 100644 arch/riscv/include/asm/syscall.h create mode 100644 arch/riscv/include/asm/unistd.h create mode 100644 arch/riscv/include/asm/vdso.h create mode 100644 arch/riscv/include/uapi/asm/Kbuild create mode 100644 arch/riscv/include/uapi/asm/auxvec.h create mode 100644 arch/riscv/include/uapi/asm/bitsperlong.h create mode 100644 arch/riscv/include/uapi/asm/byteorder.h create mode 100644 arch/riscv/include/uapi/asm/elf.h create mode 100644 arch/riscv/include/uapi/asm/hwcap.h create mode 100644 arch/riscv/include/uapi/asm/ptrace.h create mode 100644 arch/riscv/include/uapi/asm/sigcontext.h create mode 100644 arch/riscv/include/uapi/asm/siginfo.h create mode 100644 arch/riscv/include/uapi/asm/ucontext.h create mode 100644 arch/riscv/kernel/cpufeature.c create mode 100644 arch/riscv/kernel/module.c create mode 100644 arch/riscv/kernel/ptrace.c create mode 100644 arch/riscv/kernel/riscv_ksyms.c create mode 100644 arch/riscv/kernel/signal.c create mode 100644 arch/riscv/kernel/sys_riscv.c create mode 100644 arch/riscv/kernel/syscall_table.c create mode 100644 arch/riscv/kernel/vdso/.gitignore create mode 100644 arch/riscv/kernel/vdso/Makefile create mode 100644 arch/riscv/kernel/vdso/rt_sigreturn.S create mode 100644 arch/riscv/kernel/vdso/vdso.S create mode 100644 arch/riscv/kernel/vdso/vdso.lds.S
arch/riscv/include/asm/mmu.h new file +26 -0
@@ -0,0 +1,26 @@ +/* +* Copyright (C) 2012 Regents of the University of California +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + + +#ifndef _ASM_RISCV_MMU_H +#define _ASM_RISCV_MMU_H + +#ifndef __ASSEMBLY__ + +typedef struct { +void *vdso; +}mm_context_t ; + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_RISCV_MMU_H */
arch/riscv/include/asm/ptrace.h new file +118 -0
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arch/riscv/include/asm/syscall.h new file +102 -0
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arch/riscv/include/asm/unistd.h new file +16 -0
@@ -0,0 +1,16 @@ +/* +* Copyright (C) 2012 Regents of the University of California +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#define __ARCH_HAVE_MMU +#define __ARCH_WANT_SYS_CLONE +#include <uapi/asm/unistd.h>
arch/riscv/include/asm/vdso.h new file +41 -0
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arch/riscv/include/uapi/asm/Kbuild new file +27 -0
@@ -0,0 +1,27 @@ +# UAPI Header export list +include include/uapi/asm-generic/Kbuild.asm + +generic-y += setup.h +generic-y += unistd.h +generic-y += errno.h +generic-y += fcntl.h +generic-y += ioctl.h +generic-y += ioctls.h +generic-y += ipcbuf.h +generic-y += mman.h +generic-y += msgbuf.h +generic-y += param.h +generic-y += poll.h +generic-y += posix_types.h +generic-y += resource.h +generic-y += sembuf.h +generic-y += shmbuf.h +generic-y += signal.h +generic-y += socket.h +generic-y += sockios.h +generic-y += stat.h +generic-y += statfs.h +generic-y += swab.h +generic-y += termbits.h +generic-y += termios.h +generic-y += types.h
arch/riscv/include/uapi/asm/auxvec.h new file +24 -0
@@ -0,0 +1,24 @@ +/* +* Copyright (C) 2012 ARM Ltd. +* Copyright (C) 2015 Regents of the University of California +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef _UAPI_ASM_RISCV_AUXVEC_H +#define _UAPI_ASM_RISCV_AUXVEC_H + +/* vDSO location */ +#define AT_SYSINFO_EHDR 33 + +#endif /* _UAPI_ASM_RISCV_AUXVEC_H */
arch/riscv/include/uapi/asm/bitsperlong.h new file +25 -0
@@ -0,0 +1,25 @@ +/* +* Copyright (C) 2012 ARM Ltd. +* Copyright (C) 2015 Regents of the University of California +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef _UAPI_ASM_RISCV_BITSPERLONG_H +#define _UAPI_ASM_RISCV_BITSPERLONG_H + +#define __BITS_PER_LONG (__SIZEOF_POINTER__ * 8) + +#include <asm-generic/bitsperlong.h> + +#endif /* _UAPI_ASM_RISCV_BITSPERLONG_H */
arch/riscv/include/uapi/asm/byteorder.h new file +23 -0
@@ -0,0 +1,23 @@ +/* +* Copyright (C) 2012 ARM Ltd. +* Copyright (C) 2015 Regents of the University of California +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef _UAPI_ASM_RISCV_BYTEORDER_H +#define _UAPI_ASM_RISCV_BYTEORDER_H + +#include <linux/byteorder/little_endian.h> + +#endif /* _UAPI_ASM_RISCV_BYTEORDER_H */
arch/riscv/include/uapi/asm/elf.h new file +83 -0
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arch/riscv/include/uapi/asm/hwcap.h new file +36 -0
@@ -0,0 +1,36 @@ +/* +* Copied from arch/arm64/include/asm/hwcap.h +* +* Copyright (C) 2012 ARM Ltd. +* Copyright (C) 2017 SiFive +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ +#ifndef __UAPI_ASM_HWCAP_H +#define __UAPI_ASM_HWCAP_H + +/* +* Linux saves the floating-point registers according to the ISA Linux is +* executing on, as opposed to the ISA the user program is compiled for. This +* is necessary for a handful of esoteric use cases: for example, userpsace +* threading libraries must be able to examine the actual machine state in +* order to fully reconstruct the state of a thread. +*/ +#define COMPAT_HWCAP_ISA_I (1 << ('I' - 'A')) +#define COMPAT_HWCAP_ISA_M (1 << ('M' - 'A')) +#define COMPAT_HWCAP_ISA_A (1 << ('A' - 'A')) +#define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A')) +#define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) +#define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) + +#endif
arch/riscv/include/uapi/asm/ptrace.h new file +90 -0
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arch/riscv/include/uapi/asm/sigcontext.h new file +30 -0
@@ -0,0 +1,30 @@ +/* +* Copyright (C) 2012 Regents of the University of California +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef _UAPI_ASM_RISCV_SIGCONTEXT_H +#define _UAPI_ASM_RISCV_SIGCONTEXT_H + +#include <asm/ptrace.h> + +/* +* Signal context structure +* +* This contains the context saved before a signal handler is invoked; +* it is restored by sys_sigreturn / sys_rt_sigreturn. +*/ +struct sigcontext { +struct user_regs_struct sc_regs; +union __riscv_fp_state sc_fpregs; +}; + +#endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */
arch/riscv/include/uapi/asm/siginfo.h new file +24 -0
@@ -0,0 +1,24 @@ +/* +* Copyright (C) 2012 ARM Ltd. +* Copyright (C) 2016 SiFive, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ +#ifndef __ASM_SIGINFO_H +#define __ASM_SIGINFO_H + +#define __ARCH_SI_PREAMBLE_SIZE (__SIZEOF_POINTER__ == 4 ? 12 : 16) + +#include <asm-generic/siginfo.h> + +#endif
arch/riscv/include/uapi/asm/ucontext.h new file +35 -0
@@ -0,0 +1,35 @@ +/* +* Copyright (C) 2012 ARM Ltd. +* Copyright (C) 2017 SiFive, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +* +* This file was copied from arch/arm64/include/uapi/asm/ucontext.h +*/ +#ifndef _UAPI__ASM_UCONTEXT_H +#define _UAPI__ASM_UCONTEXT_H + +#include <linux/types.h> + +struct ucontext { +unsigned long uc_flags; +struct ucontext *uc_link; +stack_t uc_stack; +sigset_t uc_sigmask; +/* glibc uses a 1024-bit sigset_t */ +__u8 __unused[1024 /8 -sizeof (sigset_t)]; +/* last for future expansion */ +struct sigcontext uc_mcontext; +}; + +#endif /* _UAPI__ASM_UCONTEXT_H */
arch/riscv/kernel/cpufeature.c new file +61 -0
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arch/riscv/kernel/module.c new file +217 -0
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arch/riscv/kernel/ptrace.c new file +125 -0
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arch/riscv/kernel/riscv_ksyms.c new file +15 -0
@@ -0,0 +1,15 @@ +/* +* Copyright (C) 2017 Zihao Yu +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ + +#include <linux/export.h> +#include <linux/uaccess.h> + +/* +* Assembly functions that may be used (directly or indirectly) by modules +*/ +EXPORT_SYMBOL (__copy_user);
arch/riscv/kernel/signal.c new file +292 -0
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arch/riscv/kernel/sys_riscv.c new file +49 -0
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arch/riscv/kernel/syscall_table.c new file +25 -0
@@ -0,0 +1,25 @@ +/* +* Copyright (C) 2009 Arnd Bergmann <[email protected]> +* Copyright (C) 2012 Regents of the University of California +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation, version 2. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <linux/linkage.h> +#include <linux/syscalls.h> +#include <asm-generic/syscalls.h> + +#undef __SYSCALL +#define __SYSCALL (nr, call) [nr] = (call), + +void *sys_call_table[__NR_syscalls] = { + [0 ... __NR_syscalls -1 ] = sys_ni_syscall, +#include <asm/unistd.h> +};
arch/riscv/kernel/vdso/.gitignore new file +2 -0
@@ -0,0 +1,2 @@ +vdso.lds +*.tmp
arch/riscv/kernel/vdso/Makefile new file +63 -0
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arch/riscv/kernel/vdso/rt_sigreturn.S new file +24 -0
@@ -0,0 +1,24 @@ +/* + * Copyright (C) 2014 Regents of the University of California + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/linkage.h> +#include <asm/unistd.h> + + .text +ENTRY(__vdso_rt_sigreturn) + .cfi_startproc + .cfi_signal_frame + li a7, __NR_rt_sigreturn + scall + .cfi_endproc +ENDPROC(__vdso_rt_sigreturn)
arch/riscv/kernel/vdso/vdso.S new file +27 -0
@@ -0,0 +1,27 @@ +/* + * Copyright (C) 2014 Regents of the University of California + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/init.h> +#include <linux/linkage.h> +#include <asm/page.h> + + __PAGE_ALIGNED_DATA + + .globl vdso_start, vdso_end + .balign PAGE_SIZE +vdso_start: + .incbin "arch/riscv/kernel/vdso/vdso.so" + .balign PAGE_SIZE +vdso_end: + + .previous
arch/riscv/kernel/vdso/vdso.lds.S new file +77 -0
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Signature · 1 line
2.13.5
Palmer Dabbelt
maintainerPATCH v8 18/18 RISC-V: Build Infrastructure
In reply to Palmer DabbeltThis patch contains all the build infrastructure that actually enables the RISC-V port. This includes Makefiles, linker scripts, and Kconfig files. It also contains the only top-level change, which adds RISC-V to the list of architectures that need a sed run to produce the ARCH variable when building locally.
Signed-off-by Palmer Dabbelt <[email protected]>
--- Makefile | 3 +- arch/riscv/Kconfig | 306 ++++++++++++++++++++++++++++++ arch/riscv/Makefile | 72 +++++++ arch/riscv/configs/freedom-u500_defconfig | 52 +++++ arch/riscv/configs/spike32_defconfig | 50 +++++ arch/riscv/configs/spike64_defconfig | 46 +++++ arch/riscv/include/asm/Kbuild | 61 ++++++ arch/riscv/kernel/.gitignore | 1 + arch/riscv/kernel/Makefile | 33 ++++ arch/riscv/kernel/vmlinux.lds.S | 92 +++++++++ arch/riscv/lib/Makefile | 6 + arch/riscv/mm/Makefile | 4 + 12 files changed, 725 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/Kconfig create mode 100644 arch/riscv/Makefile create mode 100644 arch/riscv/configs/freedom-u500_defconfig create mode 100644 arch/riscv/configs/spike32_defconfig create mode 100644 arch/riscv/configs/spike64_defconfig create mode 100644 arch/riscv/include/asm/Kbuild create mode 100644 arch/riscv/kernel/.gitignore create mode 100644 arch/riscv/kernel/Makefile create mode 100644 arch/riscv/kernel/vmlinux.lds.S create mode 100644 arch/riscv/lib/Makefile create mode 100644 arch/riscv/mm/Makefile
Makefile +2 -1
@@ -225,7 +225,8 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/x86/ -e s/x86_64/x86/ \ -e s/arm.*/arm/ -e s/sa110/arm/ \ -e s/s390x/s390/ -e s/parisc64/parisc/ \ -e s/ppc.*/powerpc/ -e s/mips.*/mips/ \ - -e s/sh[234].*/sh/ -e s/aarch64.*/arm64/ ) + -e s/sh[234].*/sh/ -e s/aarch64.*/arm64/ \ + -e s/riscv.*/riscv/) # Cross compiling and selecting different set of gcc/bin-utils # ---------------------------------------------------------------------------
arch/riscv/Kconfig new file +306 -0
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arch/riscv/Makefile new file +72 -0
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arch/riscv/configs/freedom-u500_defconfig new file +52 -0
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arch/riscv/configs/spike32_defconfig new file +50 -0
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arch/riscv/configs/spike64_defconfig new file +46 -0
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arch/riscv/include/asm/Kbuild new file +61 -0
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arch/riscv/kernel/.gitignore new file +1 -0
@@ -0,0 +1 @@ +/vmlinux.lds
arch/riscv/kernel/Makefile new file +33 -0
@@ -0,0 +1,33 @@ +# +# Makefile for the RISC-V Linux kernel +# + +extra-y += head.o +extra-y += vmlinux.lds + +obj-y += cpu.o +obj-y += cpufeature.o +obj-y += entry.o +obj-y += irq.o +obj-y += process.o +obj-y += ptrace.o +obj-y += reset.o +obj-y += setup.o +obj-y += signal.o +obj-y += syscall_table.o +obj-y += sys_riscv.o +obj-y += time.o +obj-y += traps.o +obj-y += riscv_ksyms.o +obj-y += stacktrace.o +obj-y += vdso.o +obj-y += cacheinfo.o +obj-y += vdso/ + +CFLAGS_setup.o := -mcmodel=medany + +obj-$(CONFIG_SMP) += smpboot.o +obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_MODULES) += module.o + +clean:
arch/riscv/kernel/vmlinux.lds.S new file +92 -0
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arch/riscv/lib/Makefile new file +6 -0
@@ -0,0 +1,6 @@ +lib-y += delay.o +lib-y += memcpy.o +lib-y += memset.o +lib-y += uaccess.o + +lib-$(CONFIG_32BIT) += udivdi3.o
arch/riscv/mm/Makefile new file +4 -0
@@ -0,0 +1,4 @@ +obj-y += init.o +obj-y += fault.o +obj-y += extable.o +obj-y += ioremap.o
Signature · 1 line
2.13.5
Re: [PATCH v8 18/18] RISC-V: Build Infrastructure
2017-09-13 6:57 GMT+09:00 Palmer Dabbelt <[email protected]>:
Quoted 62 lines
This patch contains all the build infrastructure that actually enables the RISC-V port. This includes Makefiles, linker scripts, and
Kconfigfiles. It also contains the only top-level change, which adds RISC-V to the list of architectures that need a sed run to produce the ARCH variable when building locally.Signed-off-by Palmer Dabbelt <[email protected]>arch/riscv/include/asm/Kbuild new file +51
-0@@ -0,0 +1,61 @@ +generic-y += bugs.h +generic-y += cacheflush.h +generic-y += checksum.h +generic-y += clkdev.h +generic-y += cputime.h +generic-y += device.h +generic-y += div64.h +generic-y += dma.h +generic-y += dma-contiguous.h +generic-y += emergency-restart.h +generic-y += errno.h +generic-y += exec.h +generic-y += fb.h +generic-y += fcntl.h +generic-y += ftrace.h +generic-y += futex.h +generic-y += hardirq.h +generic-y += hash.h +generic-y += hw_irq.h +generic-y += ioctl.h +generic-y += ioctls.h +generic-y += ipcbuf.h +generic-y += irq_regs.h +generic-y += irq_work.h +generic-y += kdebug.h +generic-y += kmap_types.h +generic-y += kvm_para.h +generic-y += local.h +generic-y += mm-arch-hooks.h +generic-y += mman.h +generic-y += module.h +generic-y += msgbuf.h +generic-y += mutex.h +generic-y += param.h +generic-y += percpu.h +generic-y += poll.h +generic-y += posix_types.h +generic-y += preempt.h +generic-y += resource.h +generic-y += scatterlist.h +generic-y += sections.h +generic-y += sembuf.h +generic-y += setup.h +generic-y += shmbuf.h +generic-y += shmparam.h +generic-y += signal.h +generic-y += socket.h +generic-y += sockios.h +generic-y += stat.h +generic-y += statfs.h +generic-y += swab.h
arch/riscv/include/asm/Kbuild line 61
Quoted 10 lines
arch/riscv/include/asm/Kbuild new file +10
-0+generic-y += termbits.h +generic-y += termios.h +generic-y += topology.h +generic-y += trace_clock.h +generic-y += types.h +generic-y += unaligned.h +generic-y += user.h +generic-y += vga.h +generic-y += vmlinux.lds.h +generic-y += xor.h
Please split out exported ones into arch/riscv/include/uapi/asm/Kbuild.
Otherwise, "make headers_install" will fail.
Signature · 2 lines
Best Regards Masahiro Yamada