Skip to contentSkip to conversation

serial: serial_sh: take into account port->clk_mode for SH7785/7786

PATCH New Thomas Petazzoni 2 participants 4 messages Aug 28, 2017 – Sep 24, 2017

lore
Share & tools
lore
#0 lore raw

PATCH 1/1 serial: serial_sh: take into account port->clk_mode for SH7785/7786

In the SH7785/SH7786 case, the SCSCR value is harcoded to be 0x3a, which means bits CKE1/CKE0 have the value 10b. This tells the SCIF that the "External clock/SCIF_SCK pin functions as clock input".

However, this is not the case in all designs, and it's the purpose of the clk_mode = EXT_CLK to indicate such a setting.

In order for the serial_sh driver to work on a SH7786 platform that does not use SCIF_SCK as a clock input, we have to adjust the SCSCR_INIT value, to have CKE1/CKE0 set to 00b. This is similar to what is done for other SH platforms.

---
 drivers/serial/serial_sh.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/serial/serial_sh.h +2 -1
index 4d27122..d7bbd1a 100644
@@ -184,7 +184,8 @@ struct uart_port {
 # define SCSPTR4	0xffee0024	/* 16 bit SCIF */
 # define SCSPTR5	0xffef0024	/* 16 bit SCIF */
 # define SCIF_ORER	0x0001		/* Overrun error bit */
-# define SCSCR_INIT(port)	0x3a	/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
+# define SCSCR_INIT(port)	(port->clk_mode == EXT_CLK ? 0x3a : 0x38)
+				/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_CPU_SH7201) || \
 	defined(CONFIG_CPU_SH7203) || \
 	defined(CONFIG_CPU_SH7206) || \
Signature · 1 line
2.9.4
#1 lore raw

PATCH 1/1 serial: serial_sh: take into account port->clk_mode for SH7785/7786

Hello,

Quoted 7 lines · Thomas Petazzoni

In the SH7785/SH7786 case, the SCSCR value is harcoded to be 0x3a, which means bits CKE1/CKE0 have the value 10b. This tells the SCIF that the "External clock/SCIF_SCK pin functions as clock input".

However, this is not the case in all designs, and it's the purpose of the clk_mode = EXT_CLK to indicate such a setting.

Quoted 6 lines

In order for the serial_sh driver to work on a SH7786 platform that does not use SCIF_SCK as a clock input, we have to adjust the SCSCR_INIT value, to have CKE1/CKE0 set to 00b. This is similar to what is done for other SH platforms.

Any comments on this patch ?

Thanks,

Thomas

Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
#2 lore raw

PATCH 1/1 serial: serial_sh: take into account port->clk_mode for SH7785/7786

Hi,

2017-09-14 7:27 GMT+09:00 Thomas Petazzoni
<[email protected]>:

Quoted 10 lines

Hello,

Quoted 7 lines · Thomas Petazzoni

In the SH7785/SH7786 case, the SCSCR value is harcoded to be 0x3a, which means bits CKE1/CKE0 have the value 10b. This tells the SCIF that the "External clock/SCIF_SCK pin functions as clock input".

However, this is not the case in all designs, and it's the purpose of the clk_mode = EXT_CLK to indicate such a setting.

Quoted 8 lines
Quoted 6 lines

In order for the serial_sh driver to work on a SH7786 platform that does not use SCIF_SCK as a clock input, we have to adjust the SCSCR_INIT value, to have CKE1/CKE0 set to 00b. This is similar to what is done for other SH platforms.

Any comments on this patch ?

Sorry, reply is too late.

Applied, thanks.

Quoted 8 lines

Thanks,

Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Best regards,
Nobuhiro

Signature · 3 lines
Nobuhiro Iwamatsu
   iwamatsu at {nigauri.org / debian.org}
   GPG ID: 40AD1FA6
#3 lore raw

PATCH 1/1 serial: serial_sh: take into account port->clk_mode for SH7785/7786

Hello,

Quoted 3 lines · Nobuhiro Iwamatsu

Sorry, reply is too late.

Applied, thanks.

Thanks!

Do you have any suggestion/comments about:

Subject: [U-Boot] I/O accessors on SuperH and endianness
Date: Mon, 28 Aug 2017 14:32:49 +0200

and:

Subject: [U-Boot] Initializing global_data on SuperH before board_init_f() ? Date: Tue, 15 Aug 2017 23:07:30 +0200

Thanks!

Thomas

Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com