Skip to contentSkip to conversation

arm64: dts: renesas: r8a77970: add EtherAVB support

PATCH New Sergei Shtylyov 2 participants 2 messages Sep 15, 2017 – Sep 18, 2017

Subsystems (2)
Device tree bindings Arm/RISC-V/Renesas architecture
lore
Share & tools
lore

Sergei Shtylyov

author
#0 lore raw

PATCH v2 5/8 arm64: dts: renesas: r8a77970: add EtherAVB support

Define the generic R8A77970 part of the EtherAVB device node.

Based on the original (and large) patch by Daisuke Matsushita <[email protected]>.

Signed-off-by Vladimir Barinov <[email protected]>
Signed-off-by Sergei Shtylyov <[email protected]>
Reviewed-by Geert Uytterhoeven <[email protected]>

---
Changes in version 2:
- replaced the use of the SYSC power domain #define with a bare number;
- refreshed the patch;
- added Geert's tag.

 arch/arm64/boot/dts/renesas/r8a77970.dtsi |   44 ++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)
arch/arm64/boot/dts/renesas/r8a77970.dtsi +44 -0
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===================================================================
@@ -318,5 +318,49 @@
 			resets = <&cpg 203>;
 			status = "disabled";
 		};
+
+		avb: ethernet at e6800000 {
+			compatible = "renesas,etheravb-r8a77970",
+				     "renesas,etheravb-rcar-gen3";
+			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7",
+					  "ch8", "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15",
+					  "ch16", "ch17", "ch18", "ch19",
+					  "ch20", "ch21", "ch22", "ch23",
+					  "ch24";
+			clocks = <&cpg CPG_MOD 812>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 812>;
+			phy-mode = "rgmii-id";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 	};
 };