arm64: marvell: 7k/8k: improve network support

PATCH Superseded Antoine Tenart 4 participants 20 messages Sep 18, 2017 – Sep 20, 2017

Subsystems (3)

Device tree bindings Arm/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SoC support Marvell macchiatobin support

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Antoine Tenart

author

2017-09-18 07:58 UTC #0 lore raw

cover arm64: marvell: 7k/8k: improve network support

Hi all,

This series improves the network support on Marvell 7k and 8k platforms by adding descriptions of the comphy, and by using the comphy in already available networking ports. The series also introduces a description of the SFP ports on the Marvell Armada 7040-db and 8040-db.

Two defconfig patches also improve the Marvell ARM64 support by enabling required options allowing to use the networking ports properly.

This series follows recent improvements in the PPv2 driver.

Based on v4.14-rc1, and tested on the Marvell Armada 7040-db, 8040-db and 8040-mcbin.

Thanks!
Antoine

Antoine Tenart (8):
arm64: defconfig: enable the Marvell 10G PHY as a module
arm64: dts: marvell: extend the cp110 syscon register area length
arm64: dts: marvell: add comphy nodes on cp110 master and slave
arm64: dts: marvell: mcbin: add comphy references to Ethernet ports
arm64: dts: marvell: 7040-db: add comphy reference to Ethernet port
arm64: dts: marvell: cp110: add PPv2 port interrupts
arm64: dts: marvell: 7040-db: enable the SFP port
arm64: dts: marvell: 8040-db: enable the SFP ports

Miquel Raynal (1):
arm64: defconfig: enable Marvell CP110 comphy

 arch/arm64/boot/dts/marvell/armada-7040-db.dts     |  7 +++
 arch/arm64/boot/dts/marvell/armada-8040-db.dts     | 10 ++++
 arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts  |  3 ++
 .../boot/dts/marvell/armada-cp110-master.dtsi      | 55 +++++++++++++++++++---
 .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 55 +++++++++++++++++++---
 arch/arm64/configs/defconfig                       |  2 +
 6 files changed, 118 insertions(+), 14 deletions(-)

Signature · 1 line

2.13.5

Antoine Tenart

author

2017-09-18 07:58 UTC #1 lore raw

PATCH 1/9 arm64: defconfig: enable the Marvell 10G PHY as a module

The Marvell 10G PHY is present on mvebu platforms. Enable it as a module so that the network works on these platforms.

Signed-off-by Antoine Tenart <[email protected]>

---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

arch/arm64/configs/defconfig +1 -0

index 34480e9af2e7..4c9d4f6692dc 100644
@@ -204,6 +204,7 @@ CONFIG_STMMAC_ETH=m
 CONFIG_MDIO_BUS_MUX_MMIOREG=y
 CONFIG_AT803X_PHY=m
 CONFIG_MARVELL_PHY=m
+CONFIG_MARVELL_10G_PHY=m
 CONFIG_MESON_GXL_PHY=m
 CONFIG_MICREL_PHY=y
 CONFIG_REALTEK_PHY=m

Signature · 1 line

2.13.5

Gregory CLEMENT

2017-09-20 12:30 UTC #2 lore raw

PATCH 1/9 arm64: defconfig: enable the Marvell 10G PHY as a module

Hi Antoine,

Quoted 4 lines · Antoine Tenart

The Marvell 10G PHY is present on mvebu platforms. Enable it as a module so that the network works on these platforms.
Signed-off-by Antoine Tenart <[email protected]>

Applied on mvebu/arm64

Thanks,

Gregory

Quoted 24 lines

---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

arch/arm64/configs/defconfig +1 -0

index 34480e9af2e7..4c9d4f6692dc 100644
@@ -204,6 +204,7 @@ CONFIG_STMMAC_ETH=m
 CONFIG_MDIO_BUS_MUX_MMIOREG=y
 CONFIG_AT803X_PHY=m
 CONFIG_MARVELL_PHY=m
+CONFIG_MARVELL_10G_PHY=m
 CONFIG_MESON_GXL_PHY=m
 CONFIG_MICREL_PHY=y
 CONFIG_REALTEK_PHY=m

Signature · 7 lines

2.13.5


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Signature · 4 lines

Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Antoine Tenart

author

2017-09-18 07:58 UTC #3 lore raw

PATCH 2/9 arm64: defconfig: enable Marvell CP110 comphy

In reply to Antoine Tenart

From: Miquel Raynal <[email protected]>

The comphy is an hardware block giving access to common PHYs that can be used by various other engines (Network, SATA, ...). This is used on Marvell 7k/8k platforms for now. Enable the corresponding driver.

Signed-off-by Miquel Raynal <[email protected]>

Signed-off-by Antoine Tenart <[email protected]>

---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

arch/arm64/configs/defconfig +1 -0

index 4c9d4f6692dc..8495b88a0966 100644
@@ -535,6 +535,7 @@ CONFIG_PWM_TEGRA=m
 CONFIG_PHY_RCAR_GEN3_USB2=y
 CONFIG_PHY_HI6220_USB=y
 CONFIG_PHY_SUN4I_USB=y
+CONFIG_PHY_MVEBU_CP110_COMPHY=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_EMMC=y
 CONFIG_PHY_ROCKCHIP_PCIE=m

Signature · 1 line

2.13.5

Gregory CLEMENT

2017-09-20 12:31 UTC #4 lore raw

PATCH 2/9 arm64: defconfig: enable Marvell CP110 comphy

Hi Antoine,

Quoted 8 lines · Antoine Tenart

From: Miquel Raynal <[email protected]>
The comphy is an hardware block giving access to common PHYs that can be used by various other engines (Network, SATA, ...). This is used on Marvell 7k/8k platforms for now. Enable the corresponding driver.
Signed-off-by Miquel Raynal <[email protected]>
Signed-off-by Antoine Tenart <[email protected]>

Applied on mvebu/arm64

Thanks,

Gregory

Quoted 24 lines

---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

arch/arm64/configs/defconfig +1 -0

index 4c9d4f6692dc..8495b88a0966 100644
@@ -535,6 +535,7 @@ CONFIG_PWM_TEGRA=m
 CONFIG_PHY_RCAR_GEN3_USB2=y
 CONFIG_PHY_HI6220_USB=y
 CONFIG_PHY_SUN4I_USB=y
+CONFIG_PHY_MVEBU_CP110_COMPHY=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_EMMC=y
 CONFIG_PHY_ROCKCHIP_PCIE=m

Signature · 7 lines

2.13.5


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Signature · 4 lines

Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Antoine Tenart

author

2017-09-18 07:58 UTC #5 lore raw

PATCH 3/9 arm64: dts: marvell: extend the cp110 syscon register area length

In reply to Antoine Tenart

This patch extends on both cp110 the system register area length to include some of the comphy registers as well.

Signed-off-by Antoine Tenart <[email protected]>

---
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 2 +-
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +1 -1

index 8263a8a504a8..faf7d4a497aa 100644
@@ -143,7 +143,7 @@
 
 			cpm_syscon0: system-controller at 440000 {
 				compatible = "syscon", "simple-mfd";
-				reg = <0x440000 0x1000>;
+				reg = <0x440000 0x2000>;
 
 				cpm_clk: clock {
 					compatible = "marvell,cp110-clock";

arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +1 -1

index b71ee6c83668..02d6e2f1a7bf 100644
@@ -143,7 +143,7 @@
 
 			cps_syscon0: system-controller at 440000 {
 				compatible = "syscon", "simple-mfd";
-				reg = <0x440000 0x1000>;
+				reg = <0x440000 0x2000>;
 
 				cps_clk: clock {
 					compatible = "marvell,cp110-clock";

Signature · 1 line

2.13.5

Gregory CLEMENT

2017-09-20 12:46 UTC #6 lore raw

PATCH 3/9 arm64: dts: marvell: extend the cp110 syscon register area length

Hi Antoine,

Quoted 4 lines · Antoine Tenart

This patch extends on both cp110 the system register area length to include some of the comphy registers as well.
Signed-off-by Antoine Tenart <[email protected]>

Applied on mvebu/dt64

Thanks,

Gregory

Quoted 34 lines

---
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 2 +-
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +1 -1

index 8263a8a504a8..faf7d4a497aa 100644
@@ -143,7 +143,7 @@
 
 			cpm_syscon0: system-controller at 440000 {
 				compatible = "syscon", "simple-mfd";
-				reg = <0x440000 0x1000>;
+				reg = <0x440000 0x2000>;
 
 				cpm_clk: clock {
 					compatible = "marvell,cp110-clock";

arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +1 -1

index b71ee6c83668..02d6e2f1a7bf 100644
@@ -143,7 +143,7 @@
 
 			cps_syscon0: system-controller at 440000 {
 				compatible = "syscon", "simple-mfd";
-				reg = <0x440000 0x1000>;
+				reg = <0x440000 0x2000>;
 
 				cps_clk: clock {
 					compatible = "marvell,cp110-clock";

Signature · 1 line

2.13.5

Signature · 4 lines

Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Antoine Tenart

author

2017-09-18 07:58 UTC #7 lore raw

PATCH 4/9 arm64: dts: marvell: add comphy nodes on cp110 master and slave

In reply to Antoine Tenart

This patch describes the comphy available in the cp110 master and slave. This comphy provides serdes lanes used by various controllers such as the network one.

Signed-off-by Antoine Tenart <[email protected]>

---
 .../boot/dts/marvell/armada-cp110-master.dtsi      | 38 ++++++++++++++++++++++
 .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 38 ++++++++++++++++++++++
 2 files changed, 76 insertions(+)

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +38 -0

index faf7d4a497aa..a26948ff72b4 100644
@@ -109,6 +109,44 @@
 				};
 			};
 
+			cpm_comphy: phy at 120000 {
+				compatible = "marvell,comphy-cp110";
+				reg = <0x120000 0x6000>;
+				marvell,system-controller = <&cpm_syscon0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				cpm_comphy0: phy at 0 {
+					reg = <0>;
+					#phy-cells = <1>;
+				};
+
+				cpm_comphy1: phy at 1 {
+					reg = <1>;
+					#phy-cells = <1>;
+				};
+
+				cpm_comphy2: phy at 2 {
+					reg = <2>;
+					#phy-cells = <1>;
+				};
+
+				cpm_comphy3: phy at 3 {
+					reg = <3>;
+					#phy-cells = <1>;
+				};
+
+				cpm_comphy4: phy at 4 {
+					reg = <4>;
+					#phy-cells = <1>;
+				};
+
+				cpm_comphy5: phy at 5 {
+					reg = <5>;
+					#phy-cells = <1>;
+				};
+			};
+
 			cpm_mdio: mdio at 12a200 {
 				#address-cells = <1>;
 				#size-cells = <0>;

arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +38 -0

index 02d6e2f1a7bf..fe326074edb6 100644
@@ -109,6 +109,44 @@
 				};
 			};
 
+			cps_comphy: phy at 120000 {
+				compatible = "marvell,comphy-cp110";
+				reg = <0x120000 0x6000>;
+				marvell,system-controller = <&cps_syscon0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				cps_comphy0: phy at 0 {
+					reg = <0>;
+					#phy-cells = <1>;
+				};
+
+				cps_comphy1: phy at 1 {
+					reg = <1>;
+					#phy-cells = <1>;
+				};
+
+				cps_comphy2: phy at 2 {
+					reg = <2>;
+					#phy-cells = <1>;
+				};
+
+				cps_comphy3: phy at 3 {
+					reg = <3>;
+					#phy-cells = <1>;
+				};
+
+				cps_comphy4: phy at 4 {
+					reg = <4>;
+					#phy-cells = <1>;
+				};
+
+				cps_comphy5: phy at 5 {
+					reg = <5>;
+					#phy-cells = <1>;
+				};
+			};
+
 			cps_mdio: mdio at 12a200 {
 				#address-cells = <1>;
 				#size-cells = <0>;

Signature · 1 line

2.13.5

Gregory CLEMENT

2017-09-20 12:47 UTC #8 lore raw

PATCH 4/9 arm64: dts: marvell: add comphy nodes on cp110 master and slave

Hi Antoine,

Quoted 5 lines · Antoine Tenart

This patch describes the comphy available in the cp110 master and slave. This comphy provides serdes lanes used by various controllers such as the network one.
Signed-off-by Antoine Tenart <[email protected]>

Applied on mvebu/dt64

Thanks,

Gregory

Quoted 106 lines

---
 .../boot/dts/marvell/armada-cp110-master.dtsi      | 38 ++++++++++++++++++++++
 .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 38 ++++++++++++++++++++++
 2 files changed, 76 insertions(+)

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +38 -0

index faf7d4a497aa..a26948ff72b4 100644
@@ -109,6 +109,44 @@
 				};
 			};
 
+			cpm_comphy: phy at 120000 {
+				compatible = "marvell,comphy-cp110";
+				reg = <0x120000 0x6000>;
+				marvell,system-controller = <&cpm_syscon0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				cpm_comphy0: phy at 0 {
+					reg = <0>;
+					#phy-cells = <1>;
+				};
+
+				cpm_comphy1: phy at 1 {
+					reg = <1>;
+					#phy-cells = <1>;
+				};
+
+				cpm_comphy2: phy at 2 {
+					reg = <2>;
+					#phy-cells = <1>;
+				};
+
+				cpm_comphy3: phy at 3 {
+					reg = <3>;
+					#phy-cells = <1>;
+				};
+
+				cpm_comphy4: phy at 4 {
+					reg = <4>;
+					#phy-cells = <1>;
+				};
+
+				cpm_comphy5: phy at 5 {
+					reg = <5>;
+					#phy-cells = <1>;
+				};
+			};
+
 			cpm_mdio: mdio at 12a200 {
 				#address-cells = <1>;
 				#size-cells = <0>;

arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +38 -0

index 02d6e2f1a7bf..fe326074edb6 100644
@@ -109,6 +109,44 @@
 				};
 			};
 
+			cps_comphy: phy at 120000 {
+				compatible = "marvell,comphy-cp110";
+				reg = <0x120000 0x6000>;
+				marvell,system-controller = <&cps_syscon0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				cps_comphy0: phy at 0 {
+					reg = <0>;
+					#phy-cells = <1>;
+				};
+
+				cps_comphy1: phy at 1 {
+					reg = <1>;
+					#phy-cells = <1>;
+				};
+
+				cps_comphy2: phy at 2 {
+					reg = <2>;
+					#phy-cells = <1>;
+				};
+
+				cps_comphy3: phy at 3 {
+					reg = <3>;
+					#phy-cells = <1>;
+				};
+
+				cps_comphy4: phy at 4 {
+					reg = <4>;
+					#phy-cells = <1>;
+				};
+
+				cps_comphy5: phy at 5 {
+					reg = <5>;
+					#phy-cells = <1>;
+				};
+			};
+
 			cps_mdio: mdio at 12a200 {
 				#address-cells = <1>;
 				#size-cells = <0>;

Signature · 1 line

2.13.5

Signature · 4 lines

Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Antoine Tenart

author

2017-09-18 07:58 UTC #9 lore raw

PATCH 5/9 arm64: dts: marvell: mcbin: add comphy references to Ethernet ports

In reply to Antoine Tenart

This patch adds comphy phandles to the Ethernet ports in the mcbin device tree. The comphy is used to configure the serdes PHYs used by these ports.

Signed-off-by Antoine Tenart <[email protected]>

---
 arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 3 +++
 1 file changed, 3 insertions(+)

arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +3 -0

index acf5c7d16d79..9a3b4a1fd445 100644
@@ -223,6 +223,7 @@
 &cpm_eth0 {
 	status = "okay";
 	phy = <&phy0>;
+	phys = <&cpm_comphy4 0>;
 	phy-mode = "10gbase-kr";
 };

@@ -258,6 +259,7 @@
 &cps_eth0 {
 	status = "okay";
 	phy = <&phy8>;
+	phys = <&cps_comphy4 0>;
 	phy-mode = "10gbase-kr";
 };

@@ -266,6 +268,7 @@
 	status = "okay";
 	phy = <&ge_phy>;
 	phy-mode = "sgmii";
+	phys = <&cps_comphy0 1>;
 };
 
 &cps_pinctrl {

Signature · 1 line

2.13.5

Baruch Siach

2017-09-18 08:50 UTC #10 lore raw

PATCH 5/9 arm64: dts: marvell: mcbin: add comphy references to Ethernet ports

Hi Antoine,

Quoted 14 lines · Antoine Tenart

This patch adds comphy phandles to the Ethernet ports in the mcbin device tree. The comphy is used to configure the serdes PHYs used by these ports.
Signed-off-by Antoine Tenart <[email protected]>
---
 arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 3 +++
 1 file changed, 3 insertions(+)
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +0 -0
index acf5c7d16d79..9a3b4a1fd445 100644

arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts line 227

Quoted 5 lines

arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +1 -0

@@ -223,6 +223,7 @@
 &cpm_eth0 {
 	status = "okay";
 	phy = <&phy0>;
+	phys = <&cpm_comphy4 0>;
 	phy-mode = "10gbase-kr";

Since the 'phys' generic PHY property is unrelated to the 'phy*' Ethernet PHY properties that surround it, its location might be confusing. I think it should appear below those two other properties like you did below ...

arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts line 263

Quoted 8 lines

arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +1 -0

};

@@ -258,6 +259,7 @@
 &cps_eth0 {
 	status = "okay";
 	phy = <&phy8>;
+	phys = <&cps_comphy4 0>;
 	phy-mode = "10gbase-kr";

... not here ...

arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts line 271

Quoted 7 lines

arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +1 -0

};

@@ -266,6 +268,7 @@
 	status = "okay";
 	phy = <&ge_phy>;
 	phy-mode = "sgmii";
+	phys = <&cps_comphy0 1>;

... but here.

See also upstream commits 9a94b3a4bdfdb40 (dt-binding: phy: don't confuse with Ethernet phy properties) and c43593d81ab59b (dt-bindings: net: don't confuse with generic PHY property).

arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts line 274

Quoted 3 lines

arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +0 -0
 };
 
 &cps_pinctrl {

baruch

Signature · 3 lines

     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -

Antoine Tenart

author

2017-09-18 09:44 UTC #11 lore raw

PATCH 5/9 arm64: dts: marvell: mcbin: add comphy references to Ethernet ports

Hi Baruch,

Quoted 38 lines · Baruch Siach

Quoted 14 lines · Antoine Tenart
This patch adds comphy phandles to the Ethernet ports in the mcbin device tree. The comphy is used to configure the serdes PHYs used by these ports.
Signed-off-by Antoine Tenart <[email protected]>
---
 arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 3 +++
 1 file changed, 3 insertions(+)
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +0 -0
index acf5c7d16d79..9a3b4a1fd445 100644
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts line 227
Quoted 5 lines
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +1 -0
@@ -223,6 +223,7 @@
 &cpm_eth0 {
 	status = "okay";
 	phy = <&phy0>;
+	phys = <&cpm_comphy4 0>;
 	phy-mode = "10gbase-kr";
Since the 'phys' generic PHY property is unrelated to the 'phy*' Ethernet PHY properties that surround it, its location might be confusing. I think it should appear below those two other properties like you did below ...
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts line 263
Quoted 8 lines
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +1 -0
 };
 
@@ -258,6 +259,7 @@
 &cps_eth0 {
 	status = "okay";
 	phy = <&phy8>;
+	phys = <&cps_comphy4 0>;
 	phy-mode = "10gbase-kr";
... not here ...
Quoted 2 lines
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +0 -0
 };
 

Quoted 7 lines

arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts line 271
Quoted 5 lines
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +1 -0
@@ -266,6 +268,7 @@
 	status = "okay";
 	phy = <&ge_phy>;
 	phy-mode = "sgmii";
+	phys = <&cps_comphy0 1>;
... but here.

OK, I'll update.

Thanks,
Antoine

Signature · 10 lines

Antoine T?nart, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Andrew Lunn

maintainer

2017-09-18 13:04 UTC #12 lore raw

PATCH 5/9 arm64: dts: marvell: mcbin: add comphy references to Ethernet ports

In reply to Baruch Siach

Quoted 12 lines · Baruch Siach

Hi Antoine,
Quoted 9 lines · Antoine Tenart
This patch adds comphy phandles to the Ethernet ports in the mcbin device tree. The comphy is used to configure the serdes PHYs used by these ports.
Signed-off-by Antoine Tenart <[email protected]>
---
 arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 3 +++
 1 file changed, 3 insertions(+)

Quoted 14 lines

arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts line 227
Quoted 10 lines
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +1 -0
index acf5c7d16d79..9a3b4a1fd445 100644
@@ -223,6 +223,7 @@
 &cpm_eth0 {
 	status = "okay";
 	phy = <&phy0>;
+	phys = <&cpm_comphy4 0>;
 	phy-mode = "10gbase-kr";
Since the 'phys' generic PHY property is unrelated to the 'phy*' Ethernet PHY properties that surround it, its location might be confusing. I think it should appear below those two other properties like you did below ...

Hi Baruch, Antoine

Yes, i agree. It is confusing enough as it is, so we should not make it worse.

I even wonder if it is worth doing some renaming?

phy = <&ethernet_phy0>;
phy-mode = "10gbase-kr";
phys = <&cpm_generic_comphy4 0>;

Andrew

Antoine Tenart

author

2017-09-18 13:52 UTC #13 lore raw

PATCH 5/9 arm64: dts: marvell: mcbin: add comphy references to Ethernet ports

Hi Andrew,

Quoted 26 lines · Andrew Lunn

Quoted 10 lines · Baruch Siach
Quoted 9 lines · Antoine Tenart
This patch adds comphy phandles to the Ethernet ports in the mcbin device tree. The comphy is used to configure the serdes PHYs used by these ports.
Signed-off-by Antoine Tenart <[email protected]>
---
 arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 3 +++
 1 file changed, 3 insertions(+)
Quoted 14 lines
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts line 227
Quoted 10 lines
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +1 -0
index acf5c7d16d79..9a3b4a1fd445 100644
@@ -223,6 +223,7 @@
 &cpm_eth0 {
 	status = "okay";
 	phy = <&phy0>;
+	phys = <&cpm_comphy4 0>;
 	phy-mode = "10gbase-kr";
Since the 'phys' generic PHY property is unrelated to the 'phy*' Ethernet PHY properties that surround it, its location might be confusing. I think it should appear below those two other properties like you did below ...

Quoted 8 lines

Yes, i agree. It is confusing enough as it is, so we should not make it worse.
I even wonder if it is worth doing some renaming?
phy = <&ethernet_phy0>;
phy-mode = "10gbase-kr";
phys = <&cpm_generic_comphy4 0>;

We could also add an extra comment without renaming the comphy node, something like:

	/* Network PHY */
	phy = <&ethernet_phy0>;
	phy-mode = "10gbase-kr";
	/* Generic PHY, providing serdes lanes */
	phys = <&cpm_comphy4 0>;

Thanks,
Antoine

Signature · 10 lines

Antoine T?nart, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Andrew Lunn

maintainer

2017-09-18 16:32 UTC #14 lore raw

PATCH 5/9 arm64: dts: marvell: mcbin: add comphy references to Ethernet ports

Quoted 8 lines

We could also add an extra comment without renaming the comphy node, something like:
	/* Network PHY */
	phy = <&ethernet_phy0>;
	phy-mode = "10gbase-kr";
	/* Generic PHY, providing serdes lanes */
	phys = <&cpm_comphy4 0>;

Yes, that is good.

Thanks
Andrew

Antoine Tenart

author

2017-09-18 07:58 UTC #15 lore raw

PATCH 6/9 arm64: dts: marvell: 7040-db: add comphy reference to Ethernet port

In reply to Antoine Tenart

This patch adds a comphy phandle to the Ethernet port in the 7040-db device tree. The comphy is used to configure the serdes PHYs used by these ports.

Signed-off-by Antoine Tenart <[email protected]>

---
 arch/arm64/boot/dts/marvell/armada-7040-db.dts | 1 +
 1 file changed, 1 insertion(+)

arch/arm64/boot/dts/marvell/armada-7040-db.dts +1 -0

index 9c3bdf87e543..274d203dac13 100644
@@ -219,6 +219,7 @@
 	status = "okay";
 	phy = <&phy0>;
 	phy-mode = "sgmii";
+	phys = <&cpm_comphy0 1>;
 };
 
 &cpm_eth2 {

Signature · 1 line

2.13.5

Antoine Tenart

author

2017-09-18 07:58 UTC #16 lore raw

PATCH 7/9 arm64: dts: marvell: cp110: add PPv2 port interrupts

In reply to Antoine Tenart

Ports interrupts are used by the PPv2 driver when no PHY is connected to a port. This patch adds a description of these interrupts.

Signed-off-by Antoine Tenart <[email protected]>

Tested-by Marcin Wojtas <[email protected]>

---
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 15 +++++++++------
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  | 15 +++++++++------
 2 files changed, 18 insertions(+), 12 deletions(-)

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +9 -6

index a26948ff72b4..b1119c541f16 100644
@@ -74,9 +74,10 @@
 						     <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
-						     <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
+						     <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
+						     <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
 					interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
-							  "tx-cpu3", "rx-shared";
+							  "tx-cpu3", "rx-shared", "link";
 					port-id = <0>;
 					gop-port-id = <0>;
 					status = "disabled";

@@ -87,9 +88,10 @@
 						     <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
-						     <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
+						     <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
+						     <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
 					interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
-							  "tx-cpu3", "rx-shared";
+							  "tx-cpu3", "rx-shared", "link";
 					port-id = <1>;
 					gop-port-id = <2>;
 					status = "disabled";

@@ -100,9 +102,10 @@
 						     <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
-						     <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
+						     <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
+						     <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
 					interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
-							  "tx-cpu3", "rx-shared";
+							  "tx-cpu3", "rx-shared", "link";
 					port-id = <2>;
 					gop-port-id = <3>;
 					status = "disabled";

arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +9 -6

index fe326074edb6..497d233d6c47 100644
@@ -74,9 +74,10 @@
 						     <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
-						     <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
+						     <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
+						     <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
 					interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
-							  "tx-cpu3", "rx-shared";
+							  "tx-cpu3", "rx-shared", "link";
 					port-id = <0>;
 					gop-port-id = <0>;
 					status = "disabled";

@@ -87,9 +88,10 @@
 						     <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
-						     <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
+						     <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
+						     <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
 					interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
-							  "tx-cpu3", "rx-shared";
+							  "tx-cpu3", "rx-shared", "link";
 					port-id = <1>;
 					gop-port-id = <2>;
 					status = "disabled";

@@ -100,9 +102,10 @@
 						     <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
-						     <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
+						     <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
+						     <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
 					interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
-							  "tx-cpu3", "rx-shared";
+							  "tx-cpu3", "rx-shared", "link";
 					port-id = <2>;
 					gop-port-id = <3>;
 					status = "disabled";

Signature · 1 line

2.13.5

Gregory CLEMENT

2017-09-20 12:47 UTC #17 lore raw

PATCH 7/9 arm64: dts: marvell: cp110: add PPv2 port interrupts

Hi Antoine,

Quoted 5 lines · Antoine Tenart

Ports interrupts are used by the PPv2 driver when no PHY is connected to a port. This patch adds a description of these interrupts.
Signed-off-by Antoine Tenart <[email protected]>
Tested-by Marcin Wojtas <[email protected]>

Applied on mvebu/dt64

Thanks,

Gregory

Quoted 94 lines

---
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 15 +++++++++------
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  | 15 +++++++++------
 2 files changed, 18 insertions(+), 12 deletions(-)

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +9 -6

index a26948ff72b4..b1119c541f16 100644
@@ -74,9 +74,10 @@
 						     <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
-						     <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
+						     <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
+						     <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
 					interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
-							  "tx-cpu3", "rx-shared";
+							  "tx-cpu3", "rx-shared", "link";
 					port-id = <0>;
 					gop-port-id = <0>;
 					status = "disabled";

@@ -87,9 +88,10 @@
 						     <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
-						     <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
+						     <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
+						     <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
 					interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
-							  "tx-cpu3", "rx-shared";
+							  "tx-cpu3", "rx-shared", "link";
 					port-id = <1>;
 					gop-port-id = <2>;
 					status = "disabled";

@@ -100,9 +102,10 @@
 						     <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
-						     <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
+						     <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
+						     <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
 					interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
-							  "tx-cpu3", "rx-shared";
+							  "tx-cpu3", "rx-shared", "link";
 					port-id = <2>;
 					gop-port-id = <3>;
 					status = "disabled";

arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +9 -6

index fe326074edb6..497d233d6c47 100644
@@ -74,9 +74,10 @@
 						     <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
-						     <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
+						     <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
+						     <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
 					interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
-							  "tx-cpu3", "rx-shared";
+							  "tx-cpu3", "rx-shared", "link";
 					port-id = <0>;
 					gop-port-id = <0>;
 					status = "disabled";

@@ -87,9 +88,10 @@
 						     <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
-						     <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
+						     <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
+						     <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
 					interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
-							  "tx-cpu3", "rx-shared";
+							  "tx-cpu3", "rx-shared", "link";
 					port-id = <1>;
 					gop-port-id = <2>;
 					status = "disabled";

@@ -100,9 +102,10 @@
 						     <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
 						     <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
-						     <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
+						     <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
+						     <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
 					interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
-							  "tx-cpu3", "rx-shared";
+							  "tx-cpu3", "rx-shared", "link";
 					port-id = <2>;
 					gop-port-id = <3>;
 					status = "disabled";

Signature · 1 line

2.13.5

Signature · 4 lines

Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Antoine Tenart

author

2017-09-18 07:58 UTC #18 lore raw

PATCH 8/9 arm64: dts: marvell: 7040-db: enable the SFP port

In reply to Antoine Tenart

This patch enables the SFP port on the Armada 7040 DB as this port is now supported by the PPv2 driver (since the PHY is now optional).

Signed-off-by Antoine Tenart <[email protected]>

Tested-by Marcin Wojtas <[email protected]>

---
 arch/arm64/boot/dts/marvell/armada-7040-db.dts | 6 ++++++
 1 file changed, 6 insertions(+)

arch/arm64/boot/dts/marvell/armada-7040-db.dts +6 -0

index 274d203dac13..9ca9aa8ec46e 100644
@@ -215,6 +215,12 @@
 	status = "okay";
 };
 
+&cpm_eth0 {
+	status = "okay";
+	phy-mode = "10gbase-kr";
+	phys = <&cpm_comphy2 0>;
+};
+
 &cpm_eth1 {
 	status = "okay";
 	phy = <&phy0>;

Signature · 1 line

2.13.5

Antoine Tenart

author

2017-09-18 07:58 UTC #19 lore raw

PATCH 9/9 arm64: dts: marvell: 8040-db: enable the SFP ports

In reply to Antoine Tenart

This patch enables the SFP ports on the Armada 8040 DB as these ports are now supported by the PPv2 driver (since the PHY is now optional).

Signed-off-by Antoine Tenart <[email protected]>

Tested-by Marcin Wojtas <[email protected]>

---
 arch/arm64/boot/dts/marvell/armada-8040-db.dts | 10 ++++++++++
 1 file changed, 10 insertions(+)

arch/arm64/boot/dts/marvell/armada-8040-db.dts +10 -0

index 0d7b2ae46610..26a018329a74 100644
@@ -200,6 +200,11 @@
 	status = "okay";
 };
 
+&cpm_eth0 {
+	status = "okay";
+	phy-mode = "10gbase-kr";
+};
+
 &cpm_eth2 {
 	status = "okay";
 	phy = <&phy1>;

@@ -244,6 +249,11 @@
 	status = "okay";
 };
 
+&cps_eth0 {
+	status = "okay";
+	phy-mode = "10gbase-kr";
+};
+
 &cps_eth1 {
 	status = "okay";
 	phy = <&phy0>;

Signature · 1 line

2.13.5