drm/amdgpu: introduce AMDGPU_GEM_CREATE_EXPLICIT_SYNC v2

PATCH In review Andres Rodriguez 5 participants 10 messages Sep 19, 2017 – Oct 12, 2017 6 messages not in the archive

Subsystems (3)

DRM drivers DRM misc Radeon and amdgpu DRM drivers

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Andres Rodriguez

author

2017-09-19 12:59 UTC #0 lore raw

PATCH 1/1 drm/amdgpu: introduce AMDGPU_GEM_CREATE_EXPLICIT_SYNC v2

Introduce a flag to signal that access to a BO will be synchronized through an external mechanism.

Currently all buffers shared between contexts are subject to implicit synchronization. However, this is only required for protocols that currently don't support an explicit synchronization mechanism (DRI2/3).

This patch introduces the AMDGPU_GEM_CREATE_EXPLICIT_SYNC, so that users can specify when it is safe to disable implicit sync.

v2: only disable explicit sync in amdgpu_cs_ioctl

Signed-off-by Andres Rodriguez <[email protected]>

---

Hey Christian,

I kept the amdgpu_bo_explicit_sync() function since it makes it easier to maintain an 80 line wrap in amdgpu_cs_sync_rings()

Regards,
Andres

 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c     | 3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c    | 4 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 8 ++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c   | 7 +++++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h   | 3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    | 5 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     | 8 ++++----
 include/uapi/drm/amdgpu_drm.h              | 2 ++
 8 files changed, 29 insertions(+), 11 deletions(-)

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +2 -1

index db97e78..bc8a403 100644
@@ -704,7 +704,8 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 
 	list_for_each_entry(e, &p->validated, tv.head) {
 		struct reservation_object *resv = e->robj->tbo.resv;
-		r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
+		r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
+				     amdgpu_bo_explicit_sync(e->robj));
 
 		if (r)
 			return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +3 -1

index b0d45c8..21e9936 100644
@@ -212,7 +212,9 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
 		      AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
 		      AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 		      AMDGPU_GEM_CREATE_VRAM_CLEARED |
-		      AMDGPU_GEM_CREATE_VM_ALWAYS_VALID))
+		      AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
+		      AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
+
 		return -EINVAL;
 
 	/* reject invalid gem domains */

drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +8 -0

index c26ef53..428aae0 100644
@@ -193,6 +193,14 @@ static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
 	}
 }
 
+/**
+ * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
+ */
+static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
+{
+	return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
+}
+
 int amdgpu_bo_create(struct amdgpu_device *adev,
 			    unsigned long size, int byte_align,
 			    bool kernel, u32 domain, u64 flags,

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +5 -2

index c586f44..a4bf21f 100644
@@ -169,14 +169,14 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
  *
  * @sync: sync object to add fences from reservation object to
  * @resv: reservation object with embedded fence
- * @shared: true if we should only sync to the exclusive fence
+ * @explicit_sync: true if we should only sync to the exclusive fence
  *
  * Sync to the fence
  */
 int amdgpu_sync_resv(struct amdgpu_device *adev,
 		     struct amdgpu_sync *sync,
 		     struct reservation_object *resv,
-		     void *owner)
+		     void *owner, bool explicit_sync)
 {
 	struct reservation_object_list *flist;
 	struct dma_fence *f;

@@ -191,6 +191,9 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
 	f = reservation_object_get_excl(resv);
 	r = amdgpu_sync_fence(adev, sync, f);
 
+	if (explicit_sync)
+		return r;
+
 	flist = reservation_object_get_list(resv);
 	if (!flist || r)
 		return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h +2 -1

index dc76879..70d7e3a 100644
@@ -45,7 +45,8 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
 int amdgpu_sync_resv(struct amdgpu_device *adev,
 		     struct amdgpu_sync *sync,
 		     struct reservation_object *resv,
-		     void *owner);
+		     void *owner,
+		     bool explicit_sync);
 struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
 				     struct amdgpu_ring *ring);
 struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +3 -2

index c9c059d..bd0b03a 100644
@@ -1510,7 +1510,8 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
 	job->vm_needs_flush = vm_needs_flush;
 	if (resv) {
 		r = amdgpu_sync_resv(adev, &job->sync, resv,
-				     AMDGPU_FENCE_OWNER_UNDEFINED);
+				     AMDGPU_FENCE_OWNER_UNDEFINED,
+				     false);
 		if (r) {
 			DRM_ERROR("sync failed (%d).\n", r);
 			goto error_free;

@@ -1602,7 +1603,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
 
 	if (resv) {
 		r = amdgpu_sync_resv(adev, &job->sync, resv,
-				     AMDGPU_FENCE_OWNER_UNDEFINED);
+				     AMDGPU_FENCE_OWNER_UNDEFINED, false);
 		if (r) {
 			DRM_ERROR("sync failed (%d).\n", r);
 			goto error_free;

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +4 -4

index 2df254c..9965d68 100644
@@ -987,7 +987,7 @@ static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	int r;
 
 	amdgpu_sync_create(&sync);
-	amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner);
+	amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false);
 	r = amdgpu_sync_wait(&sync, true);
 	amdgpu_sync_free(&sync);

@@ -1128,11 +1128,11 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev,
 			amdgpu_ring_pad_ib(ring, params.ib);
 			amdgpu_sync_resv(adev, &job->sync,
 					 parent->base.bo->tbo.resv,
-					 AMDGPU_FENCE_OWNER_VM);
+					 AMDGPU_FENCE_OWNER_VM, false);
 			if (shadow)
 				amdgpu_sync_resv(adev, &job->sync,
 						 shadow->tbo.resv,
-						 AMDGPU_FENCE_OWNER_VM);
+						 AMDGPU_FENCE_OWNER_VM, false);
 
 			WARN_ON(params.ib->length_dw > ndw);
 			r = amdgpu_job_submit(job, ring, &vm->entity,

@@ -1595,7 +1595,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 		goto error_free;
 
 	r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
-			     owner);
+			     owner, false);
 	if (r)
 		goto error_free;

include/uapi/drm/amdgpu_drm.h +2 -0

index 69d64e5..96fcde8 100644
@@ -91,6 +91,8 @@ extern "C" {
 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS	(1 << 5)
 /* Flag that BO is always valid in this VM */
 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID	(1 << 6)
+/* Flag that BO sharing will be explicitly synchronized */
+#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC		(1 << 7)
 
 struct drm_amdgpu_gem_create_in  {
 	/** the requested memory size */

Signature · 6 lines

2.9.3

_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

A message that is not in the archive (sent off-list or not yet received): 20170919125918.4132-1-andresx7-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org

Christian König

2017-09-19 13:24 UTC #2 lore raw

Am 19.09.2017 um 14:59 schrieb Andres Rodriguez:

Quoted 12 lines

Introduce a flag to signal that access to a BO will be synchronized through an external mechanism.
Currently all buffers shared between contexts are subject to implicit synchronization. However, this is only required for protocols that currently don't support an explicit synchronization mechanism (DRI2/3).
This patch introduces the AMDGPU_GEM_CREATE_EXPLICIT_SYNC, so that users can specify when it is safe to disable implicit sync.
v2: only disable explicit sync in amdgpu_cs_ioctl

Quoted 7 lines

Signed-off-by Andres Rodriguez <[email protected]>
---
Hey Christian,
I kept the amdgpu_bo_explicit_sync() function since it makes it easier to maintain an 80 line wrap in amdgpu_cs_sync_rings()

Looks good to me, but I would like to see the matching user space code as well.

Especially I have no idea how you want to have DRI3 compatibility with that?

Regards,
Christian.

Quoted 171 lines

Regards,
Andres

  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c     | 3 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c    | 4 +++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 8 ++++++++
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c   | 7 +++++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h   | 3 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    | 5 +++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     | 8 ++++----
  include/uapi/drm/amdgpu_drm.h              | 2 ++
  8 files changed, 29 insertions(+), 11 deletions(-)

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +2 -1

index db97e78..bc8a403 100644
@@ -704,7 +704,8 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 
  	list_for_each_entry(e, &p->validated, tv.head) {
  		struct reservation_object *resv = e->robj->tbo.resv;
-		r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
+		r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
+				     amdgpu_bo_explicit_sync(e->robj));
 
  		if (r)
  			return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +3 -1

index b0d45c8..21e9936 100644
@@ -212,7 +212,9 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
  		      AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
  		      AMDGPU_GEM_CREATE_CPU_GTT_USWC |
  		      AMDGPU_GEM_CREATE_VRAM_CLEARED |
-		      AMDGPU_GEM_CREATE_VM_ALWAYS_VALID))
+		      AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
+		      AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
+
  		return -EINVAL;
 
  	/* reject invalid gem domains */

drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +8 -0

index c26ef53..428aae0 100644
@@ -193,6 +193,14 @@ static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
  	}
  }
 
+/**
+ * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
+ */
+static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
+{
+	return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
+}
+
  int amdgpu_bo_create(struct amdgpu_device *adev,
  			    unsigned long size, int byte_align,
  			    bool kernel, u32 domain, u64 flags,

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +5 -2

index c586f44..a4bf21f 100644
@@ -169,14 +169,14 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
   *
   * @sync: sync object to add fences from reservation object to
   * @resv: reservation object with embedded fence
- * @shared: true if we should only sync to the exclusive fence
+ * @explicit_sync: true if we should only sync to the exclusive fence
   *
   * Sync to the fence
   */
  int amdgpu_sync_resv(struct amdgpu_device *adev,
  		     struct amdgpu_sync *sync,
  		     struct reservation_object *resv,
-		     void *owner)
+		     void *owner, bool explicit_sync)
  {
  	struct reservation_object_list *flist;
  	struct dma_fence *f;

@@ -191,6 +191,9 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
  	f = reservation_object_get_excl(resv);
  	r = amdgpu_sync_fence(adev, sync, f);
 
+	if (explicit_sync)
+		return r;
+
  	flist = reservation_object_get_list(resv);
  	if (!flist || r)
  		return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h +2 -1

index dc76879..70d7e3a 100644
@@ -45,7 +45,8 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
  int amdgpu_sync_resv(struct amdgpu_device *adev,
  		     struct amdgpu_sync *sync,
  		     struct reservation_object *resv,
-		     void *owner);
+		     void *owner,
+		     bool explicit_sync);
  struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
  				     struct amdgpu_ring *ring);
  struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +3 -2

index c9c059d..bd0b03a 100644
@@ -1510,7 +1510,8 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
  	job->vm_needs_flush = vm_needs_flush;
  	if (resv) {
  		r = amdgpu_sync_resv(adev, &job->sync, resv,
-				     AMDGPU_FENCE_OWNER_UNDEFINED);
+				     AMDGPU_FENCE_OWNER_UNDEFINED,
+				     false);
  		if (r) {
  			DRM_ERROR("sync failed (%d).\n", r);
  			goto error_free;

@@ -1602,7 +1603,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
 
  	if (resv) {
  		r = amdgpu_sync_resv(adev, &job->sync, resv,
-				     AMDGPU_FENCE_OWNER_UNDEFINED);
+				     AMDGPU_FENCE_OWNER_UNDEFINED, false);
  		if (r) {
  			DRM_ERROR("sync failed (%d).\n", r);
  			goto error_free;

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +4 -4

index 2df254c..9965d68 100644
@@ -987,7 +987,7 @@ static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
  	int r;
 
  	amdgpu_sync_create(&sync);
-	amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner);
+	amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false);
  	r = amdgpu_sync_wait(&sync, true);
  	amdgpu_sync_free(&sync);

@@ -1128,11 +1128,11 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev,
  			amdgpu_ring_pad_ib(ring, params.ib);
  			amdgpu_sync_resv(adev, &job->sync,
  					 parent->base.bo->tbo.resv,
-					 AMDGPU_FENCE_OWNER_VM);
+					 AMDGPU_FENCE_OWNER_VM, false);
  			if (shadow)
  				amdgpu_sync_resv(adev, &job->sync,
  						 shadow->tbo.resv,
-						 AMDGPU_FENCE_OWNER_VM);
+						 AMDGPU_FENCE_OWNER_VM, false);
 
  			WARN_ON(params.ib->length_dw > ndw);
  			r = amdgpu_job_submit(job, ring, &vm->entity,

@@ -1595,7 +1595,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
  		goto error_free;
 
  	r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
-			     owner);
+			     owner, false);
  	if (r)
  		goto error_free;

include/uapi/drm/amdgpu_drm.h +0 -0

index 69d64e5..96fcde8 100644

include/uapi/drm/amdgpu_drm.h extern "C" { · line 98

Quoted 8 lines

include/uapi/drm/amdgpu_drm.h +2 -0

@@ -91,6 +91,8 @@ extern "C" {
  #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS	(1 << 5)
  /* Flag that BO is always valid in this VM */
  #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID	(1 << 6)
+/* Flag that BO sharing will be explicitly synchronized */
+#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC		(1 << 7)
 
  struct drm_amdgpu_gem_create_in  {
  	/** the requested memory size */

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A message that is not in the archive (sent off-list or not yet received): fa69f268-541d-8729-48cf-93ae50d44035-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org

Andres Rodriguez

author

2017-09-19 13:57 UTC #4 lore raw

Quoted 16 lines · Christian König

Am 19.09.2017 um 14:59 schrieb Andres Rodriguez:
Quoted 15 lines
Introduce a flag to signal that access to a BO will be synchronized through an external mechanism.
Currently all buffers shared between contexts are subject to implicit synchronization. However, this is only required for protocols that currently don't support an explicit synchronization mechanism (DRI2/3).
This patch introduces the AMDGPU_GEM_CREATE_EXPLICIT_SYNC, so that users can specify when it is safe to disable implicit sync.
v2: only disable explicit sync in amdgpu_cs_ioctl
Signed-off-by Andres Rodriguez <[email protected]>
---

Quoted 9 lines

Quoted 4 lines
Hey Christian,
I kept the amdgpu_bo_explicit_sync() function since it makes it easier to maintain an 80 line wrap in amdgpu_cs_sync_rings()
Looks good to me, but I would like to see the matching user space code as well.
Especially I have no idea how you want to have DRI3 compatibility with that?

No problem. I'm fixing the radv patch atm and I'll re-send it for your reference.

Regards,
Andres

Quoted 172 lines

Regards,
Christian.

Quoted 169 lines

Regards,
Andres

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 8 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 7 +++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 ++++---- include/uapi/drm/amdgpu_drm.h | 2 ++

  8 files changed, 29 insertions(+), 11 deletions(-)

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +2 -1

index db97e78..bc8a403 100644
@@ -704,7 +704,8 @@ static int amdgpu_cs_sync_rings(struct 
 amdgpu_cs_parser *p)
       list_for_each_entry(e, &p->validated, tv.head) {
           struct reservation_object *resv = e->robj->tbo.resv;
-        r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
+        r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
+                     amdgpu_bo_explicit_sync(e->robj));
           if (r)
               return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +0 -0

index b0d45c8..21e9936 100644
@@ -212,7 +212,9 @@ int amdgpu_gem_create_ioctl(struct drm_device 
 *dev, void *data,

                AMDGPU_GEM_CREATE_NO_CPU_ACCESS | AMDGPU_GEM_CREATE_CPU_GTT_USWC | AMDGPU_GEM_CREATE_VRAM_CLEARED | -              AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)) +              AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | +              AMDGPU_GEM_CREATE_EXPLICIT_SYNC)) +
          return -EINVAL;
      /* reject invalid gem domains */

drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +8 -0

index c26ef53..428aae0 100644
@@ -193,6 +193,14 @@ static inline bool 
 amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
       }
   }
+/**
+ * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
+ */
+static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
+{
+    return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
+}
+
   int amdgpu_bo_create(struct amdgpu_device *adev,
                   unsigned long size, int byte_align,
                   bool kernel, u32 domain, u64 flags,

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +2 -2

index c586f44..a4bf21f 100644
@@ -169,14 +169,14 @@ int amdgpu_sync_fence(struct amdgpu_device 
 *adev, struct amdgpu_sync *sync,
    *
    * @sync: sync object to add fences from reservation object to
    * @resv: reservation object with embedded fence
- * @shared: true if we should only sync to the exclusive fence
+ * @explicit_sync: true if we should only sync to the exclusive fence
    *
    * Sync to the fence
    */
   int amdgpu_sync_resv(struct amdgpu_device *adev,
                struct amdgpu_sync *sync,
                struct reservation_object *resv,
-             void *owner)
+             void *owner, bool explicit_sync)
   {
       struct reservation_object_list *flist;

struct dma_fence *f;

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +3 -0

@@ -191,6 +191,9 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
       f = reservation_object_get_excl(resv);
       r = amdgpu_sync_fence(adev, sync, f);
+    if (explicit_sync)
+        return r;
+
       flist = reservation_object_get_list(resv);
       if (!flist || r)
           return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h +2 -1

index dc76879..70d7e3a 100644
@@ -45,7 +45,8 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, 
 struct amdgpu_sync *sync,
   int amdgpu_sync_resv(struct amdgpu_device *adev,
                struct amdgpu_sync *sync,
                struct reservation_object *resv,
-             void *owner);
+             void *owner,
+             bool explicit_sync);
   struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
                        struct amdgpu_ring *ring);

struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +2 -1

index c9c059d..bd0b03a 100644
@@ -1510,7 +1510,8 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, 
 uint64_t src_offset,
       job->vm_needs_flush = vm_needs_flush;
       if (resv) {
           r = amdgpu_sync_resv(adev, &job->sync, resv,
-                     AMDGPU_FENCE_OWNER_UNDEFINED);
+                     AMDGPU_FENCE_OWNER_UNDEFINED,
+                     false);
           if (r) {
               DRM_ERROR("sync failed (%d).\n", r);

goto error_free;

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +1 -1

@@ -1602,7 +1603,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
       if (resv) {
           r = amdgpu_sync_resv(adev, &job->sync, resv,
-                     AMDGPU_FENCE_OWNER_UNDEFINED);
+                     AMDGPU_FENCE_OWNER_UNDEFINED, false);
           if (r) {
               DRM_ERROR("sync failed (%d).\n", r);
               goto error_free;

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +4 -4

index 2df254c..9965d68 100644
@@ -987,7 +987,7 @@ static int amdgpu_vm_wait_pd(struct amdgpu_device 
 *adev, struct amdgpu_vm *vm,
       int r;
       amdgpu_sync_create(&sync);
-    amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner);
+    amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, 
 false);
       r = amdgpu_sync_wait(&sync, true);
       amdgpu_sync_free(&sync);

@@ -1128,11 +1128,11 @@ static int amdgpu_vm_update_level(struct 
 amdgpu_device *adev,
               amdgpu_ring_pad_ib(ring, params.ib);
               amdgpu_sync_resv(adev, &job->sync,
                        parent->base.bo->tbo.resv,
-                     AMDGPU_FENCE_OWNER_VM);
+                     AMDGPU_FENCE_OWNER_VM, false);
               if (shadow)
                   amdgpu_sync_resv(adev, &job->sync,
                            shadow->tbo.resv,
-                         AMDGPU_FENCE_OWNER_VM);
+                         AMDGPU_FENCE_OWNER_VM, false);
               WARN_ON(params.ib->length_dw > ndw);
               r = amdgpu_job_submit(job, ring, &vm->entity,

@@ -1595,7 +1595,7 @@ static int amdgpu_vm_bo_update_mapping(struct 
 amdgpu_device *adev,
           goto error_free;
       r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
-                 owner);
+                 owner, false);
       if (r)
           goto error_free;

include/uapi/drm/amdgpu_drm.h +0 -0

index 69d64e5..96fcde8 100644

Quoted 10 lines

include/uapi/drm/amdgpu_drm.h extern "C" { · line 97

Quoted 8 lines

include/uapi/drm/amdgpu_drm.h +2 -0

@@ -91,6 +91,8 @@ extern "C" {
   #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS    (1 << 5)
   /* Flag that BO is always valid in this VM */
   #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID    (1 << 6)
+/* Flag that BO sharing will be explicitly synchronized */
+#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC        (1 << 7)
   struct drm_amdgpu_gem_create_in  {
       /** the requested memory size */

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Mao, David

2017-09-19 14:10 UTC #6 lore raw

Hi Andres,
The explicit sync should not be used for DrI3 and DRI2 but for cross process memory sharing, right? We still have to rely on implicit sync to guarantee the. Correct order of rendering and present. Could you confirm?

Thanks.

Sent from my iPhone

On 19 Sep 2017, at 9:57 PM, Andres Rodriguez <[email protected]<mailto:[email protected]>> wrote:

On 2017-09-19 09:24 AM, Christian König wrote:
Am 19.09.2017 um 14:59 schrieb Andres Rodriguez:
Introduce a flag to signal that access to a BO will be synchronized through an external mechanism.

This patch introduces the AMDGPU_GEM_CREATE_EXPLICIT_SYNC, so that users can specify when it is safe to disable implicit sync.

v2: only disable explicit sync in amdgpu_cs_ioctl

Signed-off-by Andres Rodriguez <[email protected]<mailto:[email protected]>>

---

Hey Christian,

I kept the amdgpu_bo_explicit_sync() function since it makes it easier to maintain an 80 line wrap in amdgpu_cs_sync_rings()
Looks good to me, but I would like to see the matching user space code as well. Especially I have no idea how you want to have DRI3 compatibility with that?

No problem. I'm fixing the radv patch atm and I'll re-send it for your reference.

Regards,
Andres

Regards,
Christian.

Regards,
Andres

  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c     | 3 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c    | 4 +++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 8 ++++++++
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c   | 7 +++++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h   | 3 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    | 5 +++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     | 8 ++++----
  include/uapi/drm/amdgpu_drm.h              | 2 ++
  8 files changed, 29 insertions(+), 11 deletions(-)

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +2 -1

index db97e78..bc8a403 100644
@@ -704,7 +704,8 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
      list_for_each_entry(e, &p->validated, tv.head) {
          struct reservation_object *resv = e->robj->tbo.resv;
-        r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
+        r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
+                     amdgpu_bo_explicit_sync(e->robj));
          if (r)
              return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +3 -1

index b0d45c8..21e9936 100644
@@ -212,7 +212,9 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
                AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
                AMDGPU_GEM_CREATE_CPU_GTT_USWC |
                AMDGPU_GEM_CREATE_VRAM_CLEARED |
-              AMDGPU_GEM_CREATE_VM_ALWAYS_VALID))
+              AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
+              AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
+
          return -EINVAL;
      /* reject invalid gem domains */

drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +8 -0

index c26ef53..428aae0 100644
@@ -193,6 +193,14 @@ static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
      }
  }
+/**
+ * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
+ */
+static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
+{
+    return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
+}
+
  int amdgpu_bo_create(struct amdgpu_device *adev,
                  unsigned long size, int byte_align,
                  bool kernel, u32 domain, u64 flags,

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +5 -2

index c586f44..a4bf21f 100644
@@ -169,14 +169,14 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
   *
   * @sync: sync object to add fences from reservation object to
   * @resv: reservation object with embedded fence
- * @shared: true if we should only sync to the exclusive fence
+ * @explicit_sync: true if we should only sync to the exclusive fence
   *
   * Sync to the fence
   */
  int amdgpu_sync_resv(struct amdgpu_device *adev,
               struct amdgpu_sync *sync,
               struct reservation_object *resv,
-             void *owner)
+             void *owner, bool explicit_sync)
  {
      struct reservation_object_list *flist;
      struct dma_fence *f;

@@ -191,6 +191,9 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
      f = reservation_object_get_excl(resv);
      r = amdgpu_sync_fence(adev, sync, f);
+    if (explicit_sync)
+        return r;
+
      flist = reservation_object_get_list(resv);
      if (!flist || r)
          return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h +2 -1

index dc76879..70d7e3a 100644
@@ -45,7 +45,8 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
  int amdgpu_sync_resv(struct amdgpu_device *adev,
               struct amdgpu_sync *sync,
               struct reservation_object *resv,
-             void *owner);
+             void *owner,
+             bool explicit_sync);
  struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
                       struct amdgpu_ring *ring);
  struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +3 -2

index c9c059d..bd0b03a 100644
@@ -1510,7 +1510,8 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
      job->vm_needs_flush = vm_needs_flush;
      if (resv) {
          r = amdgpu_sync_resv(adev, &job->sync, resv,
-                     AMDGPU_FENCE_OWNER_UNDEFINED);
+                     AMDGPU_FENCE_OWNER_UNDEFINED,
+                     false);
          if (r) {
              DRM_ERROR("sync failed (%d).\n", r);
              goto error_free;

@@ -1602,7 +1603,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
      if (resv) {
          r = amdgpu_sync_resv(adev, &job->sync, resv,
-                     AMDGPU_FENCE_OWNER_UNDEFINED);
+                     AMDGPU_FENCE_OWNER_UNDEFINED, false);
          if (r) {
              DRM_ERROR("sync failed (%d).\n", r);
              goto error_free;

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +4 -4

index 2df254c..9965d68 100644
@@ -987,7 +987,7 @@ static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
      int r;
      amdgpu_sync_create(&sync);
-    amdgpu_sync_resv(adev, &sync, vm->root.base.bo<http://root.base.bo>->tbo.resv, owner);
+    amdgpu_sync_resv(adev, &sync, vm->root.base.bo<http://root.base.bo>->tbo.resv, owner, false);
      r = amdgpu_sync_wait(&sync, true);
      amdgpu_sync_free(&sync);

@@ -1128,11 +1128,11 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev,
              amdgpu_ring_pad_ib(ring, params.ib);
              amdgpu_sync_resv(adev, &job->sync,
                       parent->base.bo<http://base.bo>->tbo.resv,
-                     AMDGPU_FENCE_OWNER_VM);
+                     AMDGPU_FENCE_OWNER_VM, false);
              if (shadow)
                  amdgpu_sync_resv(adev, &job->sync,
                           shadow->tbo.resv,
-                         AMDGPU_FENCE_OWNER_VM);
+                         AMDGPU_FENCE_OWNER_VM, false);
              WARN_ON(params.ib->length_dw > ndw);
              r = amdgpu_job_submit(job, ring, &vm->entity,

@@ -1595,7 +1595,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
          goto error_free;
      r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo<http://root.base.bo>->tbo.resv,
-                 owner);
+                 owner, false);
      if (r)
          goto error_free;

include/uapi/drm/amdgpu_drm.h +2 -0

index 69d64e5..96fcde8 100644
@@ -91,6 +91,8 @@ extern "C" {
  #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS    (1 << 5)
  /* Flag that BO is always valid in this VM */
  #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID    (1 << 6)
+/* Flag that BO sharing will be explicitly synchronized */
+#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC        (1 << 7)
  struct drm_amdgpu_gem_create_in  {
      /** the requested memory size */

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A message that is not in the archive (sent off-list or not yet received): C3B2D770-2630-497A-B73F-231993566023-5C7GfCeVMHo@public.gmane.org

Andres Rodriguez

author

2017-09-19 14:11 UTC #8 lore raw

Correct.

The idea is to only set AMDGPU_GEM_CREATE_EXPLICIT_SYNC for buffers that are not associated with dri2/3 or PRIME.

Regards,
Andres

Quoted 5 lines · David

Hi Andres,
The explicit sync should not be used for DrI3 and DRI2 but for cross process memory sharing, right? We still have to rely on implicit sync to guarantee the. Correct order of rendering and present. Could you confirm?

Quoted 221 lines

Thanks.

Sent from my iPhone

Quoted 215 lines · On 19 Sep 2017, at 9:57 PM, Andres Rodriguez <[email protected]…

Quoted 16 lines · Christian König

Am 19.09.2017 um 14:59 schrieb Andres Rodriguez:
Quoted 15 lines
Introduce a flag to signal that access to a BO will be synchronized through an external mechanism.
Currently all buffers shared between contexts are subject to implicit synchronization. However, this is only required for protocols that currently don't support an explicit synchronization mechanism (DRI2/3).
This patch introduces the AMDGPU_GEM_CREATE_EXPLICIT_SYNC, so that users can specify when it is safe to disable implicit sync.
v2: only disable explicit sync in amdgpu_cs_ioctl
Signed-off-by Andres Rodriguez <[email protected] <mailto:[email protected]>>
---

Quoted 6 lines

Quoted 4 lines
Hey Christian,
I kept the amdgpu_bo_explicit_sync() function since it makes it easier to maintain an 80 line wrap in amdgpu_cs_sync_rings()
Looks good to me, but I would like to see the matching user space code as well. Especially I have no idea how you want to have DRI3 compatibility with that?

No problem. I'm fixing the radv patch atm and I'll re-send it for your reference.

Regards,
Andres

Quoted 172 lines

Regards,
Christian.

Quoted 170 lines

Regards,
Andres

  8 files changed, 29 insertions(+), 11 deletions(-)

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +2 -1

index db97e78..bc8a403 100644
@@ -704,7 +704,8 @@ static int amdgpu_cs_sync_rings(struct 
 amdgpu_cs_parser *p)
       list_for_each_entry(e, &p->validated, tv.head) {
           struct reservation_object *resv = e->robj->tbo.resv;
-        r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
+        r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
+                     amdgpu_bo_explicit_sync(e->robj));
           if (r)
               return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +0 -0

index b0d45c8..21e9936 100644
@@ -212,7 +212,9 @@ int amdgpu_gem_create_ioctl(struct drm_device 
 *dev, void *data,

drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +8 -0

index c26ef53..428aae0 100644
@@ -193,6 +193,14 @@ static inline bool 
 amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
       }
   }
+/**
+ * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
+ */
+static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
+{
+    return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
+}
+
   int amdgpu_bo_create(struct amdgpu_device *adev,
                   unsigned long size, int byte_align,
                   bool kernel, u32 domain, u64 flags,

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +2 -2

index c586f44..a4bf21f 100644
@@ -169,14 +169,14 @@ int amdgpu_sync_fence(struct amdgpu_device 
 *adev, struct amdgpu_sync *sync,
    *
    * @sync: sync object to add fences from reservation object to
    * @resv: reservation object with embedded fence
- * @shared: true if we should only sync to the exclusive fence
+ * @explicit_sync: true if we should only sync to the exclusive fence
    *
    * Sync to the fence
    */
   int amdgpu_sync_resv(struct amdgpu_device *adev,
                struct amdgpu_sync *sync,
                struct reservation_object *resv,
-             void *owner)
+             void *owner, bool explicit_sync)
   {
       struct reservation_object_list *flist;

struct dma_fence *f;

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +3 -0

@@ -191,6 +191,9 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
       f = reservation_object_get_excl(resv);
       r = amdgpu_sync_fence(adev, sync, f);
+    if (explicit_sync)
+        return r;
+
       flist = reservation_object_get_list(resv);
       if (!flist || r)
           return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h +2 -1

index dc76879..70d7e3a 100644
@@ -45,7 +45,8 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, 
 struct amdgpu_sync *sync,
   int amdgpu_sync_resv(struct amdgpu_device *adev,
                struct amdgpu_sync *sync,
                struct reservation_object *resv,
-             void *owner);
+             void *owner,
+             bool explicit_sync);
   struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
                        struct amdgpu_ring *ring);

struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +2 -1

index c9c059d..bd0b03a 100644
@@ -1510,7 +1510,8 @@ int amdgpu_copy_buffer(struct amdgpu_ring 
 *ring, uint64_t src_offset,
       job->vm_needs_flush = vm_needs_flush;
       if (resv) {
           r = amdgpu_sync_resv(adev, &job->sync, resv,
-                     AMDGPU_FENCE_OWNER_UNDEFINED);
+                     AMDGPU_FENCE_OWNER_UNDEFINED,
+                     false);
           if (r) {
               DRM_ERROR("sync failed (%d).\n", r);

goto error_free;

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +1 -1

@@ -1602,7 +1603,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
       if (resv) {
           r = amdgpu_sync_resv(adev, &job->sync, resv,
-                     AMDGPU_FENCE_OWNER_UNDEFINED);
+                     AMDGPU_FENCE_OWNER_UNDEFINED, false);
           if (r) {
               DRM_ERROR("sync failed (%d).\n", r);
               goto error_free;

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +1 -1

index 2df254c..9965d68 100644
@@ -987,7 +987,7 @@ static int amdgpu_vm_wait_pd(struct 
 amdgpu_device *adev, struct amdgpu_vm *vm,
       int r;
       amdgpu_sync_create(&sync);
-    amdgpu_sync_resv(adev, &sync, vm->root.base.bo 
 <http://root.base.bo>->tbo.resv, owner);
+    amdgpu_sync_resv(adev, &sync, vm->root.base.bo 
 <http://root.base.bo>->tbo.resv, owner, false);
       r = amdgpu_sync_wait(&sync, true);

amdgpu_sync_free(&sync);

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +3 -3

@@ -1128,11 +1128,11 @@ static int amdgpu_vm_update_level(struct 
 amdgpu_device *adev,
               amdgpu_ring_pad_ib(ring, params.ib);
               amdgpu_sync_resv(adev, &job->sync,
                        parent->base.bo <http://base.bo>->tbo.resv,
-                     AMDGPU_FENCE_OWNER_VM);
+                     AMDGPU_FENCE_OWNER_VM, false);
               if (shadow)
                   amdgpu_sync_resv(adev, &job->sync,
                            shadow->tbo.resv,
-                         AMDGPU_FENCE_OWNER_VM);
+                         AMDGPU_FENCE_OWNER_VM, false);
               WARN_ON(params.ib->length_dw > ndw);
               r = amdgpu_job_submit(job, ring, &vm->entity,

@@ -1595,7 +1595,7 @@ static int amdgpu_vm_bo_update_mapping(struct 
 amdgpu_device *adev,
           goto error_free;
       r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo <http://root.base.bo>->tbo.resv,
-                 owner);
+                 owner, false);
       if (r)
           goto error_free;

include/uapi/drm/amdgpu_drm.h +0 -0

index 69d64e5..96fcde8 100644

Quoted 8 lines

include/uapi/drm/amdgpu_drm.h extern "C" { · line 97

Quoted 8 lines

include/uapi/drm/amdgpu_drm.h +2 -0

@@ -91,6 +91,8 @@ extern "C" {
   #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS    (1 << 5)
   /* Flag that BO is always valid in this VM */
   #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID    (1 << 6)
+/* Flag that BO sharing will be explicitly synchronized */
+#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC        (1 << 7)
   struct drm_amdgpu_gem_create_in  {
       /** the requested memory size */

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Andres Rodriguez

author

2017-09-21 14:38 UTC #9 lore raw

In reply to a message not in the archive

Hi Christian,

The reference radv patches are on the list. The basic idea is to only set the explicit sync flag for buffers allocated for dri usage.

Regards,
Andres

Quoted 197 lines · Christian König

Am 19.09.2017 um 14:59 schrieb Andres Rodriguez:

Quoted 12 lines

Introduce a flag to signal that access to a BO will be synchronized through an external mechanism.
Currently all buffers shared between contexts are subject to implicit synchronization. However, this is only required for protocols that currently don't support an explicit synchronization mechanism (DRI2/3).
This patch introduces the AMDGPU_GEM_CREATE_EXPLICIT_SYNC, so that users can specify when it is safe to disable implicit sync.
v2: only disable explicit sync in amdgpu_cs_ioctl

Quoted 7 lines

Signed-off-by Andres Rodriguez <[email protected]>
---
Hey Christian,
I kept the amdgpu_bo_explicit_sync() function since it makes it easier to maintain an 80 line wrap in amdgpu_cs_sync_rings()

Looks good to me, but I would like to see the matching user space code as well.

Especially I have no idea how you want to have DRI3 compatibility with that?

Regards,
Christian.

Quoted 169 lines

Regards,
Andres

  8 files changed, 29 insertions(+), 11 deletions(-)

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +2 -1

index db97e78..bc8a403 100644
@@ -704,7 +704,8 @@ static int amdgpu_cs_sync_rings(struct 
 amdgpu_cs_parser *p)
       list_for_each_entry(e, &p->validated, tv.head) {
           struct reservation_object *resv = e->robj->tbo.resv;
-        r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
+        r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
+                     amdgpu_bo_explicit_sync(e->robj));
           if (r)
               return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +0 -0

index b0d45c8..21e9936 100644
@@ -212,7 +212,9 @@ int amdgpu_gem_create_ioctl(struct drm_device 
 *dev, void *data,

drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +8 -0

index c26ef53..428aae0 100644
@@ -193,6 +193,14 @@ static inline bool 
 amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
       }
   }
+/**
+ * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
+ */
+static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
+{
+    return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
+}
+
   int amdgpu_bo_create(struct amdgpu_device *adev,
                   unsigned long size, int byte_align,
                   bool kernel, u32 domain, u64 flags,

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +2 -2

index c586f44..a4bf21f 100644
@@ -169,14 +169,14 @@ int amdgpu_sync_fence(struct amdgpu_device 
 *adev, struct amdgpu_sync *sync,
    *
    * @sync: sync object to add fences from reservation object to
    * @resv: reservation object with embedded fence
- * @shared: true if we should only sync to the exclusive fence
+ * @explicit_sync: true if we should only sync to the exclusive fence
    *
    * Sync to the fence
    */
   int amdgpu_sync_resv(struct amdgpu_device *adev,
                struct amdgpu_sync *sync,
                struct reservation_object *resv,
-             void *owner)
+             void *owner, bool explicit_sync)
   {
       struct reservation_object_list *flist;

struct dma_fence *f;

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +3 -0

@@ -191,6 +191,9 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
       f = reservation_object_get_excl(resv);
       r = amdgpu_sync_fence(adev, sync, f);
+    if (explicit_sync)
+        return r;
+
       flist = reservation_object_get_list(resv);
       if (!flist || r)
           return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h +2 -1

index dc76879..70d7e3a 100644
@@ -45,7 +45,8 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, 
 struct amdgpu_sync *sync,
   int amdgpu_sync_resv(struct amdgpu_device *adev,
                struct amdgpu_sync *sync,
                struct reservation_object *resv,
-             void *owner);
+             void *owner,
+             bool explicit_sync);
   struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
                        struct amdgpu_ring *ring);

struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +2 -1

index c9c059d..bd0b03a 100644
@@ -1510,7 +1510,8 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, 
 uint64_t src_offset,
       job->vm_needs_flush = vm_needs_flush;
       if (resv) {
           r = amdgpu_sync_resv(adev, &job->sync, resv,
-                     AMDGPU_FENCE_OWNER_UNDEFINED);
+                     AMDGPU_FENCE_OWNER_UNDEFINED,
+                     false);
           if (r) {
               DRM_ERROR("sync failed (%d).\n", r);

goto error_free;

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +1 -1

@@ -1602,7 +1603,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
       if (resv) {
           r = amdgpu_sync_resv(adev, &job->sync, resv,
-                     AMDGPU_FENCE_OWNER_UNDEFINED);
+                     AMDGPU_FENCE_OWNER_UNDEFINED, false);
           if (r) {
               DRM_ERROR("sync failed (%d).\n", r);
               goto error_free;

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +4 -4

index 2df254c..9965d68 100644
@@ -987,7 +987,7 @@ static int amdgpu_vm_wait_pd(struct amdgpu_device 
 *adev, struct amdgpu_vm *vm,
       int r;
       amdgpu_sync_create(&sync);
-    amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner);
+    amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, 
 false);
       r = amdgpu_sync_wait(&sync, true);
       amdgpu_sync_free(&sync);

@@ -1128,11 +1128,11 @@ static int amdgpu_vm_update_level(struct 
 amdgpu_device *adev,
               amdgpu_ring_pad_ib(ring, params.ib);
               amdgpu_sync_resv(adev, &job->sync,
                        parent->base.bo->tbo.resv,
-                     AMDGPU_FENCE_OWNER_VM);
+                     AMDGPU_FENCE_OWNER_VM, false);
               if (shadow)
                   amdgpu_sync_resv(adev, &job->sync,
                            shadow->tbo.resv,
-                         AMDGPU_FENCE_OWNER_VM);
+                         AMDGPU_FENCE_OWNER_VM, false);
               WARN_ON(params.ib->length_dw > ndw);
               r = amdgpu_job_submit(job, ring, &vm->entity,

@@ -1595,7 +1595,7 @@ static int amdgpu_vm_bo_update_mapping(struct 
 amdgpu_device *adev,
           goto error_free;
       r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
-                 owner);
+                 owner, false);
       if (r)
           goto error_free;

include/uapi/drm/amdgpu_drm.h +0 -0

index 69d64e5..96fcde8 100644

Quoted 10 lines

include/uapi/drm/amdgpu_drm.h extern "C" { · line 97

Quoted 8 lines

include/uapi/drm/amdgpu_drm.h +2 -0

@@ -91,6 +91,8 @@ extern "C" {
   #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS    (1 << 5)
   /* Flag that BO is always valid in this VM */
   #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID    (1 << 6)
+/* Flag that BO sharing will be explicitly synchronized */
+#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC        (1 << 7)
   struct drm_amdgpu_gem_create_in  {
       /** the requested memory size */

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A message that is not in the archive (sent off-list or not yet received): 23e71499-cd99-7016-fb8e-a7029dadee51-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org

Christian König

2017-09-21 18:14 UTC #11 lore raw

Patch is Reviewed-by: Christian König <[email protected]>.

Regards,
Christian.

Am 21.09.2017 um 16:38 schrieb Andres Rodriguez:

Quoted 217 lines

Hi Christian,

The reference radv patches are on the list. The basic idea is to only set the explicit sync flag for buffers allocated for dri usage.

Regards,
Andres

Quoted 199 lines · Christian König

Am 19.09.2017 um 14:59 schrieb Andres Rodriguez:

Quoted 12 lines

Introduce a flag to signal that access to a BO will be synchronized through an external mechanism.
Currently all buffers shared between contexts are subject to implicit synchronization. However, this is only required for protocols that currently don't support an explicit synchronization mechanism (DRI2/3).
This patch introduces the AMDGPU_GEM_CREATE_EXPLICIT_SYNC, so that users can specify when it is safe to disable implicit sync.
v2: only disable explicit sync in amdgpu_cs_ioctl

Quoted 7 lines

Signed-off-by Andres Rodriguez <[email protected]>
---
Hey Christian,
I kept the amdgpu_bo_explicit_sync() function since it makes it easier to maintain an 80 line wrap in amdgpu_cs_sync_rings()

Looks good to me, but I would like to see the matching user space code as well.

Especially I have no idea how you want to have DRI3 compatibility with that?

Regards,
Christian.

Quoted 171 lines

Regards,
Andres

  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c     | 3 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c    | 4 +++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 8 ++++++++
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c   | 7 +++++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h   | 3 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    | 5 +++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     | 8 ++++----
  include/uapi/drm/amdgpu_drm.h              | 2 ++
  8 files changed, 29 insertions(+), 11 deletions(-)

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +2 -1

index db97e78..bc8a403 100644
@@ -704,7 +704,8 @@ static int amdgpu_cs_sync_rings(struct 
 amdgpu_cs_parser *p)
      list_for_each_entry(e, &p->validated, tv.head) {
          struct reservation_object *resv = e->robj->tbo.resv;
-        r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
+        r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
+                     amdgpu_bo_explicit_sync(e->robj));
          if (r)
              return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +3 -1

index b0d45c8..21e9936 100644
@@ -212,7 +212,9 @@ int amdgpu_gem_create_ioctl(struct drm_device 
 *dev, void *data,
                AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
                AMDGPU_GEM_CREATE_CPU_GTT_USWC |
                AMDGPU_GEM_CREATE_VRAM_CLEARED |
-              AMDGPU_GEM_CREATE_VM_ALWAYS_VALID))
+              AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
+              AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
+
          return -EINVAL;
      /* reject invalid gem domains */

drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +2 -0

index c26ef53..428aae0 100644
@@ -193,6 +193,14 @@ static inline bool 
 amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
      }
  }
+/**
+ * amdgpu_bo_explicit_sync - return whether the bo is explicitly

synced
+ */

drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +5 -0

+static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
+{
+    return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
+}
+
  int amdgpu_bo_create(struct amdgpu_device *adev,
                  unsigned long size, int byte_align,
                  bool kernel, u32 domain, u64 flags,

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +2 -2

index c586f44..a4bf21f 100644
@@ -169,14 +169,14 @@ int amdgpu_sync_fence(struct amdgpu_device 
 *adev, struct amdgpu_sync *sync,
   *
   * @sync: sync object to add fences from reservation object to
   * @resv: reservation object with embedded fence
- * @shared: true if we should only sync to the exclusive fence
+ * @explicit_sync: true if we should only sync to the exclusive fence
   *
   * Sync to the fence
   */
  int amdgpu_sync_resv(struct amdgpu_device *adev,
               struct amdgpu_sync *sync,
               struct reservation_object *resv,
-             void *owner)
+             void *owner, bool explicit_sync)
  {
      struct reservation_object_list *flist;

      struct dma_fence *f;

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +3 -0

@@ -191,6 +191,9 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
      f = reservation_object_get_excl(resv);
      r = amdgpu_sync_fence(adev, sync, f);
+    if (explicit_sync)
+        return r;
+
      flist = reservation_object_get_list(resv);
      if (!flist || r)
          return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h +2 -1

index dc76879..70d7e3a 100644
@@ -45,7 +45,8 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, 
 struct amdgpu_sync *sync,
  int amdgpu_sync_resv(struct amdgpu_device *adev,
               struct amdgpu_sync *sync,
               struct reservation_object *resv,
-             void *owner);
+             void *owner,
+             bool explicit_sync);
  struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
                       struct amdgpu_ring *ring);

  struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +2 -1

index c9c059d..bd0b03a 100644
@@ -1510,7 +1510,8 @@ int amdgpu_copy_buffer(struct amdgpu_ring 
 *ring, uint64_t src_offset,
      job->vm_needs_flush = vm_needs_flush;
      if (resv) {
          r = amdgpu_sync_resv(adev, &job->sync, resv,
-                     AMDGPU_FENCE_OWNER_UNDEFINED);
+                     AMDGPU_FENCE_OWNER_UNDEFINED,
+                     false);
          if (r) {
              DRM_ERROR("sync failed (%d).\n", r);

              goto error_free;

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +1 -1

@@ -1602,7 +1603,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
      if (resv) {
          r = amdgpu_sync_resv(adev, &job->sync, resv,
-                     AMDGPU_FENCE_OWNER_UNDEFINED);
+                     AMDGPU_FENCE_OWNER_UNDEFINED, false);
          if (r) {
              DRM_ERROR("sync failed (%d).\n", r);
              goto error_free;

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +4 -4

index 2df254c..9965d68 100644
@@ -987,7 +987,7 @@ static int amdgpu_vm_wait_pd(struct 
 amdgpu_device *adev, struct amdgpu_vm *vm,
      int r;
      amdgpu_sync_create(&sync);
-    amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner);
+    amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, 
 owner, false);
      r = amdgpu_sync_wait(&sync, true);
      amdgpu_sync_free(&sync);

@@ -1128,11 +1128,11 @@ static int amdgpu_vm_update_level(struct 
 amdgpu_device *adev,
              amdgpu_ring_pad_ib(ring, params.ib);
              amdgpu_sync_resv(adev, &job->sync,
                       parent->base.bo->tbo.resv,
-                     AMDGPU_FENCE_OWNER_VM);
+                     AMDGPU_FENCE_OWNER_VM, false);
              if (shadow)
                  amdgpu_sync_resv(adev, &job->sync,
                           shadow->tbo.resv,
-                         AMDGPU_FENCE_OWNER_VM);
+                         AMDGPU_FENCE_OWNER_VM, false);
              WARN_ON(params.ib->length_dw > ndw);
              r = amdgpu_job_submit(job, ring, &vm->entity,

@@ -1595,7 +1595,7 @@ static int amdgpu_vm_bo_update_mapping(struct 
 amdgpu_device *adev,
          goto error_free;
      r = amdgpu_sync_resv(adev, &job->sync, 
 vm->root.base.bo->tbo.resv,
-                 owner);
+                 owner, false);
      if (r)
          goto error_free;

include/uapi/drm/amdgpu_drm.h +0 -0

index 69d64e5..96fcde8 100644

Quoted 10 lines

include/uapi/drm/amdgpu_drm.h extern "C" { · line 97

Quoted 8 lines

include/uapi/drm/amdgpu_drm.h +2 -0

@@ -91,6 +91,8 @@ extern "C" {
  #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS    (1 << 5)
  /* Flag that BO is always valid in this VM */
  #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID    (1 << 6)
+/* Flag that BO sharing will be explicitly synchronized */
+#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC        (1 << 7)
  struct drm_amdgpu_gem_create_in  {
      /** the requested memory size */

Quoted 4 lines

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Marek Olšák

2017-10-12 18:27 UTC #12 lore raw

In reply to a message not in the archive

Quoted 4 lines · Andres Rodriguez

Hi Christian,
The reference radv patches are on the list. The basic idea is to only set the explicit sync flag for buffers allocated for dri usage.

Did you mean "only set the explicit sync flag for buffers NOT allocated for dri usage"?

Marek
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Christian König

2017-10-12 18:30 UTC #14 lore raw

Am 12.10.2017 um 20:27 schrieb Marek Olšák:

Quoted 7 lines · Andres Rodriguez

Quoted 4 lines
Hi Christian,
The reference radv patches are on the list. The basic idea is to only set the explicit sync flag for buffers allocated for dri usage.
Did you mean "only set the explicit sync flag for buffers NOT allocated for dri usage"?

I really hope so, cause otherwise that wouldn't be backward compatible.

But the name indicates that no implicit sync is requested any more, so I think he got that right.

Christian.

Quoted 2 lines

Marek

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Andres Rodriguez

author

2017-10-12 18:31 UTC #15 lore raw

In reply to a message not in the archive

Quoted 9 lines · Marek Olšák

Quoted 4 lines · Andres Rodriguez
Hi Christian,
The reference radv patches are on the list. The basic idea is to only set the explicit sync flag for buffers allocated for dri usage.
Did you mean "only set the explicit sync flag for buffers NOT allocated for dri usage"?

Yes, thanks for the correction. The dri buffers use implicit sync, the rest of the buffers use explicit sync.

Regards,
Andres

Quoted 2 lines

Marek

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