huge gtt pages
Subsystems (4)
cover huge gtt pages
Bunch of changes all round, mostly in the kselftest department, of note we drop support for 1G pages for the time being, since testing has proven to be a pita, and instead focus on getting the 64K and 2M support landed.
Matthew Auld (21):
mm/shmem: introduce shmem_file_setup_with_mnt drm/i915: introduce simple gemfs
drm/i915/gemfs: enable THP
drm/i915: introduce page_sizes field to dev_info drm/i915: push set_pages down to the callers drm/i915: introduce page_size members
drm/i915: introduce vm set_pages/clear_pages drm/i915: align the vma start to the largest gtt page size drm/i915: align 64K objects to 2M
drm/i915: enable IPS bit for 64K pages
drm/i915: disable GTT cache for 2M pages drm/i915: support 2M pages for the 48b PPGTT drm/i915: add support for 64K scratch page drm/i915: support 64K pages for the 48b PPGTT drm/i915: accurate page size tracking for the ppgtt drm/i915/debugfs: include some gtt page size metrics drm/i915/selftests: huge page tests drm/i915/selftests: mix huge pages
drm/i915: disable platform support for vGPU huge gtt pages drm/i915: enable platform support for 64K pages drm/i915: enable platform support for 2M pages
drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 61 +- drivers/gpu/drm/i915/i915_drv.h | 11 +- drivers/gpu/drm/i915/i915_gem.c | 137 +- drivers/gpu/drm/i915/i915_gem_dmabuf.c | 22 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 257 ++- drivers/gpu/drm/i915/i915_gem_gtt.h | 19 +- drivers/gpu/drm/i915/i915_gem_internal.c | 18 +- drivers/gpu/drm/i915/i915_gem_object.h | 31 +- drivers/gpu/drm/i915/i915_gem_stolen.c | 16 +- drivers/gpu/drm/i915/i915_gem_userptr.c | 19 +- drivers/gpu/drm/i915/i915_gemfs.c | 66 + drivers/gpu/drm/i915/i915_gemfs.h | 34 + drivers/gpu/drm/i915/i915_pci.c | 23 + drivers/gpu/drm/i915/i915_reg.h | 3 + drivers/gpu/drm/i915/i915_vma.c | 47 +- drivers/gpu/drm/i915/i915_vma.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 8 +- drivers/gpu/drm/i915/selftests/huge_gem_object.c | 14 +- drivers/gpu/drm/i915/selftests/huge_pages.c | 1636 ++++++++++++++++++++ drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 15 +- .../gpu/drm/i915/selftests/i915_live_selftests.h | 1 + .../gpu/drm/i915/selftests/i915_mock_selftests.h | 1 + drivers/gpu/drm/i915/selftests/mock_gem_device.c | 9 + drivers/gpu/drm/i915/selftests/mock_gtt.c | 11 +- drivers/gpu/drm/i915/selftests/scatterlist.c | 15 + include/linux/shmem_fs.h | 2 + mm/shmem.c | 30 +- 28 files changed, 2374 insertions(+), 134 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_gemfs.c create mode 100644 drivers/gpu/drm/i915/i915_gemfs.h create mode 100644 drivers/gpu/drm/i915/selftests/huge_pages.c
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2.13.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 1/21 mm/shmem: introduce shmem_file_setup_with_mnt
We are planning to use our own tmpfs mnt in i915 in place of the shm_mnt, such that we can control the mount options, in particular huge=, which we require to support huge-gtt-pages. So rather than roll our own version of __shmem_file_setup, it would be preferred if we could just give shmem our mnt, and let it do the rest.
--- include/linux/shmem_fs.h | 2 ++ mm/shmem.c | 30 ++++++++++++++++++++++-------- 2 files changed, 24 insertions(+), 8 deletions(-)
include/linux/shmem_fs.h +2 -0
@@ -53,6 +53,8 @@ extern struct file *shmem_file_setup(const char *name, loff_t size, unsigned long flags);extern struct file *shmem_kernel_file_setup (const char *name,loff_t size,unsigned long flags); +extern struct file *shmem_file_setup_with_mnt (struct vfsmount *mnt, +const char *name,loff_t size,unsigned long flags);extern int shmem_zero_setup (struct vm_area_struct *);extern unsigned long shmem_get_unmapped_area (struct file *,unsigned long addr,unsigned long len,unsigned long pgoff,unsigned long flags);
mm/shmem.c +22 -8
@@ -4183,7 +4183,7 @@ static const struct dentry_operations anon_ops = { .d_dname = simple_dname }; -static struct file *__shmem_file_setup (const char *name,loff_t size, +static struct file *__shmem_file_setup (struct vfsmount *mnt,const char *name,loff_t size,unsigned long flags,unsigned int i_flags) {struct file *res;
@@ -4192,8 +4192,8 @@ static struct file *__shmem_file_setup(const char *name, loff_t size,struct super_block *sb;struct qstr this; -if (IS_ERR (shm_mnt)) -return ERR_CAST (shm_mnt); +if (IS_ERR (mnt)) +return ERR_CAST (mnt);if (size <0 || size >MAX_LFS_FILESIZE )return ERR_PTR (-EINVAL );
@@ -4205,8 +4205,8 @@ static struct file *__shmem_file_setup(const char *name, loff_t size, this.name = name; this.len =strlen (name); this.hash =0 ;/* will go */ - sb = shm_mnt->mnt_sb; - path.mnt =mntget (shm_mnt); + sb = mnt->mnt_sb; + path.mnt =mntget (mnt); path.dentry =d_alloc_pseudo (sb, &this);if (!path.dentry) goto put_memory;
@@ -4251,7 +4251,7 @@ static struct file *__shmem_file_setup(const char *name, loff_t size,*/ struct file *shmem_kernel_file_setup (const char *name,loff_t size,unsigned long flags) { -return __shmem_file_setup (name, size, flags,S_PRIVATE ); +return __shmem_file_setup (shm_mnt, name, size, flags,S_PRIVATE ); }/**
@@ -4262,11 +4262,25 @@ struct file *shmem_kernel_file_setup(const char *name, loff_t size, unsigned lon*/ struct file *shmem_file_setup (const char *name,loff_t size,unsigned long flags) { -return __shmem_file_setup (name, size, flags,0 ); +return __shmem_file_setup (shm_mnt, name, size, flags,0 ); }EXPORT_SYMBOL_GPL (shmem_file_setup);/** +* shmem_file_setup_with_mnt - get an unlinked file living in tmpfs +* @mnt: the tmpfs mount where the file will be created +* @name: name for dentry (to be seen in /proc/<pid>/maps +* @size: size to be set for the file +* @flags: VM_NORESERVE suppresses pre-accounting of the entire object size +*/ +struct file *shmem_file_setup_with_mnt (struct vfsmount *mnt,const char *name, +loff_t size,unsigned long flags) +{ +return __shmem_file_setup (mnt, name, size, flags,0 ); +} +EXPORT_SYMBOL_GPL (shmem_file_setup_with_mnt); + +/** * shmem_zero_setup - setup a shared anonymous mapping * @vma: the vma to be mmapped is prepared by do_mmap_pgoff */
@@ -4281,7 +4295,7 @@ int shmem_zero_setup(struct vm_area_struct *vma)* accessible to the user through its mapping, use S_PRIVATE flag to * bypass file security, in the same way as shmem_kernel_file_setup(). */ - file =__shmem_file_setup ("dev/zero" , size, vma->vm_flags,S_PRIVATE ); + file =shmem_kernel_file_setup ("dev/zero" , size, vma->vm_flags);if (IS_ERR (file))return PTR_ERR (file);
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PATCH 2/21 drm/i915: introduce simple gemfs
In reply to Matthew AuldNot a fully blown gemfs, just our very own tmpfs kernel mount. Doing so moves us away from the shmemfs shm_mnt, and gives us the much needed flexibility to do things like set our own mount options, namely huge= which should allow us to enable the use of transparent-huge-pages for our shmem backed objects.
v2: various improvements suggested by Joonas
v3: move gemfs instance to i915.mm and simplify now that we have file_setup_with_mnt
v4: fallback to tmpfs shm_mnt upon failure to setup gemfs
--- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_drv.h | 5 +++ drivers/gpu/drm/i915/i915_gem.c | 30 +++++++++++++- drivers/gpu/drm/i915/i915_gemfs.c | 52 ++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_gemfs.h | 34 ++++++++++++++++ drivers/gpu/drm/i915/selftests/mock_gem_device.c | 4 ++ 6 files changed, 125 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/i915_gemfs.c create mode 100644 drivers/gpu/drm/i915/i915_gemfs.h
drivers/gpu/drm/i915/Makefile +1 -0
@@ -47,6 +47,7 @@ i915-y += i915_cmd_parser.o \ i915_gem_tiling.o \ i915_gem_timeline.o \ i915_gem_userptr.o \ + i915_gemfs.o \ i915_trace_points.o \ i915_vma.o \ intel_breadcrumbs.o \
drivers/gpu/drm/i915/i915_drv.h +5 -0
@@ -1500,6 +1500,11 @@ struct i915_gem_mm {/** Usable portion of the GTT for GEM */ dma_addr_t stolen_base;/* limited to low memory (32-bit) */ +/** +* tmpfs instance used for shmem backed objects +*/ +struct vfsmount *gemfs; +/** PPGTT used for aliasing the PPGTT with the GTT */ struct i915_hw_ppgtt *aliasing_ppgtt;
drivers/gpu/drm/i915/i915_gem.c +29 -1
@@ -35,6 +35,7 @@#include "intel_drv.h" #include "intel_frontbuffer.h" #include "intel_mocs.h" +#include "i915_gemfs.h" #include <linux/dma-fence-array.h> #include <linux/kthread.h> #include <linux/reservation.h>
@@ -4251,6 +4252,29 @@ static const struct drm_i915_gem_object_ops i915_gem_object_ops = { .pwrite = i915_gem_object_pwrite_gtt, }; +static int i915_gem_object_create_shmem (struct drm_device *dev, +struct drm_gem_object *obj, +size_t size) +{ +struct drm_i915_private *i915 =to_i915 (dev); +struct file *filp; + +drm_gem_private_object_init (dev, obj, size); + +if (i915->mm.gemfs) + filp =shmem_file_setup_with_mnt (i915->mm.gemfs,"i915" , size, +VM_NORESERVE ); +else + filp =shmem_file_setup ("i915" , size,VM_NORESERVE ); + +if (IS_ERR (filp)) +return PTR_ERR (filp); + + obj->filp = filp; + +return 0 ; +} +struct drm_i915_gem_object *i915_gem_object_create (struct drm_i915_private *dev_priv,u64 size) {
@@ -4275,7 +4299,7 @@ i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)if (obj ==NULL )return ERR_PTR (-ENOMEM ); - ret =drm_gem_object_init (&dev_priv->drm, &obj->base, size); + ret =i915_gem_object_create_shmem (&dev_priv->drm, &obj->base, size);if (ret) goto fail;
@@ -4914,6 +4938,8 @@ i915_gem_load_init(struct drm_i915_private *dev_priv)spin_lock_init (&dev_priv->fb_tracking.lock); +WARN_ON (i915_gemfs_init (dev_priv)); +return 0 ; err_priorities:
@@ -4952,6 +4978,8 @@ void i915_gem_load_cleanup(struct drm_i915_private *dev_priv)/* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */ rcu_barrier (); + +i915_gemfs_fini (dev_priv); }int i915_gem_freeze (struct drm_i915_private *dev_priv)
drivers/gpu/drm/i915/i915_gemfs.c new file +52 -0
52 lines not on this page · raw message
drivers/gpu/drm/i915/i915_gemfs.h new file +34 -0
@@ -0,0 +1,34 @@ +/* +* Copyright © 2017 Intel Corporation +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice (including the next +* paragraph) shall be included in all copies or substantial portions of the +* Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +* IN THE SOFTWARE. +* +*/ + +#ifndef __I915_GEMFS_H__ +#define __I915_GEMFS_H__ + +struct drm_i915_private ; + +int i915_gemfs_init (struct drm_i915_private *i915); + +void i915_gemfs_fini (struct drm_i915_private *i915); + +#endif
drivers/gpu/drm/i915/selftests/mock_gem_device.c +4 -0
@@ -83,6 +83,8 @@ static void mock_device_release(struct drm_device *dev)kmem_cache_destroy (i915->vmas);kmem_cache_destroy (i915->objects); +i915_gemfs_fini (i915); +drm_dev_fini (&i915->drm);put_device (&i915->drm.pdev->dev); }
@@ -239,6 +241,8 @@ struct drm_i915_private *mock_gem_device(void)if (!i915->kernel_context) goto err_engine; +WARN_ON (i915_gemfs_init (i915)); +return i915; err_engine:
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2.13.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 02/21] drm/i915: introduce simple gemfs
Quoting Matthew Auld (2017-09-22 18:32:33)
Quoted 4 lines
drivers/gpu/drm/i915/i915_gem.c +4
-0+static int i915_gem_object_create_shmem (struct drm_device *dev, +struct drm_gem_object *obj, +size_t size) +{
drivers/gpu/drm/i915/i915_gem.c static const struct drm_i915_gem_object_ops i915_gem_object_ops = { · line 4268
Quoted 10 lines
drivers/gpu/drm/i915/i915_gem.c +10
-0+struct drm_i915_private *i915 =to_i915 (dev); +struct file *filp; + +drm_gem_private_object_init (dev, obj, size); + +if (i915->mm.gemfs) + filp =shmem_file_setup_with_mnt (i915->mm.gemfs,"i915" , size, +VM_NORESERVE ); +else + filp =shmem_file_setup ("i915" , size,VM_NORESERVE );
Smells like the shmem_file_setup() is fishy.
This supports my argument that you should just expand shmem_file_setup() to always take the vfsmount, passing #define TMPFS_MNT NULL. -Chris
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Re: [PATCH 02/21] drm/i915: introduce simple gemfs
In reply to Matthew AuldQuoting Matthew Auld (2017-09-22 18:32:33)
drivers/gpu/drm/i915/i915_gem.c i915_gem_load_init(struct drm_i915_private *dev_priv) · line 4941
Quoted 5 lines
drivers/gpu/drm/i915/i915_gem.c +1
-0@@ -4914,6 +4938,8 @@ i915_gem_load_init(struct drm_i915_private *dev_priv)spin_lock_init (&dev_priv->fb_tracking.lock); +WARN_ON (i915_gemfs_init (dev_priv));
Make this kinder, the driver will happily continue without a special gemfs mounting. (For mock, maybe WARN and bail for the tests that need gemfs?)
if (i915_gemfs_init(dev_priv)))
DRM_NOTE("Unable to create a private tmpfs mountpoint, hugepage support will be disabled.\n");-Chris
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PATCH 3/21 drm/i915/gemfs: enable THP
In reply to Matthew AuldEnable transparent-huge-pages through gemfs by mounting with huge=within_size.
--- drivers/gpu/drm/i915/i915_gemfs.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
drivers/gpu/drm/i915/i915_gemfs.c +14 -0
@@ -24,6 +24,7 @@#include <linux/fs.h> #include <linux/mount.h> +#include <linux/pagemap.h> #include "i915_drv.h" #include "i915_gemfs.h"
@@ -41,6 +42,19 @@ int i915_gemfs_init(struct drm_i915_private *i915)if (IS_ERR (gemfs))return PTR_ERR (gemfs); +if (has_transparent_hugepage ()) { +struct super_block *sb = gemfs->mnt_sb; +char options[] ="huge=within_size" ; +int flags =0 ; +int err; + + err = sb->s_op->remount_fs (sb, &flags, options); +if (err) { +kern_unmount (gemfs); +return err; + } + } + i915->mm.gemfs = gemfs;return 0 ;
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2.13.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 4/21 drm/i915: introduce page_sizes field to dev_info
In reply to Matthew AuldIn preparation for huge gtt pages expose page_sizes as part of the device info, to indicate the page sizes supported by the HW. Currently only 4K is supported.
v2: s/page_size_mask/page_sizes/
--- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_gtt.h | 7 ++++++- drivers/gpu/drm/i915/i915_pci.c | 20 ++++++++++++++++++++ drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 +++ 4 files changed, 30 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/i915_drv.h +1 -0
@@ -862,6 +862,7 @@ struct intel_device_info {u8 gt;/* GT number, 0 if undefined */ u8 ring_mask;/* Rings supported by the HW */ u8 num_rings; +unsigned int page_sizes;/* page sizes supported by the HW */ #define DEFINE_FLAG (name) u8 name:1DEV_INFO_FOR_EACH_FLAG (DEFINE_FLAG );#undef DEFINE_FLAG
drivers/gpu/drm/i915/i915_gem_gtt.h +6 -1
@@ -42,7 +42,12 @@#include "i915_gem_request.h" #include "i915_selftest.h" -#define I915_GTT_PAGE_SIZE 4096UL +#define I915_GTT_PAGE_SIZE_4K BIT(12) +#define I915_GTT_PAGE_SIZE_64K BIT(16) +#define I915_GTT_PAGE_SIZE_2M BIT(21) + +#define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K +#define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE#define I915_FENCE_REG_NONE -1
drivers/gpu/drm/i915/i915_pci.c +20 -0
@@ -56,6 +56,10 @@ .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }/* Keep in gen based order, and chronological order within a gen */ + +#define GEN_DEFAULT_PAGE_SIZES \ + .page_sizes = I915_GTT_PAGE_SIZE_4K +#define GEN2_FEATURES \ .gen = 2, .num_pipes = 1, \ .has_overlay = 1, .overlay_needs_physical = 1, \
@@ -65,6 +69,7 @@ .ring_mask = RENDER_RING, \ .has_snoop = true, \ GEN_DEFAULT_PIPEOFFSETS, \ + GEN_DEFAULT_PAGE_SIZES, \ CURSOR_OFFSETS static const struct intel_device_info intel_i830_info __initconst = {
@@ -98,6 +103,7 @@ static const struct intel_device_info intel_i865g_info __initconst = { .ring_mask = RENDER_RING, \ .has_snoop = true, \ GEN_DEFAULT_PIPEOFFSETS, \ + GEN_DEFAULT_PAGE_SIZES, \ CURSOR_OFFSETS static const struct intel_device_info intel_i915g_info __initconst = {
@@ -161,6 +167,7 @@ static const struct intel_device_info intel_pineview_info __initconst = { .ring_mask = RENDER_RING, \ .has_snoop = true, \ GEN_DEFAULT_PIPEOFFSETS, \ + GEN_DEFAULT_PAGE_SIZES, \ CURSOR_OFFSETS static const struct intel_device_info intel_i965g_info __initconst = {
@@ -203,6 +210,7 @@ static const struct intel_device_info intel_gm45_info __initconst = { .ring_mask = RENDER_RING | BSD_RING, \ .has_snoop = true, \ GEN_DEFAULT_PIPEOFFSETS, \ + GEN_DEFAULT_PAGE_SIZES, \ CURSOR_OFFSETS static const struct intel_device_info intel_ironlake_d_info __initconst = {
@@ -226,6 +234,7 @@ static const struct intel_device_info intel_ironlake_m_info __initconst = { .has_rc6p = 1, \ .has_aliasing_ppgtt = 1, \ GEN_DEFAULT_PIPEOFFSETS, \ + GEN_DEFAULT_PAGE_SIZES, \ CURSOR_OFFSETS#define SNB_D_PLATFORM \
@@ -269,6 +278,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info __initconst = .has_aliasing_ppgtt = 1, \ .has_full_ppgtt = 1, \ GEN_DEFAULT_PIPEOFFSETS, \ + GEN_DEFAULT_PAGE_SIZES, \ IVB_CURSOR_OFFSETS#define IVB_D_PLATFORM \
@@ -325,6 +335,7 @@ static const struct intel_device_info intel_valleyview_info __initconst = { .has_snoop = true, .ring_mask = RENDER_RING | BSD_RING | BLT_RING, .display_mmio_offset =VLV_DISPLAY_BASE , +GEN_DEFAULT_PAGE_SIZES ,GEN_DEFAULT_PIPEOFFSETS , CURSOR_OFFSETS };
@@ -363,6 +374,7 @@ static const struct intel_device_info intel_haswell_gt3_info __initconst = {#define BDW_FEATURES \ HSW_FEATURES, \ BDW_COLORS, \ + GEN_DEFAULT_PAGE_SIZES, \ .has_logical_ring_contexts = 1, \ .has_full_48bit_ppgtt = 1, \ .has_64bit_reloc = 1, \
@@ -415,13 +427,18 @@ static const struct intel_device_info intel_cherryview_info __initconst = { .has_reset_engine = 1, .has_snoop = true, .display_mmio_offset =VLV_DISPLAY_BASE , +GEN_DEFAULT_PAGE_SIZES ,GEN_CHV_PIPEOFFSETS ,CURSOR_OFFSETS , CHV_COLORS, }; +#define GEN9_DEFAULT_PAGE_SIZES \ + .page_sizes = I915_GTT_PAGE_SIZE_4K +#define SKL_PLATFORM \ BDW_FEATURES, \ + GEN9_DEFAULT_PAGE_SIZES, \ .gen = 9, \ .platform = INTEL_SKYLAKE, \ .has_csr = 1, \
@@ -477,6 +494,7 @@ static const struct intel_device_info intel_skylake_gt4_info __initconst = { .has_reset_engine = 1, \ .has_snoop = true, \ .has_ipc =1 , \ +GEN9_DEFAULT_PAGE_SIZES , \GEN_DEFAULT_PIPEOFFSETS , \IVB_CURSOR_OFFSETS , \BDW_COLORS
@@ -496,6 +514,7 @@ static const struct intel_device_info intel_geminilake_info __initconst = {#define KBL_PLATFORM \ BDW_FEATURES, \ + GEN9_DEFAULT_PAGE_SIZES, \ .gen = 9, \ .platform = INTEL_KABYLAKE, \ .has_csr = 1, \
@@ -546,6 +565,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info __initconst = {static const struct intel_device_info intel_cannonlake_gt2_info__initconst = {BDW_FEATURES , +GEN9_DEFAULT_PAGE_SIZES , \ .is_alpha_support =1 , .platform =INTEL_CANNONLAKE , .gen =10 ,
drivers/gpu/drm/i915/selftests/mock_gem_device.c +3 -0
@@ -174,6 +174,9 @@ struct drm_i915_private *mock_gem_device(void)mkwrite_device_info (i915)->gen =-1 ; +mkwrite_device_info (i915)->page_sizes = +I915_GTT_PAGE_SIZE_4K ; +spin_lock_init (&i915->mm.object_stat_lock);mock_uncore_init (i915);
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2.13.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 04/21] drm/i915: introduce page_sizes field to dev_info
Quoting Matthew Auld (2017-09-22 18:32:35)
Quoted 23 lines
In preparation for huge gtt pages expose
page_sizesas part of the device info, to indicate the page sizes supported by the HW. Currently only 4K is supported.v2: s/page_size_mask/page_sizes/
Signed-off-by Matthew Auld <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Mika Kuoppala <[email protected]>Cc Chris Wilson <[email protected]>Reviewed-by Joonas Lahtinen <[email protected]>--- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_gtt.h | 7 ++++++- drivers/gpu/drm/i915/i915_pci.c | 20 ++++++++++++++++++++ drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 +++ 4 files changed, 30 insertions(+), 1 deletion(-)drivers/gpu/drm/i915/i915_drv.h +0
-0
drivers/gpu/drm/i915/i915_drv.h struct intel_device_info { · line 865
Quoted 4 lines
drivers/gpu/drm/i915/i915_drv.h +1
-0@@ -862,6 +862,7 @@ struct intel_device_info {u8 gt;/* GT number, 0 if undefined */ u8 ring_mask;/* Rings supported by the HW */ u8 num_rings; +unsigned int page_sizes;/* page sizes supported by the HW */
Is there a naturally aligned spot we can put this? Eh, the struct is a mess.
-Chris
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PATCH 5/21 drm/i915: push set_pages down to the callers
In reply to Matthew AuldEach backend is now responsible for calling __i915_gem_object_set_pages upon successfully gathering its backing storage. This eliminates the inconsistency between the async and sync paths, which stands out even more when we start throwing around an sg_mask in a later patch.
--- drivers/gpu/drm/i915/i915_gem.c | 45 +++++++++++++----------- drivers/gpu/drm/i915/i915_gem_dmabuf.c | 15 +++++--- drivers/gpu/drm/i915/i915_gem_internal.c | 15 ++++---- drivers/gpu/drm/i915/i915_gem_object.h | 2 +- drivers/gpu/drm/i915/i915_gem_stolen.c | 16 ++++++--- drivers/gpu/drm/i915/i915_gem_userptr.c | 12 +++---- drivers/gpu/drm/i915/selftests/huge_gem_object.c | 14 ++++---- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 12 ++++--- 8 files changed, 77 insertions(+), 54 deletions(-)
drivers/gpu/drm/i915/i915_gem.c +24 -21
@@ -162,8 +162,7 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,return 0 ; } -static struct sg_table * -i915_gem_object_get_pages_phys (struct drm_i915_gem_object *obj) +static int i915_gem_object_get_pages_phys (struct drm_i915_gem_object *obj) {struct address_space *mapping = obj->base.filp->f_mapping;drm_dma_handle_t *phys;
@@ -171,9 +170,10 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)struct scatterlist *sg;char *vaddr;int i; +int err;if (WARN_ON (i915_gem_object_needs_bit17_swizzle (obj))) -return ERR_PTR (-EINVAL ); +return -EINVAL ;/* Always aligning to the object size, allows a single allocation * to handle all possible callers, and given typical object sizes,
@@ -183,7 +183,7 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)roundup_pow_of_two (obj->base.size), roundup_pow_of_two(obj->base.size));if (!phys) -return ERR_PTR (-ENOMEM ); +return -ENOMEM ; vaddr = phys->vaddr;for (i =0 ; i < obj->base.size /PAGE_SIZE ; i++) {
@@ -192,7 +192,7 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) page =shmem_read_mapping_page (mapping, i);if (IS_ERR (page)) { - st =ERR_CAST (page); + err =PTR_ERR (page); goto err_phys; }
@@ -209,13 +209,13 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) st =kmalloc (sizeof (*st),GFP_KERNEL );if (!st) { - st =ERR_PTR (-ENOMEM ); + err = -ENOMEM ; goto err_phys; }if (sg_alloc_table (st,1 ,GFP_KERNEL )) {kfree (st); - st =ERR_PTR (-ENOMEM ); + err = -ENOMEM ; goto err_phys; }
@@ -227,11 +227,15 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)sg_dma_len (sg) = obj->base.size; obj->phys_handle = phys; -return st; + +__i915_gem_object_set_pages (obj, st); + +return 0 ; err_phys:drm_pci_free (obj->base.dev, phys); -return st; + +return err; }static void __start_cpu_write (struct drm_i915_gem_object *obj)
@@ -2292,8 +2296,7 @@ static bool i915_sg_trim(struct sg_table *orig_st)return true; } -static struct sg_table * -i915_gem_object_get_pages_gtt (struct drm_i915_gem_object *obj) +static int i915_gem_object_get_pages_gtt (struct drm_i915_gem_object *obj) {struct drm_i915_private *dev_priv =to_i915 (obj->base.dev);const unsigned long page_count = obj->base.size /PAGE_SIZE ;
@@ -2317,12 +2320,12 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) st =kmalloc (sizeof (*st),GFP_KERNEL );if (st ==NULL ) -return ERR_PTR (-ENOMEM ); +return -ENOMEM ; rebuild_st:if (sg_alloc_table (st, page_count,GFP_KERNEL )) {kfree (st); -return ERR_PTR (-ENOMEM ); +return -ENOMEM ; }/* Get the list of pages out of our struct file. They'll be pinned
@@ -2430,7 +2433,9 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)if (i915_gem_object_needs_bit17_swizzle (obj))i915_gem_object_do_bit_17_swizzle (obj, st); -return st; +__i915_gem_object_set_pages (obj, st); + +return 0 ; err_sg:sg_mark_end (sg);
@@ -2451,7 +2456,7 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)if (ret == -ENOSPC ) ret = -ENOMEM ; -return ERR_PTR (ret); +return ret; } void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
@@ -2474,19 +2479,17 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,static int ____i915_gem_object_get_pages (struct drm_i915_gem_object *obj) { -struct sg_table *pages; +int err;if (unlikely (obj->mm.madv !=I915_MADV_WILLNEED )) {DRM_DEBUG ("Attempting to obtain a purgeable object\n" );return -EFAULT ; } - pages = obj->ops->get_pages (obj); -if (unlikely (IS_ERR (pages))) -return PTR_ERR (pages); + err = obj->ops->get_pages (obj); +GEM_BUG_ON (!err &&IS_ERR_OR_NULL (obj->mm.pages)); -__i915_gem_object_set_pages (obj, pages); -return 0 ; +return err; }/* Ensure that the associated pages are gathered from the backing storage
drivers/gpu/drm/i915/i915_gem_dmabuf.c +11 -4
@@ -256,11 +256,18 @@ struct dma_buf *i915_gem_prime_export(struct drm_device *dev,return drm_gem_dmabuf_export (dev, &exp_info); } -static struct sg_table * -i915_gem_object_get_pages_dmabuf (struct drm_i915_gem_object *obj) +static int i915_gem_object_get_pages_dmabuf (struct drm_i915_gem_object *obj) { -return dma_buf_map_attachment (obj->base.import_attach, -DMA_BIDIRECTIONAL ); +struct sg_table *pages; + + pages =dma_buf_map_attachment (obj->base.import_attach, +DMA_BIDIRECTIONAL ); +if (IS_ERR (pages)) +return PTR_ERR (pages); + +__i915_gem_object_set_pages (obj, pages); + +return 0 ; } static void i915_gem_object_put_pages_dmabuf(struct drm_i915_gem_object *obj,
drivers/gpu/drm/i915/i915_gem_internal.c +9 -6
@@ -44,8 +44,7 @@ static void internal_free_pages(struct sg_table *st)kfree (st); } -static struct sg_table * -i915_gem_object_get_pages_internal (struct drm_i915_gem_object *obj) +static int i915_gem_object_get_pages_internal (struct drm_i915_gem_object *obj) {struct drm_i915_private *i915 =to_i915 (obj->base.dev);struct sg_table *st;
@@ -78,12 +77,12 @@ i915_gem_object_get_pages_internal(struct drm_i915_gem_object *obj) create_st: st =kmalloc (sizeof (*st),GFP_KERNEL );if (!st) -return ERR_PTR (-ENOMEM ); +return -ENOMEM ; npages = obj->base.size /PAGE_SIZE ;if (sg_alloc_table (st, npages,GFP_KERNEL )) {kfree (st); -return ERR_PTR (-ENOMEM ); +return -ENOMEM ; } sg = st->sgl;
@@ -132,13 +131,17 @@ i915_gem_object_get_pages_internal(struct drm_i915_gem_object *obj)* object are only valid whilst active and pinned. */ obj->mm.madv =I915_MADV_DONTNEED ; -return st; + +__i915_gem_object_set_pages (obj, st); + +return 0 ; err:sg_set_page (sg,NULL ,0 ,0 );sg_mark_end (sg);internal_free_pages (st); -return ERR_PTR (-ENOMEM ); + +return -ENOMEM ; } static void i915_gem_object_put_pages_internal(struct drm_i915_gem_object *obj,
drivers/gpu/drm/i915/i915_gem_object.h +1 -1
@@ -69,7 +69,7 @@ struct drm_i915_gem_object_ops {* being released or under memory pressure (where we attempt to * reap pages for the shrinker). */ -struct sg_table *(*get_pages)(struct drm_i915_gem_object *); +int (*get_pages)(struct drm_i915_gem_object *);void (*put_pages)(struct drm_i915_gem_object *,struct sg_table *); int (*pwrite)(struct drm_i915_gem_object *,
drivers/gpu/drm/i915/i915_gem_stolen.c +11 -5
@@ -539,12 +539,18 @@ i915_pages_create_for_stolen(struct drm_device *dev,return st; } -static struct sg_table * -i915_gem_object_get_pages_stolen (struct drm_i915_gem_object *obj) +static int i915_gem_object_get_pages_stolen (struct drm_i915_gem_object *obj) { -return i915_pages_create_for_stolen (obj->base.dev, - obj->stolen->start, - obj->stolen->size); +struct sg_table *pages = +i915_pages_create_for_stolen (obj->base.dev, + obj->stolen->start, + obj->stolen->size); +if (IS_ERR (pages)) +return PTR_ERR (pages); + +__i915_gem_object_set_pages (obj, pages); + +return 0 ; } static void i915_gem_object_put_pages_stolen(struct drm_i915_gem_object *obj,
drivers/gpu/drm/i915/i915_gem_userptr.c +6 -6
@@ -434,6 +434,8 @@ __i915_gem_userptr_alloc_pages(struct drm_i915_gem_object *obj,return ERR_PTR (ret); } +__i915_gem_object_set_pages (obj, st); +return st; }
@@ -521,7 +523,6 @@ __i915_gem_userptr_get_pages_worker(struct work_struct *_work) pages =__i915_gem_userptr_alloc_pages (obj, pvec, npages);if (!IS_ERR (pages)) { -__i915_gem_object_set_pages (obj, pages); pinned =0 ; pages =NULL ; }
@@ -582,8 +583,7 @@ __i915_gem_userptr_get_pages_schedule(struct drm_i915_gem_object *obj)return ERR_PTR (-EAGAIN ); } -static struct sg_table * -i915_gem_userptr_get_pages (struct drm_i915_gem_object *obj) +static int i915_gem_userptr_get_pages (struct drm_i915_gem_object *obj) {const int num_pages = obj->base.size >>PAGE_SHIFT ;struct mm_struct *mm = obj->userptr.mm->mm;
@@ -612,9 +612,9 @@ i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj)if (obj->userptr.work) {/* active flag should still be held for the pending work */ if (IS_ERR (obj->userptr.work)) -return ERR_CAST (obj->userptr.work); +return PTR_ERR (obj->userptr.work);else -return ERR_PTR (-EAGAIN ); +return -EAGAIN ; } pvec =NULL ;
@@ -650,7 +650,7 @@ i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj)release_pages (pvec, pinned,0 );kvfree (pvec); -return pages; +return PTR_ERR_OR_ZERO (pages); } static void
drivers/gpu/drm/i915/selftests/huge_gem_object.c +8 -6
@@ -37,8 +37,7 @@ static void huge_free_pages(struct drm_i915_gem_object *obj,kfree (pages); } -static struct sg_table * -huge_get_pages (struct drm_i915_gem_object *obj) +static int huge_get_pages (struct drm_i915_gem_object *obj) {#define GFP (GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY)const unsigned long nreal = obj->scratch /PAGE_SIZE ;
@@ -49,11 +48,11 @@ huge_get_pages(struct drm_i915_gem_object *obj) pages =kmalloc (sizeof (*pages),GFP );if (!pages) -return ERR_PTR (-ENOMEM ); +return -ENOMEM ;if (sg_alloc_table (pages, npages,GFP )) {kfree (pages); -return ERR_PTR (-ENOMEM ); +return -ENOMEM ; } sg = pages->sgl;
@@ -81,11 +80,14 @@ huge_get_pages(struct drm_i915_gem_object *obj)if (i915_gem_gtt_prepare_pages (obj, pages)) goto err; -return pages; +__i915_gem_object_set_pages (obj, pages); + +return 0 ; err:huge_free_pages (obj, pages); -return ERR_PTR (-ENOMEM ); + +return -ENOMEM ;#undef GFP }
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c +7 -5
@@ -39,8 +39,7 @@ static void fake_free_pages(struct drm_i915_gem_object *obj,kfree (pages); } -static struct sg_table * -fake_get_pages (struct drm_i915_gem_object *obj) +static int fake_get_pages (struct drm_i915_gem_object *obj) {#define GFP (GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY)#define PFN_BIAS 0x1000
@@ -50,12 +49,12 @@ fake_get_pages(struct drm_i915_gem_object *obj) pages =kmalloc (sizeof (*pages),GFP );if (!pages) -return ERR_PTR (-ENOMEM ); +return -ENOMEM ; rem =round_up (obj->base.size,BIT (31 )) >>31 ;if (sg_alloc_table (pages, rem,GFP )) {kfree (pages); -return ERR_PTR (-ENOMEM ); +return -ENOMEM ; } rem = obj->base.size;
@@ -72,7 +71,10 @@ fake_get_pages(struct drm_i915_gem_object *obj)GEM_BUG_ON (rem); obj->mm.madv =I915_MADV_DONTNEED ; -return pages; + +__i915_gem_object_set_pages (obj, pages); + +return 0 ;#undef GFP }
Signature · 6 lines
2.13.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 05/21] drm/i915: push set_pages down to the callers
Quoting Matthew Auld (2017-09-22 18:32:36)
Quoted 10 lines
Each backend is now responsible for calling
__i915_gem_object_set_pagesupon successfully gathering its backing storage. This eliminates the inconsistency between the async and sync paths, which stands out even more when we start throwing around ansg_maskin a later patch.Suggested-by Chris Wilson <[email protected]>Signed-off-by Matthew Auld <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Chris Wilson <[email protected]>Reviewed-by Joonas Lahtinen <[email protected]>
-Chris
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PATCH 6/21 drm/i915: introduce page_size members
In reply to Matthew AuldIn preparation for supporting huge gtt pages for the ppgtt, we introduce page size members for gem objects. We fill in the page sizes by scanning the sg table.
v2: pass the sg_mask to set_pages
v3: calculate the sg_mask inline with populating the sg_table where possible, and pass to set_pages along with the pages.
v4: bunch of improvements from Joonas
--- drivers/gpu/drm/i915/i915_drv.h | 5 ++- drivers/gpu/drm/i915/i915_gem.c | 41 +++++++++++++++++++++--- drivers/gpu/drm/i915/i915_gem_dmabuf.c | 9 +++++- drivers/gpu/drm/i915/i915_gem_internal.c | 5 ++- drivers/gpu/drm/i915/i915_gem_object.h | 17 ++++++++++ drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +- drivers/gpu/drm/i915/i915_gem_userptr.c | 9 +++++- drivers/gpu/drm/i915/selftests/huge_gem_object.c | 2 +- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 5 ++- 9 files changed, 83 insertions(+), 12 deletions(-)
drivers/gpu/drm/i915/i915_drv.h +4 -1
@@ -3084,6 +3084,8 @@ intel_info(const struct drm_i915_private *dev_priv)#define USES_PPGTT (dev_priv) (i915_modparams.enable_ppgtt)#define USES_FULL_PPGTT (dev_priv) (i915_modparams.enable_ppgtt >= 2)#define USES_FULL_48BIT_PPGTT (dev_priv) (i915_modparams.enable_ppgtt == 3) +#define HAS_PAGE_SIZES (dev_priv, sizes) \ + ((sizes) && (((sizes) & ~(dev_priv)->info.page_sizes)) == 0)#define HAS_OVERLAY (dev_priv) ((dev_priv)->info.has_overlay)#define OVERLAY_NEEDS_PHYSICAL (dev_priv) \
@@ -3498,7 +3500,8 @@ i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, unsigned long n);void __i915_gem_object_set_pages (struct drm_i915_gem_object *obj, -struct sg_table *pages); +struct sg_table *pages, +unsigned int sg_mask);int __i915_gem_object_get_pages (struct drm_i915_gem_object *obj); static inline int __must_check
drivers/gpu/drm/i915/i915_gem.c +36 -5
98 lines not on this page · raw message
drivers/gpu/drm/i915/i915_gem_dmabuf.c +8 -1
@@ -259,13 +259,20 @@ struct dma_buf *i915_gem_prime_export(struct drm_device *dev,static int i915_gem_object_get_pages_dmabuf (struct drm_i915_gem_object *obj) {struct sg_table *pages; +struct scatterlist *sg; +unsigned int sg_mask; +int n; pages =dma_buf_map_attachment (obj->base.import_attach,DMA_BIDIRECTIONAL );if (IS_ERR (pages))return PTR_ERR (pages); -__i915_gem_object_set_pages (obj, pages); + sg_mask =0 ; +for_each_sg (pages->sgl, sg, pages->nents, n) + sg_mask |= sg->length; + +__i915_gem_object_set_pages (obj, pages, sg_mask);return 0 ; }
drivers/gpu/drm/i915/i915_gem_internal.c +4 -1
@@ -49,6 +49,7 @@ static int i915_gem_object_get_pages_internal(struct drm_i915_gem_object *obj)struct drm_i915_private *i915 =to_i915 (obj->base.dev);struct sg_table *st;struct scatterlist *sg; +unsigned int sg_mask;unsigned int npages;int max_order;gfp_t gfp;
@@ -87,6 +88,7 @@ static int i915_gem_object_get_pages_internal(struct drm_i915_gem_object *obj) sg = st->sgl; st->nents =0 ; + sg_mask =0 ; do { int order = min(fls(npages) - 1, max_order);
@@ -104,6 +106,7 @@ static int i915_gem_object_get_pages_internal(struct drm_i915_gem_object *obj) }while (1 );sg_set_page (sg, page,PAGE_SIZE << order,0 ); + sg_mask |=PAGE_SIZE << order; st->nents++; npages -=1 << order;
@@ -132,7 +135,7 @@ static int i915_gem_object_get_pages_internal(struct drm_i915_gem_object *obj)*/ obj->mm.madv =I915_MADV_DONTNEED ; -__i915_gem_object_set_pages (obj, st); +__i915_gem_object_set_pages (obj, st, sg_mask);return 0 ;
drivers/gpu/drm/i915/i915_gem_object.h +17 -0
@@ -169,6 +169,23 @@ struct drm_i915_gem_object {struct sg_table *pages;void *mapping; +struct i915_page_sizes { +/** +* The sg mask of the pages sg_table. i.e the mask of +* of the lengths for each sg entry. +*/ +unsigned int phys; + +/** +* The gtt page sizes we are allowed to use given the +* sg mask and the supported page sizes. This will +* express the smallest unit we can use for the whole +* object, as well as the larger sizes we may be able +* to use opportunistically. +*/ +unsigned int sg; + } page_sizes; +struct i915_gem_object_page_iter {struct scatterlist *sg_pos;unsigned int sg_idx;/* in pages, but 32bit eek! */
drivers/gpu/drm/i915/i915_gem_stolen.c +1 -1
@@ -548,7 +548,7 @@ static int i915_gem_object_get_pages_stolen(struct drm_i915_gem_object *obj)if (IS_ERR (pages))return PTR_ERR (pages); -__i915_gem_object_set_pages (obj, pages); +__i915_gem_object_set_pages (obj, pages, obj->stolen->size);return 0 ; }
drivers/gpu/drm/i915/i915_gem_userptr.c +8 -1
@@ -405,6 +405,9 @@ __i915_gem_userptr_alloc_pages(struct drm_i915_gem_object *obj, {unsigned int max_segment =i915_sg_segment_size ();struct sg_table *st; +struct scatterlist *sg; +unsigned int sg_mask; +int n;int ret; st =kmalloc (sizeof (*st),GFP_KERNEL );
@@ -434,7 +437,11 @@ __i915_gem_userptr_alloc_pages(struct drm_i915_gem_object *obj,return ERR_PTR (ret); } -__i915_gem_object_set_pages (obj, st); + sg_mask =0 ; +for_each_sg (st->sgl, sg, num_pages, n) + sg_mask |= sg->length; + +__i915_gem_object_set_pages (obj, st, sg_mask);return st; }
drivers/gpu/drm/i915/selftests/huge_gem_object.c +1 -1
@@ -80,7 +80,7 @@ static int huge_get_pages(struct drm_i915_gem_object *obj)if (i915_gem_gtt_prepare_pages (obj, pages)) goto err; -__i915_gem_object_set_pages (obj, pages); +__i915_gem_object_set_pages (obj, pages,PAGE_SIZE );return 0 ;
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c +4 -1
@@ -45,6 +45,7 @@ static int fake_get_pages(struct drm_i915_gem_object *obj)#define PFN_BIAS 0x1000struct sg_table *pages;struct scatterlist *sg; +unsigned int sg_mask; typeof(obj->base.size) rem; pages =kmalloc (sizeof (*pages),GFP );
@@ -57,6 +58,7 @@ static int fake_get_pages(struct drm_i915_gem_object *obj)return -ENOMEM ; } + sg_mask =0 ; rem = obj->base.size;for (sg = pages->sgl; sg; sg =sg_next (sg)) {unsigned long len =min_t (typeof (rem), rem,BIT (31 ));
@@ -65,6 +67,7 @@ static int fake_get_pages(struct drm_i915_gem_object *obj)sg_set_page (sg,pfn_to_page (PFN_BIAS ), len,0 );sg_dma_address (sg) =page_to_phys (sg_page (sg));sg_dma_len (sg) = len; + sg_mask |= len; rem -= len; }
@@ -72,7 +75,7 @@ static int fake_get_pages(struct drm_i915_gem_object *obj) obj->mm.madv =I915_MADV_DONTNEED ; -__i915_gem_object_set_pages (obj, pages); +__i915_gem_object_set_pages (obj, pages, sg_mask);return 0 ;#undef GFP
Signature · 6 lines
2.13.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 06/21] drm/i915: introduce page_size members
Quoting Matthew Auld (2017-09-22 18:32:37)
Quoted 18 lines
In preparation for supporting huge gtt pages for the ppgtt, we introduce page size members for gem objects. We fill in the page sizes by scanning the sg table.
v2: pass the
sg_masktoset_pagesv3: calculate the
sg_maskinline with populating thesg_tablewhere possible, and pass toset_pagesalong with the pages.v4: bunch of improvements from Joonas
Signed-off-by Matthew Auld <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Chris Wilson <[email protected]>Cc Daniel Vetter <[email protected]>Reviewed-by Joonas Lahtinen <[email protected]>
drivers/gpu/drm/i915/i915_gem.c void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, · line 2495
Quoted 8 lines
drivers/gpu/drm/i915/i915_gem.c +5
-0@@ -2475,6 +2488,24 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,__i915_gem_object_pin_pages (obj); obj->mm.quirked = true; } + +GEM_BUG_ON (!sg_mask); + obj->mm.page_sizes.phys = sg_mask; + +/* Calculate the supported page-sizes which fit into the given sg_mask.
The preferred style is
/*
* Calculate....
-Chris
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PATCH 7/21 drm/i915: introduce vm set_pages/clear_pages
In reply to Matthew AuldMove the setting/clearing of the vma->pages to a vm operation. Doing so neatens things up a little, but more importantly gives us a sane place to also set/clear the vma->pages_sizes, which we introduce later in preparation for supporting huge-pages.
v2: remove redundant vma->pages check
v3: GEM_BUG_ON(vma->pages) following i915_vma_remove
--- drivers/gpu/drm/i915/i915_gem_gtt.c | 70 +++++++++++++++++++------------ drivers/gpu/drm/i915/i915_gem_gtt.h | 2 + drivers/gpu/drm/i915/i915_vma.c | 27 +++++++----- drivers/gpu/drm/i915/selftests/mock_gtt.c | 11 ++--- 4 files changed, 66 insertions(+), 44 deletions(-)
drivers/gpu/drm/i915/i915_gem_gtt.c +44 -26
@@ -205,8 +205,6 @@ static int ppgtt_bind_vma(struct i915_vma *vma,return ret; } - vma->pages = vma->obj->mm.pages; -/* Currently applicable only to VLV */ pte_flags =0 ;if (vma->obj->gt_ro)
@@ -222,6 +220,26 @@ static void ppgtt_unbind_vma(struct i915_vma *vma) vma->vm->clear_range (vma->vm, vma->node.start, vma->size); } +static int ppgtt_set_pages (struct i915_vma *vma) +{ +GEM_BUG_ON (vma->pages); + + vma->pages = vma->obj->mm.pages; + +return 0 ; +} + +static void clear_pages (struct i915_vma *vma) +{ +GEM_BUG_ON (!vma->pages); + +if (vma->pages != vma->obj->mm.pages) { +sg_free_table (vma->pages); +kfree (vma->pages); + } + vma->pages =NULL ; +} +static gen8_pte_t gen8_pte_encode (dma_addr_t addr,enum i915_cache_level level) {
@@ -1454,6 +1472,8 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) ppgtt->base.cleanup = gen8_ppgtt_cleanup; ppgtt->base.unbind_vma = ppgtt_unbind_vma; ppgtt->base.bind_vma = ppgtt_bind_vma; + ppgtt->base.set_pages = ppgtt_set_pages; + ppgtt->base.clear_pages = clear_pages; ppgtt->debug_dump = gen8_dump_ppgtt;return 0 ;
@@ -1896,6 +1916,8 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; ppgtt->base.unbind_vma = ppgtt_unbind_vma; ppgtt->base.bind_vma = ppgtt_bind_vma; + ppgtt->base.set_pages = ppgtt_set_pages; + ppgtt->base.clear_pages = clear_pages; ppgtt->base.cleanup = gen6_ppgtt_cleanup; ppgtt->debug_dump = gen6_dump_ppgtt;
@@ -2407,12 +2429,6 @@ static int ggtt_bind_vma(struct i915_vma *vma,struct drm_i915_gem_object *obj = vma->obj;u32 pte_flags; -if (unlikely (!vma->pages)) { -int ret =i915_get_ggtt_vma_pages (vma); -if (ret) -return ret; - } -/* Currently applicable only to VLV */ pte_flags =0 ;if (obj->gt_ro)
@@ -2449,12 +2465,6 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma,u32 pte_flags;int ret; -if (unlikely (!vma->pages)) { - ret =i915_get_ggtt_vma_pages (vma); -if (ret) -return ret; - } -/* Currently applicable only to VLV */ pte_flags =0 ;if (vma->obj->gt_ro)
@@ -2469,7 +2479,7 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma, vma->node.start, vma->size);if (ret) - goto err_pages; +return ret; } appgtt->base.insert_entries(&appgtt->base, vma, cache_level,
@@ -2483,17 +2493,6 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma, }return 0 ; - -err_pages: -if (!(vma->flags & (I915_VMA_GLOBAL_BIND |I915_VMA_LOCAL_BIND ))) { -if (vma->pages != vma->obj->mm.pages) { -GEM_BUG_ON (!vma->pages); -sg_free_table (vma->pages); -kfree (vma->pages); - } - vma->pages =NULL ; - } -return ret; }static void aliasing_gtt_unbind_vma (struct i915_vma *vma)
@@ -2531,6 +2530,19 @@ void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,dma_unmap_sg (kdev, pages->sgl, pages->nents,PCI_DMA_BIDIRECTIONAL ); } +static int ggtt_set_pages (struct i915_vma *vma) +{ +int ret; + +GEM_BUG_ON (vma->pages); + + ret =i915_get_ggtt_vma_pages (vma); +if (ret) +return ret; + +return 0 ; +} + static void i915_gtt_color_adjust(const struct drm_mm_node *node, unsigned long color, u64 *start,
@@ -3153,6 +3165,8 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) ggtt->base.cleanup = gen6_gmch_remove; ggtt->base.bind_vma = ggtt_bind_vma; ggtt->base.unbind_vma = ggtt_unbind_vma; + ggtt->base.set_pages = ggtt_set_pages; + ggtt->base.clear_pages = clear_pages; ggtt->base.insert_page = gen8_ggtt_insert_page; ggtt->base.clear_range = nop_clear_range;if (!USES_FULL_PPGTT (dev_priv) ||intel_scanout_needs_vtd_wa (dev_priv))
@@ -3211,6 +3225,8 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) ggtt->base.insert_entries = gen6_ggtt_insert_entries; ggtt->base.bind_vma = ggtt_bind_vma; ggtt->base.unbind_vma = ggtt_unbind_vma; + ggtt->base.set_pages = ggtt_set_pages; + ggtt->base.clear_pages = clear_pages; ggtt->base.cleanup = gen6_gmch_remove; ggtt->invalidate = gen6_ggtt_invalidate;
@@ -3256,6 +3272,8 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt) ggtt->base.clear_range = i915_ggtt_clear_range; ggtt->base.bind_vma = ggtt_bind_vma; ggtt->base.unbind_vma = ggtt_unbind_vma; + ggtt->base.set_pages = ggtt_set_pages; + ggtt->base.clear_pages = clear_pages; ggtt->base.cleanup = i915_gmch_remove; ggtt->invalidate = gmch_ggtt_invalidate;
drivers/gpu/drm/i915/i915_gem_gtt.h +2 -0
@@ -334,6 +334,8 @@ struct i915_address_space {int (*bind_vma)(struct i915_vma *vma,enum i915_cache_level cache_level,u32 flags); +int (*set_pages)(struct i915_vma *vma); +void (*clear_pages)(struct i915_vma *vma); I915_SELFTEST_DECLARE(struct fault_attr fault_attr); };
drivers/gpu/drm/i915/i915_vma.c +16 -11
@@ -266,6 +266,8 @@ int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,if (bind_flags ==0 )return 0 ; +GEM_BUG_ON (!vma->pages); +trace_i915_vma_bind (vma, bind_flags); ret = vma->vm->bind_vma (vma, cache_level, bind_flags);if (ret)
@@ -471,25 +473,31 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)if (ret)return ret; +GEM_BUG_ON (vma->pages); + + ret = vma->vm->set_pages (vma); +if (ret) + goto err_unpin; +if (flags &PIN_OFFSET_FIXED ) {u64 offset = flags &PIN_OFFSET_MASK ;if (!IS_ALIGNED (offset, alignment) ||range_overflows (offset, size, end)) { ret = -EINVAL ; - goto err_unpin; + goto err_clear; } ret =i915_gem_gtt_reserve (vma->vm, &vma->node, size, offset, obj->cache_level, flags);if (ret) - goto err_unpin; + goto err_clear; }else { ret =i915_gem_gtt_insert (vma->vm, &vma->node, size, alignment, obj->cache_level, start, end, flags);if (ret) - goto err_unpin; + goto err_clear;GEM_BUG_ON (vma->node.start < start);GEM_BUG_ON (vma->node.start + vma->node.size > end);
@@ -504,6 +512,8 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)return 0 ; +err_clear: + vma->vm->clear_pages (vma); err_unpin:i915_gem_object_unpin_pages (obj);return ret;
@@ -517,6 +527,8 @@ i915_vma_remove(struct i915_vma *vma)GEM_BUG_ON (!drm_mm_node_allocated (&vma->node));GEM_BUG_ON (vma->flags & (I915_VMA_GLOBAL_BIND |I915_VMA_LOCAL_BIND )); + vma->vm->clear_pages (vma); +drm_mm_remove_node (&vma->node);list_move_tail (&vma->vm_link, &vma->vm->unbound_list);
@@ -569,8 +581,8 @@ int __i915_vma_do_pin(struct i915_vma *vma, err_remove:if ((bound &I915_VMA_BIND_MASK ) ==0 ) { -GEM_BUG_ON (vma->pages);i915_vma_remove (vma); +GEM_BUG_ON (vma->pages); } err_unpin:__i915_vma_unpin (vma);
@@ -695,13 +707,6 @@ int i915_vma_unbind(struct i915_vma *vma) } vma->flags &= ~(I915_VMA_GLOBAL_BIND |I915_VMA_LOCAL_BIND ); -if (vma->pages != obj->mm.pages) { -GEM_BUG_ON (!vma->pages); -sg_free_table (vma->pages); -kfree (vma->pages); - } - vma->pages =NULL ; -i915_vma_remove (vma); destroy:
drivers/gpu/drm/i915/selftests/mock_gtt.c +4 -7
@@ -43,7 +43,6 @@ static int mock_bind_ppgtt(struct i915_vma *vma, u32 flags) {GEM_BUG_ON (flags &I915_VMA_GLOBAL_BIND ); - vma->pages = vma->obj->mm.pages; vma->flags |=I915_VMA_LOCAL_BIND ;return 0 ; }
@@ -84,6 +83,8 @@ mock_ppgtt(struct drm_i915_private *i915, ppgtt->base.insert_entries = mock_insert_entries; ppgtt->base.bind_vma = mock_bind_ppgtt; ppgtt->base.unbind_vma = mock_unbind_ppgtt; + ppgtt->base.set_pages = ppgtt_set_pages; + ppgtt->base.clear_pages = clear_pages; ppgtt->base.cleanup = mock_cleanup;return ppgtt;
@@ -93,12 +94,6 @@ static int mock_bind_ggtt(struct i915_vma *vma, enum i915_cache_level cache_level, u32 flags) { - int err; - - err =i915_get_ggtt_vma_pages (vma); -if (err) -return err; - vma->flags |=I915_VMA_GLOBAL_BIND |I915_VMA_LOCAL_BIND ;return 0 ; }
@@ -124,6 +119,8 @@ void mock_init_ggtt(struct drm_i915_private *i915) ggtt->base.insert_entries = mock_insert_entries; ggtt->base.bind_vma = mock_bind_ggtt; ggtt->base.unbind_vma = mock_unbind_ggtt; + ggtt->base.set_pages = ggtt_set_pages; + ggtt->base.clear_pages = clear_pages; ggtt->base.cleanup = mock_cleanup;i915_address_space_init (&ggtt->base, i915,"global" );
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2.13.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 07/21] drm/i915: introduce vm set_pages/clear_pages
Quoting Matthew Auld (2017-09-22 18:32:38)
Quoted 5 lines
Move the setting/clearing of the
vma->pagesto a vm operation. Doing so neatens things up a little, but more importantly gives us a sane place to also set/clear thevma->pages_sizes, which we introduce later in preparation for supporting huge-pages.
Quoted 8 lines
v2: remove redundant
vma->pagescheckv3:
GEM_BUG_ON(vma->pages)followingi915_vma_removeSuggested-by Chris Wilson <[email protected]>Signed-off-by Matthew Auld <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Chris Wilson <[email protected]>
-Chris
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PATCH 8/21 drm/i915: align the vma start to the largest gtt page size
In reply to Matthew AuldFor the 48b PPGTT try to align the vma start address to the required page size boundary to guarantee we use said page size in the gtt. If we are dealing with multiple page sizes, we can't guarantee anything and just align to the largest. For soft pinning and objects which need to be tightly packed into the lower 32bits we don't force any alignment.
v2: various improvements suggested by Chris
v3: use set_pages and better placement of page_sizes
--- drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++++++ drivers/gpu/drm/i915/i915_vma.c | 12 ++++++++++++ drivers/gpu/drm/i915/i915_vma.h | 1 + 3 files changed, 21 insertions(+)
drivers/gpu/drm/i915/i915_gem_gtt.c +8 -0
@@ -226,6 +226,9 @@ static int ppgtt_set_pages(struct i915_vma *vma) vma->pages = vma->obj->mm.pages; + vma->page_sizes.phys = vma->obj->mm.page_sizes.phys; + vma->page_sizes.sg = vma->obj->mm.page_sizes.sg; +return 0 ; }
@@ -238,6 +241,8 @@ static void clear_pages(struct i915_vma *vma)kfree (vma->pages); } vma->pages =NULL ; + +memset (&vma->page_sizes,0 ,sizeof (struct i915_page_sizes )); } static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
@@ -2540,6 +2545,9 @@ static int ggtt_set_pages(struct i915_vma *vma)if (ret)return ret; + vma->page_sizes.phys = vma->obj->mm.page_sizes.phys; + vma->page_sizes.sg = vma->obj->mm.page_sizes.sg; +return 0 ; }
drivers/gpu/drm/i915/i915_vma.c +12 -0
@@ -493,6 +493,18 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)if (ret) goto err_clear; }else { +/* We only support huge gtt pages through the 48b PPGTT, +* however we also don't want to force any alignment for +* objects which need to be tightly packed into the low 32bits. +*/ +if (end > (1ULL <<32 ) && + vma->page_sizes.sg >I915_GTT_PAGE_SIZE ) { +u64 page_alignment = +rounddown_pow_of_two (vma->page_sizes.sg); + + alignment =max (alignment, page_alignment); + } + ret =i915_gem_gtt_insert (vma->vm, &vma->node, size, alignment, obj->cache_level, start, end, flags);
drivers/gpu/drm/i915/i915_vma.h +1 -0
@@ -55,6 +55,7 @@ struct i915_vma {void __iomem *iomap;u64 size;u64 display_alignment; +struct i915_page_sizes page_sizes;u32 fence_size;u32 fence_alignment;
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2.13.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 08/21] drm/i915: align the vma start to the largest gtt page size
Quoting Matthew Auld (2017-09-22 18:32:39)
Quoted 15 lines
For the 48b PPGTT try to align the vma start address to the required page size boundary to guarantee we use said page size in the gtt. If we are dealing with multiple page sizes, we can't guarantee anything and just align to the largest. For soft pinning and objects which need to be tightly packed into the lower 32bits we don't force any alignment.
v2: various improvements suggested by Chris
v3: use
set_pagesand better placement ofpage_sizesSigned-off-by Matthew Auld <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Chris Wilson <[email protected]>} else {
drivers/gpu/drm/i915/i915_vma.c i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) · line 500
Quoted 5 lines
drivers/gpu/drm/i915/i915_vma.c +5
-0+/* We only support huge gtt pages through the 48b PPGTT, +* however we also don't want to force any alignment for +* objects which need to be tightly packed into the low 32bits. +*/ + if (end > (1ULL << 32) &&
gcc prefers
if (upper_32_bits(end) && vma->page_sizes.sg)
-Chris
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PATCH 9/21 drm/i915: align 64K objects to 2M
In reply to Matthew AuldWe can't mix 64K and 4K pte's in the same page-table, so for now we align 64K objects to 2M to avoid any potential mixing. This is potentially wasteful but in reality shouldn't be too bad since this only applies to the virtual address space of a 48b PPGTT.
v2: don't separate logically connected ops
--- drivers/gpu/drm/i915/i915_vma.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/i915_vma.c +9 -1
@@ -500,9 +500,17 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)if (end > (1ULL <<32 ) && vma->page_sizes.sg >I915_GTT_PAGE_SIZE ) {u64 page_alignment = -rounddown_pow_of_two (vma->page_sizes.sg); +rounddown_pow_of_two (vma->page_sizes.sg | +I915_GTT_PAGE_SIZE_2M ); alignment =max (alignment, page_alignment); + +/* We can't mix 64K and 4K PTEs in the same page-table (2M +* block), and so to avoid the ugliness and complexity of +* coloring we opt for just aligning 64K objects to 2M. +*/ +if (vma->page_sizes.sg &I915_GTT_PAGE_SIZE_64K ) + size =round_up (size,I915_GTT_PAGE_SIZE_2M ); } ret = i915_gem_gtt_insert(vma->vm, &vma->node,
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2.13.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 09/21] drm/i915: align 64K objects to 2M
Quoting Matthew Auld (2017-09-22 18:32:40)
Quoted 11 lines
We can't mix 64K and 4K pte's in the same page-table, so for now we align 64K objects to 2M to avoid any potential mixing. This is potentially wasteful but in reality shouldn't be too bad since this only applies to the virtual address space of a 48b PPGTT.
v2: don't separate logically connected ops
Suggested-by Chris Wilson <[email protected]>Signed-off-by Matthew Auld <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Chris Wilson <[email protected]>
-Chris
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PATCH 10/21 drm/i915: enable IPS bit for 64K pages
In reply to Matthew AuldBefore we can enable 64K pages through the IPS bit, we must first enable it through MMIO, otherwise the page-walker will simply ignore it.
v2: add comment mentioning that 64K is BDW+
--- drivers/gpu/drm/i915/i915_gem.c | 16 ++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 19 insertions(+)
drivers/gpu/drm/i915/i915_gem.c +16 -0
@@ -4755,6 +4755,22 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv) } } +/* To support 64K PTEs we need to first enable the use of the +* Intermediate-Page-Size(IPS) bit of the PDE field via some magical +* mmio, otherwise the page-walker will simply ignore the IPS bit. This +* shouldn't be needed after GEN10. +* +* 64K pages were first introduced from BDW+, although technically they +* only *work* from gen9+. For pre-BDW we instead have the option for +* 32K pages, but we don't currently have any support for it in our +* driver. +*/ +if (HAS_PAGE_SIZES (dev_priv,I915_GTT_PAGE_SIZE_64K ) && +INTEL_GEN (dev_priv) <=10 ) +I915_WRITE (GEN8_GAMW_ECO_DEV_RW_IA , +I915_READ (GEN8_GAMW_ECO_DEV_RW_IA ) | +GAMW_ECO_ENABLE_64K_IPS_FIELD ); +i915_gem_init_swizzling (dev_priv);/*
drivers/gpu/drm/i915/i915_reg.h +3 -0
@@ -2371,6 +2371,9 @@ enum i915_power_well_id {#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18) +#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080) +#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF +#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1<<24)
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2.13.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 10/21] drm/i915: enable IPS bit for 64K pages
Quoted 27 lines · Matthew Auld
Before we can enable 64K pages through the IPS bit, we must first enable it through MMIO, otherwise the page-walker will simply ignore it.
v2: add comment mentioning that 64K is BDW+
Signed-off-by Matthew Auld <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Chris Wilson <[email protected]>--- drivers/gpu/drm/i915/i915_gem.c | 16 ++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 19 insertions(+)drivers/gpu/drm/i915/i915_gem.c +6
-0@@ -4755,6 +4755,22 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv) } } +/* To support 64K PTEs we need to first enable the use of the +* Intermediate-Page-Size(IPS) bit of the PDE field via some magical +* mmio, otherwise the page-walker will simply ignore the IPS bit. This +* shouldn't be needed after GEN10. +* +* 64K pages were first introduced from BDW+, although technically they
drivers/gpu/drm/i915/i915_gem.c int i915_gem_init_hw(struct drm_i915_private *dev_priv) · line 4773
Quoted 10 lines
drivers/gpu/drm/i915/i915_gem.c +10
-0+* only *work* from gen9+. For pre-BDW we instead have the option for +* 32K pages, but we don't currently have any support for it in our +* driver. +*/ +if (HAS_PAGE_SIZES (dev_priv,I915_GTT_PAGE_SIZE_64K ) && +INTEL_GEN (dev_priv) <=10 ) +I915_WRITE (GEN8_GAMW_ECO_DEV_RW_IA , +I915_READ (GEN8_GAMW_ECO_DEV_RW_IA ) | +GAMW_ECO_ENABLE_64K_IPS_FIELD ); +
Apparently we need this prior touching pde. Move this to gtt_write_workarounds() and you can add my,
Quoted 24 lines
drivers/gpu/drm/i915/i915_gem.c +0
-0i915_gem_init_swizzling (dev_priv);/* drivers/gpu/drm/i915/i915_reg.h +3
-0@@ -2371,6 +2371,9 @@ enum i915_power_well_id {#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18) +#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080) +#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF +#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1<<24)Signature · 6 lines
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PATCH 11/21 drm/i915: disable GTT cache for 2M pages
In reply to Matthew AuldWhen SW enables the use of 2M/1G pages, it must disable the GTT cache.
v2: don't disable for Cherryview which doesn't even support 48b PPGTT!
v3: explicitly check that the system does support 2M/1G pages
--- drivers/gpu/drm/i915/intel_pm.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)
drivers/gpu/drm/i915/intel_pm.c +5 -3
@@ -8483,10 +8483,12 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)/* * WaGttCachingOffByDefault:bdw -* GTT cache may not work with big pages, so if those -* are ever enabled GTT cache may need to be disabled. +* The GTT cache must be disabled if the system is planning to use +* 2M/1G pages. */ -I915_WRITE (HSW_GTT_CACHE_EN ,GTT_CACHE_EN_ALL ); +I915_WRITE (HSW_GTT_CACHE_EN , +HAS_PAGE_SIZES (dev_priv,I915_GTT_PAGE_SIZE_2M ) ?0 : +GTT_CACHE_EN_ALL );/* WaKVMNotificationOnConfigChange:bdw */ I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
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Re: [PATCH 11/21] drm/i915: disable GTT cache for 2M pages
Quoted 18 lines · Matthew Auld
When SW enables the use of 2M/1G pages, it must disable the GTT cache.
v2: don't disable for Cherryview which doesn't even support 48b PPGTT!
v3: explicitly check that the system does support 2M/1G pages
Signed-off-by Matthew Auld <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Chris Wilson <[email protected]>--- drivers/gpu/drm/i915/intel_pm.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)drivers/gpu/drm/i915/intel_pm.c +0
-0
drivers/gpu/drm/i915/intel_pm.c static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) · line 8487
Quoted 7 lines
drivers/gpu/drm/i915/intel_pm.c +2
-2@@ -8483,10 +8483,12 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)/* * WaGttCachingOffByDefault:bdw -* GTT cache may not work with big pages, so if those -* are ever enabled GTT cache may need to be disabled. +* The GTT cache must be disabled if the system is planning to use +* 2M/1G pages.
s/is planning to/is using
Quoted 15 lines
drivers/gpu/drm/i915/intel_pm.c +3
-1*/ -I915_WRITE (HSW_GTT_CACHE_EN ,GTT_CACHE_EN_ALL ); +I915_WRITE (HSW_GTT_CACHE_EN , +HAS_PAGE_SIZES (dev_priv,I915_GTT_PAGE_SIZE_2M ) ?0 : +GTT_CACHE_EN_ALL );/* WaKVMNotificationOnConfigChange:bdw */ I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)Signature · 6 lines
2.13.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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PATCH 12/21 drm/i915: support 2M pages for the 48b PPGTT
In reply to Matthew AuldSupport inserting 2M gtt pages into the 48b PPGTT.
v2: sanity check sg->length against page_size
v3: don't recalculate rem on each loop
whitespace breakup
--- drivers/gpu/drm/i915/i915_gem_gtt.c | 78 +++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/i915_gem_gtt.h | 2 + 2 files changed, 76 insertions(+), 4 deletions(-)
drivers/gpu/drm/i915/i915_gem_gtt.c +74 -4
@@ -1016,6 +1016,71 @@ static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm, cache_level); } +static void gen8_ppgtt_insert_huge_entries (struct i915_vma *vma, +struct i915_page_directory_pointer **pdps, +struct sgt_dma *iter, +enum i915_cache_level cache_level) +{ +const gen8_pte_t pte_encode =gen8_pte_encode (0 , cache_level); +u64 start = vma->node.start; +dma_addr_t rem = iter->sg->length; + +do { +struct gen8_insert_pte idx =gen8_insert_pte (start); +struct i915_page_directory_pointer *pdp = pdps[idx.pml4e]; +struct i915_page_directory *pd = pdp->page_directory[idx.pdpe]; +unsigned int page_size; +gen8_pte_t encode = pte_encode; +gen8_pte_t *vaddr; +u16 index, max; + +if (vma->page_sizes.sg &I915_GTT_PAGE_SIZE_2M && +IS_ALIGNED (iter->dma,I915_GTT_PAGE_SIZE_2M ) && + rem >=I915_GTT_PAGE_SIZE_2M && !idx.pte) { + index = idx.pde; + max =I915_PDES ; + page_size =I915_GTT_PAGE_SIZE_2M ; + + encode |=GEN8_PDE_PS_2M ; + + vaddr =kmap_atomic_px (pd); + }else { +struct i915_page_table *pt = pd->page_table[idx.pde]; + + index = idx.pte; + max =GEN8_PTES ; + page_size =I915_GTT_PAGE_SIZE ; + + vaddr =kmap_atomic_px (pt); + } + +do { +GEM_BUG_ON (iter->sg->length < page_size); + vaddr[index++] = encode | iter->dma; + + start += page_size; + iter->dma += page_size; + rem -= page_size; +if (iter->dma >= iter->max) { + iter->sg =__sg_next (iter->sg); +if (!iter->sg) +break ; + + rem = iter->sg->length; + iter->dma =sg_dma_address (iter->sg); + iter->max = iter->dma + rem; + +if (unlikely (!IS_ALIGNED (iter->dma, page_size))) +break ; + } + + }while (rem >= page_size && index < max); + +kunmap_atomic (vaddr); + + }while (iter->sg); +} + static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm, struct i915_vma *vma, enum i915_cache_level cache_level,
@@ -1028,11 +1093,16 @@ static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm, .max = iter.dma + iter.sg->length, };struct i915_page_directory_pointer **pdps = ppgtt->pml4.pdps; -struct gen8_insert_pte idx =gen8_insert_pte (vma->node.start); -while (gen8_ppgtt_insert_pte_entries (ppgtt, pdps[idx.pml4e++], &iter, - &idx, cache_level)) -GEM_BUG_ON (idx.pml4e >=GEN8_PML4ES_PER_PML4 ); +if (vma->page_sizes.sg >I915_GTT_PAGE_SIZE ) { +gen8_ppgtt_insert_huge_entries (vma, pdps, &iter, cache_level); + }else { +struct gen8_insert_pte idx =gen8_insert_pte (vma->node.start); + +while (gen8_ppgtt_insert_pte_entries (ppgtt, pdps[idx.pml4e++], + &iter, &idx, cache_level)) +GEM_BUG_ON (idx.pml4e >=GEN8_PML4ES_PER_PML4 ); + } } static void gen8_free_page_tables(struct i915_address_space *vm,
drivers/gpu/drm/i915/i915_gem_gtt.h +2 -0
@@ -153,6 +153,8 @@ typedef u64 gen8_ppgtt_pml4e_t;#define GEN8_PPAT_GET_AGE (x) ((x) & (3 << 4))#define CHV_PPAT_GET_SNOOP (x) ((x) & (1 << 6)) +#define GEN8_PDE_PS_2M BIT(7) +struct sg_table ;struct intel_rotation_info {
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2.13.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 12/21] drm/i915: support 2M pages for the 48b PPGTT
Quoting Matthew Auld (2017-09-22 18:32:43)
Quoted 77 lines
Support inserting 2M gtt pages into the 48b PPGTT.
v2: sanity check
sg->lengthagainstpage_sizev3: don't recalculate rem on each loop
whitespace breakupSigned-off-by Matthew Auld <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Chris Wilson <[email protected]>--- drivers/gpu/drm/i915/i915_gem_gtt.c | 78 +++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/i915_gem_gtt.h | 2 + 2 files changed, 76 insertions(+), 4 deletions(-)drivers/gpu/drm/i915/i915_gem_gtt.c +54
-0@@ -1016,6 +1016,71 @@ static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm, cache_level); } +static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma, + struct i915_page_directory_pointer **pdps, + struct sgt_dma *iter, + enum i915_cache_level cache_level) +{ + const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level); + u64 start = vma->node.start; + dma_addr_t rem = iter->sg->length; + + do { + struct gen8_insert_pte idx = gen8_insert_pte(start); + struct i915_page_directory_pointer *pdp = pdps[idx.pml4e]; + struct i915_page_directory *pd = pdp->page_directory[idx.pdpe]; + unsigned int page_size; + gen8_pte_t encode = pte_encode; + gen8_pte_t *vaddr; + u16 index, max; + + if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_2M && + IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_2M) && + rem >= I915_GTT_PAGE_SIZE_2M && !idx.pte) { + index = idx.pde; + max = I915_PDES; + page_size = I915_GTT_PAGE_SIZE_2M; + + encode |= GEN8_PDE_PS_2M; + + vaddr = kmap_atomic_px(pd); + } else { + struct i915_page_table *pt = pd->page_table[idx.pde]; + + index = idx.pte; + max = GEN8_PTES; + page_size = I915_GTT_PAGE_SIZE; + + vaddr = kmap_atomic_px(pt); + } + + do { + GEM_BUG_ON(iter->sg->length < page_size); + vaddr[index++] = encode | iter->dma; + + start += page_size; + iter->dma += page_size; + rem -= page_size; + if (iter->dma >= iter->max) { + iter->sg = __sg_next(iter->sg); + if (!iter->sg) + break; + + rem = iter->sg->length; + iter->dma = sg_dma_address(iter->sg); + iter->max = iter->dma + rem; +
drivers/gpu/drm/i915/i915_gem_gtt.c static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm, · line 1082
Quoted 10 lines
drivers/gpu/drm/i915/i915_gem_gtt.c +10
-0+if (unlikely (!IS_ALIGNED (iter->dma, page_size))) +break ; + } + + }while (rem >= page_size && index < max); + +kunmap_atomic (vaddr); + + }while (iter->sg); +}
Blank lines before '}' make feel uncomfortable, like something is missing.
-Chris
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PATCH 13/21 drm/i915: add support for 64K scratch page
In reply to Matthew AuldBefore we can fully enable 64K pages, we need to first support a 64K scratch page if we intend to support the case where we have object sizes < 2M, since any scratch PTE must also point to a 64K region. Without this our 64K usage is limited to objects which completely fill the page-table, and therefore don't need any scratch.
v2: add reminder about why 48b PPGTT
--- drivers/gpu/drm/i915/i915_gem_gtt.c | 60 ++++++++++++++++++++++++++++++------- drivers/gpu/drm/i915/i915_gem_gtt.h | 1 + 2 files changed, 50 insertions(+), 11 deletions(-)
drivers/gpu/drm/i915/i915_gem_gtt.c +49 -11
@@ -522,22 +522,59 @@ static void fill_page_dma_32(struct i915_address_space *vm,static int setup_scratch_page (struct i915_address_space *vm,gfp_t gfp) { -struct page *page; +struct page *page =NULL ;dma_addr_t addr; +int order; - page =alloc_page (gfp | __GFP_ZERO); -if (unlikely (!page)) -return -ENOMEM ; +/* In order to utilize 64K pages for an object with a size < 2M, we will +* need to support a 64K scratch page, given that every 16th entry for a +* page-table operating in 64K mode must point to a properly aligned 64K +* region, including any PTEs which happen to point to scratch. +* +* This is only relevant for the 48b PPGTT where we support +* huge-gtt-pages, see also i915_vma_insert(). +*/ +if (i915_vm_is_48bit (vm) && +HAS_PAGE_SIZES (vm->i915,I915_GTT_PAGE_SIZE_64K )) { + order =get_order (I915_GTT_PAGE_SIZE_64K ); + page =alloc_pages (gfp | __GFP_ZERO, order); +if (page) { + addr =dma_map_page (vm->dma, page,0 , +I915_GTT_PAGE_SIZE_64K , +PCI_DMA_BIDIRECTIONAL ); +if (unlikely (dma_mapping_error (vm->dma, addr))) { +__free_pages (page, order); + page =NULL ; + } - addr =dma_map_page (vm->dma, page,0 ,PAGE_SIZE , -PCI_DMA_BIDIRECTIONAL ); -if (unlikely (dma_mapping_error (vm->dma, addr))) { -__free_page (page); -return -ENOMEM ; +if (!IS_ALIGNED (addr,I915_GTT_PAGE_SIZE_64K )) { +dma_unmap_page (vm->dma, addr, +I915_GTT_PAGE_SIZE_64K , +PCI_DMA_BIDIRECTIONAL ); +__free_pages (page, order); + page =NULL ; + } + } + } + +if (!page) { + order =0 ; + page =alloc_page (gfp | __GFP_ZERO); +if (unlikely (!page)) +return -ENOMEM ; + + addr =dma_map_page (vm->dma, page,0 ,PAGE_SIZE , +PCI_DMA_BIDIRECTIONAL ); +if (unlikely (dma_mapping_error (vm->dma, addr))) { +__free_page (page); +return -ENOMEM ; + } } vm->scratch_page.page = page; vm->scratch_page.daddr = addr; + vm->scratch_page.order = order; +return 0 ; }
@@ -545,8 +582,9 @@ static void cleanup_scratch_page(struct i915_address_space *vm) {struct i915_page_dma *p = &vm->scratch_page; -dma_unmap_page (vm->dma, p->daddr,PAGE_SIZE ,PCI_DMA_BIDIRECTIONAL ); -__free_page (p->page); +dma_unmap_page (vm->dma, p->daddr,BIT (p->order) <<PAGE_SHIFT , +PCI_DMA_BIDIRECTIONAL ); +__free_pages (p->page, p->order); }static struct i915_page_table *alloc_pt (struct i915_address_space *vm)
drivers/gpu/drm/i915/i915_gem_gtt.h +1 -0
@@ -214,6 +214,7 @@ struct i915_vma;struct i915_page_dma {struct page *page; +int order;union {dma_addr_t daddr;
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2.13.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 13/21] drm/i915: add support for 64K scratch page
Quoting Matthew Auld (2017-09-22 18:32:44)
Quoted 6 lines
Before we can fully enable 64K pages, we need to first support a 64K scratch page if we intend to support the case where we have object sizes < 2M, since any scratch PTE must also point to a 64K region. Without this our 64K usage is limited to objects which completely fill the page-table, and therefore don't need any scratch.
Quoted 6 lines
v2: add reminder about why 48b PPGTT
Reported-by Chris Wilson <[email protected]>Signed-off-by Matthew Auld <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Chris Wilson <[email protected]>
We really, really should write protect the scratch page so that we can share it between ppgtt. We can't make it simply unreadable as we use it for padding.
-Chris
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PATCH 14/21 drm/i915: support 64K pages for the 48b PPGTT
In reply to Matthew AuldSupport inserting 64K pages into the 48b PPGTT.
v2: check for 64K scratch
v3: we should only have to re-adjust maybe_64K at every sg interval
--- drivers/gpu/drm/i915/i915_gem_gtt.c | 30 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_gem_gtt.h | 7 +++++++ 2 files changed, 37 insertions(+)
drivers/gpu/drm/i915/i915_gem_gtt.c +30 -0
@@ -1068,6 +1068,7 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,struct i915_page_directory_pointer *pdp = pdps[idx.pml4e];struct i915_page_directory *pd = pdp->page_directory[idx.pdpe];unsigned int page_size; +bool maybe_64K = false;gen8_pte_t encode = pte_encode;gen8_pte_t *vaddr;u16 index, max;
@@ -1089,6 +1090,13 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma, max =GEN8_PTES ; page_size =I915_GTT_PAGE_SIZE ; +if (!index && + vma->page_sizes.sg &I915_GTT_PAGE_SIZE_64K && +IS_ALIGNED (iter->dma,I915_GTT_PAGE_SIZE_64K ) && + (IS_ALIGNED (rem,I915_GTT_PAGE_SIZE_64K ) || + rem >= (max - index) <<PAGE_SHIFT )) + maybe_64K = true; + vaddr =kmap_atomic_px (pt); }
@@ -1108,6 +1116,12 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma, iter->dma =sg_dma_address (iter->sg); iter->max = iter->dma + rem; +if (maybe_64K && index < max && + !(IS_ALIGNED (iter->dma,I915_GTT_PAGE_SIZE_64K ) && + (IS_ALIGNED (rem,I915_GTT_PAGE_SIZE_64K ) || + rem >= (max - index) <<PAGE_SHIFT ))) + maybe_64K = false; +if (unlikely (!IS_ALIGNED (iter->dma, page_size)))break ; }
@@ -1116,6 +1130,22 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,kunmap_atomic (vaddr); +/* Is it safe to mark the 2M block as 64K? -- Either we have +* filled whole page-table with 64K entries, or filled part of +* it and have reached the end of the sg table and we have +* enough padding. +*/ +if (maybe_64K && + (index == max || + (i915_vm_has_scratch_64K (vma->vm) && + !iter->sg &&IS_ALIGNED (vma->node.start + + vma->node.size, +I915_GTT_PAGE_SIZE_2M )))) { + vaddr =kmap_atomic_px (pd); + vaddr[idx.pde] |=GEN8_PDE_IPS_64K ; +kunmap_atomic (vaddr); + } + }while (iter->sg); }
drivers/gpu/drm/i915/i915_gem_gtt.h +7 -0
@@ -153,6 +153,7 @@ typedef u64 gen8_ppgtt_pml4e_t;#define GEN8_PPAT_GET_AGE (x) ((x) & (3 << 4))#define CHV_PPAT_GET_SNOOP (x) ((x) & (1 << 6)) +#define GEN8_PDE_IPS_64K BIT(11)#define GEN8_PDE_PS_2M BIT(7)struct sg_table ;
@@ -351,6 +352,12 @@ i915_vm_is_48bit(const struct i915_address_space *vm)return (vm->total -1 ) >>32 ; } +static inline bool +i915_vm_has_scratch_64K (struct i915_address_space *vm) +{ +return vm->scratch_page.order ==get_order (I915_GTT_PAGE_SIZE_64K ); +} +/* The Graphics Translation Table is the way in which GEN hardware translates a * Graphics Virtual Address into a Physical Address. In addition to the normal * collateral associated with any va->pa translations GEN hardware also has a
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Re: [PATCH 14/21] drm/i915: support 64K pages for the 48b PPGTT
Quoting Matthew Auld (2017-09-22 18:32:45)
Quoted 9 lines
Support inserting 64K pages into the 48b PPGTT.
v2: check for 64K scratch
v3: we should only have to re-adjust
maybe_64Kat every sg intervalSigned-off-by Matthew Auld <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Chris Wilson <[email protected]>
-Chris
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PATCH 15/21 drm/i915: accurate page size tracking for the ppgtt
In reply to Matthew AuldNow that we support multiple page sizes for the ppgtt, it would be useful to track the real usage for debugging purposes.
--- drivers/gpu/drm/i915/i915_gem_gtt.c | 11 +++++++++++ drivers/gpu/drm/i915/i915_gem_object.h | 10 ++++++++++ 2 files changed, 21 insertions(+)
drivers/gpu/drm/i915/i915_gem_gtt.c +11 -0
@@ -1052,6 +1052,8 @@ static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm,gen8_ppgtt_insert_pte_entries (ppgtt, &ppgtt->pdp, &iter, &idx, cache_level); + + vma->page_sizes.gtt =I915_GTT_PAGE_SIZE ; } static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
@@ -1144,8 +1146,11 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma, vaddr =kmap_atomic_px (pd); vaddr[idx.pde] |=GEN8_PDE_IPS_64K ;kunmap_atomic (vaddr); + page_size =I915_GTT_PAGE_SIZE_64K ; } + vma->page_sizes.gtt |= page_size; + }while (iter->sg); }
@@ -1170,6 +1175,8 @@ static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,while (gen8_ppgtt_insert_pte_entries (ppgtt, pdps[idx.pml4e++], &iter, &idx, cache_level))GEM_BUG_ON (idx.pml4e >=GEN8_PML4ES_PER_PML4 ); + + vma->page_sizes.gtt =I915_GTT_PAGE_SIZE ; } }
@@ -1891,6 +1898,8 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, } }while (1 );kunmap_atomic (vaddr); + + vma->page_sizes.gtt =I915_GTT_PAGE_SIZE ; } static int gen6_alloc_va_range(struct i915_address_space *vm,
@@ -2581,6 +2590,8 @@ static int ggtt_bind_vma(struct i915_vma *vma, vma->vm->insert_entries (vma->vm, vma, cache_level, pte_flags);intel_runtime_pm_put (i915); + vma->page_sizes.gtt =I915_GTT_PAGE_SIZE ; +/* * Without aliasing PPGTT there's no difference between * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
drivers/gpu/drm/i915/i915_gem_object.h +10 -0
@@ -169,6 +169,7 @@ struct drm_i915_gem_object {struct sg_table *pages;void *mapping; +/* TODO: whack some of this into the error state */ struct i915_page_sizes {/** * The sg mask of the pages sg_table. i.e the mask of
@@ -184,6 +185,15 @@ struct drm_i915_gem_object {* to use opportunistically. */ unsigned int sg; + +/** +* The actual gtt page size usage. Since we can have +* multiple vma associated with this object we need to +* prevent any trampling of state, hence a copy of this +* struct also lives in each vma, therefore the gtt +* value here should only be read/write through the vma. +*/ +unsigned int gtt; } page_sizes;struct i915_gem_object_page_iter {
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Re: [PATCH 15/21] drm/i915: accurate page size tracking for the ppgtt
Quoting Matthew Auld (2017-09-22 18:32:46)
Quoted 2 lines
Now that we support multiple page sizes for the ppgtt, it would be useful to track the real usage for debugging purposes.
Now? I kind of think knowing as we add the different support is interesting.
Quoted 22 lines
Signed-off-by Matthew Auld <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Chris Wilson <[email protected]>--- drivers/gpu/drm/i915/i915_gem_gtt.c | 11 +++++++++++ drivers/gpu/drm/i915/i915_gem_object.h | 10 ++++++++++ 2 files changed, 21 insertions(+)drivers/gpu/drm/i915/i915_gem_gtt.c +2
-0@@ -1052,6 +1052,8 @@ static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm,gen8_ppgtt_insert_pte_entries (ppgtt, &ppgtt->pdp, &iter, &idx, cache_level); + + vma->page_sizes.gtt =I915_GTT_PAGE_SIZE ; } static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
drivers/gpu/drm/i915/i915_gem_gtt.c static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma, · line 1153
Quoted 8 lines
drivers/gpu/drm/i915/i915_gem_gtt.c +3
-0@@ -1144,8 +1146,11 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma, vaddr =kmap_atomic_px (pd); vaddr[idx.pde] |=GEN8_PDE_IPS_64K ;kunmap_atomic (vaddr); + page_size =I915_GTT_PAGE_SIZE_64K ; } + vma->page_sizes.gtt |= page_size; +
* mutters.
Similarly, I hope you are keeping track of all the '/* blah'
-Chris
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PATCH 16/21 drm/i915/debugfs: include some gtt page size metrics
In reply to Matthew AuldGood to know, mostly for debugging purposes.
v2: some improvements from Chris
--- drivers/gpu/drm/i915/i915_debugfs.c | 61 ++++++++++++++++++++++++++++++++++--- 1 file changed, 57 insertions(+), 4 deletions(-)
drivers/gpu/drm/i915/i915_debugfs.c +57 -4
@@ -118,6 +118,36 @@ static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)return size; } +static const char * +stringify_page_sizes (unsigned int page_sizes,char *buf,size_t len) +{ +size_t x =0 ; + +switch (page_sizes) { +case 0 : +return "" ; +case I915_GTT_PAGE_SIZE_4K : +return "4K" ; +case I915_GTT_PAGE_SIZE_64K : +return "64K" ; +case I915_GTT_PAGE_SIZE_2M : +return "2M" ; +default : +if (!buf) +return "M" ; + +if (page_sizes &I915_GTT_PAGE_SIZE_2M ) + x +=snprintf (buf + x, len - x,"2M, " ); +if (page_sizes &I915_GTT_PAGE_SIZE_64K ) + x +=snprintf (buf + x, len - x,"64K, " ); +if (page_sizes &I915_GTT_PAGE_SIZE_4K ) + x +=snprintf (buf + x, len - x,"4K, " ); + buf[x-2 ] ='\0' ; + +return buf; + } +} +static void describe_obj (struct seq_file *m,struct drm_i915_gem_object *obj) {
@@ -155,9 +185,10 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)if (!drm_mm_node_allocated (&vma->node))continue ; -seq_printf (m," (%sgtt offset: %08llx, size: %08llx" , +seq_printf (m," (%sgtt offset: %08llx, size: %08llx, pages: %s" ,i915_vma_is_ggtt (vma) ?"g" :"pp" , - vma->node.start, vma->node.size); + vma->node.start, vma->node.size, +stringify_page_sizes (vma->page_sizes.gtt,NULL ,0 ));if (i915_vma_is_ggtt (vma)) {switch (vma->ggtt_view.type) {case I915_GGTT_VIEW_NORMAL :
@@ -402,10 +433,12 @@ static int i915_gem_object_info(struct seq_file *m, void *data)struct drm_i915_private *dev_priv =node_to_i915 (m->private);struct drm_device *dev = &dev_priv->drm;struct i915_ggtt *ggtt = &dev_priv->ggtt; -u32 count, mapped_count, purgeable_count, dpy_count; -u64 size, mapped_size, purgeable_size, dpy_size; +u32 count, mapped_count, purgeable_count, dpy_count, huge_count; +u64 size, mapped_size, purgeable_size, dpy_size, huge_size;struct drm_i915_gem_object *obj; +unsigned int page_sizes =0 ;struct drm_file *file; +char buf[80 ];int ret; ret =mutex_lock_interruptible (&dev->struct_mutex);
@@ -419,6 +452,7 @@ static int i915_gem_object_info(struct seq_file *m, void *data) size = count =0 ; mapped_size = mapped_count =0 ; purgeable_size = purgeable_count =0 ; + huge_size = huge_count =0 ;list_for_each_entry (obj, &dev_priv->mm.unbound_list, global_link) { size += obj->base.size; ++count;
@@ -432,6 +466,12 @@ static int i915_gem_object_info(struct seq_file *m, void *data) mapped_count++; mapped_size += obj->base.size; } + +if (obj->mm.page_sizes.sg >I915_GTT_PAGE_SIZE ) { + huge_count++; + huge_size += obj->base.size; + page_sizes |= obj->mm.page_sizes.sg; + } }seq_printf (m,"%u unbound objects, %llu bytes\n" , count, size);
@@ -454,6 +494,12 @@ static int i915_gem_object_info(struct seq_file *m, void *data) mapped_count++; mapped_size += obj->base.size; } + +if (obj->mm.page_sizes.sg >I915_GTT_PAGE_SIZE ) { + huge_count++; + huge_size += obj->base.size; + page_sizes |= obj->mm.page_sizes.sg; + } }seq_printf (m,"%u bound objects, %llu bytes\n" , count, size);
@@ -461,11 +507,18 @@ static int i915_gem_object_info(struct seq_file *m, void *data) purgeable_count, purgeable_size);seq_printf (m,"%u mapped objects, %llu bytes\n" , mapped_count, mapped_size); +seq_printf (m,"%u huge-paged objects (%s) %llu bytes\n" , + huge_count, +stringify_page_sizes (page_sizes, buf,sizeof (buf)), + huge_size);seq_printf (m,"%u display objects (pinned), %llu bytes\n" , dpy_count, dpy_size);seq_printf (m,"%llu [%llu] gtt total\n" , ggtt->base.total, ggtt->mappable_end); +seq_printf (m,"Supported page sizes: %s\n" , +stringify_page_sizes (INTEL_INFO (dev_priv)->page_sizes, + buf,sizeof (buf)));seq_putc (m,'\n' );print_batch_pool_stats (m, dev_priv);
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Re: [PATCH 16/21] drm/i915/debugfs: include some gtt page size metrics
Quoting Matthew Auld (2017-09-22 18:32:47)
Quoted 7 lines
Good to know, mostly for debugging purposes.
v2: some improvements from Chris
Signed-off-by Matthew Auld <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Chris Wilson <[email protected]>
-Chris
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PATCH 17/21 drm/i915/selftests: huge page tests
In reply to Matthew Auldv2: mock test page support configurations and add MI_STORE_DWORD test
v3: run all mockable huge page tests on all platforms via the mock_device
v4: add pin_update regression test
various improvements suggested by Chris
v5: fix issues reported by kbuild
test single sg spanning multiple page sizes
don't explode when running the live-tests through the appgtt
v6: lots of improvements from Chris
--- drivers/gpu/drm/i915/i915_gem.c | 1 + drivers/gpu/drm/i915/i915_gem_object.h | 2 + drivers/gpu/drm/i915/selftests/huge_pages.c | 1636 ++++++++++++++++++++ .../gpu/drm/i915/selftests/i915_live_selftests.h | 1 + .../gpu/drm/i915/selftests/i915_mock_selftests.h | 1 + 5 files changed, 1641 insertions(+) create mode 100644 drivers/gpu/drm/i915/selftests/huge_pages.c
drivers/gpu/drm/i915/i915_gem.c +1 -0
@@ -5419,6 +5419,7 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align)#include "selftests/scatterlist.c" #include "selftests/mock_gem_device.c" #include "selftests/huge_gem_object.c" +#include "selftests/huge_pages.c" #include "selftests/i915_gem_object.c" #include "selftests/i915_gem_coherency.c" #endif
drivers/gpu/drm/i915/i915_gem_object.h +2 -0
@@ -196,6 +196,8 @@ struct drm_i915_gem_object {unsigned int gtt; } page_sizes; + I915_SELFTEST_DECLARE(unsigned int page_mask); +struct i915_gem_object_page_iter {struct scatterlist *sg_pos;unsigned int sg_idx;/* in pages, but 32bit eek! */
drivers/gpu/drm/i915/selftests/huge_pages.c new file +1636 -0
1,636 lines not on this page · raw message
drivers/gpu/drm/i915/selftests/i915_live_selftests.h +1 -0
@@ -15,5 +15,6 @@ selftest(objects, i915_gem_object_live_selftests) selftest(dmabuf, i915_gem_dmabuf_live_selftests) selftest(coherency, i915_gem_coherency_live_selftests) selftest(gtt, i915_gem_gtt_live_selftests) +selftest(hugepages, i915_gem_huge_page_live_selftests) selftest(contexts, i915_gem_context_live_selftests)selftest (hangcheck, intel_hangcheck_live_selftests)
drivers/gpu/drm/i915/selftests/i915_mock_selftests.h +1 -0
@@ -21,3 +21,4 @@ selftest(dmabuf, i915_gem_dmabuf_mock_selftests) selftest(vma, i915_vma_mock_selftests) selftest(evict, i915_gem_evict_mock_selftests) selftest(gtt, i915_gem_gtt_mock_selftests) +selftest (hugepages, i915_gem_huge_page_mock_selftests)
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Re: [PATCH 17/21] drm/i915/selftests: huge page tests
Quoting Matthew Auld (2017-09-22 18:32:48)
Quoted 46 lines
drivers/gpu/drm/i915/selftests/huge_pages.c new file +46
-0+static int igt_write_huge (struct drm_i915_gem_object *obj) +{ +struct drm_i915_private *i915 =to_i915 (obj->base.dev); +struct i915_gem_context *ctx = i915->kernel_context; +struct i915_address_space *vm = ctx->ppgtt ? &ctx->ppgtt->base : &i915->ggtt.base; +struct i915_vma *vma; +unsigned int flags =PIN_USER |PIN_OFFSET_FIXED ; +unsigned int max_page_size; +IGT_TIMEOUT (end_time); +u32 max; +u32 num; +u64 size; +int err; + +GEM_BUG_ON (!i915_gem_object_has_pinned_pages (obj)); + + size = obj->base.size; +if (obj->mm.page_sizes.sg &I915_GTT_PAGE_SIZE_64K ) + size =round_up (size,I915_GTT_PAGE_SIZE_2M ); + + max_page_size =rounddown_pow_of_two (obj->mm.page_sizes.sg); + max = (vm->total - size) / max_page_size; + + vma =i915_vma_instance (obj, vm,NULL ); +if (IS_ERR (vma)) +return PTR_ERR (vma); + +/* Try various offsets until we timeout -- we want to avoid +* issues hidden by effectively always using offset = 0. +*/ +for_each_prime_number_from (num,0 , max) { +u64 offset = num * max_page_size; +u32 dword; + + err =i915_vma_unbind (vma); +if (err) + goto out_vma_close; + + err =i915_vma_pin (vma, size, max_page_size, flags | offset); +if (err) { +/* The ggtt may have some pages reserved so +* refrain from erroring out. +*/ +if (err == -ENOSPC &&i915_is_ggtt (vm)) +continue ; +
drivers/gpu/drm/i915/selftests/huge_pages.c line 1098
Quoted 10 lines
drivers/gpu/drm/i915/selftests/huge_pages.c new file +10
-0+ goto out_vma_close; + } + + err =igt_check_page_sizes (vma); +if (err) + goto out_vma_unpin; + + dword =offset_in_page (num) /4 ; + + err =gpu_write (vma, ctx, dword, num +1 );
We are restricting ourselves to only testing RCS. That feels like an oversight; RCS tends to have special page table handling which may mean we miss a bug on xCS. I would run each engine for timeout. -Chris
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PATCH 18/21 drm/i915/selftests: mix huge pages
In reply to Matthew AuldTry to mix sg page sizes for 4K, 64K and 2M pages.
v2: s/BIT(x) >> 12/BIT(x) >> PAGE_SHIFT/
--- drivers/gpu/drm/i915/selftests/scatterlist.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
drivers/gpu/drm/i915/selftests/scatterlist.c +15 -0
@@ -189,6 +189,20 @@ static unsigned int random(unsigned long n,return 1 + (prandom_u32_state (rnd) %1024 ); } +static unsigned int random_page_size_pages (unsigned long n, +unsigned long count, +struct rnd_state *rnd) +{ +/* 4K, 64K, 2M */ +static unsigned int page_count[] = { +BIT (12 ) >>PAGE_SHIFT , +BIT (16 ) >>PAGE_SHIFT , +BIT (21 ) >>PAGE_SHIFT , + }; + +return page_count[(prandom_u32_state (rnd) %3 )]; +} +static inline bool page_contiguous (struct page *first,struct page *last,unsigned long npages)
@@ -252,6 +266,7 @@ static const npages_fn_t npages_funcs[] = { grow, shrink, random, + random_page_size_pages, NULL, };
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Re: [PATCH 18/21] drm/i915/selftests: mix huge pages
Quoting Matthew Auld (2017-09-22 18:32:49)
Quoted 8 lines
Try to mix sg page sizes for 4K, 64K and 2M pages.
v2: s/BIT(x) >> 12/BIT(x) >> PAGE_SHIFT/
Suggested-by Chris Wilson <[email protected]>Signed-off-by Matthew Auld <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Chris Wilson <[email protected]>
-Chris
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PATCH 19/21 drm/i915: disable platform support for vGPU huge gtt pages
In reply to Matthew AuldCurrently gvt gtt handling doesn't support huge page entries, so disable for now.
v2: remove useless 48b PPGTT check
--- drivers/gpu/drm/i915/i915_gem.c | 8 ++++++++ 1 file changed, 8 insertions(+)
drivers/gpu/drm/i915/i915_gem.c +8 -0
@@ -4831,6 +4831,14 @@ int i915_gem_init(struct drm_i915_private *dev_priv)mutex_lock (&dev_priv->drm.struct_mutex); +/* We need to fallback to 4K pages since gvt gtt handling doesn't +* support huge page entries - we will need to check either hypervisor +* mm can support huge guest page or just do emulation in gvt. +*/ +if (intel_vgpu_active (dev_priv)) +mkwrite_device_info (dev_priv)->page_sizes = +I915_GTT_PAGE_SIZE_4K ; + dev_priv->mm.unordered_timeline =dma_fence_context_alloc (1 );if (!i915_modparams.enable_execlists) {
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Re: [PATCH 19/21] drm/i915: disable platform support for vGPU huge gtt pages
Quoted 36 lines · Matthew Auld
Currently gvt gtt handling doesn't support huge page entries, so disable for now.
v2: remove useless 48b PPGTT check
Suggested-by Zhenyu Wang <[email protected]>Signed-off-by Matthew Auld <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Chris Wilson <[email protected]>Cc Zhenyu Wang <[email protected]>--- drivers/gpu/drm/i915/i915_gem.c | 8 ++++++++ 1 file changed, 8 insertions(+)drivers/gpu/drm/i915/i915_gem.c +8
-0@@ -4831,6 +4831,14 @@ int i915_gem_init(struct drm_i915_private *dev_priv)mutex_lock (&dev_priv->drm.struct_mutex); +/* We need to fallback to 4K pages since gvt gtt handling doesn't +* support huge page entries - we will need to check either hypervisor +* mm can support huge guest page or just do emulation in gvt. +*/ +if (intel_vgpu_active (dev_priv)) +mkwrite_device_info (dev_priv)->page_sizes = +I915_GTT_PAGE_SIZE_4K ; + dev_priv->mm.unordered_timeline =dma_fence_context_alloc (1 );if (!i915_modparams.enable_execlists) {Signature · 1 line
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Re: [PATCH 19/21] drm/i915: disable platform support for vGPU huge gtt pages
In reply to Matthew AuldQuoting Matthew Auld (2017-09-22 18:32:50)
Quoted 10 lines
Currently gvt gtt handling doesn't support huge page entries, so disable for now.
v2: remove useless 48b PPGTT check
Suggested-by Zhenyu Wang <[email protected]>Signed-off-by Matthew Auld <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Chris Wilson <[email protected]>Cc Zhenyu Wang <[email protected]>
-Chris
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PATCH 20/21 drm/i915: enable platform support for 64K pages
In reply to Matthew AuldFor gen9+ enable platform level support for 64K pages. Also enable for mock testing.
--- drivers/gpu/drm/i915/i915_pci.c | 3 ++- drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/i915_pci.c +2 -1
@@ -434,7 +434,8 @@ static const struct intel_device_info intel_cherryview_info __initconst = { };#define GEN9_DEFAULT_PAGE_SIZES \ - .page_sizes = I915_GTT_PAGE_SIZE_4K + .page_sizes = I915_GTT_PAGE_SIZE_4K | \ + I915_GTT_PAGE_SIZE_64K#define SKL_PLATFORM \ BDW_FEATURES, \
drivers/gpu/drm/i915/selftests/mock_gem_device.c +2 -1
@@ -175,7 +175,8 @@ struct drm_i915_private *mock_gem_device(void)mkwrite_device_info (i915)->gen =-1 ;mkwrite_device_info (i915)->page_sizes = -I915_GTT_PAGE_SIZE_4K ; +I915_GTT_PAGE_SIZE_4K | +I915_GTT_PAGE_SIZE_64K ;spin_lock_init (&i915->mm.object_stat_lock);mock_uncore_init (i915);
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Re: [PATCH 20/21] drm/i915: enable platform support for 64K pages
Quoting Matthew Auld (2017-09-22 18:32:51)
Quoted 6 lines
For gen9+ enable platform level support for 64K pages. Also enable for mock testing.
Signed-off-by Matthew Auld <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Chris Wilson <[email protected]>
-Chris
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PATCH 21/21 drm/i915: enable platform support for 2M pages
In reply to Matthew AuldFor gen8+ platforms which support the 48b PPGTT, enable platform level support for 2M pages. Also enable for mock testing.
--- drivers/gpu/drm/i915/i915_pci.c | 6 ++++-- drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 ++- 2 files changed, 6 insertions(+), 3 deletions(-)
drivers/gpu/drm/i915/i915_pci.c +4 -2
@@ -374,7 +374,8 @@ static const struct intel_device_info intel_haswell_gt3_info __initconst = {#define BDW_FEATURES \ HSW_FEATURES, \ BDW_COLORS, \ - GEN_DEFAULT_PAGE_SIZES, \ + .page_sizes = I915_GTT_PAGE_SIZE_4K | \ + I915_GTT_PAGE_SIZE_2M, \ .has_logical_ring_contexts = 1, \ .has_full_48bit_ppgtt = 1, \ .has_64bit_reloc = 1, \
@@ -435,7 +436,8 @@ static const struct intel_device_info intel_cherryview_info __initconst = {#define GEN9_DEFAULT_PAGE_SIZES \ .page_sizes = I915_GTT_PAGE_SIZE_4K | \ - I915_GTT_PAGE_SIZE_64K + I915_GTT_PAGE_SIZE_64K | \ + I915_GTT_PAGE_SIZE_2M#define SKL_PLATFORM \ BDW_FEATURES, \
drivers/gpu/drm/i915/selftests/mock_gem_device.c +2 -1
@@ -176,7 +176,8 @@ struct drm_i915_private *mock_gem_device(void)mkwrite_device_info (i915)->page_sizes =I915_GTT_PAGE_SIZE_4K | -I915_GTT_PAGE_SIZE_64K ; +I915_GTT_PAGE_SIZE_64K | +I915_GTT_PAGE_SIZE_2M ;spin_lock_init (&i915->mm.object_stat_lock);mock_uncore_init (i915);
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Re: [PATCH 21/21] drm/i915: enable platform support for 2M pages
Quoting Matthew Auld (2017-09-22 18:32:52)
Quoted 6 lines
For gen8+ platforms which support the 48b PPGTT, enable platform level support for 2M pages. Also enable for mock testing.
Signed-off-by Matthew Auld <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Chris Wilson <[email protected]>
-Chris
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Patchwork
CI✓ Fi.CI.BAT: success for huge gtt pages (rev8)
In reply to Matthew Auld== Series Details ==
== Series Details ==
Series: huge gtt pages (rev8)
URL : https://patchwork.freedesktop.org/series/25118/
State : success
== Summary ==
Series 25118v8 huge gtt pages
https://patchwork.freedesktop.org/api/1.0/series/25118/revisions/8/mbox/
Test chamelium:
Subgroup common-hpd-after-suspend:
dmesg-warn -> INCOMPLETE (fi-kbl-7500u) fdo#102505
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass -> FAIL (fi-snb-2600) fdo#100215
Test drv_module_reload:
Subgroup basic-no-display:
dmesg-warn -> PASS (fi-glk-1) fdo#102777fdo#102505 https://bugs.freedesktop.org/show_bug.cgi?id=102505
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:441s fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:468s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:422s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:524s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:273s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:497s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:497s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:490s fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:538s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:419s fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:567s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:431s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:405s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:434s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:493s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:466s fi-kbl-7500u total:9 pass:3 dwarn:0 dfail:0 fail:0 skip:5 fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:579s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:583s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:541s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:458s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:752s fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:489s fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:473s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:568s fi-snb-2600 total:289 pass:248 dwarn:0 dfail:0 fail:2 skip:39 time:418s
e0e308721fd283e1c5777657a5941f178f0d49e6 drm-tip: 2017y-09m-22d-13h-31m-38s UTC integration manifest fafcc7641de1 drm/i915: enable platform support for 2M pages0843fe3f3920 drm/i915: enable platform support for 64K pages4789d9fc4867 drm/i915: disable platform support for vGPU huge gtt pages6fd60979baf8 drm/i915/selftests: mix huge pagesf55bd2a1bc16 drm/i915/selftests: huge page tests9d27d66adbaa drm/i915/debugfs: include some gtt page size metrics78507af39439 drm/i915: accurate page size tracking for the ppgttb9d8182acd0e drm/i915: support 64K pages for the 48b PPGTTad258a420212 drm/i915: add support for 64K scratch pagec85ffe144db8 drm/i915: support 2M pages for the 48b PPGTTb2a0ef69b032 drm/i915: disable GTT cache for 2M pages3ecbcf4bae2e drm/i915: enable IPS bit for 64K pages921f83b3b726 drm/i915: align 64K objects to 2M3bc740d468a9 drm/i915: align the vma start to the largest gtt page size406d01e9a408 drm/i915: introduce vm set_pages/clear_pages4f583f3fa7d3 drm/i915: introduce page_size members1d8bc4028cc3 drm/i915: push set_pages down to the callersa4a00da9f6e4 drm/i915: introduce page_sizes field to dev_info2b4997d0cf32 drm/i915/gemfs: enable THP34579418914a drm/i915: introduce simple gemfsa20198f8fbe2 mm/shmem: introduce shmem_file_setup_with_mnt
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5796/
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Patchwork
CI✗ Fi.CI.IGT: failure for huge gtt pages (rev8)
In reply to Matthew Auld== Series Details ==
== Series Details ==
Series: huge gtt pages (rev8)
URL : https://patchwork.freedesktop.org/series/25118/
State : failure
== Summary ==
Test perf:
Subgroup blocking:
pass -> FAIL (shard-hsw) fdo#102252
Test kms_flip:
Subgroup plain-flip-ts-check-interruptible:
pass -> FAIL (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-indfb-draw-blt:
skip -> PASS (shard-hsw)
Test gem_flink_race:
Subgroup flink_close:
fail -> PASS (shard-hsw) fdo#102655fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102655 https://bugs.freedesktop.org/show_bug.cgi?id=102655
shard-hsw total:2429 pass:1334 dwarn:1 dfail:0 fail:11 skip:1083 time:9812s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5796/shards.html
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