drm/amdgpu: replace dev_* with DRM_DEV_* equivalents

index a52795d..c59b701 100644
@@ -245,7 +245,7 @@ static struct device *get_mfd_cell_dev(const char *device_name, int r)
 	snprintf(auto_dev_name, sizeof(auto_dev_name),
 		 "%s.%d.auto", device_name, r);
 	dev = bus_find_device_by_name(&platform_bus_type, NULL, auto_dev_name);
-	dev_info(dev, "device %s added to pm domain\n", auto_dev_name);
+	DRM_DEV_INFO(dev, "device %s added to pm domain\n", auto_dev_name);
 
 	return dev;
 }

@@ -394,7 +394,7 @@ static int acp_hw_init(void *handle)
 			dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
 			r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev);
 			if (r) {
-				dev_err(dev, "Failed to add dev to genpd\n");
+				DRM_DEV_ERROR(dev, "Failed to add dev to genpd\n");
 				return r;
 			}
 		}

@@ -425,7 +425,7 @@ static int acp_hw_fini(void *handle)
 			ret = pm_genpd_remove_device(&adev->acp.acp_genpd->gpd, dev);
 			/* If removal fails, dont giveup and try rest */
 			if (ret)
-				dev_err(dev, "remove dev from genpd failed\n");
+				DRM_DEV_ERROR(dev, "remove dev from genpd failed\n");
 		}
 		kfree(adev->acp.acp_genpd);
 	}

index 5432af3..ad1a19f2 100644
@@ -85,7 +85,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
 		kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
 		break;
 	default:
-		dev_info(adev->dev, "kfd not supported on this ASIC\n");
+		DRM_DEV_INFO(adev->dev, "kfd not supported on this ASIC\n");
 		return;
 	}
 

@@ -186,7 +186,7 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
 			     AMDGPU_GEM_CREATE_CPU_GTT_USWC, NULL, NULL, 0,
 			     &(*mem)->bo);
 	if (r) {
-		dev_err(adev->dev,
+		DRM_DEV_ERROR(adev->dev,
 			"failed to allocate BO for amdkfd (%d)\n", r);
 		return r;
 	}

@@ -194,21 +194,21 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
 	/* map the buffer */
 	r = amdgpu_bo_reserve((*mem)->bo, true);
 	if (r) {
-		dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
 		goto allocate_mem_reserve_bo_failed;
 	}
 
 	r = amdgpu_bo_pin((*mem)->bo, AMDGPU_GEM_DOMAIN_GTT,
 				&(*mem)->gpu_addr);
 	if (r) {
-		dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
 		goto allocate_mem_pin_bo_failed;
 	}
 	*gpu_addr = (*mem)->gpu_addr;
 
 	r = amdgpu_bo_kmap((*mem)->bo, &(*mem)->cpu_ptr);
 	if (r) {
-		dev_err(adev->dev,
+		DRM_DEV_ERROR(adev->dev,
 			"(%d) failed to map bo to kernel for amdkfd\n", r);
 		goto allocate_mem_kmap_bo_failed;
 	}

176 lines not on this page · raw message

index 6ad2432..dec1a78 100644
@@ -529,7 +529,7 @@ amdgpu_user_framebuffer_create(struct drm_device *dev,
 
 	obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
 	if (obj ==  NULL) {
-		dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
+		DRM_DEV_ERROR(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
 			"can't create framebuffer\n", mode_cmd->handles[0]);
 		return ERR_PTR(-ENOENT);
 	}

index 9afa9c0..7ec3ff8 100644
@@ -167,7 +167,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
 		ret = amdgpu_bo_set_tiling_flags(abo,
 						 tiling_flags);
 		if (ret)
-			dev_err(adev->dev, "FB failed to set tiling flags\n");
+			DRM_DEV_ERROR(adev->dev, "FB failed to set tiling flags\n");
 	}
 
 

index 333bad7..e926962 100644
@@ -340,7 +340,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
 	ring->fence_drv.irq_type = irq_type;
 	ring->fence_drv.initialized = true;
 
-	dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
+	DRM_DEV_INFO(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
 		 "cpu addr 0x%p\n", ring->idx,
 		 ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
 	return 0;

@@ -423,7 +423,7 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
 int amdgpu_fence_driver_init(struct amdgpu_device *adev)
 {
 	if (amdgpu_debugfs_fence_init(adev))
-		dev_err(adev->dev, "fence debugfs file creation failed\n");
+		DRM_DEV_ERROR(adev->dev, "fence debugfs file creation failed\n");
 
 	return 0;
 }

index 7171968..9e8682e 100644
@@ -181,7 +181,7 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
 
 	r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
 	if (r) {
-		dev_err(adev->dev, "leaking bo va because "
+		DRM_DEV_ERROR(adev->dev, "leaking bo va because "
 			"we fail to reserve bo (%d)\n", r);
 		return;
 	}

@@ -194,7 +194,7 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
 
 			r = amdgpu_vm_clear_freed(adev, vm, &fence);
 			if (unlikely(r)) {
-				dev_err(adev->dev, "failed to clear page "
+				DRM_DEV_ERROR(adev->dev, "failed to clear page "
 					"tables on GEM object close (%d)\n", r);
 			}
 

@@ -556,7 +556,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 	int r = 0;
 
 	if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
-		dev_err(&dev->pdev->dev,
+		DRM_DEV_ERROR(&dev->pdev->dev,
 			"va_address 0x%lX is in reserved area 0x%X\n",
 			(unsigned long)args->va_address,
 			AMDGPU_VA_RESERVED_SIZE);

@@ -564,7 +564,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 	}
 
 	if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
-		dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
+		DRM_DEV_ERROR(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
 			args->flags);
 		return -EINVAL;
 	}

@@ -576,7 +576,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 	case AMDGPU_VA_OP_REPLACE:
 		break;
 	default:
-		dev_err(&dev->pdev->dev, "unsupported operation %d\n",
+		DRM_DEV_ERROR(&dev->pdev->dev, "unsupported operation %d\n",
 			args->operation);
 		return -EINVAL;
 	}

index 4f6c68f..9d2f793 100644
@@ -174,7 +174,7 @@ static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
 		return 0;
 	}
 
-	dev_err(adev->dev, "Failed to find a queue for KIQ\n");
+	DRM_DEV_ERROR(adev->dev, "Failed to find a queue for KIQ\n");
 	return -EINVAL;
 }
 

index 659997b..d8a06a1 100644
@@ -66,7 +66,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 		r = amdgpu_sa_bo_new(&adev->ring_tmp_bo,
 				      &ib->sa_bo, size, 256);
 		if (r) {
-			dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
+			DRM_DEV_ERROR(adev->dev, "failed to get a new IB (%d)\n", r);
 			return r;
 		}
 

@@ -145,12 +145,12 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	}
 
 	if (!ring->ready) {
-		dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name);
+		DRM_DEV_ERROR(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name);
 		return -EINVAL;
 	}
 
 	if (vm && !job->vm_id) {
-		dev_err(adev->dev, "VM IB without ID\n");
+		DRM_DEV_ERROR(adev->dev, "VM IB without ID\n");
 		return -EINVAL;
 	}
 

@@ -159,7 +159,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 
 	r = amdgpu_ring_alloc(ring, alloc_size);
 	if (r) {
-		dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
+		DRM_DEV_ERROR(adev->dev, "scheduling IB failed (%d).\n", r);
 		return r;
 	}
 

@@ -228,7 +228,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 
 	r = amdgpu_fence_emit(ring, f);
 	if (r) {
-		dev_err(adev->dev, "failed to emit fence (%d)\n", r);
+		DRM_DEV_ERROR(adev->dev, "failed to emit fence (%d)\n", r);
 		if (job && job->vm_id)
 			amdgpu_vm_reset_id(adev, ring->funcs->vmhub,
 					   job->vm_id);

@@ -286,7 +286,7 @@ int amdgpu_ib_pool_init(struct amdgpu_device *adev)
 
 	adev->ib_pool_ready = true;
 	if (amdgpu_debugfs_sa_init(adev)) {
-		dev_err(adev->dev, "failed to register debugfs file for SA\n");
+		DRM_DEV_ERROR(adev->dev, "failed to register debugfs file for SA\n");
 	}
 	return 0;
 }

index 3ab4c65..134c09b 100644
@@ -94,14 +94,14 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
 	} else {
 		r = amdgpu_wb_get(adev, &adev->irq.ih.wptr_offs);
 		if (r) {
-			dev_err(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r);
+			DRM_DEV_ERROR(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r);
 			return r;
 		}
 
 		r = amdgpu_wb_get(adev, &adev->irq.ih.rptr_offs);
 		if (r) {
 			amdgpu_wb_free(adev, adev->irq.ih.wptr_offs);
-			dev_err(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r);
+			DRM_DEV_ERROR(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r);
 			return r;
 		}
 

index 538e5f2..9cbd4bb 100644
@@ -237,7 +237,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
 		int ret = pci_enable_msi(adev->pdev);
 		if (!ret) {
 			adev->irq.msi_enabled = true;
-			dev_info(adev->dev, "amdgpu: using MSI.\n");
+			DRM_DEV_INFO(adev->dev, "amdgpu: using MSI.\n");
 		}
 	}
 

index e162290..5e2f59a 100644
@@ -95,9 +95,9 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
 		case CHIP_VERDE:
 		case CHIP_OLAND:
 		case CHIP_HAINAN:
-			dev_info(dev->dev,
+			DRM_DEV_INFO(dev->dev,
 				 "SI support provided by radeon.\n");
-			dev_info(dev->dev,
+			DRM_DEV_INFO(dev->dev,
 				 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
 				);
 			return -ENODEV;

@@ -112,9 +112,9 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
 		case CHIP_HAWAII:
 		case CHIP_KABINI:
 		case CHIP_MULLINS:
-			dev_info(dev->dev,
+			DRM_DEV_INFO(dev->dev,
 				 "CIK support provided by radeon.\n");
-			dev_info(dev->dev,
+			DRM_DEV_INFO(dev->dev,
 				 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
 				);
 			return -ENODEV;

@@ -144,7 +144,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
 	 */
 	r = amdgpu_device_init(adev, dev, dev->pdev, flags);
 	if (r) {
-		dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
+		DRM_DEV_ERROR(&dev->pdev->dev, "Fatal error during GPU init\n");
 		goto out;
 	}
 

@@ -154,7 +154,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
 	if (!r) {
 		acpi_status = amdgpu_acpi_init(adev);
 		if (acpi_status)
-		dev_dbg(&dev->pdev->dev,
+		DRM_DEV_DEBUG(&dev->pdev->dev,
 				"Error during ACPI methods call\n");
 	}
 

index 9e495da..1ea977f 100644
@@ -202,7 +202,7 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
 				     AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 				     NULL, NULL, 0, bo_ptr);
 		if (r) {
-			dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
+			DRM_DEV_ERROR(adev->dev, "(%d) failed to allocate kernel bo\n",
 				r);
 			return r;
 		}

@@ -211,20 +211,20 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
 
 	r = amdgpu_bo_reserve(*bo_ptr, false);
 	if (r) {
-		dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) failed to reserve kernel bo\n", r);
 		goto error_free;
 	}
 
 	r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
 	if (r) {
-		dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) kernel bo pin failed\n", r);
 		goto error_unreserve;
 	}
 
 	if (cpu_addr) {
 		r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
 		if (r) {
-			dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
+			DRM_DEV_ERROR(adev->dev, "(%d) kernel bo map failed\n", r);
 			goto error_unreserve;
 		}
 	}

@@ -730,7 +730,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 
 	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 	if (unlikely(r)) {
-		dev_err(adev->dev, "%p pin failed\n", bo);
+		DRM_DEV_ERROR(adev->dev, "%p pin failed\n", bo);
 		goto error;
 	}
 

@@ -738,7 +738,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 	if (gpu_addr != NULL) {
 		r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
 		if (unlikely(r)) {
-			dev_err(adev->dev, "%p bind failed\n", bo);
+			DRM_DEV_ERROR(adev->dev, "%p bind failed\n", bo);
 			goto error;
 		}
 		*gpu_addr = amdgpu_bo_gpu_offset(bo);

@@ -778,7 +778,7 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 	}
 	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 	if (unlikely(r)) {
-		dev_err(adev->dev, "%p validate failed for unpin\n", bo);
+		DRM_DEV_ERROR(adev->dev, "%p validate failed for unpin\n", bo);
 		goto error;
 	}
 

index 7df503a..dfb6254 100644
@@ -1363,7 +1363,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 								   hwmon_groups);
 	if (IS_ERR(adev->pm.int_hwmon_dev)) {
 		ret = PTR_ERR(adev->pm.int_hwmon_dev);
-		dev_err(adev->dev,
+		DRM_DEV_ERROR(adev->dev,
 			"Unable to register hwmon device: %d\n", ret);
 		return ret;
 	}

index 5ce6528..2d5b2e9 100644
@@ -195,25 +195,25 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
 
 	r = amdgpu_wb_get(adev, &ring->rptr_offs);
 	if (r) {
-		dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
 		return r;
 	}
 
 	r = amdgpu_wb_get(adev, &ring->wptr_offs);
 	if (r) {
-		dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
 		return r;
 	}
 
 	r = amdgpu_wb_get(adev, &ring->fence_offs);
 	if (r) {
-		dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
 		return r;
 	}
 
 	r = amdgpu_wb_get(adev, &ring->cond_exe_offs);
 	if (r) {
-		dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
 		return r;
 	}
 	ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);

@@ -223,7 +223,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
 
 	r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
 	if (r) {
-		dev_err(adev->dev, "failed initializing fences (%d).\n", r);
+		DRM_DEV_ERROR(adev->dev, "failed initializing fences (%d).\n", r);
 		return r;
 	}
 

@@ -240,7 +240,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
 					    &ring->gpu_addr,
 					    (void **)&ring->ring);
 		if (r) {
-			dev_err(adev->dev, "(%d) ring create failed\n", r);
+			DRM_DEV_ERROR(adev->dev, "(%d) ring create failed\n", r);
 			return r;
 		}
 		amdgpu_ring_clear_ring(ring);

index 3144400..66f5b98 100644
@@ -66,7 +66,7 @@ int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
 	r = amdgpu_bo_create(adev, size, align, true, domain,
 			     0, NULL, NULL, 0, &sa_manager->bo);
 	if (r) {
-		dev_err(adev->dev, "(%d) failed to allocate bo for manager\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) failed to allocate bo for manager\n", r);
 		return r;
 	}
 

@@ -82,7 +82,7 @@ void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
 		sa_manager->hole = &sa_manager->olist,
 		amdgpu_sa_bo_try_free(sa_manager);
 		if (!list_empty(&sa_manager->olist)) {
-			dev_err(adev->dev, "sa_manager is not empty, clearing anyway\n");
+			DRM_DEV_ERROR(adev->dev, "sa_manager is not empty, clearing anyway\n");
 		}
 	}
 	list_for_each_entry_safe(sa_bo, tmp, &sa_manager->olist, olist) {

@@ -98,20 +98,20 @@ int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
 	int r;
 
 	if (sa_manager->bo == NULL) {
-		dev_err(adev->dev, "no bo for sa manager\n");
+		DRM_DEV_ERROR(adev->dev, "no bo for sa manager\n");
 		return -EINVAL;
 	}
 
 	/* map the buffer */
 	r = amdgpu_bo_reserve(sa_manager->bo, false);
 	if (r) {
-		dev_err(adev->dev, "(%d) failed to reserve manager bo\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) failed to reserve manager bo\n", r);
 		return r;
 	}
 	r = amdgpu_bo_pin(sa_manager->bo, sa_manager->domain, &sa_manager->gpu_addr);
 	if (r) {
 		amdgpu_bo_unreserve(sa_manager->bo);
-		dev_err(adev->dev, "(%d) failed to pin manager bo\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) failed to pin manager bo\n", r);
 		return r;
 	}
 	r = amdgpu_bo_kmap(sa_manager->bo, &sa_manager->cpu_ptr);

@@ -126,7 +126,7 @@ int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
 	int r;
 
 	if (sa_manager->bo == NULL) {
-		dev_err(adev->dev, "no bo for sa manager\n");
+		DRM_DEV_ERROR(adev->dev, "no bo for sa manager\n");
 		return -EINVAL;
 	}
 

index 36c7633..15b9466 100644
@@ -381,26 +381,26 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
 				AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 				NULL, NULL, 0, bo);
 	if (err) {
-		dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err);
+		DRM_DEV_ERROR(adev->dev, "(%d) Firmware buffer allocate failed\n", err);
 		goto failed;
 	}
 
 	err = amdgpu_bo_reserve(*bo, false);
 	if (err) {
-		dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err);
+		DRM_DEV_ERROR(adev->dev, "(%d) Firmware buffer reserve failed\n", err);
 		goto failed_reserve;
 	}
 
 	err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
 				&fw_mc_addr);
 	if (err) {
-		dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err);
+		DRM_DEV_ERROR(adev->dev, "(%d) Firmware buffer pin failed\n", err);
 		goto failed_pin;
 	}
 
 	err = amdgpu_bo_kmap(*bo, &fw_buf_ptr);
 	if (err) {
-		dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err);
+		DRM_DEV_ERROR(adev->dev, "(%d) Firmware buffer kmap failed\n", err);
 		goto failed_kmap;
 	}
 

index e19928d..c8ccee6 100644
@@ -173,14 +173,14 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
 
 	r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
 	if (r) {
-		dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
+		DRM_DEV_ERROR(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
 			fw_name);
 		return r;
 	}
 
 	r = amdgpu_ucode_validate(adev->uvd.fw);
 	if (r) {
-		dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
+		DRM_DEV_ERROR(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
 			fw_name);
 		release_firmware(adev->uvd.fw);
 		adev->uvd.fw = NULL;

@@ -225,7 +225,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
 				    AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.vcpu_bo,
 				    &adev->uvd.gpu_addr, &adev->uvd.cpu_addr);
 	if (r) {
-		dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) failed to allocate UVD bo\n", r);
 		return r;
 	}
 

index c855366..ea5c6e1 100644
@@ -140,14 +140,14 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
 
 	r = request_firmware(&adev->vce.fw, fw_name, adev->dev);
 	if (r) {
-		dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
+		DRM_DEV_ERROR(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
 			fw_name);
 		return r;
 	}
 
 	r = amdgpu_ucode_validate(adev->vce.fw);
 	if (r) {
-		dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
+		DRM_DEV_ERROR(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
 			fw_name);
 		release_firmware(adev->vce.fw);
 		adev->vce.fw = NULL;

@@ -169,7 +169,7 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
 				    AMDGPU_GEM_DOMAIN_VRAM, &adev->vce.vcpu_bo,
 				    &adev->vce.gpu_addr, &adev->vce.cpu_addr);
 	if (r) {
-		dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) failed to allocate VCE bo\n", r);
 		return r;
 	}
 

@@ -264,14 +264,14 @@ int amdgpu_vce_resume(struct amdgpu_device *adev)
 
 	r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
 	if (r) {
-		dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) failed to reserve VCE bo\n", r);
 		return r;
 	}
 
 	r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);
 	if (r) {
 		amdgpu_bo_unreserve(adev->vce.vcpu_bo);
-		dev_err(adev->dev, "(%d) VCE map failed\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) VCE map failed\n", r);
 		return r;
 	}
 

index 041e012..c1f05e3 100644
@@ -70,14 +70,14 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 
 	r = request_firmware(&adev->vcn.fw, fw_name, adev->dev);
 	if (r) {
-		dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n",
+		DRM_DEV_ERROR(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n",
 			fw_name);
 		return r;
 	}
 
 	r = amdgpu_ucode_validate(adev->vcn.fw);
 	if (r) {
-		dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n",
+		DRM_DEV_ERROR(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n",
 			fw_name);
 		release_firmware(adev->vcn.fw);
 		adev->vcn.fw = NULL;

@@ -99,7 +99,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 				    AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
 				    &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
 	if (r) {
-		dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) failed to allocate vcn bo\n", r);
 		return r;
 	}
 

index bd20ff0..c264a80 100644
@@ -363,7 +363,7 @@ int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
 	eaddr = saddr + size - 1;
 	last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
 	if (last_pfn >= adev->vm_manager.max_pfn) {
-		dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n",
+		DRM_DEV_ERROR(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n",
 			last_pfn, adev->vm_manager.max_pfn);
 		return -EINVAL;
 	}

@@ -2090,7 +2090,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
 	tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
 	if (tmp) {
 		/* bo and tmp overlap, invalid addr */
-		dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
+		DRM_DEV_ERROR(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
 			"0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
 			tmp->start, tmp->last + 1);
 		return -EINVAL;

@@ -2591,7 +2591,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 	amd_sched_entity_fini(vm->entity.sched, &vm->entity);
 
 	if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
-		dev_err(adev->dev, "still active bo inside vm\n");
+		DRM_DEV_ERROR(adev->dev, "still active bo inside vm\n");
 	}
 	rbtree_postorder_for_each_entry_safe(mapping, tmp,
 					     &vm->va.rb_root, rb) {

index 567c4a5..9485ee0 100644
@@ -1158,7 +1158,7 @@ static int cik_gpu_pci_config_reset(struct amdgpu_device *adev)
 	u32 i;
 	int r = -EINVAL;
 
-	dev_info(adev->dev, "GPU pci config reset\n");
+	DRM_DEV_INFO(adev->dev, "GPU pci config reset\n");
 
 	if (adev->flags & AMD_IS_APU)
 		kv_save_regs_for_reset(adev, &kv_save);

index b891843..0010624 100644
@@ -385,7 +385,7 @@ static int cik_ih_soft_reset(void *handle)
 	if (srbm_soft_reset) {
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 		tmp |= srbm_soft_reset;
-		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
+		DRM_DEV_INFO(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 		WREG32(mmSRBM_SOFT_RESET, tmp);
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 

index f508f4d..b066b6f 100644
@@ -628,7 +628,7 @@ static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
 
 	r = amdgpu_wb_get(adev, &index);
 	if (r) {
-		dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) failed to allocate wb slot\n", r);
 		return r;
 	}
 

@@ -688,7 +688,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 
 	r = amdgpu_wb_get(adev, &index);
 	if (r) {
-		dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 		return r;
 	}
 

@@ -1118,7 +1118,7 @@ static int cik_sdma_soft_reset(void *handle)
 	if (srbm_soft_reset) {
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 		tmp |= srbm_soft_reset;
-		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
+		DRM_DEV_INFO(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 		WREG32(mmSRBM_SOFT_RESET, tmp);
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 

index 0c1209c..88a4e89 100644
@@ -364,7 +364,7 @@ static int cz_ih_soft_reset(void *handle)
 	if (srbm_soft_reset) {
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 		tmp |= srbm_soft_reset;
-		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
+		DRM_DEV_INFO(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 		WREG32(mmSRBM_SOFT_RESET, tmp);
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 

index 4e519dc..d9b4e30 100644
@@ -2969,7 +2969,7 @@ static int dce_v10_0_soft_reset(void *handle)
 	if (srbm_soft_reset) {
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 		tmp |= srbm_soft_reset;
-		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
+		DRM_DEV_INFO(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 		WREG32(mmSRBM_SOFT_RESET, tmp);
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 

index 11edc75..37e8a84 100644
@@ -3088,7 +3088,7 @@ static int dce_v11_0_soft_reset(void *handle)
 	if (srbm_soft_reset) {
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 		tmp |= srbm_soft_reset;
-		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
+		DRM_DEV_INFO(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 		WREG32(mmSRBM_SOFT_RESET, tmp);
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 

index 9cf14b8..bcdd5a0 100644
@@ -2860,7 +2860,7 @@ static int dce_v8_0_soft_reset(void *handle)
 	if (srbm_soft_reset) {
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 		tmp |= srbm_soft_reset;
-		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
+		DRM_DEV_INFO(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 		WREG32(mmSRBM_SOFT_RESET, tmp);
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 

index 0086876..ccd10d7e 100644
@@ -4797,7 +4797,7 @@ static int gfx_v7_0_soft_reset(void *handle)
 		if (grbm_soft_reset) {
 			tmp = RREG32(mmGRBM_SOFT_RESET);
 			tmp |= grbm_soft_reset;
-			dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
+			DRM_DEV_INFO(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
 			WREG32(mmGRBM_SOFT_RESET, tmp);
 			tmp = RREG32(mmGRBM_SOFT_RESET);
 

@@ -4811,7 +4811,7 @@ static int gfx_v7_0_soft_reset(void *handle)
 		if (srbm_soft_reset) {
 			tmp = RREG32(mmSRBM_SOFT_RESET);
 			tmp |= srbm_soft_reset;
-			dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
+			DRM_DEV_INFO(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 			WREG32(mmSRBM_SOFT_RESET, tmp);
 			tmp = RREG32(mmSRBM_SOFT_RESET);
 

index fc260c1..a3e08f9 100644
@@ -1105,7 +1105,7 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
 
 out:
 	if (err) {
-		dev_err(adev->dev,
+		DRM_DEV_ERROR(adev->dev,
 			"gfx8: Failed to load firmware \"%s\"\n",
 			fw_name);
 		release_firmware(adev->gfx.pfp_fw);

@@ -5163,7 +5163,7 @@ static int gfx_v8_0_soft_reset(void *handle)
 	if (grbm_soft_reset) {
 		tmp = RREG32(mmGRBM_SOFT_RESET);
 		tmp |= grbm_soft_reset;
-		dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
+		DRM_DEV_INFO(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
 		WREG32(mmGRBM_SOFT_RESET, tmp);
 		tmp = RREG32(mmGRBM_SOFT_RESET);
 

@@ -5177,7 +5177,7 @@ static int gfx_v8_0_soft_reset(void *handle)
 	if (srbm_soft_reset) {
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 		tmp |= srbm_soft_reset;
-		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
+		DRM_DEV_INFO(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 		WREG32(mmSRBM_SOFT_RESET, tmp);
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 

index 69182ee..a48f4b3 100644
@@ -547,7 +547,7 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 
 out:
 	if (err) {
-		dev_err(adev->dev,
+		DRM_DEV_ERROR(adev->dev,
 			"gfx9: Failed to load firmware \"%s\"\n",
 			fw_name);
 		release_firmware(adev->gfx.pfp_fw);

@@ -780,7 +780,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
 					      &adev->gfx.rlc.clear_state_gpu_addr,
 					      (void **)&adev->gfx.rlc.cs_ptr);
 		if (r) {
-			dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
+			DRM_DEV_ERROR(adev->dev, "(%d) failed to create rlc csb bo\n",
 				r);
 			gfx_v9_0_rlc_fini(adev);
 			return r;

@@ -801,7 +801,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
 					      &adev->gfx.rlc.cp_table_gpu_addr,
 					      (void **)&adev->gfx.rlc.cp_table_ptr);
 		if (r) {
-			dev_err(adev->dev,
+			DRM_DEV_ERROR(adev->dev,
 				"(%d) failed to create cp table bo\n", r);
 			gfx_v9_0_rlc_fini(adev);
 			return r;

@@ -1018,7 +1018,7 @@ static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
 	int r;
 
 	if (size_se < 0) {
-		dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
+		DRM_DEV_ERROR(adev->dev, "Buffer size is invalid: %d\n", size_se);
 		return -EINVAL;
 	}
 	size_se = size_se ? size_se : default_size_se;

@@ -1030,7 +1030,7 @@ static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
 				    &ngg_buf->gpu_addr,
 				    NULL);
 	if (r) {
-		dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) failed to create NGG buffer\n", r);
 		return r;
 	}
 	ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);

@@ -1074,7 +1074,7 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
 				    amdgpu_prim_buf_per_se,
 				    64 * 1024);
 	if (r) {
-		dev_err(adev->dev, "Failed to create Primitive Buffer\n");
+		DRM_DEV_ERROR(adev->dev, "Failed to create Primitive Buffer\n");
 		goto err;
 	}
 

@@ -1083,7 +1083,7 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
 				    amdgpu_pos_buf_per_se,
 				    256 * 1024);
 	if (r) {
-		dev_err(adev->dev, "Failed to create Position Buffer\n");
+		DRM_DEV_ERROR(adev->dev, "Failed to create Position Buffer\n");
 		goto err;
 	}
 

@@ -1092,7 +1092,7 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
 				    amdgpu_cntl_sb_buf_per_se,
 				    256);
 	if (r) {
-		dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
+		DRM_DEV_ERROR(adev->dev, "Failed to create Control Sideband Buffer\n");
 		goto err;
 	}
 

@@ -1104,7 +1104,7 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
 				    amdgpu_param_buf_per_se,
 				    512 * 1024);
 	if (r) {
-		dev_err(adev->dev, "Failed to create Parameter Cache\n");
+		DRM_DEV_ERROR(adev->dev, "Failed to create Parameter Cache\n");
 		goto err;
 	}
 

@@ -2990,7 +2990,7 @@ static int gfx_v9_0_soft_reset(void *handle)
 		if (grbm_soft_reset) {
 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 			tmp |= grbm_soft_reset;
-			dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
+			DRM_DEV_INFO(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 

index 5be9c83..6959c30 100644
@@ -144,7 +144,7 @@ static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
 
 out:
 	if (err) {
-		dev_err(adev->dev,
+		DRM_DEV_ERROR(adev->dev,
 		       "si_mc: Failed to load firmware \"%s\"\n",
 		       fw_name);
 		release_firmware(adev->mc.fw);

@@ -481,7 +481,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 	u32 field;
 
 	if (adev->gart.robj == NULL) {
-		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
+		DRM_DEV_ERROR(adev->dev, "No VRAM object for PCIE GART.\n");
 		return -EINVAL;
 	}
 	r = amdgpu_gart_table_vram_pin(adev);

@@ -560,7 +560,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 		gmc_v6_0_set_fault_enable_default(adev, true);
 
 	gmc_v6_0_gart_flush_gpu_tlb(adev, 0);
-	dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
+	DRM_DEV_INFO(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
 		 (unsigned)(adev->mc.gart_size >> 20),
 		 (unsigned long long)adev->gart.table_addr);
 	adev->gart.ready = true;

@@ -635,7 +635,7 @@ static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
 	mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 			      MEMORY_CLIENT_ID);
 
-	dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
+	DRM_DEV_ERROR(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 	       protections, vmid, addr,
 	       REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 			     MEMORY_CLIENT_RW) ?

@@ -854,7 +854,7 @@ static int gmc_v6_0_sw_init(void *handle)
 
 	r = gmc_v6_0_init_microcode(adev);
 	if (r) {
-		dev_err(adev->dev, "Failed to load mc firmware!\n");
+		DRM_DEV_ERROR(adev->dev, "Failed to load mc firmware!\n");
 		return r;
 	}
 

@@ -915,7 +915,7 @@ static int gmc_v6_0_hw_init(void *handle)
 	if (!(adev->flags & AMD_IS_APU)) {
 		r = gmc_v6_0_mc_load_microcode(adev);
 		if (r) {
-			dev_err(adev->dev, "Failed to load MC firmware!\n");
+			DRM_DEV_ERROR(adev->dev, "Failed to load MC firmware!\n");
 			return r;
 		}
 	}

@@ -1012,7 +1012,7 @@ static int gmc_v6_0_soft_reset(void *handle)
 
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 		tmp |= srbm_soft_reset;
-		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
+		DRM_DEV_INFO(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 		WREG32(mmSRBM_SOFT_RESET, tmp);
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 

@@ -1085,11 +1085,11 @@ static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
 		gmc_v6_0_set_fault_enable_default(adev, false);
 
 	if (printk_ratelimit()) {
-		dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
+		DRM_DEV_ERROR(adev->dev, "GPU fault detected: %d 0x%08x\n",
 			entry->src_id, entry->src_data[0]);
-		dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
+		DRM_DEV_ERROR(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
 			addr);
-		dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
+		DRM_DEV_ERROR(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
 			status);
 		gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
 	}

index eace9e7..e274989 100644
@@ -585,7 +585,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 	u32 tmp, field;
 
 	if (adev->gart.robj == NULL) {
-		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
+		DRM_DEV_ERROR(adev->dev, "No VRAM object for PCIE GART.\n");
 		return -EINVAL;
 	}
 	r = amdgpu_gart_table_vram_pin(adev);

@@ -761,7 +761,7 @@ static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
 	mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 			      MEMORY_CLIENT_ID);
 
-	dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
+	DRM_DEV_ERROR(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 	       protections, vmid, addr,
 	       REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 			     MEMORY_CLIENT_RW) ?

@@ -1170,7 +1170,7 @@ static int gmc_v7_0_soft_reset(void *handle)
 
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 		tmp |= srbm_soft_reset;
-		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
+		DRM_DEV_INFO(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 		WREG32(mmSRBM_SOFT_RESET, tmp);
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 

@@ -1250,11 +1250,11 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
 		gmc_v7_0_set_fault_enable_default(adev, false);
 
 	if (printk_ratelimit()) {
-		dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
+		DRM_DEV_ERROR(adev->dev, "GPU fault detected: %d 0x%08x\n",
 			entry->src_id, entry->src_data[0]);
-		dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
+		DRM_DEV_ERROR(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
 			addr);
-		dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
+		DRM_DEV_ERROR(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
 			status);
 		gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
 	}

index 3b3326d..f1f83f3 100644
@@ -784,7 +784,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 	u32 tmp, field;
 
 	if (adev->gart.robj == NULL) {
-		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
+		DRM_DEV_ERROR(adev->dev, "No VRAM object for PCIE GART.\n");
 		return -EINVAL;
 	}
 	r = amdgpu_gart_table_vram_pin(adev);

@@ -977,7 +977,7 @@ static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
 	mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 			      MEMORY_CLIENT_ID);
 
-	dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
+	DRM_DEV_ERROR(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 	       protections, vmid, addr,
 	       REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 			     MEMORY_CLIENT_RW) ?

@@ -1304,7 +1304,7 @@ static int gmc_v8_0_soft_reset(void *handle)
 
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 		tmp |= srbm_soft_reset;
-		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
+		DRM_DEV_INFO(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 		WREG32(mmSRBM_SOFT_RESET, tmp);
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 

@@ -1381,9 +1381,9 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
 	u32 addr, status, mc_client;
 
 	if (amdgpu_sriov_vf(adev)) {
-		dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
+		DRM_DEV_ERROR(adev->dev, "GPU fault detected: %d 0x%08x\n",
 			entry->src_id, entry->src_data[0]);
-		dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
+		DRM_DEV_ERROR(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
 		return 0;
 	}
 

@@ -1400,11 +1400,11 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
 		gmc_v8_0_set_fault_enable_default(adev, false);
 
 	if (printk_ratelimit()) {
-		dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
+		DRM_DEV_ERROR(adev->dev, "GPU fault detected: %d 0x%08x\n",
 			entry->src_id, entry->src_data[0]);
-		dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
+		DRM_DEV_ERROR(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
 			addr);
-		dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
+		DRM_DEV_ERROR(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
 			status);
 		gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
 	}

index d04d0b1..94df18f8 100644
@@ -150,15 +150,15 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 	}
 
 	if (printk_ratelimit()) {
-		dev_err(adev->dev,
+		DRM_DEV_ERROR(adev->dev,
 			"[%s] VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u)\n",
 			entry->vm_id_src ? "mmhub" : "gfxhub",
 			entry->src_id, entry->ring_id, entry->vm_id,
 			entry->pas_id);
-		dev_err(adev->dev, "  at page 0x%016llx from %d\n",
+		DRM_DEV_ERROR(adev->dev, "  at page 0x%016llx from %d\n",
 			addr, entry->client_id);
 		if (!amdgpu_sriov_vf(adev))
-			dev_err(adev->dev,
+			DRM_DEV_ERROR(adev->dev,
 				"VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 				status);
 	}

@@ -403,7 +403,7 @@ static int gmc_v9_0_late_init(void *handle)
 		unsigned vmhub = ring->funcs->vmhub;
 
 		ring->vm_inv_eng = vm_inv_eng[vmhub]++;
-		dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",
+		DRM_DEV_INFO(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",
 			 ring->idx, ring->name, ring->vm_inv_eng,
 			 ring->funcs->vmhub);
 	}

@@ -706,7 +706,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
 		(const u32)ARRAY_SIZE(golden_settings_vega10_hdp));
 
 	if (adev->gart.robj == NULL) {
-		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
+		DRM_DEV_ERROR(adev->dev, "No VRAM object for PCIE GART.\n");
 		return -EINVAL;
 	}
 	r = amdgpu_gart_table_vram_pin(adev);

index 7a0ea27..3f98734 100644
@@ -364,7 +364,7 @@ static int iceland_ih_soft_reset(void *handle)
 	if (srbm_soft_reset) {
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 		tmp |= srbm_soft_reset;
-		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
+		DRM_DEV_INFO(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 		WREG32(mmSRBM_SOFT_RESET, tmp);
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 

index f7cf994..ff7f21d 100644
@@ -122,7 +122,7 @@ int psp_v10_0_init_microcode(struct psp_context *psp)
 	return 0;
 out:
 	if (err) {
-		dev_err(adev->dev,
+		DRM_DEV_ERROR(adev->dev,
 			"psp v10.0: Failed to load firmware \"%s\"\n",
 			fw_name);
 		release_firmware(adev->psp.asd_fw);

index 2a535a4..8b3b87a 100644
@@ -150,7 +150,7 @@ int psp_v3_1_init_microcode(struct psp_context *psp)
 	return 0;
 out:
 	if (err) {
-		dev_err(adev->dev,
+		DRM_DEV_ERROR(adev->dev,
 			"psp v3.1: Failed to load firmware \"%s\"\n",
 			fw_name);
 		release_firmware(adev->psp.sos_fw);

index f2d0710..c8192d7 100644
@@ -612,7 +612,7 @@ static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
 
 	r = amdgpu_wb_get(adev, &index);
 	if (r) {
-		dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) failed to allocate wb slot\n", r);
 		return r;
 	}
 

@@ -674,7 +674,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 
 	r = amdgpu_wb_get(adev, &index);
 	if (r) {
-		dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 		return r;
 	}
 

@@ -1063,7 +1063,7 @@ static int sdma_v2_4_soft_reset(void *handle)
 	if (srbm_soft_reset) {
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 		tmp |= srbm_soft_reset;
-		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
+		DRM_DEV_INFO(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 		WREG32(mmSRBM_SOFT_RESET, tmp);
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 

index b1de44f..16cf82c 100644
@@ -856,7 +856,7 @@ static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
 
 	r = amdgpu_wb_get(adev, &index);
 	if (r) {
-		dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) failed to allocate wb slot\n", r);
 		return r;
 	}
 

@@ -918,7 +918,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 
 	r = amdgpu_wb_get(adev, &index);
 	if (r) {
-		dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 		return r;
 	}
 

@@ -1366,7 +1366,7 @@ static int sdma_v3_0_soft_reset(void *handle)
 	if (srbm_soft_reset) {
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 		tmp |= srbm_soft_reset;
-		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
+		DRM_DEV_INFO(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 		WREG32(mmSRBM_SOFT_RESET, tmp);
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 

index fd7c72a..4652505 100644
@@ -888,7 +888,7 @@ static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
 
 	r = amdgpu_wb_get(adev, &index);
 	if (r) {
-		dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) failed to allocate wb slot\n", r);
 		return r;
 	}
 

@@ -950,7 +950,7 @@ static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 
 	r = amdgpu_wb_get(adev, &index);
 	if (r) {
-		dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 		return r;
 	}
 

index 112969f..25485e4 100644
@@ -223,7 +223,7 @@ static int si_dma_ring_test_ring(struct amdgpu_ring *ring)
 
 	r = amdgpu_wb_get(adev, &index);
 	if (r) {
-		dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%d) failed to allocate wb slot\n", r);
 		return r;
 	}
 

@@ -283,7 +283,7 @@ static int si_dma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 
 	r = amdgpu_wb_get(adev, &index);
 	if (r) {
-		dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
+		DRM_DEV_ERROR(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 		return r;
 	}
 

index ce25e03..8d6da5d 100644
@@ -241,7 +241,7 @@ static int si_ih_soft_reset(void *handle)
 	if (srbm_soft_reset) {
 		tmp = RREG32(SRBM_SOFT_RESET);
 		tmp |= srbm_soft_reset;
-		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
+		DRM_DEV_INFO(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 		WREG32(SRBM_SOFT_RESET, tmp);
 		tmp = RREG32(SRBM_SOFT_RESET);
 

index f2c3a49..6021f54 100644
@@ -411,7 +411,7 @@ static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev)
 {
 	u32 i;
 
-	dev_info(adev->dev, "GPU pci config reset\n");
+	DRM_DEV_INFO(adev->dev, "GPU pci config reset\n");
 
 	/* disable BM */
 	pci_clear_master(adev->pdev);

index 923df2c..f9a8960 100644
@@ -427,7 +427,7 @@ static int tonga_ih_soft_reset(void *handle)
 
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 		tmp |= srbm_soft_reset;
-		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
+		DRM_DEV_INFO(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 		WREG32(mmSRBM_SOFT_RESET, tmp);
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 

index 31db356..f43248a 100644
@@ -783,7 +783,7 @@ static int uvd_v6_0_soft_reset(void *handle)
 
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 		tmp |= srbm_soft_reset;
-		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
+		DRM_DEV_INFO(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 		WREG32(mmSRBM_SOFT_RESET, tmp);
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 

index 23a8575..c11760d 100644
@@ -713,7 +713,7 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
 	}
 
 	if (!loop) {
-		dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
+		DRM_DEV_ERROR(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
 		return -EBUSY;
 	}
 

index 90332f5..dd771bd 100644
@@ -658,7 +658,7 @@ static int vce_v3_0_soft_reset(void *handle)
 
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 		tmp |= srbm_soft_reset;
-		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
+		DRM_DEV_INFO(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 		WREG32(mmSRBM_SOFT_RESET, tmp);
 		tmp = RREG32(mmSRBM_SOFT_RESET);
 

index 11134d5..d3d1f60 100644
@@ -192,7 +192,7 @@ static int vce_v4_0_mmsch_start(struct amdgpu_device *adev,
 	}
 
 	if (!loop) {
-		dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
+		DRM_DEV_ERROR(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
 		return -EBUSY;
 	}
 

index 9ff69b9..04d4400 100644
@@ -661,7 +661,7 @@ static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
 {
 	u32 i;
 
-	dev_info(adev->dev, "GPU pci config reset\n");
+	DRM_DEV_INFO(adev->dev, "GPU pci config reset\n");
 
 	/* disable BM */
 	pci_clear_master(adev->pdev);