amdgpu/dc: constify a bunch of dc structs.

PATCH In review Dave Airlie 2 participants 3 messages Sep 29, 2017 2 messages not in the archive

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DRM drivers Radeon and amdgpu DRM drivers AMD display core

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Dave Airlie

author

2017-09-29 00:39 UTC #0 lore raw

PATCH 1/2 amdgpu/dc: constify a bunch of dc structs.

From: Dave Airlie <[email protected]>

Signed-off-by Dave Airlie <[email protected]>

---
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c                 | 8 ++++----
 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c         | 2 +-
 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c                | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c   | 2 +-
 5 files changed, 8 insertions(+), 8 deletions(-)

drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +4 -4

index 3e9ff2f5..9031d22 100644
@@ -51,7 +51,7 @@
 	clk_dce->base.ctx
 
 /* Max clock values for each state indexed by "enum clocks_state": */
-static struct state_dependent_clocks dce80_max_clks_by_state[] = {
+static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
 /* ClocksStateInvalid - should not be used */
 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */

@@ -63,7 +63,7 @@ static struct state_dependent_clocks dce80_max_clks_by_state[] = {
 /* ClocksStatePerformance */
 { .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
 
-static struct state_dependent_clocks dce110_max_clks_by_state[] = {
+static const struct state_dependent_clocks dce110_max_clks_by_state[] = {
 /*ClocksStateInvalid - should not be used*/
 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/

@@ -75,7 +75,7 @@ static struct state_dependent_clocks dce110_max_clks_by_state[] = {
 /*ClocksStatePerformance*/
 { .display_clk_khz = 643000, .pixel_clk_khz = 400000 } };
 
-static struct state_dependent_clocks dce112_max_clks_by_state[] = {
+static const struct state_dependent_clocks dce112_max_clks_by_state[] = {
 /*ClocksStateInvalid - should not be used*/
 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/

@@ -87,7 +87,7 @@ static struct state_dependent_clocks dce112_max_clks_by_state[] = {
 /*ClocksStatePerformance*/
 { .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } };
 
-static struct state_dependent_clocks dce120_max_clks_by_state[] = {
+static const struct state_dependent_clocks dce120_max_clks_by_state[] = {
 /*ClocksStateInvalid - should not be used*/
 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/

drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +1 -1

index 6b5d594..a6f93a42 100644
@@ -302,7 +302,7 @@ static const struct dce_opp_mask opp_mask = {
 	AUD_COMMON_REG_LIST(id)\
 }
 
-static struct dce_audio_registers audio_regs[] = {
+static const struct dce_audio_registers audio_regs[] = {
 	audio_regs(0),
 	audio_regs(1),
 	audio_regs(2),

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +1 -1

index 58a070d..791c9b0 100644
@@ -1109,7 +1109,7 @@ static bool dce120_arm_vert_intr(
 	return true;
 }
 
-static struct timing_generator_funcs dce120_tg_funcs = {
+static const struct timing_generator_funcs dce120_tg_funcs = {
 		.validate_timing = dce120_tg_validate_timing,
 		.program_timing = dce120_tg_program_timing,
 		.enable_crtc = dce120_timing_generator_enable_crtc,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +1 -1

index 4876941..ac03b04 100644
@@ -373,7 +373,7 @@ void ippn10_cnv_setup (
 	}
 }
 
-static struct transform_funcs dcn10_dpp_funcs = {
+static const struct transform_funcs dcn10_dpp_funcs = {
 		.transform_reset = dpp_reset,
 		.transform_set_scaler = dcn10_dpp_dscl_set_scaler_manual_scale,
 		.transform_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +1 -1

index 2d3dd9a..7cd10cb 100644
@@ -1146,7 +1146,7 @@ void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10,
 }
 
 
-static struct timing_generator_funcs dcn10_tg_funcs = {
+static const struct timing_generator_funcs dcn10_tg_funcs = {
 		.validate_timing = tgn10_validate_timing,
 		.program_timing = tgn10_program_timing,
 		.program_global_sync = tgn10_program_global_sync,

Signature · 6 lines

2.9.4

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Dave Airlie

author

2017-09-29 00:39 UTC #2 lore raw

PATCH 2/2 amdgpu/pp: constify soft_dummy_pp_table.

From: Dave Airlie <[email protected]>

Signed-off-by Dave Airlie <[email protected]>

---
 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c +1 -1

index 485f7eb..afae32e 100644
@@ -790,7 +790,7 @@ static const ATOM_PPLIB_STATE_V2 *get_state_entry_v2(
 	return pstate;
 }
 
-static unsigned char soft_dummy_pp_table[] = {
+static const unsigned char soft_dummy_pp_table[] = {
 	0xe1, 0x01, 0x06, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x00, 0x4a, 0x00, 0x6c, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x42, 0x00, 0x02, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
 	0x00, 0x4e, 0x00, 0x88, 0x00, 0x00, 0x9e, 0x00, 0x17, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,

Signature · 6 lines

2.9.4

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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Alex Deucher

Reviewed-by

2017-09-29 14:34 UTC #4 lore raw

Re: [PATCH 2/2] amdgpu/pp: constify soft_dummy_pp_table.

Quoted 3 lines · Dave Airlie

From: Dave Airlie <[email protected]>
Signed-off-by Dave Airlie <[email protected]>

Reviewed-by Alex Deucher <[email protected]>

Quoted 20 lines

---
 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c +1 -2

index 485f7eb..afae32e 100644
@@ -790,7 +790,7 @@ static const ATOM_PPLIB_STATE_V2 *get_state_entry_v2(
        return pstate;
 }
 
-static unsigned char soft_dummy_pp_table[] = {
+static const unsigned char soft_dummy_pp_table[] = {
        0xe1, 0x01, 0x06, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x00, 0x4a, 0x00, 0x6c, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x42, 0x00, 0x02, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
        0x00, 0x4e, 0x00, 0x88, 0x00, 0x00, 0x9e, 0x00, 0x17, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
--

2.9.4

Quoted 4 lines

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_______________________________________________
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