add initial RISC-V architecture support
Subsystems (5)
v4 cover add initial RISC-V architecture support
This patchseries adds initial RISC-V architecture support for barebox.
See Documentation/boards/riscv.rst for instructions.
You can obtain this patchseries from github:
$ git clone -b 20170929.riscv https://github.com/frantony/barebox
Changes since RFC v3 (20161212) (http://lists.infradead.org/pipermail/barebox/2016-December/028716.html)
* drop SiFive support, add support for custom Erizo SoC;
* barebox runs on real hardware (e.g. DE0-Nano FPGA board,
see https://github.com/miet-riscv-workgroup/rv32-simple-soc for details);
* introduce NMON for RISC-V;
* add relocator to start.S.
Changes since RFC v2 (20161113) (http://lists.infradead.org/pipermail/barebox/2016-November/028533.html):
* add RV32 support.
Changes since RFC v1 (20161013) (http://lists.infradead.org/pipermail/barebox/2016-October/028309.html):
* drop spike pk support;
* add qemu-sifive board support;
* add Documentation/boards/riscv.rst;
* fix guard macro names
TODOs:
* add pbl support;
* sync with https://github.com/riscv/riscv-linux;
* RV64 definitions are unused now;
* sync MIPS debug_ll codes with RISC-V;
* add support for Opencores I2C and SPI IP-blocks.
Antony Pavlov (10):
Add initial RISC-V architecture support
RISC-V: add Erizo SoC support
RISC-V: add low-level debug macros for ns16550
RISC-V: add nmon nano-monitor
RISC-V: erizo: add DEBUG_LL support
RISC-V: erizo: enable NMON
RISC-V: erizo: add nmon image creation
RISC-V: add erizo_generic_defconfig
scripts: add nmon-loader
Documentation: add RISC-V docs
Documentation/boards/riscv.rst | 110 ++++++++++++ arch/riscv/Kconfig | 110 ++++++++++++ arch/riscv/Makefile | 82 +++++++++ arch/riscv/boards/erizo-generic/.gitignore | 1 + arch/riscv/boards/erizo-generic/Makefile | 1 + arch/riscv/boards/erizo-generic/board.c | 28 +++ arch/riscv/boot/Makefile | 2 + arch/riscv/boot/main_entry.c | 40 +++++ arch/riscv/boot/start.S | 88 ++++++++++ arch/riscv/configs/erizo_generic_defconfig | 55 ++++++ arch/riscv/dts/.gitignore | 1 + arch/riscv/dts/Makefile | 9 + arch/riscv/dts/erizo.dtsi | 46 +++++ arch/riscv/dts/erizo_generic.dts | 31 ++++ arch/riscv/dts/skeleton.dtsi | 13 ++ arch/riscv/include/asm/barebox.h | 1 + arch/riscv/include/asm/bitops.h | 35 ++++ arch/riscv/include/asm/bitsperlong.h | 10 ++ arch/riscv/include/asm/byteorder.h | 10 ++ arch/riscv/include/asm/common.h | 6 + arch/riscv/include/asm/debug_ll_ns16550.h | 186 ++++++++++++++++++++ arch/riscv/include/asm/elf.h | 11 ++ arch/riscv/include/asm/io.h | 8 + arch/riscv/include/asm/mmu.h | 6 + arch/riscv/include/asm/posix_types.h | 1 + arch/riscv/include/asm/riscv_nmon.h | 234 ++++++++++++++++++++++++++ arch/riscv/include/asm/sections.h | 1 + arch/riscv/include/asm/string.h | 1 + arch/riscv/include/asm/swab.h | 6 + arch/riscv/include/asm/types.h | 60 +++++++ arch/riscv/include/asm/unaligned.h | 19 +++ arch/riscv/lib/.gitignore | 1 + arch/riscv/lib/Makefile | 9 + arch/riscv/lib/ashldi3.c | 28 +++ arch/riscv/lib/ashrdi3.c | 30 ++++ arch/riscv/lib/asm-offsets.c | 12 ++ arch/riscv/lib/barebox.lds.S | 89 ++++++++++ arch/riscv/lib/dtb.c | 41 +++++ arch/riscv/lib/libgcc.h | 29 ++++ arch/riscv/lib/lshrdi3.c | 28 +++ arch/riscv/lib/riscv_timer.c | 68 ++++++++ arch/riscv/mach-erizo/Kconfig | 11 ++ arch/riscv/mach-erizo/Makefile | 3 + arch/riscv/mach-erizo/include/mach/debug_ll.h | 37 ++++ drivers/of/Kconfig | 2 +- scripts/erizo-nmon-image | 3 + scripts/nmon-loader | 31 ++++ 47 files changed, 1633 insertions(+), 1 deletion(-) create mode 100644 Documentation/boards/riscv.rst create mode 100644 arch/riscv/Kconfig create mode 100644 arch/riscv/Makefile create mode 100644 arch/riscv/boards/erizo-generic/.gitignore create mode 100644 arch/riscv/boards/erizo-generic/Makefile create mode 100644 arch/riscv/boards/erizo-generic/board.c create mode 100644 arch/riscv/boot/Makefile create mode 100644 arch/riscv/boot/main_entry.c create mode 100644 arch/riscv/boot/start.S create mode 100644 arch/riscv/configs/erizo_generic_defconfig create mode 100644 arch/riscv/dts/.gitignore create mode 100644 arch/riscv/dts/Makefile create mode 100644 arch/riscv/dts/erizo.dtsi create mode 100644 arch/riscv/dts/erizo_generic.dts create mode 100644 arch/riscv/dts/skeleton.dtsi create mode 100644 arch/riscv/include/asm/barebox.h create mode 100644 arch/riscv/include/asm/bitops.h create mode 100644 arch/riscv/include/asm/bitsperlong.h create mode 100644 arch/riscv/include/asm/byteorder.h create mode 100644 arch/riscv/include/asm/common.h create mode 100644 arch/riscv/include/asm/debug_ll_ns16550.h create mode 100644 arch/riscv/include/asm/elf.h create mode 100644 arch/riscv/include/asm/io.h create mode 100644 arch/riscv/include/asm/mmu.h create mode 100644 arch/riscv/include/asm/posix_types.h create mode 100644 arch/riscv/include/asm/riscv_nmon.h create mode 100644 arch/riscv/include/asm/sections.h create mode 100644 arch/riscv/include/asm/string.h create mode 100644 arch/riscv/include/asm/swab.h create mode 100644 arch/riscv/include/asm/types.h create mode 100644 arch/riscv/include/asm/unaligned.h create mode 100644 arch/riscv/lib/.gitignore create mode 100644 arch/riscv/lib/Makefile create mode 100644 arch/riscv/lib/ashldi3.c create mode 100644 arch/riscv/lib/ashrdi3.c create mode 100644 arch/riscv/lib/asm-offsets.c create mode 100644 arch/riscv/lib/barebox.lds.S create mode 100644 arch/riscv/lib/dtb.c create mode 100644 arch/riscv/lib/libgcc.h create mode 100644 arch/riscv/lib/lshrdi3.c create mode 100644 arch/riscv/lib/riscv_timer.c create mode 100644 arch/riscv/mach-erizo/Kconfig create mode 100644 arch/riscv/mach-erizo/Makefile create mode 100644 arch/riscv/mach-erizo/include/mach/debug_ll.h create mode 100755 scripts/erizo-nmon-image create mode 100755 scripts/nmon-loader
Signature · 7 lines
2.14.1 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
RFC v4 1/10 Add initial RISC-V architecture support
Signed-off-by Antony Pavlov <[email protected]>
--
TODOs:
* split patch;
--- arch/riscv/Kconfig | 73 +++++++++++++++++++++++++++++ arch/riscv/Makefile | 68 +++++++++++++++++++++++++++ arch/riscv/boot/Makefile | 2 + arch/riscv/boot/main_entry.c | 40 ++++++++++++++++ arch/riscv/boot/start.S | 74 ++++++++++++++++++++++++++++++ arch/riscv/dts/.gitignore | 1 + arch/riscv/dts/Makefile | 9 ++++ arch/riscv/dts/skeleton.dtsi | 13 ++++++ arch/riscv/include/asm/barebox.h | 1 + arch/riscv/include/asm/bitops.h | 35 ++++++++++++++ arch/riscv/include/asm/bitsperlong.h | 10 ++++ arch/riscv/include/asm/byteorder.h | 10 ++++ arch/riscv/include/asm/common.h | 6 +++ arch/riscv/include/asm/elf.h | 11 +++++ arch/riscv/include/asm/io.h | 8 ++++ arch/riscv/include/asm/mmu.h | 6 +++ arch/riscv/include/asm/posix_types.h | 1 + arch/riscv/include/asm/sections.h | 1 + arch/riscv/include/asm/string.h | 1 + arch/riscv/include/asm/swab.h | 6 +++ arch/riscv/include/asm/types.h | 60 ++++++++++++++++++++++++ arch/riscv/include/asm/unaligned.h | 19 ++++++++ arch/riscv/lib/.gitignore | 1 + arch/riscv/lib/Makefile | 9 ++++ arch/riscv/lib/ashldi3.c | 28 ++++++++++++ arch/riscv/lib/ashrdi3.c | 30 ++++++++++++ arch/riscv/lib/asm-offsets.c | 12 +++++ arch/riscv/lib/barebox.lds.S | 89 ++++++++++++++++++++++++++++++++++++ arch/riscv/lib/dtb.c | 41 +++++++++++++++++ arch/riscv/lib/libgcc.h | 29 ++++++++++++ arch/riscv/lib/lshrdi3.c | 28 ++++++++++++ arch/riscv/lib/riscv_timer.c | 68 +++++++++++++++++++++++++++ drivers/of/Kconfig | 2 +- 33 files changed, 791 insertions(+), 1 deletion(-)
arch/riscv/Kconfig new file +73 -0
@@ -0,0 +1,73 @@ +config RISCV + bool + select GENERIC_FIND_NEXT_BIT + select HAVE_CONFIGURABLE_MEMORY_LAYOUT + select HAVE_CONFIGURABLE_TEXT_BASE + select GPIOLIB + select OFTREE + select COMMON_CLK + select COMMON_CLK_OF_PROVIDER + select CLKDEV_LOOKUP + default y + +config ARCH_TEXT_BASE + hex + default 0x0 + +config GENERIC_LINKER_SCRIPT + bool + default y + +menu "Machine selection" + +choice + prompt "CPU selection" + default CPU_RV_GENERIC + +config CPU_RV_GENERIC + bool "Generic RISC-V" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + +endchoice + +config CPU_SUPPORTS_32BIT_KERNEL + bool +config CPU_SUPPORTS_64BIT_KERNEL + bool + +choice + prompt "barebox code model" + default 64BIT + +config 32BIT + bool "32-bit barebox" + depends on CPU_SUPPORTS_32BIT_KERNEL + help + Select this option to build a 32-bit barebox. + +config 64BIT + bool "64-bit barebox" + depends on CPU_SUPPORTS_64BIT_KERNEL + help + Select this option to build a 64-bit barebox. + +endchoice + +config BUILTIN_DTB + bool "link a DTB into the barebox image" + depends on OFTREE + +config BUILTIN_DTB_NAME + string "DTB to build into the barebox image" + depends on BUILTIN_DTB + +endmenu + +source common/Kconfig +source commands/Kconfig +source net/Kconfig +source drivers/Kconfig +source fs/Kconfig +source lib/Kconfig +source crypto/Kconfig
arch/riscv/Makefile new file +68 -0
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arch/riscv/boot/Makefile new file +2 -0
@@ -0,0 +1,2 @@ +obj-y += start.o +obj-y += main_entry.o
arch/riscv/boot/main_entry.c new file +40 -0
@@ -0,0 +1,40 @@ +/* +* Copyright (C) 2016 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#include <common.h> +#include <memory.h> +#include <asm-generic/memory_layout.h> +#include <asm/sections.h> + +void main_entry (void ); + +/** +* Called plainly from assembler code +* +* @note The C environment isn't initialized yet +*/ +void main_entry (void ) +{ +/* clear the BSS first */ +memset (__bss_start,0x00 , __bss_stop - __bss_start); + +mem_malloc_init ((void *)MALLOC_BASE , + (void *)(MALLOC_BASE +MALLOC_SIZE -1 )); + +start_barebox (); +}
arch/riscv/boot/start.S new file +74 -0
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arch/riscv/dts/.gitignore new file +1 -0
@@ -0,0 +1 @@ +*dtb*
arch/riscv/dts/Makefile new file +9 -0
@@ -0,0 +1,9 @@ +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) +obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o + +# just to build a built-in.o. Otherwise compilation fails when no devicetree is +# created. +obj- += dummy.o + +always := $(dtb-y) +clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts
arch/riscv/dts/skeleton.dtsi new file +13 -0
@@ -0,0 +1,13 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <2>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0 0>; }; +};
arch/riscv/include/asm/barebox.h new file +1 -0
@@ -0,0 +1 @@ +/* dummy */
arch/riscv/include/asm/bitops.h new file +35 -0
@@ -0,0 +1,35 @@ +/* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* +*/ + +#ifndef _ASM_BITOPS_H_ +#define _ASM_BITOPS_H_ + +#include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/ffz.h> +#include <asm-generic/bitops/hweight.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/find.h> +#include <asm-generic/bitops/ops.h> + +#define set_bit (x, y) __set_bit(x, y) +#define clear_bit (x, y) __clear_bit(x, y) +#define change_bit (x, y) __change_bit(x, y) +#define test_and_set_bit (x, y) __test_and_set_bit(x, y) +#define test_and_clear_bit (x, y) __test_and_clear_bit(x, y) +#define test_and_change_bit (x, y) __test_and_change_bit(x, y) + +#endif /* _ASM_BITOPS_H_ */
arch/riscv/include/asm/bitsperlong.h new file +10 -0
@@ -0,0 +1,10 @@ +#ifndef __ASM_BITSPERLONG_H +#define __ASM_BITSPERLONG_H + +#ifdef __riscv64 +#define BITS_PER_LONG 64 +#else +#define BITS_PER_LONG 32 +#endif + +#endif /* __ASM_BITSPERLONG_H */
arch/riscv/include/asm/byteorder.h new file +10 -0
@@ -0,0 +1,10 @@ +#ifndef _ASM_RISCV_BYTEORDER_H +#define _ASM_RISCV_BYTEORDER_H + +#if defined(__RISCVEB__) +#include <linux/byteorder/big_endian.h> +#else +#include <linux/byteorder/little_endian.h> +#endif + +#endif /* _ASM_RISCV_BYTEORDER_H */
arch/riscv/include/asm/common.h new file +6 -0
@@ -0,0 +1,6 @@ +#ifndef ASM_RISCV_COMMON_H +#define ASM_RISCV_COMMON_H + +/* nothing special yet */ + +#endif /* ASM_RISCV_COMMON_H */
arch/riscv/include/asm/elf.h new file +11 -0
@@ -0,0 +1,11 @@ +#ifndef __ASM_RISCV_ELF_H__ +#define __ASM_RISCV_ELF_H__ + +#if __SIZEOF_POINTER__ ==8 +#define ELF_CLASS ELFCLASS64 +#define CONFIG_PHYS_ADDR_T_64BIT +#else +#define ELF_CLASS ELFCLASS32 +#endif + +#endif /* __ASM_RISCV_ELF_H__ */
arch/riscv/include/asm/io.h new file +8 -0
@@ -0,0 +1,8 @@ +#ifndef __ASM_RISCV_IO_H +#define __ASM_RISCV_IO_H + +#define IO_SPACE_LIMIT 0 + +#include <asm-generic/io.h> + +#endif /* __ASM_RISCV_IO_H */
arch/riscv/include/asm/mmu.h new file +6 -0
@@ -0,0 +1,6 @@ +#ifndef __ASM_MMU_H +#define __ASM_MMU_H + +#define MAP_ARCH_DEFAULT MAP_UNCACHED + +#endif /* __ASM_MMU_H */
arch/riscv/include/asm/posix_types.h new file +1 -0
@@ -0,0 +1 @@ +#include <asm-generic/posix_types.h>
arch/riscv/include/asm/sections.h new file +1 -0
@@ -0,0 +1 @@ +#include <asm-generic/sections.h>
arch/riscv/include/asm/string.h new file +1 -0
@@ -0,0 +1 @@ +/* dummy */
arch/riscv/include/asm/swab.h new file +6 -0
@@ -0,0 +1,6 @@ +#ifndef _ASM_SWAB_H +#define _ASM_SWAB_H + +/* nothing. use generic functions */ + +#endif /* _ASM_SWAB_H */
arch/riscv/include/asm/types.h new file +60 -0
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arch/riscv/include/asm/unaligned.h new file +19 -0
@@ -0,0 +1,19 @@ +#ifndef _ASM_RISCV_UNALIGNED_H +#define _ASM_RISCV_UNALIGNED_H + +/* +* FIXME: this file is copy-n-pasted from sandbox's unaligned.h +*/ + +#include <linux/unaligned/access_ok.h> +#include <linux/unaligned/generic.h> + +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le +#else +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be +#endif + +#endif /* _ASM_RISCV_UNALIGNED_H */
arch/riscv/lib/.gitignore new file +1 -0
@@ -0,0 +1 @@ +barebox.lds
arch/riscv/lib/Makefile new file +9 -0
@@ -0,0 +1,9 @@ +extra-$(CONFIG_GENERIC_LINKER_SCRIPT) += barebox.lds + +obj-y += riscv_timer.o + +obj-$(CONFIG_32BIT) += lshrdi3.o +obj-$(CONFIG_32BIT) += ashldi3.o +obj-$(CONFIG_32BIT) += ashrdi3.o + +obj-$(CONFIG_BUILTIN_DTB) += dtb.o
arch/riscv/lib/ashldi3.c new file +28 -0
@@ -0,0 +1,28 @@ +#include <module.h> + +#include "libgcc.h" + +long long __ashldi3 (long long u,word_type b) +{ +DWunion uu, w; +word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { + w.s.low =0 ; + w.s.high = (unsigned int ) uu.s.low << -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.low >> bm; + + w.s.low = (unsigned int ) uu.s.low << b; + w.s.high = ((unsigned int ) uu.s.high << b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__ashldi3);
arch/riscv/lib/ashrdi3.c new file +30 -0
@@ -0,0 +1,30 @@ +#include <module.h> + +#include "libgcc.h" + +long long __ashrdi3 (long long u,word_type b) +{ +DWunion uu, w; +word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { +/* w.s.high = 1..1 or 0..0 */ + w.s.high = + uu.s.high >>31 ; + w.s.low = uu.s.high >> -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.high << bm; + + w.s.high = uu.s.high >> b; + w.s.low = ((unsigned int ) uu.s.low >> b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__ashrdi3);
arch/riscv/lib/asm-offsets.c new file +12 -0
@@ -0,0 +1,12 @@ +/* +* Generate definitions needed by assembly language modules. +* This code generates raw asm output which is post-processed to extract +* and format the required data. +*/ + +#include <linux/kbuild.h> + +int main (void ) +{ +return 0 ; +}
arch/riscv/lib/barebox.lds.S new file +89 -0
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arch/riscv/lib/dtb.c new file +41 -0
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arch/riscv/lib/libgcc.h new file +29 -0
@@ -0,0 +1,29 @@ +#ifndef __ASM_LIBGCC_H +#define __ASM_LIBGCC_H + +#include <asm/byteorder.h> + +typedef int word_type __attribute__ ((mode (__word__))); + +#ifdef __BIG_ENDIAN +struct DWstruct { +int high, low; +}; +#elif defined(__LITTLE_ENDIAN) +struct DWstruct { +int low, high; +}; +#else +#error I feel sick. +#endif + +typedef union { +struct DWstruct s; +long long ll; +}DWunion ; + +long long __lshrdi3 (long long u,word_type b); +long long __ashldi3 (long long u,word_type b); +long long __ashrdi3 (long long u,word_type b); + +#endif /* __ASM_LIBGCC_H */
arch/riscv/lib/lshrdi3.c new file +28 -0
@@ -0,0 +1,28 @@ +#include <module.h> + +#include "libgcc.h" + +long long __lshrdi3 (long long u,word_type b) +{ +DWunion uu, w; +word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { + w.s.high =0 ; + w.s.low = (unsigned int ) uu.s.high >> -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.high << bm; + + w.s.high = (unsigned int ) uu.s.high >> b; + w.s.low = ((unsigned int ) uu.s.low >> b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__lshrdi3);
arch/riscv/lib/riscv_timer.c new file +68 -0
68 lines not on this page · raw message
drivers/of/Kconfig +1 -1
@@ -4,7 +4,7 @@ config OFTREE config OFTREE_MEM_GENERIC depends on OFTREE - depends on PPC || ARM || EFI_BOOTUP || OPENRISC || SANDBOX + depends on PPC || ARM || EFI_BOOTUP || OPENRISC || SANDBOX || RISCV def_bool y config DTC
Signature · 7 lines
2.14.1 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC v4 01/10] Add initial RISC-V architecture support
Hi,
hm... mostly looks identical with existing arch
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
Quoted 284 lines
Signed-off-by Antony Pavlov <[email protected]>--
TODOs:* split patch;
--- arch/riscv/Kconfig | 73 +++++++++++++++++++++++++++++ arch/riscv/Makefile | 68 +++++++++++++++++++++++++++ arch/riscv/boot/Makefile | 2 + arch/riscv/boot/main_entry.c | 40 ++++++++++++++++ arch/riscv/boot/start.S | 74 ++++++++++++++++++++++++++++++ arch/riscv/dts/.gitignore | > arch/riscv/dts/Makefile | 9 ++++ arch/riscv/dts/skeleton.dtsi | 13 ++++++ arch/riscv/include/asm/barebox.h | 1 + arch/riscv/include/asm/bitops.h | 35 ++++++++++++++ arch/riscv/include/asm/bitsperlong.h | 10 ++++ arch/riscv/include/asm/byteorder.h | 10 ++++ arch/riscv/include/asm/common.h | 6 +++ arch/riscv/include/asm/elf.h | 11 +++++ arch/riscv/include/asm/io.h | 8 ++++ arch/riscv/include/asm/mmu.h | 6 +++ arch/riscv/include/asm/posix_types.h | 1 + arch/riscv/include/asm/sections.h | 1 + arch/riscv/include/asm/string.h | 1 + arch/riscv/include/asm/swab.h | 6 +++ arch/riscv/include/asm/types.h | 60 ++++++++++++++++++++++++ arch/riscv/include/asm/unaligned.h | 19 ++++++++ arch/riscv/lib/.gitignore | 1 + arch/riscv/lib/Makefile | 9 ++++ arch/riscv/lib/ashldi3.c | 28 ++++++++++++ arch/riscv/lib/ashrdi3.c | 30 ++++++++++++ arch/riscv/lib/asm-offsets.c | 12 +++++ arch/riscv/lib/barebox.lds.S | 89 ++++++++++++++++++++++++++++++++++++ arch/riscv/lib/dtb.c | 41 +++++++++++++++++ arch/riscv/lib/libgcc.h | 29 ++++++++++++ arch/riscv/lib/lshrdi3.c | 28 ++++++++++++ arch/riscv/lib/riscv_timer.c | 68 +++++++++++++++++++++++++++ drivers/of/Kconfig | 2 +- 33 files changed, 791 insertions(+), 1 deletion(-)arch/riscv/Kconfig new file +73
-0@@ -0,0 +1,73 @@ +config RISCV + bool + select GENERIC_FIND_NEXT_BIT + select HAVE_CONFIGURABLE_MEMORY_LAYOUT + select HAVE_CONFIGURABLE_TEXT_BASE + select GPIOLIB + select OFTREE + select COMMON_CLK + select COMMON_CLK_OF_PROVIDER + select CLKDEV_LOOKUP + default y + +config ARCH_TEXT_BASE + hex + default 0x0 + +config GENERIC_LINKER_SCRIPT + bool + default y + +menu "Machine selection" + +choice + prompt "CPU selection" + default CPU_RV_GENERIC + +config CPU_RV_GENERIC + bool "Generic RISC-V" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + +endchoice + +config CPU_SUPPORTS_32BIT_KERNEL + bool +config CPU_SUPPORTS_64BIT_KERNEL + bool + +choice + prompt "barebox code model" + default 64BIT + +config 32BIT + bool "32-bit barebox" + depends on CPU_SUPPORTS_32BIT_KERNEL + help + Select this option to build a 32-bit barebox. + +config 64BIT + bool "64-bit barebox" + depends on CPU_SUPPORTS_64BIT_KERNEL + help + Select this option to build a 64-bit barebox. + +endchoice + +config BUILTIN_DTB + bool "link a DTB into the barebox image" + depends on OFTREE + +config BUILTIN_DTB_NAME + string "DTB to build into the barebox image" + depends on BUILTIN_DTB + +endmenu + +source common/Kconfig +source commands/Kconfig +source net/Kconfig +source drivers/Kconfig +source fs/Kconfig +source lib/Kconfig +source crypto/Kconfigarch/riscv/Makefile new file +68
-0@@ -0,0 +1,68 @@ +CPPFLAGS += -fno-strict-aliasing + +cflags-y += -fno-pic -pipe +cflags-y += -Wall -Wmissing-prototypes -Wstrict-prototypes \ + -Wno-uninitialized -Wno-format -Wno-main -mcmodel=medany + +LDFLAGS += $(ldflags-y) +LDFLAGS_barebox += -nostdlib + +TEXT_BASE = $(CONFIG_TEXT_BASE) +CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE) + +ifndef CONFIG_MODULES +# Add cleanup flags +CPPFLAGS += -fdata-sections -ffunction-sections +LDFLAGS_barebox += -static --gc-sections +endif + +KBUILD_BINARY := barebox.bin + +machdirs := $(patsubst %,arch/riscv/mach-%/,$(machine-y)) + +ifneq ($(board-y),) +BOARD := arch/riscv/boards/$(board-y)/ +else +BOARD := +endif + +ifeq ($(KBUILD_SRC),) +CPPFLAGS += -I$(BOARD)/include +else +CPPFLAGS += -I$(srctree)/$(BOARD)/include +endif + +ifeq ($(KBUILD_SRC),) +CPPFLAGS += $(patsubst %,-I%include,$(machdirs)) +else +CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) +endif + +archprepare: maketools + +PHONY += maketools + +ifneq ($(machine-y),) +MACH := arch/riscv/mach-$(machine-y)/ +else +MACH := +endif + +ifneq ($(board-y),) +BOARD := arch/riscv/boards/$(board-y)/ +else +BOARD := +endif + +common-y += $(BOARD) $(MACH) +common-y += arch/riscv/lib/ +common-y += arch/riscv/boot/ + +common-$(CONFIG_OFTREE) += arch/riscv/dts/ + +CPPFLAGS += $(cflags-y) +CFLAGS += $(cflags-y) + +lds-y := arch/riscv/lib/barebox.lds + +CLEAN_FILES += arch/riscv/lib/barebox.ldsarch/riscv/boot/Makefile new file +2
-0@@ -0,0 +1,2 @@ +obj-y += start.o +obj-y += main_entry.oarch/riscv/boot/main_entry.c new file +40
-0@@ -0,0 +1,40 @@ +/* +* Copyright (C) 2016 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#include <common.h> +#include <memory.h> +#include <asm-generic/memory_layout.h> +#include <asm/sections.h> + +void main_entry (void ); + +/** +* Called plainly from assembler code +* +* @note The C environment isn't initialized yet +*/ +void main_entry (void ) +{ +/* clear the BSS first */ +memset (__bss_start,0x00 , __bss_stop - __bss_start); + +mem_malloc_init ((void *)MALLOC_BASE , + (void *)(MALLOC_BASE +MALLOC_SIZE -1 )); + +start_barebox (); +}arch/riscv/boot/start.S new file +31
-0@@ -0,0 +1,74 @@ +/* + * Startup Code for MIPS CPU + * + * based on coreboot/src/arch/riscv/bootblock.S + * + * Copyright (C) 2016 Antony Pavlov <[email protected]> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm-generic/memory_layout.h> + + .text + .section ".text_entry" + .align 2 + +.globl _start +_start: + li sp, STACK_BASE + STACK_SIZE +
arch/riscv/boot/start.S line 41
Quoted 10 lines
arch/riscv/boot/start.S new file +10
-0+ # make room for HLS and initialize it + addi sp, sp, -64 /* MENTRY_FRAME_SIZE */ + + # poison the stack + li t1, STACK_BASE + li t0, 0xdeadbeef + sw t0, 0(t1) + + # clear any pending interrupts + //csrwi mip, 0
should be removed.
Quoted 62 lines
arch/riscv/boot/start.S new file +32
-0+ /* copy barebox to link location */ + + la a0, _start /* a0 <- _start actual address */ + li a1, CONFIG_TEXT_BASE /* a1 <- _start link address */ + + beq a0, a1, main_entry + + la a2, __bss_start + +#define LONGSIZE 4 + +copy_loop: + /* copy from source address [a0] */ + lw t0, LONGSIZE * 0(a0) + lw t1, LONGSIZE * 1(a0) + lw t2, LONGSIZE * 2(a0) + lw t3, LONGSIZE * 3(a0) + /* copy to target address [a1] */ + sw t0, LONGSIZE * 0(a1) + sw t1, LONGSIZE * 1(a1) + sw t2, LONGSIZE * 2(a1) + sw t3, LONGSIZE * 3(a1) + addi a0, a0, LONGSIZE * 2 + addi a1, a1, LONGSIZE * 2 + bgeu a2, a0, copy_loop + + /* Alas! At the moment I can't load main_entry __link__ address + into a0 with la. Use CONFIG_TEXT_BASE instead. This solution + leads to extra cycles for repeat sp initialization. */ + + li a0, CONFIG_TEXT_BASE + jalr a0arch/riscv/dts/.gitignore new file +1
-0@@ -0,0 +1 @@ +*dtb*arch/riscv/dts/Makefile new file +9
-0@@ -0,0 +1,9 @@ +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) +obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o + +# just to build a built-in.o. Otherwise compilation fails when no devicetree is +# created. +obj- += dummy.o + +always := $(dtb-y) +clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dtsarch/riscv/dts/skeleton.dtsi new file +2
-0@@ -0,0 +1,13 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and
arch/riscv/dts/skeleton.dtsi line 12
Quoted 10 lines
arch/riscv/dts/skeleton.dtsi new file +10
-0+ * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <2>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0 0>; };
"reg = <0 0>" instead?
Quoted 667 lines
arch/riscv/dts/skeleton.dtsi new file +1
-0+};arch/riscv/include/asm/barebox.h new file +1
-0@@ -0,0 +1 @@ +/* dummy */ arch/riscv/include/asm/bitops.h new file +35
-0@@ -0,0 +1,35 @@ +/* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* +*/ + +#ifndef _ASM_BITOPS_H_ +#define _ASM_BITOPS_H_ + +#include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/ffz.h> +#include <asm-generic/bitops/hweight.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/find.h> +#include <asm-generic/bitops/ops.h> + +#define set_bit (x, y) __set_bit(x, y) +#define clear_bit (x, y) __clear_bit(x, y) +#define change_bit (x, y) __change_bit(x, y) +#define test_and_set_bit (x, y) __test_and_set_bit(x, y) +#define test_and_clear_bit (x, y) __test_and_clear_bit(x, y) +#define test_and_change_bit (x, y) __test_and_change_bit(x, y) + +#endif /* _ASM_BITOPS_H_ */ arch/riscv/include/asm/bitsperlong.h new file +10
-0@@ -0,0 +1,10 @@ +#ifndef __ASM_BITSPERLONG_H +#define __ASM_BITSPERLONG_H + +#ifdef __riscv64 +#define BITS_PER_LONG 64 +#else +#define BITS_PER_LONG 32 +#endif + +#endif /* __ASM_BITSPERLONG_H */ arch/riscv/include/asm/byteorder.h new file +10
-0@@ -0,0 +1,10 @@ +#ifndef _ASM_RISCV_BYTEORDER_H +#define _ASM_RISCV_BYTEORDER_H + +#if defined(__RISCVEB__) +#include <linux/byteorder/big_endian.h> +#else +#include <linux/byteorder/little_endian.h> +#endif + +#endif /* _ASM_RISCV_BYTEORDER_H */ arch/riscv/include/asm/common.h new file +6
-0@@ -0,0 +1,6 @@ +#ifndef ASM_RISCV_COMMON_H +#define ASM_RISCV_COMMON_H + +/* nothing special yet */ + +#endif /* ASM_RISCV_COMMON_H */ arch/riscv/include/asm/elf.h new file +11
-0@@ -0,0 +1,11 @@ +#ifndef __ASM_RISCV_ELF_H__ +#define __ASM_RISCV_ELF_H__ + +#if __SIZEOF_POINTER__ ==8 +#define ELF_CLASS ELFCLASS64 +#define CONFIG_PHYS_ADDR_T_64BIT +#else +#define ELF_CLASS ELFCLASS32 +#endif + +#endif /* __ASM_RISCV_ELF_H__ */ arch/riscv/include/asm/io.h new file +8
-0@@ -0,0 +1,8 @@ +#ifndef __ASM_RISCV_IO_H +#define __ASM_RISCV_IO_H + +#define IO_SPACE_LIMIT 0 + +#include <asm-generic/io.h> + +#endif /* __ASM_RISCV_IO_H */ arch/riscv/include/asm/mmu.h new file +6
-0@@ -0,0 +1,6 @@ +#ifndef __ASM_MMU_H +#define __ASM_MMU_H + +#define MAP_ARCH_DEFAULT MAP_UNCACHED + +#endif /* __ASM_MMU_H */ arch/riscv/include/asm/posix_types.h new file +1
-0@@ -0,0 +1 @@ +#include <asm-generic/posix_types.h> arch/riscv/include/asm/sections.h new file +1
-0@@ -0,0 +1 @@ +#include <asm-generic/sections.h> arch/riscv/include/asm/string.h new file +1
-0@@ -0,0 +1 @@ +/* dummy */ arch/riscv/include/asm/swab.h new file +6
-0@@ -0,0 +1,6 @@ +#ifndef _ASM_SWAB_H +#define _ASM_SWAB_H + +/* nothing. use generic functions */ + +#endif /* _ASM_SWAB_H */ arch/riscv/include/asm/types.h new file +60
-0@@ -0,0 +1,60 @@ +#ifndef __ASM_RISCV_TYPES_H +#define __ASM_RISCV_TYPES_H + +#ifdef __riscv64 +/* +* This is used in dlmalloc. On RISCV64 we need it to be 64 bit +*/ +#define INTERNAL_SIZE_T unsigned long + +/* +* This is a Kconfig variable in the Kernel, but we want to detect +* this during compile time, so we set it here. +*/ +#define CONFIG_PHYS_ADDR_T_64BIT + +#endif + +typedef unsigned short umode_t ; + +/* +* __xx is ok: it doesn't pollute the POSIX namespace. Use these in the +* header files exported to user space +*/ + +typedef __signed__ char __s8; +typedef unsigned char __u8 ; + +typedef __signed__ short __s16 ; +typedef unsigned short __u16 ; + +typedef __signed__ int __s32; +typedef unsigned int __u32 ; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64 ; +typedef unsigned long long __u64 ; +#endif + +/* +* These aren't exported outside the kernel to avoid name space clashes +*/ +#ifdef __KERNEL__ + +typedef signed char s8 ; +typedef unsigned char u8 ; + +typedef signed short s16 ; +typedef unsigned short u16 ; + +typedef signed int s32 ; +typedef unsigned int u32 ; + +typedef signed long long s64 ; +typedef unsigned long long u64 ; + +#include <asm/bitsperlong.h> + +#endif /* __KERNEL__ */ + +#endif /* __ASM_RISCV_TYPES_H */ arch/riscv/include/asm/unaligned.h new file +19
-0@@ -0,0 +1,19 @@ +#ifndef _ASM_RISCV_UNALIGNED_H +#define _ASM_RISCV_UNALIGNED_H + +/* +* FIXME: this file is copy-n-pasted from sandbox's unaligned.h +*/ + +#include <linux/unaligned/access_ok.h> +#include <linux/unaligned/generic.h> + +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le +#else +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be +#endif + +#endif /* _ASM_RISCV_UNALIGNED_H */ arch/riscv/lib/.gitignore new file +1
-0@@ -0,0 +1 @@ +barebox.ldsarch/riscv/lib/Makefile new file +9
-0@@ -0,0 +1,9 @@ +extra-$(CONFIG_GENERIC_LINKER_SCRIPT) += barebox.lds + +obj-y += riscv_timer.o + +obj-$(CONFIG_32BIT) += lshrdi3.o +obj-$(CONFIG_32BIT) += ashldi3.o +obj-$(CONFIG_32BIT) += ashrdi3.o + +obj-$(CONFIG_BUILTIN_DTB) += dtb.oarch/riscv/lib/ashldi3.c new file +28
-0@@ -0,0 +1,28 @@ +#include <module.h> + +#include "libgcc.h" + +long long __ashldi3 (long long u,word_type b) +{ +DWunion uu, w; +word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { + w.s.low =0 ; + w.s.high = (unsigned int ) uu.s.low << -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.low >> bm; + + w.s.low = (unsigned int ) uu.s.low << b; + w.s.high = ((unsigned int ) uu.s.high << b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__ashldi3);arch/riscv/lib/ashrdi3.c new file +29
-0@@ -0,0 +1,30 @@ +#include <module.h> + +#include "libgcc.h" + +long long __ashrdi3 (long long u,word_type b) +{ + DWunion uu, w> + word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { +/* w.s.high = 1..1 or 0..0 */ + w.s.high = + uu.s.high >>31 ; + w.s.low = uu.s.high >> -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.high << bm; + + w.s.high = uu.s.high >> b; + w.s.low = ((unsigned int ) uu.s.low >> b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__ashrdi3);arch/riscv/lib/asm-offsets.c new file +12
-0@@ -0,0 +1,12 @@ +/* +* Generate definitions needed by assembly language modules. +* This code generates raw asm output which is post-processed to extract +* and format the required data. +*/ + +#include <linux/kbuild.h> + +int main (void ) +{ +return 0 ; +}arch/riscv/lib/barebox.lds.S new file +89
-0@@ -0,0 +1,89 @@ +/* + * Copyright (C) 2016 Antony Pavlov <[email protected]> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm-generic/barebox.lds.h> + +OUTPUT_ARCH(riscv) +ENTRY(_start) +SECTIONS +{ + . = TEXT_BASE; + + . = ALIGN(8); + .text : + { + _stext = .; + _start = .; + KEEP(*(.text_entry*)) + _text = .; + __bare_init_start = .; + *(.text_bare_init*) + __bare_init_end = .; + *(.text*) + } + BAREBOX_BARE_INIT_SIZE + + PRE_IMAGE + + . = ALIGN(8); + .rodata : { *(.rodata*) } + + _etext = .; /* End of text and rodata section */ + _sdata = .; + + . = ALIGN(8); + .data : { *(.data*) } + + .barebox_imd : { BAREBOX_IMD } + + . = ALIGN(8); + .got : { *(.got*) } + + . = .; + __barebox_cmd_start = .; + .barebox_cmd : { BAREBOX_CMDS } + __barebox_cmd_end = .; + + __barebox_magicvar_start = .; + .barebox_magicvar : { BAREBOX_MAGICVARS } + __barebox_magicvar_end = .; + + __barebox_initcalls_start = .; + .barebox_initcalls : { INITCALLS } + __barebox_initcalls_end = .; + + __barebox_exitcalls_start = .; + .barebox_exitcalls : { EXITCALLS } + __barebox_exitcalls_end = .; + + __usymtab_start = .; + __usymtab : { BAREBOX_SYMS } + __usymtab_end = .; + + .rela.dyn : { *(.rela*) } + + .oftables : { BAREBOX_CLK_TABLE() } + + .dtb : { BAREBOX_DTB() } + + _edata = .; + . = ALIGN(8); + __bss_start = .; + .bss : { *(.bss*) *(.sbss*) } + __bss_stop = .; + _end = .; +}arch/riscv/lib/dtb.c new file +41
-0@@ -0,0 +1,41 @@ +/* +* Copyright (C) 2016 Antony Pavlov <[email protected]> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ +#include <common.h> +#include <init.h> +#include <of.h> + +extern char __dtb_start[]; + +static int of_riscv_init (void ) +{ +struct device_node *root; + + root =of_get_root_node (); +if (root) +return 0 ; + + root =of_unflatten_dtb (__dtb_start); +if (!IS_ERR (root)) { +pr_debug ("using internal DTB\n" ); +of_set_root_node (root); +if (IS_ENABLED (CONFIG_OFDEVICE )) +of_probe (); + } + +return 0 ; +} +core_initcall (of_riscv_init);arch/riscv/lib/libgcc.h new file +28
-0@@ -0,0 +1,29 @@ +#ifndef __ASM_LIBGCC_H +#define __ASM_LIBGCC_H + +#include <asm/byteorder.h> + +typedef int word_type __attribute__ ((mode (__word__))); +#ifdef __BIG_ENDIAN +struct DWstruct { +int high, low; +}; +#elif defined(__LITTLE_ENDIAN) +struct DWstruct { +int low, high; +}; +#else +#error I feel sick. +#endif + +typedef union { +struct DWstruct s; +long long ll; +}DWunion ; + +long long __lshrdi3 (long long u,word_type b); +long long __ashldi3 (long long u,word_type b); +long long __ashrdi3 (long long u,word_type b); + +#endif /* __ASM_LIBGCC_H */ arch/riscv/lib/lshrdi3.c new file +28
-0@@ -0,0 +1,28 @@ +#include <module.h> + +#include "libgcc.h" + +long long __lshrdi3 (long long u,word_type b) +{ +DWunion uu, w; +word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { + w.s.high =0 ; + w.s.low = (unsigned int ) uu.s.high >> -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.high << bm; + + w.s.high = (unsigned int ) uu.s.high >> b; + w.s.low = ((unsigned int ) uu.s.low >> b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__lshrdi3);arch/riscv/lib/riscv_timer.c new file +68
-0@@ -0,0 +1,68 @@ +/* +* Copyright (C) 2017 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +/** +* @file +* @brief Clocksource based on RISCV cycle CSR timer +*/ + +#include <init.h> +#include <of.h> +#include <linux/clk.h> +#include <clock.h> +#include <io.h> + +static uint64_t rdcycle_read (void ) +{ + registerunsigned long __v; + + __asm__ __volatile__ ("rdcycle %0" :"=r" (__v)); + +return __v; +} + +static struct clocksource rdcycle_cs = { + .read = rdcycle_read, + .mask =CLOCKSOURCE_MASK (32 ), +}; + +static int rdcycle_cs_init (void ) +{ +unsigned int cycle_frequency; + +/* default rate: 100 MHz */ + cycle_frequency =100000000 ; + +if (IS_ENABLED (CONFIG_OFTREE )) { +struct device_node *np; +struct clk *clk; + + np =of_get_cpu_node (0 ,NULL ); +if (np) { + clk =of_clk_get (np,0 ); +if (!IS_ERR (clk)) { + cycle_frequency =clk_get_rate (clk); + } + } + } + +clocks_calc_mult_shift (&rdcycle_cs.mult, &rdcycle_cs.shift, + cycle_frequency,NSEC_PER_SEC ,10 ); + +return init_clock (&rdcycle_cs); +} +postcore_initcall (rdcycle_cs_init);drivers/of/Kconfig +1
-1@@ -4,7 +4,7 @@ config OFTREE config OFTREE_MEM_GENERIC depends on OFTREE - depends on PPC || ARM || EFI_BOOTUP || OPENRISC || SANDBOX + depends on PPC || ARM || EFI_BOOTUP || OPENRISC || SANDBOX || RISCV def_bool y config DTC
Signature · 2 lines
Regards, Oleksij
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Re: [RFC v4 01/10] Add initial RISC-V architecture support
Quoted 3 lines · On Fri, 29 Sep 2017 14:07:09 +0200 Oleksij Rempel <[email protected]>…
Hi,
hm... mostly looks identical with existing arch
What do you mean when you say "existing arch"?
...
Quoted 1 line
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
...
Quoted 41 lines
Quoted 41 lines
arch/riscv/boot/start.S new file +35
-0@@ -0,0 +1,74 @@ +/* + * Startup Code for MIPS CPU + * + * based on coreboot/src/arch/riscv/bootblock.S + * + * Copyright (C) 2016 Antony Pavlov <[email protected]> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm-generic/memory_layout.h> + + .text + .section ".text_entry" + .align 2 + +.globl _start +_start: + li sp, STACK_BASE + STACK_SIZE + + # make room for HLS and initialize it + addi sp, sp, -64 /* MENTRY_FRAME_SIZE */ + + # poison the stack
Quoted 8 lines
arch/riscv/boot/start.S line 41
Quoted 6 lines
arch/riscv/boot/start.S new file +6
-0+ li t1, STACK_BASE + li t0, 0xdeadbeef + sw t0, 0(t1) + + # clear any pending interrupts + //csrwi mip, 0should be removed.
Actually not!
I have imported this code from coreboot.
I have commented this line because csrwi does not worked in some cases.
But I have to make additional investigations on csrwi.
Quoted 67 lines
Quoted 67 lines
arch/riscv/boot/start.S new file +32
-0+ /* copy barebox to link location */ + + la a0, _start /* a0 <- _start actual address */ + li a1, CONFIG_TEXT_BASE /* a1 <- _start link address */ + + beq a0, a1, main_entry + + la a2, __bss_start + +#define LONGSIZE 4 + +copy_loop: + /* copy from source address [a0] */ + lw t0, LONGSIZE * 0(a0) + lw t1, LONGSIZE * 1(a0) + lw t2, LONGSIZE * 2(a0) + lw t3, LONGSIZE * 3(a0) + /* copy to target address [a1] */ + sw t0, LONGSIZE * 0(a1) + sw t1, LONGSIZE * 1(a1) + sw t2, LONGSIZE * 2(a1) + sw t3, LONGSIZE * 3(a1) + addi a0, a0, LONGSIZE * 2 + addi a1, a1, LONGSIZE * 2 + bgeu a2, a0, copy_loop + + /* Alas! At the moment I can't load main_entry __link__ address + into a0 with la. Use CONFIG_TEXT_BASE instead. This solution + leads to extra cycles for repeat sp initialization. */ + + li a0, CONFIG_TEXT_BASE + jalr a0arch/riscv/dts/.gitignore new file +1
-0@@ -0,0 +1 @@ +*dtb*arch/riscv/dts/Makefile new file +9
-0@@ -0,0 +1,9 @@ +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) +obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o + +# just to build a built-in.o. Otherwise compilation fails when no devicetree is +# created. +obj- += dummy.o + +always := $(dtb-y) +clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dtsarch/riscv/dts/skeleton.dtsi new file +6
-0@@ -0,0 +1,13 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + */ +
Quoted 8 lines
arch/riscv/dts/skeleton.dtsi line 12
Quoted 6 lines
arch/riscv/dts/skeleton.dtsi new file +6
-0+/ { + #address-cells = <2>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0 0>; };"reg = <0 0>" instead?
no.
We have
#address-cells = <2>; #size-cells = <1>;
here.
Signature · 7 lines
Best regards, Antony Pavlov _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC v4 01/10] Add initial RISC-V architecture support
Hi,
Am 30.09.2017 um 13:57 schrieb Antony Pavlov:
Quoted 8 lines
Quoted 3 lines · On Fri, 29 Sep 2017 14:07:09 +0200 Oleksij Rempel <[email protected]>…
Hi,
hm... mostly looks identical with existing arch
What do you mean when you say "existing arch"?
it is a note for me. I just compared it with MIPS
Quoted 4 lines
...
Quoted 1 line
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
...
Quoted 8 lines
Quoted 8 lines
arch/riscv/boot/start.S line 2
Quoted 8 lines
arch/riscv/boot/start.S new file +2
-0@@ -0,0 +1,74 @@ +/* + * Startup Code for MIPS CPU
Beside here is a copy paste ^^^ artefact :)
Quoted 4 lines
Quoted 4 lines
Quoted 4 lines
arch/riscv/boot/start.S new file +4
-0+ * based on coreboot/src/arch/riscv/bootblock.S + * + * Copyright (C) 2016 Antony Pavlov <[email protected]> + *
Signature · 2 lines
Regards, Oleksij
_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC v4 01/10] Add initial RISC-V architecture support
Quoted 17 lines · On Mon, 2 Oct 2017 09:43:02 +0200 Oleksij Rempel <[email protected]> wrote:
Hi,
Am 30.09.2017 um 13:57 schrieb Antony Pavlov:
Quoted 8 lines
Quoted 3 lines · On Fri, 29 Sep 2017 14:07:09 +0200 Oleksij Rempel <[email protected]>…
Hi,
hm... mostly looks identical with existing arch
What do you mean when you say "existing arch"?
it is a note for me. I just compared it with MIPS
Quoted 4 lines
...
Quoted 1 line
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
...
Quoted 10 lines
Quoted 8 lines
Quoted 8 lines
arch/riscv/boot/start.S line 2
Quoted 8 lines
arch/riscv/boot/start.S new file +2
-0@@ -0,0 +1,74 @@ +/* + * Startup Code for MIPS CPUBeside here is a copy paste ^^^ artefact :)
Thanks! I have just fixed this.
Quoted 5 lines
Quoted 5 lines
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Quoted 5 lines
arch/riscv/boot/start.S new file +4
-0+ * based on coreboot/src/arch/riscv/bootblock.S + * + * Copyright (C) 2016 Antony Pavlov <[email protected]> + *
Signature · 7 lines
Best regards, Antony Pavlov _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC v4 01/10] Add initial RISC-V architecture support
In reply to Antony PavlovHi,
Quoted 60 lines · Antony Pavlov
Quoted 3 lines · On Fri, 29 Sep 2017 14:07:09 +0200 Oleksij Rempel <[email protected]>…
Hi,
hm... mostly looks identical with existing arch
What do you mean when you say "existing arch"?
...
Quoted 1 line
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
...
Quoted 40 lines
Quoted 40 lines
arch/riscv/boot/start.S new file +34
-0@@ -0,0 +1,74 @@ +/* + * Startup Code for MIPS CPU + * + * based on coreboot/src/arch/riscv/bootblock.S + * + * Copyright (C) 2016 Antony Pavlov <[email protected]> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm-generic/memory_layout.h> + + .text + .section ".text_entry" + .align 2 + +.globl _start +_start: + li sp, STACK_BASE + STACK_SIZE + + # make room for HLS and initialize it + addi sp, sp, -64 /* MENTRY_FRAME_SIZE */ +Quoted 8 lines
arch/riscv/boot/start.S line 41
Quoted 7 lines
arch/riscv/boot/start.S new file +7
-0+ # poison the stack + li t1, STACK_BASE + li t0, 0xdeadbeef + sw t0, 0(t1) + + # clear any pending interrupts + //csrwi mip, 0should be removed.
Quoted 8 lines
Actually not!
I have imported this code from coreboot.
I have commented this line because csrwi does not worked in some cases.
But I have to make additional investigations on csrwi.
CSRRWI is part of the base integer instruction set and the machine mode is mandatory. If there are troubles with this instruction, the core has a faulty design. So executing this line should be okay even if there is no interrupt controller.
Signature · 9 lines
Mit freundlichen Grüßen, With best regards, Daniel Schultz _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC v4 01/10] Add initial RISC-V architecture support
Quoted 68 lines · On Mon, 2 Oct 2017 12:04:30 +0200 Daniel Schultz <[email protected]> wrote:
Hi,
Quoted 64 lines · Antony Pavlov
Quoted 3 lines · On Fri, 29 Sep 2017 14:07:09 +0200 Oleksij Rempel <[email protected]>…
Hi,
hm... mostly looks identical with existing arch
What do you mean when you say "existing arch"?
...
Quoted 1 line
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
...
Quoted 40 lines
Quoted 40 lines
arch/riscv/boot/start.S new file +34
-0@@ -0,0 +1,74 @@ +/* + * Startup Code for MIPS CPU + * + * based on coreboot/src/arch/riscv/bootblock.S + * + * Copyright (C) 2016 Antony Pavlov <[email protected]> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm-generic/memory_layout.h> + + .text + .section ".text_entry" + .align 2 + +.globl _start +_start: + li sp, STACK_BASE + STACK_SIZE + + # make room for HLS and initialize it + addi sp, sp, -64 /* MENTRY_FRAME_SIZE */ +Quoted 8 lines
arch/riscv/boot/start.S line 41
Quoted 7 lines
arch/riscv/boot/start.S new file +7
-0+ # poison the stack + li t1, STACK_BASE + li t0, 0xdeadbeef + sw t0, 0(t1) + + # clear any pending interrupts + //csrwi mip, 0should be removed.
Actually not!
I have imported this code from coreboot.
Quoted 9 lines
Quoted 4 lines
I have commented this line because csrwi does not worked in some cases.
But I have to make additional investigations on csrwi.
CSRRWI is part of the base integer instruction set and the machine mode is mandatory. If there are troubles with this instruction, the core has a faulty design. So executing this line should be okay even if there is no interrupt controller.
It's not a bug, it's a feature :)
At the moment I use picorv32 core.
Here is a quote from https://github.com/cliffordwolf/picorv32#custom-instructions-for-irq-handling
The IRQ handling features in PicoRV32 do not follow the RISC-V Privileged ISA specification. Instead a small set of very simple custom instructions is used to implement IRQ handling with minimal hardware overhead.
I'm planning to make it possible to use another core instead of picorv32 in Eriso SoC, so I can introduce something like SYS_HAS_PICORV32_CPU Kconfig macro.
Quoted 10 lines
Signature · 9 lines
Mit freundlichen Grüßen, With best regards, Daniel Schultz _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Signature · 7 lines
Best regards, Antony Pavlov _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC v4 01/10] Add initial RISC-V architecture support
In reply to Oleksij RempelHi,
Quoted 986 lines · Oleksij Rempel
Hi,
hm... mostly looks identical with existing arch
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
Quoted 284 lines
Signed-off-by Antony Pavlov <[email protected]>--
TODOs:* split patch;
--- arch/riscv/Kconfig | 73 +++++++++++++++++++++++++++++ arch/riscv/Makefile | 68 +++++++++++++++++++++++++++ arch/riscv/boot/Makefile | 2 + arch/riscv/boot/main_entry.c | 40 ++++++++++++++++ arch/riscv/boot/start.S | 74 ++++++++++++++++++++++++++++++ arch/riscv/dts/.gitignore | > arch/riscv/dts/Makefile | 9 ++++ arch/riscv/dts/skeleton.dtsi | 13 ++++++ arch/riscv/include/asm/barebox.h | 1 + arch/riscv/include/asm/bitops.h | 35 ++++++++++++++ arch/riscv/include/asm/bitsperlong.h | 10 ++++ arch/riscv/include/asm/byteorder.h | 10 ++++ arch/riscv/include/asm/common.h | 6 +++ arch/riscv/include/asm/elf.h | 11 +++++ arch/riscv/include/asm/io.h | 8 ++++ arch/riscv/include/asm/mmu.h | 6 +++ arch/riscv/include/asm/posix_types.h | 1 + arch/riscv/include/asm/sections.h | 1 + arch/riscv/include/asm/string.h | 1 + arch/riscv/include/asm/swab.h | 6 +++ arch/riscv/include/asm/types.h | 60 ++++++++++++++++++++++++ arch/riscv/include/asm/unaligned.h | 19 ++++++++ arch/riscv/lib/.gitignore | 1 + arch/riscv/lib/Makefile | 9 ++++ arch/riscv/lib/ashldi3.c | 28 ++++++++++++ arch/riscv/lib/ashrdi3.c | 30 ++++++++++++ arch/riscv/lib/asm-offsets.c | 12 +++++ arch/riscv/lib/barebox.lds.S | 89 ++++++++++++++++++++++++++++++++++++ arch/riscv/lib/dtb.c | 41 +++++++++++++++++ arch/riscv/lib/libgcc.h | 29 ++++++++++++ arch/riscv/lib/lshrdi3.c | 28 ++++++++++++ arch/riscv/lib/riscv_timer.c | 68 +++++++++++++++++++++++++++ drivers/of/Kconfig | 2 +- 33 files changed, 791 insertions(+), 1 deletion(-)arch/riscv/Kconfig new file +73
-0@@ -0,0 +1,73 @@ +config RISCV + bool + select GENERIC_FIND_NEXT_BIT + select HAVE_CONFIGURABLE_MEMORY_LAYOUT + select HAVE_CONFIGURABLE_TEXT_BASE + select GPIOLIB + select OFTREE + select COMMON_CLK + select COMMON_CLK_OF_PROVIDER + select CLKDEV_LOOKUP + default y + +config ARCH_TEXT_BASE + hex + default 0x0 + +config GENERIC_LINKER_SCRIPT + bool + default y + +menu "Machine selection" + +choice + prompt "CPU selection" + default CPU_RV_GENERIC + +config CPU_RV_GENERIC + bool "Generic RISC-V" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + +endchoice + +config CPU_SUPPORTS_32BIT_KERNEL + bool +config CPU_SUPPORTS_64BIT_KERNEL + bool + +choice + prompt "barebox code model" + default 64BIT + +config 32BIT + bool "32-bit barebox" + depends on CPU_SUPPORTS_32BIT_KERNEL + help + Select this option to build a 32-bit barebox. + +config 64BIT + bool "64-bit barebox" + depends on CPU_SUPPORTS_64BIT_KERNEL + help + Select this option to build a 64-bit barebox. + +endchoice + +config BUILTIN_DTB + bool "link a DTB into the barebox image" + depends on OFTREE + +config BUILTIN_DTB_NAME + string "DTB to build into the barebox image" + depends on BUILTIN_DTB + +endmenu + +source common/Kconfig +source commands/Kconfig +source net/Kconfig +source drivers/Kconfig +source fs/Kconfig +source lib/Kconfig +source crypto/Kconfigarch/riscv/Makefile new file +68
-0@@ -0,0 +1,68 @@ +CPPFLAGS += -fno-strict-aliasing + +cflags-y += -fno-pic -pipe +cflags-y += -Wall -Wmissing-prototypes -Wstrict-prototypes \ + -Wno-uninitialized -Wno-format -Wno-main -mcmodel=medany + +LDFLAGS += $(ldflags-y) +LDFLAGS_barebox += -nostdlib + +TEXT_BASE = $(CONFIG_TEXT_BASE) +CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE) + +ifndef CONFIG_MODULES +# Add cleanup flags +CPPFLAGS += -fdata-sections -ffunction-sections +LDFLAGS_barebox += -static --gc-sections +endif + +KBUILD_BINARY := barebox.bin + +machdirs := $(patsubst %,arch/riscv/mach-%/,$(machine-y)) + +ifneq ($(board-y),) +BOARD := arch/riscv/boards/$(board-y)/ +else +BOARD := +endif + +ifeq ($(KBUILD_SRC),) +CPPFLAGS += -I$(BOARD)/include +else +CPPFLAGS += -I$(srctree)/$(BOARD)/include +endif + +ifeq ($(KBUILD_SRC),) +CPPFLAGS += $(patsubst %,-I%include,$(machdirs)) +else +CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) +endif + +archprepare: maketools + +PHONY += maketools + +ifneq ($(machine-y),) +MACH := arch/riscv/mach-$(machine-y)/ +else +MACH := +endif + +ifneq ($(board-y),) +BOARD := arch/riscv/boards/$(board-y)/ +else +BOARD := +endif + +common-y += $(BOARD) $(MACH) +common-y += arch/riscv/lib/ +common-y += arch/riscv/boot/ + +common-$(CONFIG_OFTREE) += arch/riscv/dts/ + +CPPFLAGS += $(cflags-y) +CFLAGS += $(cflags-y) + +lds-y := arch/riscv/lib/barebox.lds + +CLEAN_FILES += arch/riscv/lib/barebox.ldsarch/riscv/boot/Makefile new file +2
-0@@ -0,0 +1,2 @@ +obj-y += start.o +obj-y += main_entry.oarch/riscv/boot/main_entry.c new file +40
-0@@ -0,0 +1,40 @@ +/* +* Copyright (C) 2016 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#include <common.h> +#include <memory.h> +#include <asm-generic/memory_layout.h> +#include <asm/sections.h> + +void main_entry (void ); + +/** +* Called plainly from assembler code +* +* @note The C environment isn't initialized yet +*/ +void main_entry (void ) +{ +/* clear the BSS first */ +memset (__bss_start,0x00 , __bss_stop - __bss_start); + +mem_malloc_init ((void *)MALLOC_BASE , + (void *)(MALLOC_BASE +MALLOC_SIZE -1 )); + +start_barebox (); +}arch/riscv/boot/start.S new file +31
-0@@ -0,0 +1,74 @@ +/* + * Startup Code for MIPS CPU + * + * based on coreboot/src/arch/riscv/bootblock.S + * + * Copyright (C) 2016 Antony Pavlov <[email protected]> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm-generic/memory_layout.h> + + .text + .section ".text_entry" + .align 2 + +.globl _start +_start: + li sp, STACK_BASE + STACK_SIZE +arch/riscv/boot/start.S line 41
Quoted 10 lines
arch/riscv/boot/start.S new file +10
-0+ # make room for HLS and initialize it + addi sp, sp, -64 /* MENTRY_FRAME_SIZE */ + + # poison the stack + li t1, STACK_BASE + li t0, 0xdeadbeef + sw t0, 0(t1) + + # clear any pending interrupts + //csrwi mip, 0should be removed.
Quoted 62 lines
arch/riscv/boot/start.S new file +32
-0+ /* copy barebox to link location */ + + la a0, _start /* a0 <- _start actual address */ + li a1, CONFIG_TEXT_BASE /* a1 <- _start link address */ + + beq a0, a1, main_entry + + la a2, __bss_start + +#define LONGSIZE 4 + +copy_loop: + /* copy from source address [a0] */ + lw t0, LONGSIZE * 0(a0) + lw t1, LONGSIZE * 1(a0) + lw t2, LONGSIZE * 2(a0) + lw t3, LONGSIZE * 3(a0) + /* copy to target address [a1] */ + sw t0, LONGSIZE * 0(a1) + sw t1, LONGSIZE * 1(a1) + sw t2, LONGSIZE * 2(a1) + sw t3, LONGSIZE * 3(a1) + addi a0, a0, LONGSIZE * 2 + addi a1, a1, LONGSIZE * 2 + bgeu a2, a0, copy_loop + + /* Alas! At the moment I can't load main_entry __link__ address + into a0 with la. Use CONFIG_TEXT_BASE instead. This solution + leads to extra cycles for repeat sp initialization. */ + + li a0, CONFIG_TEXT_BASE + jalr a0arch/riscv/dts/.gitignore new file +1
-0@@ -0,0 +1 @@ +*dtb*arch/riscv/dts/Makefile new file +9
-0@@ -0,0 +1,9 @@ +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) +obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o + +# just to build a built-in.o. Otherwise compilation fails when no devicetree is +# created. +obj- += dummy.o + +always := $(dtb-y) +clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dtsarch/riscv/dts/skeleton.dtsi new file +2
-0@@ -0,0 +1,13 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include andarch/riscv/dts/skeleton.dtsi line 12
Quoted 10 lines
arch/riscv/dts/skeleton.dtsi new file +10
-0+ * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <2>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0 0>; };"reg = <0 0>" instead?
Quoted 611 lines
arch/riscv/dts/skeleton.dtsi new file +1
-0+};arch/riscv/include/asm/barebox.h new file +1
-0@@ -0,0 +1 @@ +/* dummy */ arch/riscv/include/asm/bitops.h new file +35
-0@@ -0,0 +1,35 @@ +/* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* +*/ + +#ifndef _ASM_BITOPS_H_ +#define _ASM_BITOPS_H_ + +#include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/ffz.h> +#include <asm-generic/bitops/hweight.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/find.h> +#include <asm-generic/bitops/ops.h> + +#define set_bit (x, y) __set_bit(x, y) +#define clear_bit (x, y) __clear_bit(x, y) +#define change_bit (x, y) __change_bit(x, y) +#define test_and_set_bit (x, y) __test_and_set_bit(x, y) +#define test_and_clear_bit (x, y) __test_and_clear_bit(x, y) +#define test_and_change_bit (x, y) __test_and_change_bit(x, y) + +#endif /* _ASM_BITOPS_H_ */ arch/riscv/include/asm/bitsperlong.h new file +10
-0@@ -0,0 +1,10 @@ +#ifndef __ASM_BITSPERLONG_H +#define __ASM_BITSPERLONG_H + +#ifdef __riscv64 +#define BITS_PER_LONG 64 +#else +#define BITS_PER_LONG 32 +#endif + +#endif /* __ASM_BITSPERLONG_H */ arch/riscv/include/asm/byteorder.h new file +10
-0@@ -0,0 +1,10 @@ +#ifndef _ASM_RISCV_BYTEORDER_H +#define _ASM_RISCV_BYTEORDER_H + +#if defined(__RISCVEB__) +#include <linux/byteorder/big_endian.h> +#else +#include <linux/byteorder/little_endian.h> +#endif + +#endif /* _ASM_RISCV_BYTEORDER_H */ arch/riscv/include/asm/common.h new file +6
-0@@ -0,0 +1,6 @@ +#ifndef ASM_RISCV_COMMON_H +#define ASM_RISCV_COMMON_H + +/* nothing special yet */ + +#endif /* ASM_RISCV_COMMON_H */ arch/riscv/include/asm/elf.h new file +11
-0@@ -0,0 +1,11 @@ +#ifndef __ASM_RISCV_ELF_H__ +#define __ASM_RISCV_ELF_H__ + +#if __SIZEOF_POINTER__ ==8 +#define ELF_CLASS ELFCLASS64 +#define CONFIG_PHYS_ADDR_T_64BIT +#else +#define ELF_CLASS ELFCLASS32 +#endif + +#endif /* __ASM_RISCV_ELF_H__ */ arch/riscv/include/asm/io.h new file +8
-0@@ -0,0 +1,8 @@ +#ifndef __ASM_RISCV_IO_H +#define __ASM_RISCV_IO_H + +#define IO_SPACE_LIMIT 0 + +#include <asm-generic/io.h> + +#endif /* __ASM_RISCV_IO_H */ arch/riscv/include/asm/mmu.h new file +6
-0@@ -0,0 +1,6 @@ +#ifndef __ASM_MMU_H +#define __ASM_MMU_H + +#define MAP_ARCH_DEFAULT MAP_UNCACHED + +#endif /* __ASM_MMU_H */ arch/riscv/include/asm/posix_types.h new file +1
-0@@ -0,0 +1 @@ +#include <asm-generic/posix_types.h> arch/riscv/include/asm/sections.h new file +1
-0@@ -0,0 +1 @@ +#include <asm-generic/sections.h> arch/riscv/include/asm/string.h new file +1
-0@@ -0,0 +1 @@ +/* dummy */ arch/riscv/include/asm/swab.h new file +6
-0@@ -0,0 +1,6 @@ +#ifndef _ASM_SWAB_H +#define _ASM_SWAB_H + +/* nothing. use generic functions */ + +#endif /* _ASM_SWAB_H */ arch/riscv/include/asm/types.h new file +60
-0@@ -0,0 +1,60 @@ +#ifndef __ASM_RISCV_TYPES_H +#define __ASM_RISCV_TYPES_H + +#ifdef __riscv64 +/* +* This is used in dlmalloc. On RISCV64 we need it to be 64 bit +*/ +#define INTERNAL_SIZE_T unsigned long + +/* +* This is a Kconfig variable in the Kernel, but we want to detect +* this during compile time, so we set it here. +*/ +#define CONFIG_PHYS_ADDR_T_64BIT + +#endif + +typedef unsigned short umode_t ; + +/* +* __xx is ok: it doesn't pollute the POSIX namespace. Use these in the +* header files exported to user space +*/ + +typedef __signed__ char __s8; +typedef unsigned char __u8 ; + +typedef __signed__ short __s16 ; +typedef unsigned short __u16 ; + +typedef __signed__ int __s32; +typedef unsigned int __u32 ; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64 ; +typedef unsigned long long __u64 ; +#endif + +/* +* These aren't exported outside the kernel to avoid name space clashes +*/ +#ifdef __KERNEL__ + +typedef signed char s8 ; +typedef unsigned char u8 ; + +typedef signed short s16 ; +typedef unsigned short u16 ; + +typedef signed int s32 ; +typedef unsigned int u32 ; + +typedef signed long long s64 ; +typedef unsigned long long u64 ; + +#include <asm/bitsperlong.h> + +#endif /* __KERNEL__ */ + +#endif /* __ASM_RISCV_TYPES_H */ arch/riscv/include/asm/unaligned.h new file +19
-0@@ -0,0 +1,19 @@ +#ifndef _ASM_RISCV_UNALIGNED_H +#define _ASM_RISCV_UNALIGNED_H + +/* +* FIXME: this file is copy-n-pasted from sandbox's unaligned.h +*/ + +#include <linux/unaligned/access_ok.h> +#include <linux/unaligned/generic.h> + +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le +#else +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be +#endif + +#endif /* _ASM_RISCV_UNALIGNED_H */ arch/riscv/lib/.gitignore new file +1
-0@@ -0,0 +1 @@ +barebox.ldsarch/riscv/lib/Makefile new file +9
-0@@ -0,0 +1,9 @@ +extra-$(CONFIG_GENERIC_LINKER_SCRIPT) += barebox.lds + +obj-y += riscv_timer.o + +obj-$(CONFIG_32BIT) += lshrdi3.o +obj-$(CONFIG_32BIT) += ashldi3.o +obj-$(CONFIG_32BIT) += ashrdi3.o + +obj-$(CONFIG_BUILTIN_DTB) += dtb.oarch/riscv/lib/ashldi3.c new file +28
-0@@ -0,0 +1,28 @@ +#include <module.h> + +#include "libgcc.h" + +long long __ashldi3 (long long u,word_type b) +{ +DWunion uu, w; +word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { + w.s.low =0 ; + w.s.high = (unsigned int ) uu.s.low << -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.low >> bm; + + w.s.low = (unsigned int ) uu.s.low << b; + w.s.high = ((unsigned int ) uu.s.high << b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__ashldi3);arch/riscv/lib/ashrdi3.c new file +29
-0@@ -0,0 +1,30 @@ +#include <module.h> + +#include "libgcc.h" + +long long __ashrdi3 (long long u,word_type b) +{ + DWunion uu, w> + word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { +/* w.s.high = 1..1 or 0..0 */ + w.s.high = + uu.s.high >>31 ; + w.s.low = uu.s.high >> -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.high << bm; + + w.s.high = uu.s.high >> b; + w.s.low = ((unsigned int ) uu.s.low >> b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__ashrdi3);arch/riscv/lib/asm-offsets.c new file +12
-0@@ -0,0 +1,12 @@ +/* +* Generate definitions needed by assembly language modules. +* This code generates raw asm output which is post-processed to extract +* and format the required data. +*/ + +#include <linux/kbuild.h> + +int main (void ) +{ +return 0 ; +}arch/riscv/lib/barebox.lds.S new file +89
-0@@ -0,0 +1,89 @@ +/* + * Copyright (C) 2016 Antony Pavlov <[email protected]> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm-generic/barebox.lds.h> + +OUTPUT_ARCH(riscv) +ENTRY(_start) +SECTIONS +{ + . = TEXT_BASE; + + . = ALIGN(8); + .text : + { + _stext = .; + _start = .; + KEEP(*(.text_entry*)) + _text = .; + __bare_init_start = .; + *(.text_bare_init*) + __bare_init_end = .; + *(.text*) + } + BAREBOX_BARE_INIT_SIZE + + PRE_IMAGE + + . = ALIGN(8); + .rodata : { *(.rodata*) } + + _etext = .; /* End of text and rodata section */ + _sdata = .; + + . = ALIGN(8); + .data : { *(.data*) } + + .barebox_imd : { BAREBOX_IMD } + + . = ALIGN(8); + .got : { *(.got*) } + + . = .; + __barebox_cmd_start = .; + .barebox_cmd : { BAREBOX_CMDS } + __barebox_cmd_end = .; + + __barebox_magicvar_start = .; + .barebox_magicvar : { BAREBOX_MAGICVARS } + __barebox_magicvar_end = .; + + __barebox_initcalls_start = .; + .barebox_initcalls : { INITCALLS } + __barebox_initcalls_end = .; + + __barebox_exitcalls_start = .; + .barebox_exitcalls : { EXITCALLS } + __barebox_exitcalls_end = .; + + __usymtab_start = .; + __usymtab : { BAREBOX_SYMS } + __usymtab_end = .; + + .rela.dyn : { *(.rela*) } + + .oftables : { BAREBOX_CLK_TABLE() } + + .dtb : { BAREBOX_DTB() } + + _edata = .; + . = ALIGN(8); + __bss_start = .; + .bss : { *(.bss*) *(.sbss*) } + __bss_stop = .; + _end = .; +}arch/riscv/lib/dtb.c new file +41
-0@@ -0,0 +1,41 @@ +/* +* Copyright (C) 2016 Antony Pavlov <[email protected]> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ +#include <common.h> +#include <init.h> +#include <of.h> + +extern char __dtb_start[]; + +static int of_riscv_init (void ) +{ +struct device_node *root; + + root =of_get_root_node (); +if (root) +return 0 ; + + root =of_unflatten_dtb (__dtb_start); +if (!IS_ERR (root)) { +pr_debug ("using internal DTB\n" ); +of_set_root_node (root); +if (IS_ENABLED (CONFIG_OFDEVICE )) +of_probe (); + } + +return 0 ; +} +core_initcall (of_riscv_init);arch/riscv/lib/libgcc.h new file +28
-0@@ -0,0 +1,29 @@ +#ifndef __ASM_LIBGCC_H +#define __ASM_LIBGCC_H + +#include <asm/byteorder.h> + +typedef int word_type __attribute__ ((mode (__word__))); +#ifdef __BIG_ENDIAN +struct DWstruct { +int high, low; +}; +#elif defined(__LITTLE_ENDIAN) +struct DWstruct { +int low, high; +}; +#else +#error I feel sick. +#endif + +typedef union { +struct DWstruct s; +long long ll; +}DWunion ; + +long long __lshrdi3 (long long u,word_type b); +long long __ashldi3 (long long u,word_type b); +long long __ashrdi3 (long long u,word_type b); + +#endif /* __ASM_LIBGCC_H */ arch/riscv/lib/lshrdi3.c new file +28
-0@@ -0,0 +1,28 @@ +#include <module.h> + +#include "libgcc.h" + +long long __lshrdi3 (long long u,word_type b) +{ +DWunion uu, w; +word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { + w.s.high =0 ; + w.s.low = (unsigned int ) uu.s.high >> -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.high << bm; + + w.s.high = (unsigned int ) uu.s.high >> b; + w.s.low = ((unsigned int ) uu.s.low >> b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__lshrdi3);arch/riscv/lib/riscv_timer.c new file +26
-0@@ -0,0 +1,68 @@ +/* +* Copyright (C) 2017 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +/** +* @file +* @brief Clocksource based on RISCV cycle CSR timer +*/ + +#include <init.h> +#include <of.h> +#include <linux/clk.h> +#include <clock.h>
Quoted 8 lines
arch/riscv/lib/riscv_timer.c line 34
Quoted 8 lines
arch/riscv/lib/riscv_timer.c new file +8
-0+#include <io.h> + +static uint64_t rdcycle_read (void ) +{ + registerunsigned long __v; + + __asm__ __volatile__ ("rdcycle %0" :"=r" (__v)); +
Maybe you should also add support for 32-bit cores.
Quoted 8 lines
Quoted 8 lines
arch/riscv/lib/riscv_timer.c new file +8
-0+return __v; +} + +static struct clocksource rdcycle_cs = { + .read = rdcycle_read, + .mask =CLOCKSOURCE_MASK (32 ), +}; +
Signature · 9 lines
Mit freundlichen Grüßen, With best regards, Daniel Schultz _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC v4 01/10] Add initial RISC-V architecture support
Quoted 991 lines · On Mon, 2 Oct 2017 12:08:58 +0200 Daniel Schultz <[email protected]> wrote:
Hi,
Quoted 987 lines · Oleksij Rempel
Hi,
hm... mostly looks identical with existing arch
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
Quoted 284 lines
Signed-off-by Antony Pavlov <[email protected]>--
TODOs:* split patch;
--- arch/riscv/Kconfig | 73 +++++++++++++++++++++++++++++ arch/riscv/Makefile | 68 +++++++++++++++++++++++++++ arch/riscv/boot/Makefile | 2 + arch/riscv/boot/main_entry.c | 40 ++++++++++++++++ arch/riscv/boot/start.S | 74 ++++++++++++++++++++++++++++++ arch/riscv/dts/.gitignore | > arch/riscv/dts/Makefile | 9 ++++ arch/riscv/dts/skeleton.dtsi | 13 ++++++ arch/riscv/include/asm/barebox.h | 1 + arch/riscv/include/asm/bitops.h | 35 ++++++++++++++ arch/riscv/include/asm/bitsperlong.h | 10 ++++ arch/riscv/include/asm/byteorder.h | 10 ++++ arch/riscv/include/asm/common.h | 6 +++ arch/riscv/include/asm/elf.h | 11 +++++ arch/riscv/include/asm/io.h | 8 ++++ arch/riscv/include/asm/mmu.h | 6 +++ arch/riscv/include/asm/posix_types.h | 1 + arch/riscv/include/asm/sections.h | 1 + arch/riscv/include/asm/string.h | 1 + arch/riscv/include/asm/swab.h | 6 +++ arch/riscv/include/asm/types.h | 60 ++++++++++++++++++++++++ arch/riscv/include/asm/unaligned.h | 19 ++++++++ arch/riscv/lib/.gitignore | 1 + arch/riscv/lib/Makefile | 9 ++++ arch/riscv/lib/ashldi3.c | 28 ++++++++++++ arch/riscv/lib/ashrdi3.c | 30 ++++++++++++ arch/riscv/lib/asm-offsets.c | 12 +++++ arch/riscv/lib/barebox.lds.S | 89 ++++++++++++++++++++++++++++++++++++ arch/riscv/lib/dtb.c | 41 +++++++++++++++++ arch/riscv/lib/libgcc.h | 29 ++++++++++++ arch/riscv/lib/lshrdi3.c | 28 ++++++++++++ arch/riscv/lib/riscv_timer.c | 68 +++++++++++++++++++++++++++ drivers/of/Kconfig | 2 +- 33 files changed, 791 insertions(+), 1 deletion(-)arch/riscv/Kconfig new file +73
-0@@ -0,0 +1,73 @@ +config RISCV + bool + select GENERIC_FIND_NEXT_BIT + select HAVE_CONFIGURABLE_MEMORY_LAYOUT + select HAVE_CONFIGURABLE_TEXT_BASE + select GPIOLIB + select OFTREE + select COMMON_CLK + select COMMON_CLK_OF_PROVIDER + select CLKDEV_LOOKUP + default y + +config ARCH_TEXT_BASE + hex + default 0x0 + +config GENERIC_LINKER_SCRIPT + bool + default y + +menu "Machine selection" + +choice + prompt "CPU selection" + default CPU_RV_GENERIC + +config CPU_RV_GENERIC + bool "Generic RISC-V" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + +endchoice + +config CPU_SUPPORTS_32BIT_KERNEL + bool +config CPU_SUPPORTS_64BIT_KERNEL + bool + +choice + prompt "barebox code model" + default 64BIT + +config 32BIT + bool "32-bit barebox" + depends on CPU_SUPPORTS_32BIT_KERNEL + help + Select this option to build a 32-bit barebox. + +config 64BIT + bool "64-bit barebox" + depends on CPU_SUPPORTS_64BIT_KERNEL + help + Select this option to build a 64-bit barebox. + +endchoice + +config BUILTIN_DTB + bool "link a DTB into the barebox image" + depends on OFTREE + +config BUILTIN_DTB_NAME + string "DTB to build into the barebox image" + depends on BUILTIN_DTB + +endmenu + +source common/Kconfig +source commands/Kconfig +source net/Kconfig +source drivers/Kconfig +source fs/Kconfig +source lib/Kconfig +source crypto/Kconfigarch/riscv/Makefile new file +68
-0@@ -0,0 +1,68 @@ +CPPFLAGS += -fno-strict-aliasing + +cflags-y += -fno-pic -pipe +cflags-y += -Wall -Wmissing-prototypes -Wstrict-prototypes \ + -Wno-uninitialized -Wno-format -Wno-main -mcmodel=medany + +LDFLAGS += $(ldflags-y) +LDFLAGS_barebox += -nostdlib + +TEXT_BASE = $(CONFIG_TEXT_BASE) +CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE) + +ifndef CONFIG_MODULES +# Add cleanup flags +CPPFLAGS += -fdata-sections -ffunction-sections +LDFLAGS_barebox += -static --gc-sections +endif + +KBUILD_BINARY := barebox.bin + +machdirs := $(patsubst %,arch/riscv/mach-%/,$(machine-y)) + +ifneq ($(board-y),) +BOARD := arch/riscv/boards/$(board-y)/ +else +BOARD := +endif + +ifeq ($(KBUILD_SRC),) +CPPFLAGS += -I$(BOARD)/include +else +CPPFLAGS += -I$(srctree)/$(BOARD)/include +endif + +ifeq ($(KBUILD_SRC),) +CPPFLAGS += $(patsubst %,-I%include,$(machdirs)) +else +CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) +endif + +archprepare: maketools + +PHONY += maketools + +ifneq ($(machine-y),) +MACH := arch/riscv/mach-$(machine-y)/ +else +MACH := +endif + +ifneq ($(board-y),) +BOARD := arch/riscv/boards/$(board-y)/ +else +BOARD := +endif + +common-y += $(BOARD) $(MACH) +common-y += arch/riscv/lib/ +common-y += arch/riscv/boot/ + +common-$(CONFIG_OFTREE) += arch/riscv/dts/ + +CPPFLAGS += $(cflags-y) +CFLAGS += $(cflags-y) + +lds-y := arch/riscv/lib/barebox.lds + +CLEAN_FILES += arch/riscv/lib/barebox.ldsarch/riscv/boot/Makefile new file +2
-0@@ -0,0 +1,2 @@ +obj-y += start.o +obj-y += main_entry.oarch/riscv/boot/main_entry.c new file +40
-0@@ -0,0 +1,40 @@ +/* +* Copyright (C) 2016 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#include <common.h> +#include <memory.h> +#include <asm-generic/memory_layout.h> +#include <asm/sections.h> + +void main_entry (void ); + +/** +* Called plainly from assembler code +* +* @note The C environment isn't initialized yet +*/ +void main_entry (void ) +{ +/* clear the BSS first */ +memset (__bss_start,0x00 , __bss_stop - __bss_start); + +mem_malloc_init ((void *)MALLOC_BASE , + (void *)(MALLOC_BASE +MALLOC_SIZE -1 )); + +start_barebox (); +}arch/riscv/boot/start.S new file +31
-0@@ -0,0 +1,74 @@ +/* + * Startup Code for MIPS CPU + * + * based on coreboot/src/arch/riscv/bootblock.S + * + * Copyright (C) 2016 Antony Pavlov <[email protected]> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm-generic/memory_layout.h> + + .text + .section ".text_entry" + .align 2 + +.globl _start +_start: + li sp, STACK_BASE + STACK_SIZE +arch/riscv/boot/start.S line 41
Quoted 10 lines
arch/riscv/boot/start.S new file +10
-0+ # make room for HLS and initialize it + addi sp, sp, -64 /* MENTRY_FRAME_SIZE */ + + # poison the stack + li t1, STACK_BASE + li t0, 0xdeadbeef + sw t0, 0(t1) + + # clear any pending interrupts + //csrwi mip, 0should be removed.
Quoted 62 lines
arch/riscv/boot/start.S new file +32
-0+ /* copy barebox to link location */ + + la a0, _start /* a0 <- _start actual address */ + li a1, CONFIG_TEXT_BASE /* a1 <- _start link address */ + + beq a0, a1, main_entry + + la a2, __bss_start + +#define LONGSIZE 4 + +copy_loop: + /* copy from source address [a0] */ + lw t0, LONGSIZE * 0(a0) + lw t1, LONGSIZE * 1(a0) + lw t2, LONGSIZE * 2(a0) + lw t3, LONGSIZE * 3(a0) + /* copy to target address [a1] */ + sw t0, LONGSIZE * 0(a1) + sw t1, LONGSIZE * 1(a1) + sw t2, LONGSIZE * 2(a1) + sw t3, LONGSIZE * 3(a1) + addi a0, a0, LONGSIZE * 2 + addi a1, a1, LONGSIZE * 2 + bgeu a2, a0, copy_loop + + /* Alas! At the moment I can't load main_entry __link__ address + into a0 with la. Use CONFIG_TEXT_BASE instead. This solution + leads to extra cycles for repeat sp initialization. */ + + li a0, CONFIG_TEXT_BASE + jalr a0arch/riscv/dts/.gitignore new file +1
-0@@ -0,0 +1 @@ +*dtb*arch/riscv/dts/Makefile new file +9
-0@@ -0,0 +1,9 @@ +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) +obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o + +# just to build a built-in.o. Otherwise compilation fails when no devicetree is +# created. +obj- += dummy.o + +always := $(dtb-y) +clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dtsarch/riscv/dts/skeleton.dtsi new file +2
-0@@ -0,0 +1,13 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include andarch/riscv/dts/skeleton.dtsi line 12
Quoted 10 lines
arch/riscv/dts/skeleton.dtsi new file +10
-0+ * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <2>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0 0>; };"reg = <0 0>" instead?
Quoted 612 lines
arch/riscv/dts/skeleton.dtsi new file +1
-0+};arch/riscv/include/asm/barebox.h new file +1
-0@@ -0,0 +1 @@ +/* dummy */ arch/riscv/include/asm/bitops.h new file +35
-0@@ -0,0 +1,35 @@ +/* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* +*/ + +#ifndef _ASM_BITOPS_H_ +#define _ASM_BITOPS_H_ + +#include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/ffz.h> +#include <asm-generic/bitops/hweight.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/find.h> +#include <asm-generic/bitops/ops.h> + +#define set_bit (x, y) __set_bit(x, y) +#define clear_bit (x, y) __clear_bit(x, y) +#define change_bit (x, y) __change_bit(x, y) +#define test_and_set_bit (x, y) __test_and_set_bit(x, y) +#define test_and_clear_bit (x, y) __test_and_clear_bit(x, y) +#define test_and_change_bit (x, y) __test_and_change_bit(x, y) + +#endif /* _ASM_BITOPS_H_ */ arch/riscv/include/asm/bitsperlong.h new file +10
-0@@ -0,0 +1,10 @@ +#ifndef __ASM_BITSPERLONG_H +#define __ASM_BITSPERLONG_H + +#ifdef __riscv64 +#define BITS_PER_LONG 64 +#else +#define BITS_PER_LONG 32 +#endif + +#endif /* __ASM_BITSPERLONG_H */ arch/riscv/include/asm/byteorder.h new file +10
-0@@ -0,0 +1,10 @@ +#ifndef _ASM_RISCV_BYTEORDER_H +#define _ASM_RISCV_BYTEORDER_H + +#if defined(__RISCVEB__) +#include <linux/byteorder/big_endian.h> +#else +#include <linux/byteorder/little_endian.h> +#endif + +#endif /* _ASM_RISCV_BYTEORDER_H */ arch/riscv/include/asm/common.h new file +6
-0@@ -0,0 +1,6 @@ +#ifndef ASM_RISCV_COMMON_H +#define ASM_RISCV_COMMON_H + +/* nothing special yet */ + +#endif /* ASM_RISCV_COMMON_H */ arch/riscv/include/asm/elf.h new file +11
-0@@ -0,0 +1,11 @@ +#ifndef __ASM_RISCV_ELF_H__ +#define __ASM_RISCV_ELF_H__ + +#if __SIZEOF_POINTER__ ==8 +#define ELF_CLASS ELFCLASS64 +#define CONFIG_PHYS_ADDR_T_64BIT +#else +#define ELF_CLASS ELFCLASS32 +#endif + +#endif /* __ASM_RISCV_ELF_H__ */ arch/riscv/include/asm/io.h new file +8
-0@@ -0,0 +1,8 @@ +#ifndef __ASM_RISCV_IO_H +#define __ASM_RISCV_IO_H + +#define IO_SPACE_LIMIT 0 + +#include <asm-generic/io.h> + +#endif /* __ASM_RISCV_IO_H */ arch/riscv/include/asm/mmu.h new file +6
-0@@ -0,0 +1,6 @@ +#ifndef __ASM_MMU_H +#define __ASM_MMU_H + +#define MAP_ARCH_DEFAULT MAP_UNCACHED + +#endif /* __ASM_MMU_H */ arch/riscv/include/asm/posix_types.h new file +1
-0@@ -0,0 +1 @@ +#include <asm-generic/posix_types.h> arch/riscv/include/asm/sections.h new file +1
-0@@ -0,0 +1 @@ +#include <asm-generic/sections.h> arch/riscv/include/asm/string.h new file +1
-0@@ -0,0 +1 @@ +/* dummy */ arch/riscv/include/asm/swab.h new file +6
-0@@ -0,0 +1,6 @@ +#ifndef _ASM_SWAB_H +#define _ASM_SWAB_H + +/* nothing. use generic functions */ + +#endif /* _ASM_SWAB_H */ arch/riscv/include/asm/types.h new file +60
-0@@ -0,0 +1,60 @@ +#ifndef __ASM_RISCV_TYPES_H +#define __ASM_RISCV_TYPES_H + +#ifdef __riscv64 +/* +* This is used in dlmalloc. On RISCV64 we need it to be 64 bit +*/ +#define INTERNAL_SIZE_T unsigned long + +/* +* This is a Kconfig variable in the Kernel, but we want to detect +* this during compile time, so we set it here. +*/ +#define CONFIG_PHYS_ADDR_T_64BIT + +#endif + +typedef unsigned short umode_t ; + +/* +* __xx is ok: it doesn't pollute the POSIX namespace. Use these in the +* header files exported to user space +*/ + +typedef __signed__ char __s8; +typedef unsigned char __u8 ; + +typedef __signed__ short __s16 ; +typedef unsigned short __u16 ; + +typedef __signed__ int __s32; +typedef unsigned int __u32 ; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64 ; +typedef unsigned long long __u64 ; +#endif + +/* +* These aren't exported outside the kernel to avoid name space clashes +*/ +#ifdef __KERNEL__ + +typedef signed char s8 ; +typedef unsigned char u8 ; + +typedef signed short s16 ; +typedef unsigned short u16 ; + +typedef signed int s32 ; +typedef unsigned int u32 ; + +typedef signed long long s64 ; +typedef unsigned long long u64 ; + +#include <asm/bitsperlong.h> + +#endif /* __KERNEL__ */ + +#endif /* __ASM_RISCV_TYPES_H */ arch/riscv/include/asm/unaligned.h new file +19
-0@@ -0,0 +1,19 @@ +#ifndef _ASM_RISCV_UNALIGNED_H +#define _ASM_RISCV_UNALIGNED_H + +/* +* FIXME: this file is copy-n-pasted from sandbox's unaligned.h +*/ + +#include <linux/unaligned/access_ok.h> +#include <linux/unaligned/generic.h> + +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le +#else +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be +#endif + +#endif /* _ASM_RISCV_UNALIGNED_H */ arch/riscv/lib/.gitignore new file +1
-0@@ -0,0 +1 @@ +barebox.ldsarch/riscv/lib/Makefile new file +9
-0@@ -0,0 +1,9 @@ +extra-$(CONFIG_GENERIC_LINKER_SCRIPT) += barebox.lds + +obj-y += riscv_timer.o + +obj-$(CONFIG_32BIT) += lshrdi3.o +obj-$(CONFIG_32BIT) += ashldi3.o +obj-$(CONFIG_32BIT) += ashrdi3.o + +obj-$(CONFIG_BUILTIN_DTB) += dtb.oarch/riscv/lib/ashldi3.c new file +28
-0@@ -0,0 +1,28 @@ +#include <module.h> + +#include "libgcc.h" + +long long __ashldi3 (long long u,word_type b) +{ +DWunion uu, w; +word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { + w.s.low =0 ; + w.s.high = (unsigned int ) uu.s.low << -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.low >> bm; + + w.s.low = (unsigned int ) uu.s.low << b; + w.s.high = ((unsigned int ) uu.s.high << b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__ashldi3);arch/riscv/lib/ashrdi3.c new file +29
-0@@ -0,0 +1,30 @@ +#include <module.h> + +#include "libgcc.h" + +long long __ashrdi3 (long long u,word_type b) +{ + DWunion uu, w> + word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { +/* w.s.high = 1..1 or 0..0 */ + w.s.high = + uu.s.high >>31 ; + w.s.low = uu.s.high >> -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.high << bm; + + w.s.high = uu.s.high >> b; + w.s.low = ((unsigned int ) uu.s.low >> b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__ashrdi3);arch/riscv/lib/asm-offsets.c new file +12
-0@@ -0,0 +1,12 @@ +/* +* Generate definitions needed by assembly language modules. +* This code generates raw asm output which is post-processed to extract +* and format the required data. +*/ + +#include <linux/kbuild.h> + +int main (void ) +{ +return 0 ; +}arch/riscv/lib/barebox.lds.S new file +89
-0@@ -0,0 +1,89 @@ +/* + * Copyright (C) 2016 Antony Pavlov <[email protected]> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm-generic/barebox.lds.h> + +OUTPUT_ARCH(riscv) +ENTRY(_start) +SECTIONS +{ + . = TEXT_BASE; + + . = ALIGN(8); + .text : + { + _stext = .; + _start = .; + KEEP(*(.text_entry*)) + _text = .; + __bare_init_start = .; + *(.text_bare_init*) + __bare_init_end = .; + *(.text*) + } + BAREBOX_BARE_INIT_SIZE + + PRE_IMAGE + + . = ALIGN(8); + .rodata : { *(.rodata*) } + + _etext = .; /* End of text and rodata section */ + _sdata = .; + + . = ALIGN(8); + .data : { *(.data*) } + + .barebox_imd : { BAREBOX_IMD } + + . = ALIGN(8); + .got : { *(.got*) } + + . = .; + __barebox_cmd_start = .; + .barebox_cmd : { BAREBOX_CMDS } + __barebox_cmd_end = .; + + __barebox_magicvar_start = .; + .barebox_magicvar : { BAREBOX_MAGICVARS } + __barebox_magicvar_end = .; + + __barebox_initcalls_start = .; + .barebox_initcalls : { INITCALLS } + __barebox_initcalls_end = .; + + __barebox_exitcalls_start = .; + .barebox_exitcalls : { EXITCALLS } + __barebox_exitcalls_end = .; + + __usymtab_start = .; + __usymtab : { BAREBOX_SYMS } + __usymtab_end = .; + + .rela.dyn : { *(.rela*) } + + .oftables : { BAREBOX_CLK_TABLE() } + + .dtb : { BAREBOX_DTB() } + + _edata = .; + . = ALIGN(8); + __bss_start = .; + .bss : { *(.bss*) *(.sbss*) } + __bss_stop = .; + _end = .; +}arch/riscv/lib/dtb.c new file +41
-0@@ -0,0 +1,41 @@ +/* +* Copyright (C) 2016 Antony Pavlov <[email protected]> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ +#include <common.h> +#include <init.h> +#include <of.h> + +extern char __dtb_start[]; + +static int of_riscv_init (void ) +{ +struct device_node *root; + + root =of_get_root_node (); +if (root) +return 0 ; + + root =of_unflatten_dtb (__dtb_start); +if (!IS_ERR (root)) { +pr_debug ("using internal DTB\n" ); +of_set_root_node (root); +if (IS_ENABLED (CONFIG_OFDEVICE )) +of_probe (); + } + +return 0 ; +} +core_initcall (of_riscv_init);arch/riscv/lib/libgcc.h new file +28
-0@@ -0,0 +1,29 @@ +#ifndef __ASM_LIBGCC_H +#define __ASM_LIBGCC_H + +#include <asm/byteorder.h> + +typedef int word_type __attribute__ ((mode (__word__))); +#ifdef __BIG_ENDIAN +struct DWstruct { +int high, low; +}; +#elif defined(__LITTLE_ENDIAN) +struct DWstruct { +int low, high; +}; +#else +#error I feel sick. +#endif + +typedef union { +struct DWstruct s; +long long ll; +}DWunion ; + +long long __lshrdi3 (long long u,word_type b); +long long __ashldi3 (long long u,word_type b); +long long __ashrdi3 (long long u,word_type b); + +#endif /* __ASM_LIBGCC_H */ arch/riscv/lib/lshrdi3.c new file +28
-0@@ -0,0 +1,28 @@ +#include <module.h> + +#include "libgcc.h" + +long long __lshrdi3 (long long u,word_type b) +{ +DWunion uu, w; +word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { + w.s.high =0 ; + w.s.low = (unsigned int ) uu.s.high >> -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.high << bm; + + w.s.high = (unsigned int ) uu.s.high >> b; + w.s.low = ((unsigned int ) uu.s.low >> b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__lshrdi3);arch/riscv/lib/riscv_timer.c new file +27
-0@@ -0,0 +1,68 @@ +/* +* Copyright (C) 2017 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +/** +* @file +* @brief Clocksource based on RISCV cycle CSR timer +*/ + +#include <init.h> +#include <of.h> +#include <linux/clk.h> +#include <clock.h> +#include <io.h>
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arch/riscv/lib/riscv_timer.c line 34
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arch/riscv/lib/riscv_timer.c new file +7
-0+ +static uint64_t rdcycle_read (void ) +{ + registerunsigned long __v; + + __asm__ __volatile__ ("rdcycle %0" :"=r" (__v)); +Maybe you should also add support for 32-bit cores.
That do you mean?
rdcycle pseudo op should return 32 low bits of cycle counter on 32-bit core.
Quoted 19 lines
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arch/riscv/lib/riscv_timer.c new file +8
-0+return __v; +} + +static struct clocksource rdcycle_cs = { + .read = rdcycle_read, + .mask =CLOCKSOURCE_MASK (32 ), +}; +Signature · 9 lines
Mit freundlichen Grüßen, With best regards, Daniel Schultz _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Signature · 7 lines
Best regards, Antony Pavlov _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC v4 01/10] Add initial RISC-V architecture support
Hi,
Quoted 1,007 lines · Antony Pavlov
Quoted 991 lines · On Mon, 2 Oct 2017 12:08:58 +0200 Daniel Schultz <[email protected]> wrote:
Hi,
Quoted 987 lines · Oleksij Rempel
Hi,
hm... mostly looks identical with existing arch
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
Quoted 284 lines
Signed-off-by Antony Pavlov <[email protected]>--
TODOs:* split patch;
--- arch/riscv/Kconfig | 73 +++++++++++++++++++++++++++++ arch/riscv/Makefile | 68 +++++++++++++++++++++++++++ arch/riscv/boot/Makefile | 2 + arch/riscv/boot/main_entry.c | 40 ++++++++++++++++ arch/riscv/boot/start.S | 74 ++++++++++++++++++++++++++++++ arch/riscv/dts/.gitignore | > arch/riscv/dts/Makefile | 9 ++++ arch/riscv/dts/skeleton.dtsi | 13 ++++++ arch/riscv/include/asm/barebox.h | 1 + arch/riscv/include/asm/bitops.h | 35 ++++++++++++++ arch/riscv/include/asm/bitsperlong.h | 10 ++++ arch/riscv/include/asm/byteorder.h | 10 ++++ arch/riscv/include/asm/common.h | 6 +++ arch/riscv/include/asm/elf.h | 11 +++++ arch/riscv/include/asm/io.h | 8 ++++ arch/riscv/include/asm/mmu.h | 6 +++ arch/riscv/include/asm/posix_types.h | 1 + arch/riscv/include/asm/sections.h | 1 + arch/riscv/include/asm/string.h | 1 + arch/riscv/include/asm/swab.h | 6 +++ arch/riscv/include/asm/types.h | 60 ++++++++++++++++++++++++ arch/riscv/include/asm/unaligned.h | 19 ++++++++ arch/riscv/lib/.gitignore | 1 + arch/riscv/lib/Makefile | 9 ++++ arch/riscv/lib/ashldi3.c | 28 ++++++++++++ arch/riscv/lib/ashrdi3.c | 30 ++++++++++++ arch/riscv/lib/asm-offsets.c | 12 +++++ arch/riscv/lib/barebox.lds.S | 89 ++++++++++++++++++++++++++++++++++++ arch/riscv/lib/dtb.c | 41 +++++++++++++++++ arch/riscv/lib/libgcc.h | 29 ++++++++++++ arch/riscv/lib/lshrdi3.c | 28 ++++++++++++ arch/riscv/lib/riscv_timer.c | 68 +++++++++++++++++++++++++++ drivers/of/Kconfig | 2 +- 33 files changed, 791 insertions(+), 1 deletion(-)arch/riscv/Kconfig new file +73
-0@@ -0,0 +1,73 @@ +config RISCV + bool + select GENERIC_FIND_NEXT_BIT + select HAVE_CONFIGURABLE_MEMORY_LAYOUT + select HAVE_CONFIGURABLE_TEXT_BASE + select GPIOLIB + select OFTREE + select COMMON_CLK + select COMMON_CLK_OF_PROVIDER + select CLKDEV_LOOKUP + default y + +config ARCH_TEXT_BASE + hex + default 0x0 + +config GENERIC_LINKER_SCRIPT + bool + default y + +menu "Machine selection" + +choice + prompt "CPU selection" + default CPU_RV_GENERIC + +config CPU_RV_GENERIC + bool "Generic RISC-V" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + +endchoice + +config CPU_SUPPORTS_32BIT_KERNEL + bool +config CPU_SUPPORTS_64BIT_KERNEL + bool + +choice + prompt "barebox code model" + default 64BIT + +config 32BIT + bool "32-bit barebox" + depends on CPU_SUPPORTS_32BIT_KERNEL + help + Select this option to build a 32-bit barebox. + +config 64BIT + bool "64-bit barebox" + depends on CPU_SUPPORTS_64BIT_KERNEL + help + Select this option to build a 64-bit barebox. + +endchoice + +config BUILTIN_DTB + bool "link a DTB into the barebox image" + depends on OFTREE + +config BUILTIN_DTB_NAME + string "DTB to build into the barebox image" + depends on BUILTIN_DTB + +endmenu + +source common/Kconfig +source commands/Kconfig +source net/Kconfig +source drivers/Kconfig +source fs/Kconfig +source lib/Kconfig +source crypto/Kconfigarch/riscv/Makefile new file +68
-0@@ -0,0 +1,68 @@ +CPPFLAGS += -fno-strict-aliasing + +cflags-y += -fno-pic -pipe +cflags-y += -Wall -Wmissing-prototypes -Wstrict-prototypes \ + -Wno-uninitialized -Wno-format -Wno-main -mcmodel=medany + +LDFLAGS += $(ldflags-y) +LDFLAGS_barebox += -nostdlib + +TEXT_BASE = $(CONFIG_TEXT_BASE) +CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE) + +ifndef CONFIG_MODULES +# Add cleanup flags +CPPFLAGS += -fdata-sections -ffunction-sections +LDFLAGS_barebox += -static --gc-sections +endif + +KBUILD_BINARY := barebox.bin + +machdirs := $(patsubst %,arch/riscv/mach-%/,$(machine-y)) + +ifneq ($(board-y),) +BOARD := arch/riscv/boards/$(board-y)/ +else +BOARD := +endif + +ifeq ($(KBUILD_SRC),) +CPPFLAGS += -I$(BOARD)/include +else +CPPFLAGS += -I$(srctree)/$(BOARD)/include +endif + +ifeq ($(KBUILD_SRC),) +CPPFLAGS += $(patsubst %,-I%include,$(machdirs)) +else +CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) +endif + +archprepare: maketools + +PHONY += maketools + +ifneq ($(machine-y),) +MACH := arch/riscv/mach-$(machine-y)/ +else +MACH := +endif + +ifneq ($(board-y),) +BOARD := arch/riscv/boards/$(board-y)/ +else +BOARD := +endif + +common-y += $(BOARD) $(MACH) +common-y += arch/riscv/lib/ +common-y += arch/riscv/boot/ + +common-$(CONFIG_OFTREE) += arch/riscv/dts/ + +CPPFLAGS += $(cflags-y) +CFLAGS += $(cflags-y) + +lds-y := arch/riscv/lib/barebox.lds + +CLEAN_FILES += arch/riscv/lib/barebox.ldsarch/riscv/boot/Makefile new file +2
-0@@ -0,0 +1,2 @@ +obj-y += start.o +obj-y += main_entry.oarch/riscv/boot/main_entry.c new file +40
-0@@ -0,0 +1,40 @@ +/* +* Copyright (C) 2016 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#include <common.h> +#include <memory.h> +#include <asm-generic/memory_layout.h> +#include <asm/sections.h> + +void main_entry (void ); + +/** +* Called plainly from assembler code +* +* @note The C environment isn't initialized yet +*/ +void main_entry (void ) +{ +/* clear the BSS first */ +memset (__bss_start,0x00 , __bss_stop - __bss_start); + +mem_malloc_init ((void *)MALLOC_BASE , + (void *)(MALLOC_BASE +MALLOC_SIZE -1 )); + +start_barebox (); +}arch/riscv/boot/start.S new file +31
-0@@ -0,0 +1,74 @@ +/* + * Startup Code for MIPS CPU + * + * based on coreboot/src/arch/riscv/bootblock.S + * + * Copyright (C) 2016 Antony Pavlov <[email protected]> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm-generic/memory_layout.h> + + .text + .section ".text_entry" + .align 2 + +.globl _start +_start: + li sp, STACK_BASE + STACK_SIZE +arch/riscv/boot/start.S line 41
Quoted 10 lines
arch/riscv/boot/start.S new file +10
-0+ # make room for HLS and initialize it + addi sp, sp, -64 /* MENTRY_FRAME_SIZE */ + + # poison the stack + li t1, STACK_BASE + li t0, 0xdeadbeef + sw t0, 0(t1) + + # clear any pending interrupts + //csrwi mip, 0should be removed.
Quoted 62 lines
arch/riscv/boot/start.S new file +32
-0+ /* copy barebox to link location */ + + la a0, _start /* a0 <- _start actual address */ + li a1, CONFIG_TEXT_BASE /* a1 <- _start link address */ + + beq a0, a1, main_entry + + la a2, __bss_start + +#define LONGSIZE 4 + +copy_loop: + /* copy from source address [a0] */ + lw t0, LONGSIZE * 0(a0) + lw t1, LONGSIZE * 1(a0) + lw t2, LONGSIZE * 2(a0) + lw t3, LONGSIZE * 3(a0) + /* copy to target address [a1] */ + sw t0, LONGSIZE * 0(a1) + sw t1, LONGSIZE * 1(a1) + sw t2, LONGSIZE * 2(a1) + sw t3, LONGSIZE * 3(a1) + addi a0, a0, LONGSIZE * 2 + addi a1, a1, LONGSIZE * 2 + bgeu a2, a0, copy_loop + + /* Alas! At the moment I can't load main_entry __link__ address + into a0 with la. Use CONFIG_TEXT_BASE instead. This solution + leads to extra cycles for repeat sp initialization. */ + + li a0, CONFIG_TEXT_BASE + jalr a0arch/riscv/dts/.gitignore new file +1
-0@@ -0,0 +1 @@ +*dtb*arch/riscv/dts/Makefile new file +9
-0@@ -0,0 +1,9 @@ +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) +obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o + +# just to build a built-in.o. Otherwise compilation fails when no devicetree is +# created. +obj- += dummy.o + +always := $(dtb-y) +clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dtsarch/riscv/dts/skeleton.dtsi new file +2
-0@@ -0,0 +1,13 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include andarch/riscv/dts/skeleton.dtsi line 12
Quoted 10 lines
arch/riscv/dts/skeleton.dtsi new file +10
-0+ * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <2>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0 0>; };"reg = <0 0>" instead?
Quoted 612 lines
arch/riscv/dts/skeleton.dtsi new file +1
-0+};arch/riscv/include/asm/barebox.h new file +1
-0@@ -0,0 +1 @@ +/* dummy */ arch/riscv/include/asm/bitops.h new file +35
-0@@ -0,0 +1,35 @@ +/* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* +*/ + +#ifndef _ASM_BITOPS_H_ +#define _ASM_BITOPS_H_ + +#include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/ffz.h> +#include <asm-generic/bitops/hweight.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/find.h> +#include <asm-generic/bitops/ops.h> + +#define set_bit (x, y) __set_bit(x, y) +#define clear_bit (x, y) __clear_bit(x, y) +#define change_bit (x, y) __change_bit(x, y) +#define test_and_set_bit (x, y) __test_and_set_bit(x, y) +#define test_and_clear_bit (x, y) __test_and_clear_bit(x, y) +#define test_and_change_bit (x, y) __test_and_change_bit(x, y) + +#endif /* _ASM_BITOPS_H_ */ arch/riscv/include/asm/bitsperlong.h new file +10
-0@@ -0,0 +1,10 @@ +#ifndef __ASM_BITSPERLONG_H +#define __ASM_BITSPERLONG_H + +#ifdef __riscv64 +#define BITS_PER_LONG 64 +#else +#define BITS_PER_LONG 32 +#endif + +#endif /* __ASM_BITSPERLONG_H */ arch/riscv/include/asm/byteorder.h new file +10
-0@@ -0,0 +1,10 @@ +#ifndef _ASM_RISCV_BYTEORDER_H +#define _ASM_RISCV_BYTEORDER_H + +#if defined(__RISCVEB__) +#include <linux/byteorder/big_endian.h> +#else +#include <linux/byteorder/little_endian.h> +#endif + +#endif /* _ASM_RISCV_BYTEORDER_H */ arch/riscv/include/asm/common.h new file +6
-0@@ -0,0 +1,6 @@ +#ifndef ASM_RISCV_COMMON_H +#define ASM_RISCV_COMMON_H + +/* nothing special yet */ + +#endif /* ASM_RISCV_COMMON_H */ arch/riscv/include/asm/elf.h new file +11
-0@@ -0,0 +1,11 @@ +#ifndef __ASM_RISCV_ELF_H__ +#define __ASM_RISCV_ELF_H__ + +#if __SIZEOF_POINTER__ ==8 +#define ELF_CLASS ELFCLASS64 +#define CONFIG_PHYS_ADDR_T_64BIT +#else +#define ELF_CLASS ELFCLASS32 +#endif + +#endif /* __ASM_RISCV_ELF_H__ */ arch/riscv/include/asm/io.h new file +8
-0@@ -0,0 +1,8 @@ +#ifndef __ASM_RISCV_IO_H +#define __ASM_RISCV_IO_H + +#define IO_SPACE_LIMIT 0 + +#include <asm-generic/io.h> + +#endif /* __ASM_RISCV_IO_H */ arch/riscv/include/asm/mmu.h new file +6
-0@@ -0,0 +1,6 @@ +#ifndef __ASM_MMU_H +#define __ASM_MMU_H + +#define MAP_ARCH_DEFAULT MAP_UNCACHED + +#endif /* __ASM_MMU_H */ arch/riscv/include/asm/posix_types.h new file +1
-0@@ -0,0 +1 @@ +#include <asm-generic/posix_types.h> arch/riscv/include/asm/sections.h new file +1
-0@@ -0,0 +1 @@ +#include <asm-generic/sections.h> arch/riscv/include/asm/string.h new file +1
-0@@ -0,0 +1 @@ +/* dummy */ arch/riscv/include/asm/swab.h new file +6
-0@@ -0,0 +1,6 @@ +#ifndef _ASM_SWAB_H +#define _ASM_SWAB_H + +/* nothing. use generic functions */ + +#endif /* _ASM_SWAB_H */ arch/riscv/include/asm/types.h new file +60
-0@@ -0,0 +1,60 @@ +#ifndef __ASM_RISCV_TYPES_H +#define __ASM_RISCV_TYPES_H + +#ifdef __riscv64 +/* +* This is used in dlmalloc. On RISCV64 we need it to be 64 bit +*/ +#define INTERNAL_SIZE_T unsigned long + +/* +* This is a Kconfig variable in the Kernel, but we want to detect +* this during compile time, so we set it here. +*/ +#define CONFIG_PHYS_ADDR_T_64BIT + +#endif + +typedef unsigned short umode_t ; + +/* +* __xx is ok: it doesn't pollute the POSIX namespace. Use these in the +* header files exported to user space +*/ + +typedef __signed__ char __s8; +typedef unsigned char __u8 ; + +typedef __signed__ short __s16 ; +typedef unsigned short __u16 ; + +typedef __signed__ int __s32; +typedef unsigned int __u32 ; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64 ; +typedef unsigned long long __u64 ; +#endif + +/* +* These aren't exported outside the kernel to avoid name space clashes +*/ +#ifdef __KERNEL__ + +typedef signed char s8 ; +typedef unsigned char u8 ; + +typedef signed short s16 ; +typedef unsigned short u16 ; + +typedef signed int s32 ; +typedef unsigned int u32 ; + +typedef signed long long s64 ; +typedef unsigned long long u64 ; + +#include <asm/bitsperlong.h> + +#endif /* __KERNEL__ */ + +#endif /* __ASM_RISCV_TYPES_H */ arch/riscv/include/asm/unaligned.h new file +19
-0@@ -0,0 +1,19 @@ +#ifndef _ASM_RISCV_UNALIGNED_H +#define _ASM_RISCV_UNALIGNED_H + +/* +* FIXME: this file is copy-n-pasted from sandbox's unaligned.h +*/ + +#include <linux/unaligned/access_ok.h> +#include <linux/unaligned/generic.h> + +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le +#else +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be +#endif + +#endif /* _ASM_RISCV_UNALIGNED_H */ arch/riscv/lib/.gitignore new file +1
-0@@ -0,0 +1 @@ +barebox.ldsarch/riscv/lib/Makefile new file +9
-0@@ -0,0 +1,9 @@ +extra-$(CONFIG_GENERIC_LINKER_SCRIPT) += barebox.lds + +obj-y += riscv_timer.o + +obj-$(CONFIG_32BIT) += lshrdi3.o +obj-$(CONFIG_32BIT) += ashldi3.o +obj-$(CONFIG_32BIT) += ashrdi3.o + +obj-$(CONFIG_BUILTIN_DTB) += dtb.oarch/riscv/lib/ashldi3.c new file +28
-0@@ -0,0 +1,28 @@ +#include <module.h> + +#include "libgcc.h" + +long long __ashldi3 (long long u,word_type b) +{ +DWunion uu, w; +word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { + w.s.low =0 ; + w.s.high = (unsigned int ) uu.s.low << -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.low >> bm; + + w.s.low = (unsigned int ) uu.s.low << b; + w.s.high = ((unsigned int ) uu.s.high << b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__ashldi3);arch/riscv/lib/ashrdi3.c new file +29
-0@@ -0,0 +1,30 @@ +#include <module.h> + +#include "libgcc.h" + +long long __ashrdi3 (long long u,word_type b) +{ + DWunion uu, w> + word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { +/* w.s.high = 1..1 or 0..0 */ + w.s.high = + uu.s.high >>31 ; + w.s.low = uu.s.high >> -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.high << bm; + + w.s.high = uu.s.high >> b; + w.s.low = ((unsigned int ) uu.s.low >> b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__ashrdi3);arch/riscv/lib/asm-offsets.c new file +12
-0@@ -0,0 +1,12 @@ +/* +* Generate definitions needed by assembly language modules. +* This code generates raw asm output which is post-processed to extract +* and format the required data. +*/ + +#include <linux/kbuild.h> + +int main (void ) +{ +return 0 ; +}arch/riscv/lib/barebox.lds.S new file +89
-0@@ -0,0 +1,89 @@ +/* + * Copyright (C) 2016 Antony Pavlov <[email protected]> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm-generic/barebox.lds.h> + +OUTPUT_ARCH(riscv) +ENTRY(_start) +SECTIONS +{ + . = TEXT_BASE; + + . = ALIGN(8); + .text : + { + _stext = .; + _start = .; + KEEP(*(.text_entry*)) + _text = .; + __bare_init_start = .; + *(.text_bare_init*) + __bare_init_end = .; + *(.text*) + } + BAREBOX_BARE_INIT_SIZE + + PRE_IMAGE + + . = ALIGN(8); + .rodata : { *(.rodata*) } + + _etext = .; /* End of text and rodata section */ + _sdata = .; + + . = ALIGN(8); + .data : { *(.data*) } + + .barebox_imd : { BAREBOX_IMD } + + . = ALIGN(8); + .got : { *(.got*) } + + . = .; + __barebox_cmd_start = .; + .barebox_cmd : { BAREBOX_CMDS } + __barebox_cmd_end = .; + + __barebox_magicvar_start = .; + .barebox_magicvar : { BAREBOX_MAGICVARS } + __barebox_magicvar_end = .; + + __barebox_initcalls_start = .; + .barebox_initcalls : { INITCALLS } + __barebox_initcalls_end = .; + + __barebox_exitcalls_start = .; + .barebox_exitcalls : { EXITCALLS } + __barebox_exitcalls_end = .; + + __usymtab_start = .; + __usymtab : { BAREBOX_SYMS } + __usymtab_end = .; + + .rela.dyn : { *(.rela*) } + + .oftables : { BAREBOX_CLK_TABLE() } + + .dtb : { BAREBOX_DTB() } + + _edata = .; + . = ALIGN(8); + __bss_start = .; + .bss : { *(.bss*) *(.sbss*) } + __bss_stop = .; + _end = .; +}arch/riscv/lib/dtb.c new file +41
-0@@ -0,0 +1,41 @@ +/* +* Copyright (C) 2016 Antony Pavlov <[email protected]> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ +#include <common.h> +#include <init.h> +#include <of.h> + +extern char __dtb_start[]; + +static int of_riscv_init (void ) +{ +struct device_node *root; + + root =of_get_root_node (); +if (root) +return 0 ; + + root =of_unflatten_dtb (__dtb_start); +if (!IS_ERR (root)) { +pr_debug ("using internal DTB\n" ); +of_set_root_node (root); +if (IS_ENABLED (CONFIG_OFDEVICE )) +of_probe (); + } + +return 0 ; +} +core_initcall (of_riscv_init);arch/riscv/lib/libgcc.h new file +28
-0@@ -0,0 +1,29 @@ +#ifndef __ASM_LIBGCC_H +#define __ASM_LIBGCC_H + +#include <asm/byteorder.h> + +typedef int word_type __attribute__ ((mode (__word__))); +#ifdef __BIG_ENDIAN +struct DWstruct { +int high, low; +}; +#elif defined(__LITTLE_ENDIAN) +struct DWstruct { +int low, high; +}; +#else +#error I feel sick. +#endif + +typedef union { +struct DWstruct s; +long long ll; +}DWunion ; + +long long __lshrdi3 (long long u,word_type b); +long long __ashldi3 (long long u,word_type b); +long long __ashrdi3 (long long u,word_type b); + +#endif /* __ASM_LIBGCC_H */ arch/riscv/lib/lshrdi3.c new file +28
-0@@ -0,0 +1,28 @@ +#include <module.h> + +#include "libgcc.h" + +long long __lshrdi3 (long long u,word_type b) +{ +DWunion uu, w; +word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { + w.s.high =0 ; + w.s.low = (unsigned int ) uu.s.high >> -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.high << bm; + + w.s.high = (unsigned int ) uu.s.high >> b; + w.s.low = ((unsigned int ) uu.s.low >> b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__lshrdi3);arch/riscv/lib/riscv_timer.c new file +27
-0@@ -0,0 +1,68 @@ +/* +* Copyright (C) 2017 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +/** +* @file +* @brief Clocksource based on RISCV cycle CSR timer +*/ + +#include <init.h> +#include <of.h> +#include <linux/clk.h> +#include <clock.h> +#include <io.h> Quoted 8 lines
Quoted 7 lines
arch/riscv/lib/riscv_timer.c line 34
Quoted 7 lines
arch/riscv/lib/riscv_timer.c new file +7
-0+ +static uint64_t rdcycle_read (void ) +{ + registerunsigned long __v; + + __asm__ __volatile__ ("rdcycle %0" :"=r" (__v)); +Maybe you should also add support for 32-bit cores.
That do you mean?
rdcycle pseudo op should return 32 low bits of cycle counter on 32-bit core.
Quoted 8 lines
Quoted 8 lines
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arch/riscv/lib/riscv_timer.c line 42
Quoted 8 lines
arch/riscv/lib/riscv_timer.c new file +8
-0+return __v; +} + +static struct clocksource rdcycle_cs = { + .read = rdcycle_read, + .mask =CLOCKSOURCE_MASK (32 ), +}; +
Aah I was a little bit confused by the return value type. You could expand the mask to 64 and write something like that:
register unsigned long __v;
register unsigned long __t;uint64_t time;
#ifdef RISCV_64BIT
__asm__ __volatile__ ("rdcycle %0" : "=r" (__v)); return __v;
#else
do {
__asm__ __volatile__ ("rdcycle %0" : "=r" (__v)); } while (__v == 0); //maybe with an additional counter as timeout __asm__ __volatile__ ("rdcycleh %0" : "=r" (__t)); time = (__t << 32) & __v;
return time;
#endif
I don't know if this works, but we should always support both register widths.
BTW: Sometimes your license header are from 2016.
Signature · 9 lines
Mit freundlichen Grüßen, With best regards, Daniel Schultz _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC v4 01/10] Add initial RISC-V architecture support
Quoted 1,039 lines · On Thu, 5 Oct 2017 12:55:09 +0200 Daniel Schultz <[email protected]> wrote:
Hi,
Quoted 1,007 lines · Antony Pavlov
Quoted 991 lines · On Mon, 2 Oct 2017 12:08:58 +0200 Daniel Schultz <[email protected]> wrote:
Hi,
Quoted 987 lines · Oleksij Rempel
Hi,
hm... mostly looks identical with existing arch
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
Quoted 284 lines
Signed-off-by Antony Pavlov <[email protected]>--
TODOs:* split patch;
--- arch/riscv/Kconfig | 73 +++++++++++++++++++++++++++++ arch/riscv/Makefile | 68 +++++++++++++++++++++++++++ arch/riscv/boot/Makefile | 2 + arch/riscv/boot/main_entry.c | 40 ++++++++++++++++ arch/riscv/boot/start.S | 74 ++++++++++++++++++++++++++++++ arch/riscv/dts/.gitignore | > arch/riscv/dts/Makefile | 9 ++++ arch/riscv/dts/skeleton.dtsi | 13 ++++++ arch/riscv/include/asm/barebox.h | 1 + arch/riscv/include/asm/bitops.h | 35 ++++++++++++++ arch/riscv/include/asm/bitsperlong.h | 10 ++++ arch/riscv/include/asm/byteorder.h | 10 ++++ arch/riscv/include/asm/common.h | 6 +++ arch/riscv/include/asm/elf.h | 11 +++++ arch/riscv/include/asm/io.h | 8 ++++ arch/riscv/include/asm/mmu.h | 6 +++ arch/riscv/include/asm/posix_types.h | 1 + arch/riscv/include/asm/sections.h | 1 + arch/riscv/include/asm/string.h | 1 + arch/riscv/include/asm/swab.h | 6 +++ arch/riscv/include/asm/types.h | 60 ++++++++++++++++++++++++ arch/riscv/include/asm/unaligned.h | 19 ++++++++ arch/riscv/lib/.gitignore | 1 + arch/riscv/lib/Makefile | 9 ++++ arch/riscv/lib/ashldi3.c | 28 ++++++++++++ arch/riscv/lib/ashrdi3.c | 30 ++++++++++++ arch/riscv/lib/asm-offsets.c | 12 +++++ arch/riscv/lib/barebox.lds.S | 89 ++++++++++++++++++++++++++++++++++++ arch/riscv/lib/dtb.c | 41 +++++++++++++++++ arch/riscv/lib/libgcc.h | 29 ++++++++++++ arch/riscv/lib/lshrdi3.c | 28 ++++++++++++ arch/riscv/lib/riscv_timer.c | 68 +++++++++++++++++++++++++++ drivers/of/Kconfig | 2 +- 33 files changed, 791 insertions(+), 1 deletion(-)arch/riscv/Kconfig new file +73
-0@@ -0,0 +1,73 @@ +config RISCV + bool + select GENERIC_FIND_NEXT_BIT + select HAVE_CONFIGURABLE_MEMORY_LAYOUT + select HAVE_CONFIGURABLE_TEXT_BASE + select GPIOLIB + select OFTREE + select COMMON_CLK + select COMMON_CLK_OF_PROVIDER + select CLKDEV_LOOKUP + default y + +config ARCH_TEXT_BASE + hex + default 0x0 + +config GENERIC_LINKER_SCRIPT + bool + default y + +menu "Machine selection" + +choice + prompt "CPU selection" + default CPU_RV_GENERIC + +config CPU_RV_GENERIC + bool "Generic RISC-V" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + +endchoice + +config CPU_SUPPORTS_32BIT_KERNEL + bool +config CPU_SUPPORTS_64BIT_KERNEL + bool + +choice + prompt "barebox code model" + default 64BIT + +config 32BIT + bool "32-bit barebox" + depends on CPU_SUPPORTS_32BIT_KERNEL + help + Select this option to build a 32-bit barebox. + +config 64BIT + bool "64-bit barebox" + depends on CPU_SUPPORTS_64BIT_KERNEL + help + Select this option to build a 64-bit barebox. + +endchoice + +config BUILTIN_DTB + bool "link a DTB into the barebox image" + depends on OFTREE + +config BUILTIN_DTB_NAME + string "DTB to build into the barebox image" + depends on BUILTIN_DTB + +endmenu + +source common/Kconfig +source commands/Kconfig +source net/Kconfig +source drivers/Kconfig +source fs/Kconfig +source lib/Kconfig +source crypto/Kconfigarch/riscv/Makefile new file +68
-0@@ -0,0 +1,68 @@ +CPPFLAGS += -fno-strict-aliasing + +cflags-y += -fno-pic -pipe +cflags-y += -Wall -Wmissing-prototypes -Wstrict-prototypes \ + -Wno-uninitialized -Wno-format -Wno-main -mcmodel=medany + +LDFLAGS += $(ldflags-y) +LDFLAGS_barebox += -nostdlib + +TEXT_BASE = $(CONFIG_TEXT_BASE) +CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE) + +ifndef CONFIG_MODULES +# Add cleanup flags +CPPFLAGS += -fdata-sections -ffunction-sections +LDFLAGS_barebox += -static --gc-sections +endif + +KBUILD_BINARY := barebox.bin + +machdirs := $(patsubst %,arch/riscv/mach-%/,$(machine-y)) + +ifneq ($(board-y),) +BOARD := arch/riscv/boards/$(board-y)/ +else +BOARD := +endif + +ifeq ($(KBUILD_SRC),) +CPPFLAGS += -I$(BOARD)/include +else +CPPFLAGS += -I$(srctree)/$(BOARD)/include +endif + +ifeq ($(KBUILD_SRC),) +CPPFLAGS += $(patsubst %,-I%include,$(machdirs)) +else +CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) +endif + +archprepare: maketools + +PHONY += maketools + +ifneq ($(machine-y),) +MACH := arch/riscv/mach-$(machine-y)/ +else +MACH := +endif + +ifneq ($(board-y),) +BOARD := arch/riscv/boards/$(board-y)/ +else +BOARD := +endif + +common-y += $(BOARD) $(MACH) +common-y += arch/riscv/lib/ +common-y += arch/riscv/boot/ + +common-$(CONFIG_OFTREE) += arch/riscv/dts/ + +CPPFLAGS += $(cflags-y) +CFLAGS += $(cflags-y) + +lds-y := arch/riscv/lib/barebox.lds + +CLEAN_FILES += arch/riscv/lib/barebox.ldsarch/riscv/boot/Makefile new file +2
-0@@ -0,0 +1,2 @@ +obj-y += start.o +obj-y += main_entry.oarch/riscv/boot/main_entry.c new file +40
-0@@ -0,0 +1,40 @@ +/* +* Copyright (C) 2016 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#include <common.h> +#include <memory.h> +#include <asm-generic/memory_layout.h> +#include <asm/sections.h> + +void main_entry (void ); + +/** +* Called plainly from assembler code +* +* @note The C environment isn't initialized yet +*/ +void main_entry (void ) +{ +/* clear the BSS first */ +memset (__bss_start,0x00 , __bss_stop - __bss_start); + +mem_malloc_init ((void *)MALLOC_BASE , + (void *)(MALLOC_BASE +MALLOC_SIZE -1 )); + +start_barebox (); +}arch/riscv/boot/start.S new file +31
-0@@ -0,0 +1,74 @@ +/* + * Startup Code for MIPS CPU + * + * based on coreboot/src/arch/riscv/bootblock.S + * + * Copyright (C) 2016 Antony Pavlov <[email protected]> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm-generic/memory_layout.h> + + .text + .section ".text_entry" + .align 2 + +.globl _start +_start: + li sp, STACK_BASE + STACK_SIZE +arch/riscv/boot/start.S line 41
Quoted 10 lines
arch/riscv/boot/start.S new file +10
-0+ # make room for HLS and initialize it + addi sp, sp, -64 /* MENTRY_FRAME_SIZE */ + + # poison the stack + li t1, STACK_BASE + li t0, 0xdeadbeef + sw t0, 0(t1) + + # clear any pending interrupts + //csrwi mip, 0should be removed.
Quoted 62 lines
arch/riscv/boot/start.S new file +32
-0+ /* copy barebox to link location */ + + la a0, _start /* a0 <- _start actual address */ + li a1, CONFIG_TEXT_BASE /* a1 <- _start link address */ + + beq a0, a1, main_entry + + la a2, __bss_start + +#define LONGSIZE 4 + +copy_loop: + /* copy from source address [a0] */ + lw t0, LONGSIZE * 0(a0) + lw t1, LONGSIZE * 1(a0) + lw t2, LONGSIZE * 2(a0) + lw t3, LONGSIZE * 3(a0) + /* copy to target address [a1] */ + sw t0, LONGSIZE * 0(a1) + sw t1, LONGSIZE * 1(a1) + sw t2, LONGSIZE * 2(a1) + sw t3, LONGSIZE * 3(a1) + addi a0, a0, LONGSIZE * 2 + addi a1, a1, LONGSIZE * 2 + bgeu a2, a0, copy_loop + + /* Alas! At the moment I can't load main_entry __link__ address + into a0 with la. Use CONFIG_TEXT_BASE instead. This solution + leads to extra cycles for repeat sp initialization. */ + + li a0, CONFIG_TEXT_BASE + jalr a0arch/riscv/dts/.gitignore new file +1
-0@@ -0,0 +1 @@ +*dtb*arch/riscv/dts/Makefile new file +9
-0@@ -0,0 +1,9 @@ +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) +obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o + +# just to build a built-in.o. Otherwise compilation fails when no devicetree is +# created. +obj- += dummy.o + +always := $(dtb-y) +clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dtsarch/riscv/dts/skeleton.dtsi new file +2
-0@@ -0,0 +1,13 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include andarch/riscv/dts/skeleton.dtsi line 12
Quoted 10 lines
arch/riscv/dts/skeleton.dtsi new file +10
-0+ * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <2>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0 0>; };"reg = <0 0>" instead?
Quoted 612 lines
arch/riscv/dts/skeleton.dtsi new file +1
-0+};arch/riscv/include/asm/barebox.h new file +1
-0@@ -0,0 +1 @@ +/* dummy */ arch/riscv/include/asm/bitops.h new file +35
-0@@ -0,0 +1,35 @@ +/* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* +*/ + +#ifndef _ASM_BITOPS_H_ +#define _ASM_BITOPS_H_ + +#include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/ffz.h> +#include <asm-generic/bitops/hweight.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/find.h> +#include <asm-generic/bitops/ops.h> + +#define set_bit (x, y) __set_bit(x, y) +#define clear_bit (x, y) __clear_bit(x, y) +#define change_bit (x, y) __change_bit(x, y) +#define test_and_set_bit (x, y) __test_and_set_bit(x, y) +#define test_and_clear_bit (x, y) __test_and_clear_bit(x, y) +#define test_and_change_bit (x, y) __test_and_change_bit(x, y) + +#endif /* _ASM_BITOPS_H_ */ arch/riscv/include/asm/bitsperlong.h new file +10
-0@@ -0,0 +1,10 @@ +#ifndef __ASM_BITSPERLONG_H +#define __ASM_BITSPERLONG_H + +#ifdef __riscv64 +#define BITS_PER_LONG 64 +#else +#define BITS_PER_LONG 32 +#endif + +#endif /* __ASM_BITSPERLONG_H */ arch/riscv/include/asm/byteorder.h new file +10
-0@@ -0,0 +1,10 @@ +#ifndef _ASM_RISCV_BYTEORDER_H +#define _ASM_RISCV_BYTEORDER_H + +#if defined(__RISCVEB__) +#include <linux/byteorder/big_endian.h> +#else +#include <linux/byteorder/little_endian.h> +#endif + +#endif /* _ASM_RISCV_BYTEORDER_H */ arch/riscv/include/asm/common.h new file +6
-0@@ -0,0 +1,6 @@ +#ifndef ASM_RISCV_COMMON_H +#define ASM_RISCV_COMMON_H + +/* nothing special yet */ + +#endif /* ASM_RISCV_COMMON_H */ arch/riscv/include/asm/elf.h new file +11
-0@@ -0,0 +1,11 @@ +#ifndef __ASM_RISCV_ELF_H__ +#define __ASM_RISCV_ELF_H__ + +#if __SIZEOF_POINTER__ ==8 +#define ELF_CLASS ELFCLASS64 +#define CONFIG_PHYS_ADDR_T_64BIT +#else +#define ELF_CLASS ELFCLASS32 +#endif + +#endif /* __ASM_RISCV_ELF_H__ */ arch/riscv/include/asm/io.h new file +8
-0@@ -0,0 +1,8 @@ +#ifndef __ASM_RISCV_IO_H +#define __ASM_RISCV_IO_H + +#define IO_SPACE_LIMIT 0 + +#include <asm-generic/io.h> + +#endif /* __ASM_RISCV_IO_H */ arch/riscv/include/asm/mmu.h new file +6
-0@@ -0,0 +1,6 @@ +#ifndef __ASM_MMU_H +#define __ASM_MMU_H + +#define MAP_ARCH_DEFAULT MAP_UNCACHED + +#endif /* __ASM_MMU_H */ arch/riscv/include/asm/posix_types.h new file +1
-0@@ -0,0 +1 @@ +#include <asm-generic/posix_types.h> arch/riscv/include/asm/sections.h new file +1
-0@@ -0,0 +1 @@ +#include <asm-generic/sections.h> arch/riscv/include/asm/string.h new file +1
-0@@ -0,0 +1 @@ +/* dummy */ arch/riscv/include/asm/swab.h new file +6
-0@@ -0,0 +1,6 @@ +#ifndef _ASM_SWAB_H +#define _ASM_SWAB_H + +/* nothing. use generic functions */ + +#endif /* _ASM_SWAB_H */ arch/riscv/include/asm/types.h new file +60
-0@@ -0,0 +1,60 @@ +#ifndef __ASM_RISCV_TYPES_H +#define __ASM_RISCV_TYPES_H + +#ifdef __riscv64 +/* +* This is used in dlmalloc. On RISCV64 we need it to be 64 bit +*/ +#define INTERNAL_SIZE_T unsigned long + +/* +* This is a Kconfig variable in the Kernel, but we want to detect +* this during compile time, so we set it here. +*/ +#define CONFIG_PHYS_ADDR_T_64BIT + +#endif + +typedef unsigned short umode_t ; + +/* +* __xx is ok: it doesn't pollute the POSIX namespace. Use these in the +* header files exported to user space +*/ + +typedef __signed__ char __s8; +typedef unsigned char __u8 ; + +typedef __signed__ short __s16 ; +typedef unsigned short __u16 ; + +typedef __signed__ int __s32; +typedef unsigned int __u32 ; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64 ; +typedef unsigned long long __u64 ; +#endif + +/* +* These aren't exported outside the kernel to avoid name space clashes +*/ +#ifdef __KERNEL__ + +typedef signed char s8 ; +typedef unsigned char u8 ; + +typedef signed short s16 ; +typedef unsigned short u16 ; + +typedef signed int s32 ; +typedef unsigned int u32 ; + +typedef signed long long s64 ; +typedef unsigned long long u64 ; + +#include <asm/bitsperlong.h> + +#endif /* __KERNEL__ */ + +#endif /* __ASM_RISCV_TYPES_H */ arch/riscv/include/asm/unaligned.h new file +19
-0@@ -0,0 +1,19 @@ +#ifndef _ASM_RISCV_UNALIGNED_H +#define _ASM_RISCV_UNALIGNED_H + +/* +* FIXME: this file is copy-n-pasted from sandbox's unaligned.h +*/ + +#include <linux/unaligned/access_ok.h> +#include <linux/unaligned/generic.h> + +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le +#else +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be +#endif + +#endif /* _ASM_RISCV_UNALIGNED_H */ arch/riscv/lib/.gitignore new file +1
-0@@ -0,0 +1 @@ +barebox.ldsarch/riscv/lib/Makefile new file +9
-0@@ -0,0 +1,9 @@ +extra-$(CONFIG_GENERIC_LINKER_SCRIPT) += barebox.lds + +obj-y += riscv_timer.o + +obj-$(CONFIG_32BIT) += lshrdi3.o +obj-$(CONFIG_32BIT) += ashldi3.o +obj-$(CONFIG_32BIT) += ashrdi3.o + +obj-$(CONFIG_BUILTIN_DTB) += dtb.oarch/riscv/lib/ashldi3.c new file +28
-0@@ -0,0 +1,28 @@ +#include <module.h> + +#include "libgcc.h" + +long long __ashldi3 (long long u,word_type b) +{ +DWunion uu, w; +word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { + w.s.low =0 ; + w.s.high = (unsigned int ) uu.s.low << -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.low >> bm; + + w.s.low = (unsigned int ) uu.s.low << b; + w.s.high = ((unsigned int ) uu.s.high << b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__ashldi3);arch/riscv/lib/ashrdi3.c new file +29
-0@@ -0,0 +1,30 @@ +#include <module.h> + +#include "libgcc.h" + +long long __ashrdi3 (long long u,word_type b) +{ + DWunion uu, w> + word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { +/* w.s.high = 1..1 or 0..0 */ + w.s.high = + uu.s.high >>31 ; + w.s.low = uu.s.high >> -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.high << bm; + + w.s.high = uu.s.high >> b; + w.s.low = ((unsigned int ) uu.s.low >> b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__ashrdi3);arch/riscv/lib/asm-offsets.c new file +12
-0@@ -0,0 +1,12 @@ +/* +* Generate definitions needed by assembly language modules. +* This code generates raw asm output which is post-processed to extract +* and format the required data. +*/ + +#include <linux/kbuild.h> + +int main (void ) +{ +return 0 ; +}arch/riscv/lib/barebox.lds.S new file +89
-0@@ -0,0 +1,89 @@ +/* + * Copyright (C) 2016 Antony Pavlov <[email protected]> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm-generic/barebox.lds.h> + +OUTPUT_ARCH(riscv) +ENTRY(_start) +SECTIONS +{ + . = TEXT_BASE; + + . = ALIGN(8); + .text : + { + _stext = .; + _start = .; + KEEP(*(.text_entry*)) + _text = .; + __bare_init_start = .; + *(.text_bare_init*) + __bare_init_end = .; + *(.text*) + } + BAREBOX_BARE_INIT_SIZE + + PRE_IMAGE + + . = ALIGN(8); + .rodata : { *(.rodata*) } + + _etext = .; /* End of text and rodata section */ + _sdata = .; + + . = ALIGN(8); + .data : { *(.data*) } + + .barebox_imd : { BAREBOX_IMD } + + . = ALIGN(8); + .got : { *(.got*) } + + . = .; + __barebox_cmd_start = .; + .barebox_cmd : { BAREBOX_CMDS } + __barebox_cmd_end = .; + + __barebox_magicvar_start = .; + .barebox_magicvar : { BAREBOX_MAGICVARS } + __barebox_magicvar_end = .; + + __barebox_initcalls_start = .; + .barebox_initcalls : { INITCALLS } + __barebox_initcalls_end = .; + + __barebox_exitcalls_start = .; + .barebox_exitcalls : { EXITCALLS } + __barebox_exitcalls_end = .; + + __usymtab_start = .; + __usymtab : { BAREBOX_SYMS } + __usymtab_end = .; + + .rela.dyn : { *(.rela*) } + + .oftables : { BAREBOX_CLK_TABLE() } + + .dtb : { BAREBOX_DTB() } + + _edata = .; + . = ALIGN(8); + __bss_start = .; + .bss : { *(.bss*) *(.sbss*) } + __bss_stop = .; + _end = .; +}arch/riscv/lib/dtb.c new file +41
-0@@ -0,0 +1,41 @@ +/* +* Copyright (C) 2016 Antony Pavlov <[email protected]> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ +#include <common.h> +#include <init.h> +#include <of.h> + +extern char __dtb_start[]; + +static int of_riscv_init (void ) +{ +struct device_node *root; + + root =of_get_root_node (); +if (root) +return 0 ; + + root =of_unflatten_dtb (__dtb_start); +if (!IS_ERR (root)) { +pr_debug ("using internal DTB\n" ); +of_set_root_node (root); +if (IS_ENABLED (CONFIG_OFDEVICE )) +of_probe (); + } + +return 0 ; +} +core_initcall (of_riscv_init);arch/riscv/lib/libgcc.h new file +28
-0@@ -0,0 +1,29 @@ +#ifndef __ASM_LIBGCC_H +#define __ASM_LIBGCC_H + +#include <asm/byteorder.h> + +typedef int word_type __attribute__ ((mode (__word__))); +#ifdef __BIG_ENDIAN +struct DWstruct { +int high, low; +}; +#elif defined(__LITTLE_ENDIAN) +struct DWstruct { +int low, high; +}; +#else +#error I feel sick. +#endif + +typedef union { +struct DWstruct s; +long long ll; +}DWunion ; + +long long __lshrdi3 (long long u,word_type b); +long long __ashldi3 (long long u,word_type b); +long long __ashrdi3 (long long u,word_type b); + +#endif /* __ASM_LIBGCC_H */ arch/riscv/lib/lshrdi3.c new file +28
-0@@ -0,0 +1,28 @@ +#include <module.h> + +#include "libgcc.h" + +long long __lshrdi3 (long long u,word_type b) +{ +DWunion uu, w; +word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { + w.s.high =0 ; + w.s.low = (unsigned int ) uu.s.high >> -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.high << bm; + + w.s.high = (unsigned int ) uu.s.high >> b; + w.s.low = ((unsigned int ) uu.s.low >> b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__lshrdi3);arch/riscv/lib/riscv_timer.c new file +27
-0@@ -0,0 +1,68 @@ +/* +* Copyright (C) 2017 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +/** +* @file +* @brief Clocksource based on RISCV cycle CSR timer +*/ + +#include <init.h> +#include <of.h> +#include <linux/clk.h> +#include <clock.h> +#include <io.h> Quoted 8 lines
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arch/riscv/lib/riscv_timer.c line 34
Quoted 7 lines
arch/riscv/lib/riscv_timer.c new file +7
-0+ +static uint64_t rdcycle_read (void ) +{ + registerunsigned long __v; + + __asm__ __volatile__ ("rdcycle %0" :"=r" (__v)); +Maybe you should also add support for 32-bit cores.
That do you mean?
rdcycle pseudo op should return 32 low bits of cycle counter on 32-bit core.
Quoted 8 lines
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arch/riscv/lib/riscv_timer.c line 42
Quoted 8 lines
arch/riscv/lib/riscv_timer.c new file +8
-0+return __v; +} + +static struct clocksource rdcycle_cs = { + .read = rdcycle_read, + .mask =CLOCKSOURCE_MASK (32 ), +}; +Aah I was a little bit confused by the return value type. You could expand the mask to 64 and write something like that:
register unsigned long
__v;
register unsigned long__t;uint64_ttime;#ifdef
RISCV_64BIT
__asm____volatile__("rdcycle %0" : "=r" (__v)); return__v;
#else
do {
__asm____volatile__("rdcycle %0" : "=r" (__v)); } while (__v== 0); //maybe with an additional counter as timeout__asm____volatile__("rdcycleh %0" : "=r" (__t)); time = (__t<< 32) &__v;
return time;
#endif
Quoted 4 lines
I don't know if this works, but we should always support both register widths.
BTW: Sometimes your license header are from 2016.
RISC-V RFC patchseries v1 was proposed in 2016, see
http://lists.infradead.org/pipermail/barebox/2016-October/028309.html
I have not introduced sizeble changes in this files in 2017.
Signature · 7 lines
Best regards, Antony Pavlov _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
RFC v4 2/10 RISC-V: add Erizo SoC support
In reply to Antony PavlovErizo is an opensource hardware SoC for FPGA.
Signed-off-by Antony Pavlov <[email protected]>
--- arch/riscv/Kconfig | 11 +++++++ arch/riscv/Makefile | 3 ++ arch/riscv/boards/erizo-generic/.gitignore | 1 + arch/riscv/boards/erizo-generic/Makefile | 1 + arch/riscv/boards/erizo-generic/board.c | 28 ++++++++++++++++++ arch/riscv/dts/erizo.dtsi | 46 ++++++++++++++++++++++++++++++ arch/riscv/dts/erizo_generic.dts | 31 ++++++++++++++++++++ arch/riscv/mach-erizo/Kconfig | 11 +++++++ arch/riscv/mach-erizo/Makefile | 3 ++ 9 files changed, 135 insertions(+)
arch/riscv/Kconfig +11 -0
@@ -20,6 +20,15 @@ config GENERIC_LINKER_SCRIPT menu "Machine selection" +choice + prompt "System type" + default MACH_ERIZO + +config MACH_ERIZO + bool "erizo family" + +endchoice + choice prompt "CPU selection" default CPU_RV_GENERIC
@@ -62,6 +71,8 @@ config BUILTIN_DTB_NAME string "DTB to build into the barebox image" depends on BUILTIN_DTB +source arch/riscv/mach-erizo/Kconfig + endmenu source common/Kconfig
arch/riscv/Makefile +3 -0
@@ -7,6 +7,9 @@ cflags-y += -Wall -Wmissing-prototypes -Wstrict-prototypes \ LDFLAGS += $(ldflags-y) LDFLAGS_barebox += -nostdlib +machine-$(CONFIG_MACH_ERIZO) := erizo +board-$(CONFIG_BOARD_ERIZO_GENERIC) := erizo-generic + TEXT_BASE = $(CONFIG_TEXT_BASE) CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE)
arch/riscv/boards/erizo-generic/.gitignore new file +1 -0
@@ -0,0 +1 @@ +barebox.lds
arch/riscv/boards/erizo-generic/Makefile new file +1 -0
@@ -0,0 +1 @@ +obj-y += board.o
arch/riscv/boards/erizo-generic/board.c new file +28 -0
@@ -0,0 +1,28 @@ +/* +* Copyright (C) 2016 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#include <common.h> +#include <driver.h> +#include <init.h> + +static int hostname_init (void ) +{ +barebox_set_hostname ("barebox" ); + +return 0 ; +} +postcore_initcall (hostname_init);
arch/riscv/dts/erizo.dtsi new file +46 -0
46 lines not on this page · raw message
arch/riscv/dts/erizo_generic.dts new file +31 -0
@@ -0,0 +1,31 @@ +#include "erizo.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "generic Erizo SoC board"; + compatible = "miet-riscv-workgroup,erizo-generic-board"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x00800000>; + }; + + spi0 { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpio-sck = <&gpio0 0 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio0 1 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio0 2 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + m25p128@0 { + compatible = "m25p128", "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; +};
arch/riscv/mach-erizo/Kconfig new file +11 -0
@@ -0,0 +1,11 @@ +if MACH_ERIZO + +choice + prompt "Board type" + +config BOARD_ERIZO_GENERIC + bool "erizo generic board" + +endchoice + +endif
arch/riscv/mach-erizo/Makefile new file +3 -0
@@ -0,0 +1,3 @@ +# just to build a built-in.o. Otherwise compilation fails when no o-files is +# created. +obj- += dummy.o
Signature · 7 lines
2.14.1 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC v4 02/10] RISC-V: add Erizo SoC support
Probably it is better to send it as patch not as RFC ;)
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
Quoted 92 lines
Erizo is an opensource hardware SoC for FPGA.
Signed-off-by Antony Pavlov <[email protected]>--- arch/riscv/Kconfig | 11 +++++++ arch/riscv/Makefile | 3 ++ arch/riscv/boards/erizo-generic/.gitignore | 1 + arch/riscv/boards/erizo-generic/Makefile | 1 + arch/riscv/boards/erizo-generic/board.c | 28 ++++++++++++++++++ arch/riscv/dts/erizo.dtsi | 46 ++++++++++++++++++++++++++++++ arch/riscv/dts/erizo_generic.dts | 31 ++++++++++++++++++++ arch/riscv/mach-erizo/Kconfig | 11 +++++++ arch/riscv/mach-erizo/Makefile | 3 ++ 9 files changed, 135 insertions(+)arch/riscv/Kconfig +11
-0@@ -20,6 +20,15 @@ config GENERIC_LINKER_SCRIPT menu "Machine selection" +choice + prompt "System type" + default MACH_ERIZO + +config MACH_ERIZO + bool "erizo family" + +endchoice + choice prompt "CPU selection" default CPU_RV_GENERIC@@ -62,6 +71,8 @@ config BUILTIN_DTB_NAME string "DTB to build into the barebox image" depends on BUILTIN_DTB +source arch/riscv/mach-erizo/Kconfig + endmenu source common/Kconfigarch/riscv/Makefile +3
-0@@ -7,6 +7,9 @@ cflags-y += -Wall -Wmissing-prototypes -Wstrict-prototypes \ LDFLAGS += $(ldflags-y) LDFLAGS_barebox += -nostdlib +machine-$(CONFIG_MACH_ERIZO) := erizo +board-$(CONFIG_BOARD_ERIZO_GENERIC) := erizo-generic + TEXT_BASE = $(CONFIG_TEXT_BASE) CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE)arch/riscv/boards/erizo-generic/.gitignore new file +1
-0@@ -0,0 +1 @@ +barebox.ldsarch/riscv/boards/erizo-generic/Makefile new file +1
-0@@ -0,0 +1 @@ +obj-y += board.oarch/riscv/boards/erizo-generic/board.c new file +14
-0@@ -0,0 +1,28 @@ +/* +* Copyright (C) 2016 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details.
arch/riscv/boards/erizo-generic/board.c line 24
Quoted 10 lines
arch/riscv/boards/erizo-generic/board.c new file +10
-0+* +*/ + +#include <common.h> +#include <driver.h> +#include <init.h> + +static int hostname_init (void ) +{ +barebox_set_hostname ("barebox" );
please, use board name. Maybe: erizo-generic or so. For network boot the filenames will be constructed as following:
username-hostname-filetype
Quoted 120 lines
arch/riscv/boards/erizo-generic/board.c new file +4
-0+ +return 0 ; +} +postcore_initcall (hostname_init);arch/riscv/dts/erizo.dtsi new file +46
-0@@ -0,0 +1,46 @@ +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + compatible = "miet-riscv-workgroup,erizo"; + + #address-cells = <1>; + #size-cells = <1>; + + clocks { + ref_clk: ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "cliffordwolf,picorv32"; + clocks = <&ref_clk>; + reg = <0>; + }; + }; + + uart0: uart@90000000 { + compatible = "ns16550a"; + reg = <0x90000000 0x20>; + reg-shift = <2>; + clocks = <&ref_clk>; + }; + + gpio0: gpio@91000000 { + compatible = "wd,mbl-gpio"; + reg-names = "dat", "dirout"; + reg = <0x91000000 0x4>, + <0x91000004 0x4>; + #gpio-cells = <2>; + gpio-controller; + }; +};arch/riscv/dts/erizo_generic.dts new file +31
-0@@ -0,0 +1,31 @@ +#include "erizo.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "generic Erizo SoC board"; + compatible = "miet-riscv-workgroup,erizo-generic-board"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x00800000>; + }; + + spi0 { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpio-sck = <&gpio0 0 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio0 1 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio0 2 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + m25p128@0 { + compatible = "m25p128", "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; +};arch/riscv/mach-erizo/Kconfig new file +11
-0@@ -0,0 +1,11 @@ +if MACH_ERIZO + +choice + prompt "Board type" + +config BOARD_ERIZO_GENERIC + bool "erizo generic board" + +endchoice + +endifarch/riscv/mach-erizo/Makefile new file +3
-0@@ -0,0 +1,3 @@ +# just to build a built-in.o. Otherwise compilation fails when no o-files is +# created. +obj- += dummy.o
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Re: [RFC v4 02/10] RISC-V: add Erizo SoC support
Quoted 1 line · On Fri, 29 Sep 2017 14:18:40 +0200 Oleksij Rempel <[email protected]>…
Probably it is better to send it as patch not as RFC ;)
There are still some issues.
Quoted 1 line
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
...
Quoted 26 lines
Quoted 26 lines
arch/riscv/boards/erizo-generic/board.c new file +20
-0@@ -0,0 +1,28 @@ +/* +* Copyright (C) 2016 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#include <common.h> +#include <driver.h> +#include <init.h>
Quoted 8 lines
arch/riscv/boards/erizo-generic/board.c line 24
Quoted 4 lines
arch/riscv/boards/erizo-generic/board.c new file +4
-0+ +static int hostname_init (void ) +{ +barebox_set_hostname ("barebox" );please, use board name. Maybe: erizo-generic or so. For network boot the filenames will be constructed as following:
username-hostname-filetype
That's a good point!
Quoted 5 lines
Quoted 5 lines
arch/riscv/boards/erizo-generic/board.c new file +4
-0+ +return 0 ; +} +postcore_initcall (hostname_init);
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Best regards, Antony Pavlov _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
RFC v4 3/10 RISC-V: add low-level debug macros for ns16550
In reply to Antony PavlovThis patch adds macros for ns16550 port initialisation and single char output. The macros can be used in MIPS asm pbl code.
Signed-off-by Antony Pavlov <[email protected]>
--- arch/riscv/include/asm/debug_ll_ns16550.h | 186 ++++++++++++++++++++++++++++++ 1 file changed, 186 insertions(+)
arch/riscv/include/asm/debug_ll_ns16550.h new file +186 -0
@@ -0,0 +1,186 @@ +/* +* Copyright (C) 2016, 2017 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +/** @file +* This file contains declaration for early output support +*/ +#ifndef __INCLUDE_RISCV_ASM_DEBUG_LL_NS16550_H__ +#define __INCLUDE_RISCV_ASM_DEBUG_LL_NS16550_H__ + +#include <linux/kconfig.h> + +#ifdef CONFIG_DEBUG_LL + +#ifndef DEBUG_LL_UART_ADDR +#error DEBUG_LL_UART_ADDR is undefined! +#endif + +#ifndef DEBUG_LL_UART_SHIFT +#error DEBUG_LL_UART_SHIFT is undefined! +#endif + +#ifndef DEBUG_LL_UART_DIVISOR +#error DEBUG_LL_UART_DIVISOR is undefined! +#endif + +#endif /* CONFIG_DEBUG_LL */ + +#define UART_THR (0x0 << DEBUG_LL_UART_SHIFT) +#define UART_RBR (0x0 << DEBUG_LL_UART_SHIFT) +#define UART_DLL (0x0 << DEBUG_LL_UART_SHIFT) +#define UART_DLM (0x1 << DEBUG_LL_UART_SHIFT) +#define UART_LCR (0x3 << DEBUG_LL_UART_SHIFT) +#define UART_LSR (0x5 << DEBUG_LL_UART_SHIFT) + +#define UART_LCR_W 0x07/* Set UART to 8,N,2 & DLAB = 0 */ +#define UART_LCR_DLAB 0x87/* Set UART to 8,N,2 & DLAB = 1 */ + +#define UART_LSR_DR 0x01/* UART received data present */ +#define UART_LSR_THRE 0x20/* Xmit holding register empty */ + +#if defined(DEBUG_LL_UART_IOSIZE32 ) +#define UART_REG_L lw +#define UART_REG_S sw +#elif defined(DEBUG_LL_UART_IOSIZE8 ) +#define UART_REG_L lbu +#define UART_REG_S sb +#else +#error "Please define DEBUG_LL_UART_IOSIZE{8,32}" +#endif + +#ifndef __ASSEMBLY__ +/* +* C macros +*/ + +#include <asm/io.h> + +static inline void PUTC_LL (char ch) +{ +#ifdef CONFIG_DEBUG_LL +while (!(__raw_readl ((u8 *)DEBUG_LL_UART_ADDR +UART_LSR ) &UART_LSR_THRE )) + ; +__raw_writel (ch, (u8 *)DEBUG_LL_UART_ADDR +UART_THR ); +#endif /* CONFIG_DEBUG_LL */ +} + +static inline void debug_ll_ns16550_init (void ) +{ +#ifdef CONFIG_DEBUG_LL +__raw_writel (UART_LCR_DLAB , (u8 *)DEBUG_LL_UART_ADDR +UART_LCR ); +__raw_writel (DEBUG_LL_UART_DIVISOR &0xff , (u8 *)DEBUG_LL_UART_ADDR +UART_DLL ); +__raw_writel ((DEBUG_LL_UART_DIVISOR >>8 ) &0xff , (u8 *)DEBUG_LL_UART_ADDR +UART_DLM ); +__raw_writel (UART_LCR_W , (u8 *)DEBUG_LL_UART_ADDR +UART_LCR ); +#endif /* CONFIG_DEBUG_LL */ +} +#else /* __ASSEMBLY__ */ +/* +* Macros for use in assembly language code +*/ + +.macro debug_ll_ns16550_init +#ifdef CONFIG_DEBUG_LL + li t0, DEBUG_LL_UART_ADDR + + li t1, UART_LCR_DLAB /* DLAB on */ + UART_REG_S t1, UART_LCR(t0) /* Write it out */ + + li t1, DEBUG_LL_UART_DIVISOR + UART_REG_S t1, UART_DLL(t0) /* write low order byte */ + srl t1, t1, 8 + UART_REG_S t1, UART_DLM(t0) /* write high order byte */ + + li t1, UART_LCR_W /* DLAB off */ + UART_REG_S t1, UART_LCR(t0) /* Write it out */ +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * output a character in a0 + */ +.macro debug_ll_outc_a0 +#ifdef CONFIG_DEBUG_LL + + li t0, DEBUG_LL_UART_ADDR + +201: + UART_REG_L t1, UART_LSR(t0) /* get line status */ + andi t1, t1, UART_LSR_THRE /* check for transmitter empty */ + beqz t1, 201b /* try again */ + + UART_REG_S a0, UART_THR(t0) /* write the character */ + +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * output a character + */ +.macro debug_ll_outc chr +#ifdef CONFIG_DEBUG_LL + li a0, \chr + debug_ll_outc_a0 +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * output CR + NL + */ +.macro debug_ll_ns16550_outnl +#ifdef CONFIG_DEBUG_LL + debug_ll_outc '\r' + debug_ll_outc '\n' +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * check character in input buffer + * return value: + * v0 = 0 no character in input buffer + * v0 != 0 character in input buffer + */ +.macro debug_ll_tstc +#ifdef CONFIG_DEBUG_LL + li t0, DEBUG_LL_UART_ADDR + + /* get line status and check for data present */ + UART_REG_L s0, UART_LSR(t0) + andi s0, s0, UART_LSR_DR + +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * get character to v0 + */ +.macro debug_ll_getc +#ifdef CONFIG_DEBUG_LL + +204: + debug_ll_tstc + + /* try again */ + beqz s0, 204b + + /* read a character */ + UART_REG_L s0, UART_RBR(t0) + +#endif /* CONFIG_DEBUG_LL */ +.endm +#endif /* __ASSEMBLY__ */ + +#endif /* __INCLUDE_RISCV_ASM_DEBUG_LL_NS16550_H__ */
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2.14.1 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
RFC v4 4/10 RISC-V: add nmon nano-monitor
In reply to Antony Pavlovnmon is a tiny (<1024 bytes) monitor program
for the RV32I processors.
It can operate with NO working RAM at all!
It uses only the processor registers and NS16550-compatible UART port for operation, so it can be used for a memory controller setup code debugging.
Signed-off-by Antony Pavlov <[email protected]>
--- arch/riscv/Kconfig | 24 ++++ arch/riscv/boot/start.S | 14 +++ arch/riscv/include/asm/riscv_nmon.h | 234 ++++++++++++++++++++++++++++++++++++ 3 files changed, 272 insertions(+)
arch/riscv/Kconfig +24 -0
@@ -75,6 +75,30 @@ source arch/riscv/mach-erizo/Kconfig endmenu +menu "RISC-V specific settings" + +config HAS_NMON + bool + +config NMON + bool "nmon" + depends on HAS_NMON + depends on DEBUG_LL + help + Say yes here to add the nmon to pbl. + nmon -- nano-monitor program for the RISC-V processors. + It can operate with NO working RAM, using only + the processor registers. + +config NMON_HELP + bool "nmon help message" + depends on NMON + help + Say yes here to get the nmon commands message on + every nmon start. + +endmenu + source common/Kconfig source commands/Kconfig source net/Kconfig
arch/riscv/boot/start.S +14 -0
@@ -21,12 +21,21 @@ #include <asm-generic/memory_layout.h> +#include "mach/debug_ll.h" + +#include "asm/riscv_nmon.h" + .text .section ".text_entry" .align 2 .globl _start _start: + + debug_ll_ns16550_init + + riscv_nmon + li sp, STACK_BASE + STACK_SIZE # make room for HLS and initialize it
@@ -66,9 +75,14 @@ copy_loop: addi a1, a1, LONGSIZE * 2 bgeu a2, a0, copy_loop + nmon_outs copy_loop_done_message + /* Alas! At the moment I can't load main_entry __link__ address into a0 with la. Use CONFIG_TEXT_BASE instead. This solution leads to extra cycles for repeat sp initialization. */ li a0, CONFIG_TEXT_BASE jalr a0 + +copy_loop_done_message: + .asciz "\r\ncopy loop done\r\nrestarting...\r\n"
arch/riscv/include/asm/riscv_nmon.h new file +234 -0
234 lines not on this page · raw message
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2.14.1 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC v4 04/10] RISC-V: add nmon nano-monitor
Same as for MIPS
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
arch/riscv/include/asm/riscv_nmon.h
Quoted 97 lines
nmon is a tiny (<1024 bytes) monitor program
for the RV32I processors.It can operate with NO working RAM at all!
It uses only the processor registers and NS16550-compatible UART port for operation, so it can be used for a memory controller setup code debugging.
Signed-off-by Antony Pavlov <[email protected]>--- arch/riscv/Kconfig | 24 ++++ arch/riscv/boot/start.S | 14 +++ arch/riscv/include/asm/riscv_nmon.h | 234 ++++++++++++++++++++++++++++++++++++ 3 files changed, 272 insertions(+)arch/riscv/Kconfig +24
-0@@ -75,6 +75,30 @@ source arch/riscv/mach-erizo/Kconfig endmenu +menu "RISC-V specific settings" + +config HAS_NMON + bool + +config NMON + bool "nmon" + depends on HAS_NMON + depends on DEBUG_LL + help + Say yes here to add the nmon to pbl. + nmon -- nano-monitor program for the RISC-V processors. + It can operate with NO working RAM, using only + the processor registers. + +config NMON_HELP + bool "nmon help message" + depends on NMON + help + Say yes here to get the nmon commands message on + every nmon start. + +endmenu + source common/Kconfig source commands/Kconfig source net/Kconfigarch/riscv/boot/start.S +14
-0@@ -21,12 +21,21 @@ #include <asm-generic/memory_layout.h> +#include "mach/debug_ll.h" + +#include "asm/riscv_nmon.h" + .text .section ".text_entry" .align 2 .globl _start _start: + + debug_ll_ns16550_init + + riscv_nmon + li sp, STACK_BASE + STACK_SIZE # make room for HLS and initialize it@@ -66,9 +75,14 @@ copy_loop: addi a1, a1, LONGSIZE * 2 bgeu a2, a0, copy_loop + nmon_outs copy_loop_done_message + /* Alas! At the moment I can't load main_entry __link__ address into a0 with la. Use CONFIG_TEXT_BASE instead. This solution leads to extra cycles for repeat sp initialization. */ li a0, CONFIG_TEXT_BASE jalr a0 + +copy_loop_done_message: + .asciz "\r\ncopy loop done\r\nrestarting...\r\n"arch/riscv/include/asm/riscv_nmon.h new file +0
-0
may be arch/riscv/include/asm/pbl_nmon.h instead?
to use same naming shema as for existing arch:arch/mips/include/asm/pbl_nmon.h
every thing else seems to be nearly identical with MIPS, except some instruction differences.
Quoted 236 lines
arch/riscv/include/asm/riscv_nmon.h new file +234
-0@@ -0,0 +1,234 @@ +/* +* nano-monitor for RISC-V CPU +* +* Copyright (C) 2016, 2017 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#ifndef __ASM_RISCV_NMON_H +#define __ASM_RISCV_NMON_H + +#define CODE_ESC 0x1b + +.macro nmon_outs msg + + la a1, \msg + + jal _nmon_outs + +.endm + +/* + * output a 32-bit value in hex + */ +.macro debug_ll_outhexw +#ifdef CONFIG_DEBUG_LL + move t6, a0 + li t5, 32 + +202: + addi t5, t5, -4 + srl a0, t6, t5 + + /* output one hex digit */ + andi a0, a0, 15 + li t4, 10 + blt a0, t4, 203f + + addi a0, a0, ('a' - '9' - 1) + +203: + addi a0, a0, '0' + + debug_ll_outc_a0 + + li t4, 1 + bge t5, t4, 202b + +#endif /* CONFIG_DEBUG_LL */ +.endm + +.macro riscv_nmon + +nmon_main_help: +#ifdef CONFIG_NMON_HELP + nmon_outs msg_nmon_help +#endif /* CONFIG_NMON_HELP */ + +nmon_main: + nmon_outs msg_prompt + + debug_ll_getc + + li a0, 'q' + bne s0, a0, 3f + + jal _nmon_outc_a0 + + j nmon_exit + +3: + li a0, 'd' + beq s0, a0, nmon_cmd_d + + li a0, 'w' + beq s0, a0, nmon_cmd_w + + li a0, 'g' + beq s0, a0, nmon_cmd_g + + j nmon_main_help + +nmon_cmd_d: + jal _nmon_outc_a0 + + li a0, ' ' + jal _nmon_outc_a0 + + jal _nmon_gethexw + + nmon_outs msg_nl + + lw a0, (s0) + debug_ll_outhexw + + j nmon_main + +nmon_cmd_w: + jal _nmon_outc_a0 + + li a0, ' ' + jal _nmon_outc_a0 + + jal _nmon_gethexw + move s2, s0 + + li a0, ' ' + jal _nmon_outc_a0 + jal _nmon_gethexw + + sw s0, 0(s2) + j nmon_main + +nmon_cmd_g: + jal _nmon_outc_a0 + + li a0, ' ' + jal _nmon_outc_a0 + + jal _nmon_gethexw + move s2, s0 + + nmon_outs msg_nl + + jalr s2 + j nmon_main + +_nmon_outc_a0: + debug_ll_outc_a0 + jr ra + +_nmon_outs: + + lb a0, 0(a1) + addi a1, a1, 1 + beqz a0, _nmon_jr_ra_exit + + debug_ll_outc_a0 + + j _nmon_outs + +_nmon_gethexw: + + li t3, 8 + li t2, 0 + +_get_hex_digit: + debug_ll_getc + + li s1, CODE_ESC + beq s0, s1, nmon_main + + li s1, '0' + bge s0, s1, 0f + j _get_hex_digit + +0: + li s1, '9' + ble s0, s1, 9f + + li s1, 'f' + ble s0, s1, 1f + j _get_hex_digit + +1: + li s1, 'a' + bge s0, s1, 8f + + j _get_hex_digit + +8: /* s0 \in {'a', 'b' ... 'f'} */ + sub a3, s0, s1 + addi a3, a3, 0xa + j 0f + +9: /* s0 \in {'0', '1' ... '9'} */ + li a3, '0' + sub a3, s0, a3 + +0: move a0, s0 + debug_ll_outc_a0 + + sll t2, t2, 4 + or t2, t2, a3 + li t0, 1 + sub t3, t3, t0 + + beqz t3, 0f + + j _get_hex_digit + +0: + move s0, t2 + +_nmon_jr_ra_exit: + jr ra + +msg_prompt: + .asciz "\r\nnmon> " + +msg_nl: + .asciz "\r\n" + +msg_bsp: + .asciz "\b \b" + +#ifdef CONFIG_NMON_HELP +msg_nmon_help: + .ascii "\r\n\r\nnmon commands:\r\n" + .ascii " q - quit\r\n" + .ascii " d <addr> - read 32-bit word from <addr>\r\n" + .ascii " w <addr> <val> - write 32-bit word to <addr>\r\n" + .ascii " g <addr> - jump to <addr>\r\n" + .asciz " use <ESC> key to interrupt current command\r\n" +#endif /* CONFIG_NMON_HELP */ + + .align 2 +nmon_exit: + nmon_outs msg_nl + +.endm + +#endif /* __ASM_RISCV_NMON_H */
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Re: [RFC v4 04/10] RISC-V: add nmon nano-monitor
Quoted 2 lines · On Fri, 29 Sep 2017 14:26:34 +0200 Oleksij Rempel <[email protected]>…
Same as for MIPS
Yes, I have based arch/riscv on arch/mips.
Quoted 1 line
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
...
Quoted 9 lines
arch/riscv/include/asm/riscv_nmon.h
Quoted 5 lines
arch/riscv/include/asm/riscv_nmon.h new file +0
-0may be
arch/riscv/include/asm/pbl_nmon.hinstead?
to use same naming shema as for existing arch:arch/mips/include/asm/pbl_nmon.h
Contrariwise! I have a plan to sync mips naming schema with riscv.
Quoted 2 lines
every thing else seems to be nearly identical with MIPS, except some instruction differences.
Little wonder, since RISC-V ISA looks like reduced MIPS ISA.
I can recomend the notable paper on ISA ideas behind RISC-V
Design of the RISC-V Instruction Set Architecture by Andrew Waterman
http://escholarship.org/uc/item/7zj0b3m7#page-14
Quoted 242 lines
Quoted 236 lines
arch/riscv/include/asm/riscv_nmon.h new file +234
-0@@ -0,0 +1,234 @@ +/* +* nano-monitor for RISC-V CPU +* +* Copyright (C) 2016, 2017 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#ifndef __ASM_RISCV_NMON_H +#define __ASM_RISCV_NMON_H + +#define CODE_ESC 0x1b + +.macro nmon_outs msg + + la a1, \msg + + jal _nmon_outs + +.endm + +/* + * output a 32-bit value in hex + */ +.macro debug_ll_outhexw +#ifdef CONFIG_DEBUG_LL + move t6, a0 + li t5, 32 + +202: + addi t5, t5, -4 + srl a0, t6, t5 + + /* output one hex digit */ + andi a0, a0, 15 + li t4, 10 + blt a0, t4, 203f + + addi a0, a0, ('a' - '9' - 1) + +203: + addi a0, a0, '0' + + debug_ll_outc_a0 + + li t4, 1 + bge t5, t4, 202b + +#endif /* CONFIG_DEBUG_LL */ +.endm + +.macro riscv_nmon + +nmon_main_help: +#ifdef CONFIG_NMON_HELP + nmon_outs msg_nmon_help +#endif /* CONFIG_NMON_HELP */ + +nmon_main: + nmon_outs msg_prompt + + debug_ll_getc + + li a0, 'q' + bne s0, a0, 3f + + jal _nmon_outc_a0 + + j nmon_exit + +3: + li a0, 'd' + beq s0, a0, nmon_cmd_d + + li a0, 'w' + beq s0, a0, nmon_cmd_w + + li a0, 'g' + beq s0, a0, nmon_cmd_g + + j nmon_main_help + +nmon_cmd_d: + jal _nmon_outc_a0 + + li a0, ' ' + jal _nmon_outc_a0 + + jal _nmon_gethexw + + nmon_outs msg_nl + + lw a0, (s0) + debug_ll_outhexw + + j nmon_main + +nmon_cmd_w: + jal _nmon_outc_a0 + + li a0, ' ' + jal _nmon_outc_a0 + + jal _nmon_gethexw + move s2, s0 + + li a0, ' ' + jal _nmon_outc_a0 + jal _nmon_gethexw + + sw s0, 0(s2) + j nmon_main + +nmon_cmd_g: + jal _nmon_outc_a0 + + li a0, ' ' + jal _nmon_outc_a0 + + jal _nmon_gethexw + move s2, s0 + + nmon_outs msg_nl + + jalr s2 + j nmon_main + +_nmon_outc_a0: + debug_ll_outc_a0 + jr ra + +_nmon_outs: + + lb a0, 0(a1) + addi a1, a1, 1 + beqz a0, _nmon_jr_ra_exit + + debug_ll_outc_a0 + + j _nmon_outs + +_nmon_gethexw: + + li t3, 8 + li t2, 0 + +_get_hex_digit: + debug_ll_getc + + li s1, CODE_ESC + beq s0, s1, nmon_main + + li s1, '0' + bge s0, s1, 0f + j _get_hex_digit + +0: + li s1, '9' + ble s0, s1, 9f + + li s1, 'f' + ble s0, s1, 1f + j _get_hex_digit + +1: + li s1, 'a' + bge s0, s1, 8f + + j _get_hex_digit + +8: /* s0 \in {'a', 'b' ... 'f'} */ + sub a3, s0, s1 + addi a3, a3, 0xa + j 0f + +9: /* s0 \in {'0', '1' ... '9'} */ + li a3, '0' + sub a3, s0, a3 + +0: move a0, s0 + debug_ll_outc_a0 + + sll t2, t2, 4 + or t2, t2, a3 + li t0, 1 + sub t3, t3, t0 + + beqz t3, 0f + + j _get_hex_digit + +0: + move s0, t2 + +_nmon_jr_ra_exit: + jr ra + +msg_prompt: + .asciz "\r\nnmon> " + +msg_nl: + .asciz "\r\n" + +msg_bsp: + .asciz "\b \b" + +#ifdef CONFIG_NMON_HELP +msg_nmon_help: + .ascii "\r\n\r\nnmon commands:\r\n" + .ascii " q - quit\r\n" + .ascii " d <addr> - read 32-bit word from <addr>\r\n" + .ascii " w <addr> <val> - write 32-bit word to <addr>\r\n" + .ascii " g <addr> - jump to <addr>\r\n" + .asciz " use <ESC> key to interrupt current command\r\n" +#endif /* CONFIG_NMON_HELP */ + + .align 2 +nmon_exit: + nmon_outs msg_nl + +.endm + +#endif /* __ASM_RISCV_NMON_H */ Signature · 2 lines
Regards, Oleksij
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RFC v4 5/10 RISC-V: erizo: add DEBUG_LL support
In reply to Antony PavlovSigned-off-by Antony Pavlov <[email protected]>
--- arch/riscv/Kconfig | 1 + arch/riscv/mach-erizo/include/mach/debug_ll.h | 37 +++++++++++++++++++++++++++ 2 files changed, 38 insertions(+)
arch/riscv/Kconfig +1 -0
@@ -26,6 +26,7 @@ choice config MACH_ERIZO bool "erizo family" + select HAS_DEBUG_LL endchoice
arch/riscv/mach-erizo/include/mach/debug_ll.h new file +37 -0
@@ -0,0 +1,37 @@ +/* +* Copyright (C) 2017 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#ifndef __MACH_ERIZO_DEBUG_LL__ +#define __MACH_ERIZO_DEBUG_LL__ + +/** @file +* This File contains declaration for early output support +*/ + +#include <linux/kconfig.h> + +#define DEBUG_LL_UART_ADDR 0x90000000 +#define DEBUG_LL_UART_SHIFT 2 +#define DEBUG_LL_UART_IOSIZE32 + +#define DEBUG_LL_UART_CLK (24000000 / 16) +#define DEBUG_LL_UART_BPS CONFIG_BAUDRATE +#define DEBUG_LL_UART_DIVISOR (DEBUG_LL_UART_CLK / DEBUG_LL_UART_BPS) + +#include <asm/debug_ll_ns16550.h> + +#endif /* __MACH_ERIZO_DEBUG_LL__ */
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RFC v4 6/10 RISC-V: erizo: enable NMON
In reply to Antony PavlovSigned-off-by Antony Pavlov <[email protected]>
--- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+)
arch/riscv/Kconfig +1 -0
@@ -27,6 +27,7 @@ choice config MACH_ERIZO bool "erizo family" select HAS_DEBUG_LL + select HAS_NMON endchoice
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RFC v4 7/10 RISC-V: erizo: add nmon image creation
In reply to Antony PavlovSigned-off-by Antony Pavlov <[email protected]>
--- arch/riscv/Makefile | 11 +++++++++++ scripts/erizo-nmon-image | 3 +++ 2 files changed, 14 insertions(+)
arch/riscv/Makefile +11 -0
@@ -69,3 +69,14 @@ CFLAGS += $(cflags-y) lds-y := arch/riscv/lib/barebox.lds CLEAN_FILES += arch/riscv/lib/barebox.lds + +ifeq ($(CONFIG_MACH_ERIZO),y) +KBUILD_IMAGE := barebox.erizo.nmon +endif + +quiet_cmd_erizo_nmon_image = MKIMAGE $@ + cmd_erizo_nmon_image = $(srctree)/scripts/erizo-nmon-image $< $@ || \ + echo "WARNING: Couldn't create erizo nmon image due to previous errors." + +barebox.erizo.nmon: $(KBUILD_BINARY) FORCE + $(call if_changed,erizo_nmon_image)
scripts/erizo-nmon-image new file +3 -0
@@ -0,0 +1,3 @@ +#!/bin/sh + +hexdump -v -e '/4 "%08x\n"' $1 | perl -e '$a = 0x80000000; while (<>) { chop; printf("expect \"nmon> \"\n"); printf("send \"w%08x$_\"\n", $a); $a = $a + 4; }' > $2
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RFC v4 8/10 RISC-V: add erizo_generic_defconfig
In reply to Antony PavlovSigned-off-by Antony Pavlov <[email protected]>
--- arch/riscv/configs/erizo_generic_defconfig | 55 ++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+)
arch/riscv/configs/erizo_generic_defconfig new file +55 -0
@@ -0,0 +1,55 @@ +CONFIG_32BIT=y +CONFIG_BUILTIN_DTB=y +CONFIG_BUILTIN_DTB_NAME="erizo_generic" +# CONFIG_GLOBALVAR is not set +CONFIG_TEXT_BASE=0x80000000 +CONFIG_MEMORY_LAYOUT_FIXED=y +CONFIG_STACK_BASE=0x800e0000 +CONFIG_STACK_SIZE=0x20000 +CONFIG_MALLOC_BASE=0x80100000 +CONFIG_MALLOC_SIZE=0x100000 +CONFIG_MALLOC_TLSF=y +CONFIG_PANIC_HANG=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +# CONFIG_ERRNO_MESSAGES is not set +# CONFIG_TIMESTAMP is not set +# CONFIG_BOOTM is not set +# CONFIG_ENV_HANDLING is not set +CONFIG_POLLER=y +CONFIG_DEBUG_LL=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_IMD=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_GO=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_CMP=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SPI=y +CONFIG_CMD_OF_DUMP=y +CONFIG_CMD_TIME=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_OFDEVICE=y +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_SPI_GPIO=y +CONFIG_I2C=y +CONFIG_I2C_GPIO=y +CONFIG_MTD=y +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_MTD_M25P80=y +CONFIG_CLOCKSOURCE_DUMMY_RATE=60000 +CONFIG_EEPROM_AT25=y +CONFIG_EEPROM_AT24=y +CONFIG_GPIO_GENERIC_PLATFORM=y +# CONFIG_PINCTRL is not set +CONFIG_DIGEST_CRC32_GENERIC=y
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Re: [RFC v4 08/10] RISC-V: add erizo_generic_defconfig
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
Quoted 53 lines
Signed-off-by Antony Pavlov <[email protected]>--- arch/riscv/configs/erizo_generic_defconfig | 55 ++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+)arch/riscv/configs/erizo_generic_defconfig new file +42
-0@@ -0,0 +1,55 @@ +CONFIG_32BIT=y +CONFIG_BUILTIN_DTB=y +CONFIG_BUILTIN_DTB_NAME="erizo_generic" +# CONFIG_GLOBALVAR is not set +CONFIG_TEXT_BASE=0x80000000 +CONFIG_MEMORY_LAYOUT_FIXED=y +CONFIG_STACK_BASE=0x800e0000 +CONFIG_STACK_SIZE=0x20000 +CONFIG_MALLOC_BASE=0x80100000 +CONFIG_MALLOC_SIZE=0x100000 +CONFIG_MALLOC_TLSF=y +CONFIG_PANIC_HANG=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +# CONFIG_ERRNO_MESSAGES is not set +# CONFIG_TIMESTAMP is not set +# CONFIG_BOOTM is not set +# CONFIG_ENV_HANDLING is not set +CONFIG_POLLER=y +CONFIG_DEBUG_LL=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_IMD=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_GO=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_CMP=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SPI=y +CONFIG_CMD_OF_DUMP=y +CONFIG_CMD_TIME=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_OFDEVICE=y
arch/riscv/configs/erizo_generic_defconfig line 52
Quoted 10 lines
arch/riscv/configs/erizo_generic_defconfig new file +10
-0+CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_SPI_GPIO=y +CONFIG_I2C=y +CONFIG_I2C_GPIO=y +CONFIG_MTD=y +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_MTD_M25P80=y +CONFIG_CLOCKSOURCE_DUMMY_RATE=60000 +CONFIG_EEPROM_AT25=y +CONFIG_EEPROM_AT24=y
hm... none of it seems to be in devicetree. Do you need this eeproms?
Quoted 4 lines
arch/riscv/configs/erizo_generic_defconfig new file +3
-0+CONFIG_GPIO_GENERIC_PLATFORM=y +# CONFIG_PINCTRL is not set +CONFIG_DIGEST_CRC32_GENERIC=y
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Re: [RFC v4 08/10] RISC-V: add erizo_generic_defconfig
Quoted 58 lines · On Fri, 29 Sep 2017 14:29:21 +0200 Oleksij Rempel <[email protected]>…
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
Quoted 57 lines
Signed-off-by Antony Pavlov <[email protected]>--- arch/riscv/configs/erizo_generic_defconfig | 55 ++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+)arch/riscv/configs/erizo_generic_defconfig new file +46
-0@@ -0,0 +1,55 @@ +CONFIG_32BIT=y +CONFIG_BUILTIN_DTB=y +CONFIG_BUILTIN_DTB_NAME="erizo_generic" +# CONFIG_GLOBALVAR is not set +CONFIG_TEXT_BASE=0x80000000 +CONFIG_MEMORY_LAYOUT_FIXED=y +CONFIG_STACK_BASE=0x800e0000 +CONFIG_STACK_SIZE=0x20000 +CONFIG_MALLOC_BASE=0x80100000 +CONFIG_MALLOC_SIZE=0x100000 +CONFIG_MALLOC_TLSF=y +CONFIG_PANIC_HANG=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +# CONFIG_ERRNO_MESSAGES is not set +# CONFIG_TIMESTAMP is not set +# CONFIG_BOOTM is not set +# CONFIG_ENV_HANDLING is not set +CONFIG_POLLER=y +CONFIG_DEBUG_LL=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_IMD=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_GO=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_CMP=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SPI=y +CONFIG_CMD_OF_DUMP=y +CONFIG_CMD_TIME=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_OFDEVICE=y +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_SPI_GPIO=y +CONFIG_I2C=y +CONFIG_I2C_GPIO=y
Quoted 8 lines
arch/riscv/configs/erizo_generic_defconfig line 52
Quoted 6 lines
arch/riscv/configs/erizo_generic_defconfig new file +6
-0+CONFIG_MTD=y +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_MTD_M25P80=y +CONFIG_CLOCKSOURCE_DUMMY_RATE=60000 +CONFIG_EEPROM_AT25=y +CONFIG_EEPROM_AT24=yhm... none of it seems to be in devicetree. Do you need this eeproms?
My bad! These options used in development branch.
In my RICS-V TODO list I have the 'add support for Opencores I2C and SPI IP-blocks' record.
At the moment I work on testing bitbanged SPI and I2C on real FPGA boards. Next I will try to use Opencores I2C and SPI IP-blocks instead of GPIO bitbang.
Quoted 5 lines
Quoted 5 lines
arch/riscv/configs/erizo_generic_defconfig new file +3
-0+CONFIG_GPIO_GENERIC_PLATFORM=y +# CONFIG_PINCTRL is not set +CONFIG_DIGEST_CRC32_GENERIC=y
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RFC v4 9/10 scripts: add nmon-loader
In reply to Antony PavlovSigned-off-by Antony Pavlov <[email protected]>
--- scripts/nmon-loader | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)
scripts/nmon-loader new file +31 -0
@@ -0,0 +1,31 @@ +#!/usr/bin/expect -f + +# device +set image [lindex $argv 0]; +set modem [lindex $argv 1]; +set speed [lindex $argv 2]; + +if {$argc != 3} { + puts "Usage:" + puts " nmon-loader.expect <file> <device> <speed>" + exit 2 +} + +# keep it open +exec sh -c "sleep 3 < $modem" & + +# serial port parameters +exec stty -F $modem $speed raw -clocal -echo -istrip -hup + +# connect +send_user "connecting to $modem, exit with ~.\n" +spawn -open [open $modem w+] +send_user "connected\n" +send "\r" + +source $image + +interact { + ~- exit + ~~ {send "\034"} +}
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RFC v4 10/10 Documentation: add RISC-V docs
In reply to Antony PavlovSigned-off-by Antony Pavlov <[email protected]>
--- Documentation/boards/riscv.rst | 110 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+)
Documentation/boards/riscv.rst new file +110 -0
@@ -0,0 +1,110 @@ +RISC-V +====== + +At the moment only qemu emulator is supported (see https://github.com/riscv/riscv-isa-sim +for details). + +Running RISC-V barebox on qemu +------------------------------ + +Obtain RISC-V GCC/Newlib Toolchain, +see https://github.com/riscv/riscv-tools/blob/master/README.md +for details. The ``build.sh`` script from ``riscv-tools`` should +create toolchain. + +Next compile qemu emulator:: + + $ git clone -b 20170824.erizo https://github.com/miet-riscv-workgroup/riscv-qemu + $ cd riscv-qemu + $ cap="no" ./configure \ + --extra-cflags="-Wno-maybe-uninitialized" \ + --audio-drv-list="" \ + --disable-attr \ + --disable-blobs \ + --disable-bluez \ + --disable-brlapi \ + --disable-curl \ + --disable-curses \ + --disable-docs \ + --disable-kvm \ + --disable-spice \ + --disable-sdl \ + --disable-vde \ + --disable-vnc-sasl \ + --disable-werror \ + --enable-trace-backend=simple \ + --disable-stack-protector \ + --target-list=riscv32-softmmu,riscv64-softmmu + $ make + + +Next compile barebox:: + + $ make erizo_generic_defconfig ARCH=riscv + ... + $ make ARCH=riscv CROSS_COMPILE=<path to your riscv toolchain>/riscv32-unknown-elf- + +Run barebox:: + + $ <path to riscv-qemu source>/riscv32-softmmu/qemu-system-riscv32 \ + -nographic -M erizo -bios <path to barebox sources >/barebox.bin \ + -serial stdio -monitor none -trace file=/dev/null + + nmon> q + + copy loop done + restarting... + + nmon> q + Switch to console [cs0] + + + barebox 2017.08.0-00102-g212af75153 #1 Mon Sep 4 20:54:31 MSK 2017 + + + Board: generic Erizo SoC board + m25p80 m25p128@00: unrecognized JEDEC id bytes: 00, 0, 0 + m25p80 m25p128@00: probe failed: error 2 + malloc space: 0x80100000 -> 0x801fffff (size 1 MiB) + running /env/bin/init... + /env/bin/init not found + barebox:/ + + +Running RISC-V barebox on DE0-Nano FPGA board +--------------------------------------------- + +See https://github.com/open-design/riscv-soc-cores/ for instructions +on DE0-Nano bitstream generation and loading. + +Connect to board's UART with your favorite serial communication software +(e.g. minicom) and check 'nmon> ' prompt (nmon runs from onchip ROM). + +Next close your communication software and use ./scripts/nmon-loader +to load barebox image into board's DRAM, e.g. + + # ./scripts/nmon-loader barebox.erizo.nmon /dev/ttyUSB1 115200 + +Wait several munutes for 'nmon> ' prompt. + +Next, start barebox from DRAM: + + nmon> g 80000000 + +You should see one more 'nmon> ' prompt (this nmon runs from DRAM). +Exit nmon with 'q' command: + + nmon> q + Switch to console [cs0] + + + barebox 2017.08.0-00102-g212af75153 #1 Mon Sep 4 20:54:31 MSK 2017 + + + Board: generic Erizo SoC board + m25p80 m25p128@00: unrecognized JEDEC id bytes: 00, 0, 0 + m25p80 m25p128@00: probe failed: error 2 + malloc space: 0x80100000 -> 0x801fffff (size 1 MiB) + running /env/bin/init... + /env/bin/init not found + barebox:/
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Re: [RFC v4 10/10] Documentation: add RISC-V docs
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
Quoted 107 lines
Signed-off-by Antony Pavlov <[email protected]>--- Documentation/boards/riscv.rst | 110 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+)Documentation/boards/riscv.rst new file +96
-0@@ -0,0 +1,110 @@ +RISC-V +====== + +At the moment only qemu emulator is supported (see https://github.com/riscv/riscv-isa-sim +for details). + +Running RISC-V barebox on qemu +------------------------------ + +Obtain RISC-V GCC/Newlib Toolchain, +see https://github.com/riscv/riscv-tools/blob/master/README.md +for details. The ``build.sh`` script from ``riscv-tools`` should +create toolchain. + +Next compile qemu emulator:: + + $ git clone -b 20170824.erizo https://github.com/miet-riscv-workgroup/riscv-qemu + $ cd riscv-qemu + $ cap="no" ./configure \ + --extra-cflags="-Wno-maybe-uninitialized" \ + --audio-drv-list="" \ + --disable-attr \ + --disable-blobs \ + --disable-bluez \ + --disable-brlapi \ + --disable-curl \ + --disable-curses \ + --disable-docs \ + --disable-kvm \ + --disable-spice \ + --disable-sdl \ + --disable-vde \ + --disable-vnc-sasl \ + --disable-werror \ + --enable-trace-backend=simple \ + --disable-stack-protector \ + --target-list=riscv32-softmmu,riscv64-softmmu + $ make + + +Next compile barebox:: + + $ make erizo_generic_defconfig ARCH=riscv + ... + $ make ARCH=riscv CROSS_COMPILE=<path to your riscv toolchain>/riscv32-unknown-elf- + +Run barebox:: + + $ <path to riscv-qemu source>/riscv32-softmmu/qemu-system-riscv32 \ + -nographic -M erizo -bios <path to barebox sources >/barebox.bin \ + -serial stdio -monitor none -trace file=/dev/null + + nmon> q + + copy loop done + restarting... + + nmon> q + Switch to console [cs0] + + + barebox 2017.08.0-00102-g212af75153 #1 Mon Sep 4 20:54:31 MSK 2017 + + + Board: generic Erizo SoC board + m25p80 m25p128@00: unrecognized JEDEC id bytes: 00, 0, 0 + m25p80 m25p128@00: probe failed: error 2 + malloc space: 0x80100000 -> 0x801fffff (size 1 MiB) + running /env/bin/init... + /env/bin/init not found + barebox:/ + + +Running RISC-V barebox on DE0-Nano FPGA board +--------------------------------------------- + +See https://github.com/open-design/riscv-soc-cores/ for instructions +on DE0-Nano bitstream generation and loading. + +Connect to board's UART with your favorite serial communication software +(e.g. minicom) and check 'nmon> ' prompt (nmon runs from onchip ROM). + +Next close your communication software and use ./scripts/nmon-loader +to load barebox image into board's DRAM, e.g. + + # ./scripts/nmon-loader barebox.erizo.nmon /dev/ttyUSB1 115200 + +Wait several munutes for 'nmon> ' prompt. + +Next, start barebox from DRAM: + + nmon> g 80000000 + +You should see one more 'nmon> ' prompt (this nmon runs from DRAM). +Exit nmon with 'q' command: +
Documentation/boards/riscv.rst line 106
Quoted 10 lines
Documentation/boards/riscv.rst new file +10
-0+ nmon> q + Switch to console [cs0] + + + barebox 2017.08.0-00102-g212af75153 #1 Mon Sep 4 20:54:31 MSK 2017 + + + Board: generic Erizo SoC board + m25p80 m25p128@00: unrecognized JEDEC id bytes: 00, 0, 0 + m25p80 m25p128@00: probe failed: error 2
hmmm... not working example?
Documentation/boards/riscv.rst line 71
Quoted 4 lines
Documentation/boards/riscv.rst new file +4
-0+ malloc space: 0x80100000 -> 0x801fffff (size 1 MiB) + running /env/bin/init... + /env/bin/init not found + barebox:/
some parts are missing in defconfig. Barebox shell can display hostname and so on ;)
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Re: [RFC v4 10/10] Documentation: add RISC-V docs
Quoted 112 lines · On Fri, 29 Sep 2017 14:35:37 +0200 Oleksij Rempel <[email protected]>…
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
Quoted 111 lines
Signed-off-by Antony Pavlov <[email protected]>--- Documentation/boards/riscv.rst | 110 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+)Documentation/boards/riscv.rst new file +100
-0@@ -0,0 +1,110 @@ +RISC-V +====== + +At the moment only qemu emulator is supported (see https://github.com/riscv/riscv-isa-sim +for details). + +Running RISC-V barebox on qemu +------------------------------ + +Obtain RISC-V GCC/Newlib Toolchain, +see https://github.com/riscv/riscv-tools/blob/master/README.md +for details. The ``build.sh`` script from ``riscv-tools`` should +create toolchain. + +Next compile qemu emulator:: + + $ git clone -b 20170824.erizo https://github.com/miet-riscv-workgroup/riscv-qemu + $ cd riscv-qemu + $ cap="no" ./configure \ + --extra-cflags="-Wno-maybe-uninitialized" \ + --audio-drv-list="" \ + --disable-attr \ + --disable-blobs \ + --disable-bluez \ + --disable-brlapi \ + --disable-curl \ + --disable-curses \ + --disable-docs \ + --disable-kvm \ + --disable-spice \ + --disable-sdl \ + --disable-vde \ + --disable-vnc-sasl \ + --disable-werror \ + --enable-trace-backend=simple \ + --disable-stack-protector \ + --target-list=riscv32-softmmu,riscv64-softmmu + $ make + + +Next compile barebox:: + + $ make erizo_generic_defconfig ARCH=riscv + ... + $ make ARCH=riscv CROSS_COMPILE=<path to your riscv toolchain>/riscv32-unknown-elf- + +Run barebox:: + + $ <path to riscv-qemu source>/riscv32-softmmu/qemu-system-riscv32 \ + -nographic -M erizo -bios <path to barebox sources >/barebox.bin \ + -serial stdio -monitor none -trace file=/dev/null + + nmon> q + + copy loop done + restarting... + + nmon> q + Switch to console [cs0] + + + barebox 2017.08.0-00102-g212af75153 #1 Mon Sep 4 20:54:31 MSK 2017 + + + Board: generic Erizo SoC board + m25p80 m25p128@00: unrecognized JEDEC id bytes: 00, 0, 0 + m25p80 m25p128@00: probe failed: error 2 + malloc space: 0x80100000 -> 0x801fffff (size 1 MiB) + running /env/bin/init... + /env/bin/init not found + barebox:/ + + +Running RISC-V barebox on DE0-Nano FPGA board +--------------------------------------------- + +See https://github.com/open-design/riscv-soc-cores/ for instructions +on DE0-Nano bitstream generation and loading. + +Connect to board's UART with your favorite serial communication software +(e.g. minicom) and check 'nmon> ' prompt (nmon runs from onchip ROM). + +Next close your communication software and use ./scripts/nmon-loader +to load barebox image into board's DRAM, e.g. + + # ./scripts/nmon-loader barebox.erizo.nmon /dev/ttyUSB1 115200 + +Wait several munutes for 'nmon> ' prompt. + +Next, start barebox from DRAM: + + nmon> g 80000000 + +You should see one more 'nmon> ' prompt (this nmon runs from DRAM). +Exit nmon with 'q' command: + + nmon> q + Switch to console [cs0] + +
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Documentation/boards/riscv.rst line 67
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Documentation/boards/riscv.rst new file +6
-0+ barebox 2017.08.0-00102-g212af75153 #1 Mon Sep 4 20:54:31 MSK 2017 + + + Board: generic Erizo SoC board + m25p80 m25p128@00: unrecognized JEDEC id bytes: 00, 0, 0 + m25p80 m25p128@00: probe failed: error 2hmmm... not working example?
At the moment I run risc-v barebox on several FPGA boards. SPI flash chip is absent on some boards.
This log was produced by SPI-flash-chip-less board.
Also SPI flash chip emulation is absent for Erizo qemu board.
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Documentation/boards/riscv.rst line 71
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Documentation/boards/riscv.rst new file +4
-0+ malloc space: 0x80100000 -> 0x801fffff (size 1 MiB) + running /env/bin/init... + /env/bin/init not found + barebox:/some parts are missing in defconfig. Barebox shell can display hostname and so on ;)
Signature · 2 lines
Regards, Oleksij
Signature · 7 lines
Best regards, Antony Pavlov _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox