drm/amdgpu: revert tile table update for oland (for v4.10 to v4.12)
Subsystems (3)
PATCH 1/1 drm/amdgpu: revert tile table update for oland (for v4.10 to v4.12)
Several users have complained that the tile table update broke Oland support. Despite several attempts to fix it, the root cause is still unknown at this point and no solution is available. As it is not acceptable to leave a known regression breaking a major functionality in the kernel for several releases, let's just reverse this optimization for now. It can be implemented again later if and only if the breakage is understood and fixed.
As there were no complaints for Hainan so far, only the Oland part of the offending commit is reverted. Optimization is preserved on Hainan, so this commit isn't an actual revert of the original.
This fixes bug #194761:
https://bugzilla.kernel.org/show_bug.cgi?id=194761
Reviewed-by Marek Olšák <[email protected]>
Signed-off-by Jean Delvare <[email protected]>
Fixes f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan")
Cc Flora Cui <[email protected]>
Cc Junwei Zhang <[email protected]>
Signed-off-by Alex Deucher <[email protected]>
---
This version of the fix is suitable for kernels v4.10 to v4.12. I know there currently is none of these tree maintained as stable or longterm, but as I did the backport for myself anyway, I'm posting it here in case anybody else needs it.
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 243 +++++++++++++++++++++++++++++++++- 1 file changed, 241 insertions(+), 2 deletions(-)
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +241 -2
@@ -701,8 +701,247 @@ static void gfx_v6_0_tiling_mode_table_i adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;WREG32 (mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); } - }else if (adev->asic_type ==CHIP_OLAND || - adev->asic_type ==CHIP_HAINAN ) { + }else if (adev->asic_type ==CHIP_OLAND ) { +for (reg_offset =0 ; reg_offset < num_tile_mode_states; reg_offset++) { +switch (reg_offset) { +case 0 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P4_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_64B ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_4 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_4 )); +break ; +case 1 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P4_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_128B ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_4 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_4 )); +break ; +case 2 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P4_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_256B ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_4 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_4 )); +break ; +case 3 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P4_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_128B ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_4 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_4 )); +break ; +case 4 : + gb_tile_moden = (ARRAY_MODE (ARRAY_1D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P4_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_64B ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +break ; +case 5 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P4_8x16) | +TILE_SPLIT (split_equal_to_row_size) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +break ; +case 6 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P4_8x16) | +TILE_SPLIT (split_equal_to_row_size) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_1 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +break ; +case 7 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P4_8x16) | +TILE_SPLIT (split_equal_to_row_size) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_4 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_4 )); +break ; +case 8 : + gb_tile_moden = (ARRAY_MODE (ARRAY_LINEAR_ALIGNED ) | +MICRO_TILE_MODE (ADDR_SURF_DISPLAY_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P4_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_64B ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +break ; +case 9 : + gb_tile_moden = (ARRAY_MODE (ARRAY_1D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_DISPLAY_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P4_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_64B ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +break ; +case 10 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_DISPLAY_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P4_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_256B ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_4 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_4 )); +break ; +case 11 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_DISPLAY_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P4_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_256B ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +break ; +case 12 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_DISPLAY_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P4_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_512B ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_1 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +break ; +case 13 : + gb_tile_moden = (ARRAY_MODE (ARRAY_1D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P4_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_64B ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +break ; +case 14 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P4_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_256B ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_4 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +break ; +case 15 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P4_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_256B ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +break ; +case 16 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P4_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_512B ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_1 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +break ; +case 17 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P4_8x16) | +TILE_SPLIT (split_equal_to_row_size) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_1 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +break ; +case 21 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P8_32x32_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_256B ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_2 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_4 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +break ; +case 22 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P8_32x32_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_256B ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_4 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_4 )); +break ; +case 23 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P8_32x32_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_256B ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +break ; +case 24 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P8_32x32_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_512B ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_1 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +break ; +case 25 : + gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +PIPE_CONFIG (ADDR_SURF_P8_32x32_8x16) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_1KB ) | +NUM_BANKS (ADDR_SURF_8_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_1 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_1 )); +break ; +default : + gb_tile_moden =0 ; +break ; + } + adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; +WREG32 (mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); + } + }else if (adev->asic_type ==CHIP_HAINAN ) {for (reg_offset =0 ; reg_offset < num_tile_mode_states; reg_offset++) {switch (reg_offset) {case 0 :
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Jean Delvare SUSE L3 Support