IGT PMU support
Subsystems (2)
v4 cover IGT PMU support
From: Tvrtko Ursulin <[email protected]>
1.
Fixes for intel-gpu-overlay to work on top of the proposed i915 PMU perf API.
2.
New test to exercise the same API.
3.
Update to gem_wsim and media-bench.pl to be able to use engine busyness via PMU for making balancing decisions.
v2:
* Added gem_wsim and media-bench.pl patches.
* Comments and fixes for the perf_pmu test.
v3:
* A bunch of review feedback implemented.
v4:
* Tests for semaphore waits and event waits.
* Review feedabck.
* RAPL PMU for intel-gpu-overlay.
Tvrtko Ursulin (7):
intel-gpu-overlay: Move local perf implementation to a library
intel-gpu-overlay: Consolidate perf PMU access to library
intel-gpu-overlay: Fix interrupts PMU readout
intel-gpu-overlay: Catch-up to new i915 PMU tests/perf_pmu: Tests for i915 PMU API
gem_wsim: Busy stats balancers
media-bench.pl: Add busy balancers to the list
benchmarks/Makefile.am | 2 +- benchmarks/gem_wsim.c | 142 +++++++ lib/Makefile.am | 6 +- lib/igt_gt.c | 50 +++ lib/igt_gt.h | 38 ++ lib/igt_perf.c | 58 +++ lib/igt_perf.h | 96 +++++ overlay/Makefile.am | 6 +- overlay/gem-interrupts.c | 25 +- overlay/gpu-freq.c | 29 +- overlay/gpu-perf.c | 3 +- overlay/gpu-top.c | 87 ++--- overlay/perf.c | 26 -- overlay/perf.h | 64 ---- overlay/power.c | 22 +- overlay/rc6.c | 41 +- scripts/media-bench.pl | 5 +- tests/Makefile.am | 1 + tests/Makefile.sources | 1 + tests/perf_pmu.c | 957 +++++++++++++++++++++++++++++++++++++++++++++++ 20 files changed, 1425 insertions(+), 234 deletions(-) create mode 100644 lib/igt_perf.c create mode 100644 lib/igt_perf.h delete mode 100644 overlay/perf.c delete mode 100644 overlay/perf.h create mode 100644 tests/perf_pmu.c
Signature · 6 lines
2.9.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 1/9 intel-gpu-overlay: Move local perf implementation to a library
From: Tvrtko Ursulin <[email protected]>
Idea is to avoid duplication across multiple users in upcoming patches.
v2: Commit message and use a separate library instead of piggy-
backing to libintel_tools. (Chris Wilson)
--- lib/Makefile.am | 6 +++++- overlay/perf.c => lib/igt_perf.c | 2 +- overlay/perf.h => lib/igt_perf.h | 2 ++ overlay/Makefile.am | 6 ++---- overlay/gem-interrupts.c | 3 ++- overlay/gpu-freq.c | 3 ++- overlay/gpu-perf.c | 3 ++- overlay/gpu-top.c | 3 ++- overlay/power.c | 3 ++- overlay/rc6.c | 3 ++- 10 files changed, 22 insertions(+), 12 deletions(-) rename overlay/perf.c => lib/igt_perf.c (94%) rename overlay/perf.h => lib/igt_perf.h (99%)
lib/Makefile.am +5 -1
@@ -7,7 +7,11 @@ include Makefile.sources libintel_tools_la_SOURCES = $(lib_source_list) -noinst_LTLIBRARIES = libintel_tools.la +libigt_perf_la_SOURCES = \ + igt_perf.c \ + igt_perf.h + +noinst_LTLIBRARIES = libintel_tools.la libigt_perf.la noinst_HEADERS = check-ndebug.h if HAVE_LIBDRM_VC4
lib/igt_perf.c renamed from overlay/perf.c +1 -1
@@ -3,7 +3,7 @@#include <unistd.h> #include <stdlib.h> -#include "perf.h" +#include "igt_perf.h" uint64_t i915_type_id (void ) {
lib/igt_perf.h renamed from overlay/perf.h +2 -0
@@ -1,6 +1,8 @@#ifndef I915_PERF_H #define I915_PERF_H +#include <stdint.h> +#include <linux/perf_event.h> #define I915_SAMPLE_BUSY 0
overlay/Makefile.am +2 -4
@@ -4,8 +4,8 @@ endif AM_CPPFLAGS = -I. AM_CFLAGS = $(DRM_CFLAGS) $(PCIACCESS_CFLAGS) $(CWARNFLAGS) \ - $(CAIRO_CFLAGS) $(OVERLAY_CFLAGS) $(WERROR_CFLAGS) -LDADD = $(DRM_LIBS) $(PCIACCESS_LIBS) $(CAIRO_LIBS) $(OVERLAY_LIBS) + $(CAIRO_CFLAGS) $(OVERLAY_CFLAGS) $(WERROR_CFLAGS) -I$(srcdir)/../lib +LDADD = $(DRM_LIBS) $(PCIACCESS_LIBS) $(CAIRO_LIBS) $(OVERLAY_LIBS) $(top_builddir)/lib/libigt_perf.la intel_gpu_overlay_SOURCES = \ chart.h \
@@ -29,8 +29,6 @@ intel_gpu_overlay_SOURCES = \ igfx.c \ overlay.h \ overlay.c \ - perf.h \ - perf.c \ power.h \ power.c \ rc6.h \
overlay/gem-interrupts.c +2 -1
@@ -31,9 +31,10 @@#include <string.h> #include <ctype.h> +#include "igt_perf.h" +#include "gem-interrupts.h" #include "debugfs.h" -#include "perf.h" static int perf_open (void ) {
overlay/gpu-freq.c +2 -1
@@ -28,9 +28,10 @@#include <string.h> #include <stdio.h> +#include "igt_perf.h" +#include "gpu-freq.h" #include "debugfs.h" -#include "perf.h" static int perf_i915_open (int config,int group) {
overlay/gpu-perf.c +2 -1
@@ -34,7 +34,8 @@#include <fcntl.h> #include <errno.h> -#include "perf.h" +#include "igt_perf.h" +#include "gpu-perf.h" #include "debugfs.h"
overlay/gpu-top.c +2 -1
@@ -31,7 +31,8 @@#include <errno.h> #include <assert.h> -#include "perf.h" +#include "igt_perf.h" +#include "igfx.h" #include "gpu-top.h"
overlay/power.c +2 -1
@@ -31,7 +31,8 @@#include <time.h> #include <errno.h> -#include "perf.h" +#include "igt_perf.h" +#include "power.h" #include "debugfs.h"
overlay/rc6.c +2 -1
@@ -31,8 +31,9 @@#include <time.h> #include <errno.h> +#include "igt_perf.h" +#include "rc6.h" -#include "perf.h" static int perf_i915_open (int config,int group) {
Signature · 6 lines
2.9.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v3 1/9 intel-gpu-overlay: Move local perf implementation to a library
From: Tvrtko Ursulin <[email protected]>
Idea is to avoid duplication across multiple users in upcoming patches.
v2: Commit message and use a separate library instead of piggy-
backing to libintel_tools. (Chris Wilson)
v3: Add Petri's meson build recipe.
--- lib/Makefile.am | 6 +++++- overlay/perf.c => lib/igt_perf.c | 2 +- overlay/perf.h => lib/igt_perf.h | 2 ++ lib/meson.build | 4 ++++ overlay/Makefile.am | 6 ++---- overlay/gem-interrupts.c | 3 ++- overlay/gpu-freq.c | 3 ++- overlay/gpu-perf.c | 3 ++- overlay/gpu-top.c | 3 ++- overlay/meson.build | 2 +- overlay/power.c | 3 ++- overlay/rc6.c | 3 ++- 12 files changed, 27 insertions(+), 13 deletions(-) rename overlay/perf.c => lib/igt_perf.c (94%) rename overlay/perf.h => lib/igt_perf.h (99%)
lib/Makefile.am +5 -1
@@ -7,7 +7,11 @@ include Makefile.sources libintel_tools_la_SOURCES = $(lib_source_list) -noinst_LTLIBRARIES = libintel_tools.la +libigt_perf_la_SOURCES = \ + igt_perf.c \ + igt_perf.h + +noinst_LTLIBRARIES = libintel_tools.la libigt_perf.la noinst_HEADERS = check-ndebug.h if HAVE_LIBDRM_VC4
lib/igt_perf.c renamed from overlay/perf.c +1 -1
@@ -3,7 +3,7 @@#include <unistd.h> #include <stdlib.h> -#include "perf.h" +#include "igt_perf.h" uint64_t i915_type_id (void ) {
lib/igt_perf.h renamed from overlay/perf.h +2 -0
@@ -1,6 +1,8 @@#ifndef I915_PERF_H #define I915_PERF_H +#include <stdint.h> +#include <linux/perf_event.h> #define I915_SAMPLE_BUSY 0
lib/meson.build +4 -0
@@ -181,4 +181,8 @@ lib_igt = declare_dependency(link_with : lib_igt_build, igt_deps = [ lib_igt ] + lib_deps +lib_igt_perf = static_library('igt_perf', + ['igt_perf.c'] +) + subdir('tests')
overlay/Makefile.am +2 -4
@@ -4,8 +4,8 @@ endif AM_CPPFLAGS = -I. AM_CFLAGS = $(DRM_CFLAGS) $(PCIACCESS_CFLAGS) $(CWARNFLAGS) \ - $(CAIRO_CFLAGS) $(OVERLAY_CFLAGS) $(WERROR_CFLAGS) -LDADD = $(DRM_LIBS) $(PCIACCESS_LIBS) $(CAIRO_LIBS) $(OVERLAY_LIBS) + $(CAIRO_CFLAGS) $(OVERLAY_CFLAGS) $(WERROR_CFLAGS) -I$(srcdir)/../lib +LDADD = $(DRM_LIBS) $(PCIACCESS_LIBS) $(CAIRO_LIBS) $(OVERLAY_LIBS) $(top_builddir)/lib/libigt_perf.la intel_gpu_overlay_SOURCES = \ chart.h \
@@ -29,8 +29,6 @@ intel_gpu_overlay_SOURCES = \ igfx.c \ overlay.h \ overlay.c \ - perf.h \ - perf.c \ power.h \ power.c \ rc6.h \
overlay/gem-interrupts.c +2 -1
@@ -31,9 +31,10 @@#include <string.h> #include <ctype.h> +#include "igt_perf.h" +#include "gem-interrupts.h" #include "debugfs.h" -#include "perf.h" static int perf_open (void ) {
overlay/gpu-freq.c +2 -1
@@ -28,9 +28,10 @@#include <string.h> #include <stdio.h> +#include "igt_perf.h" +#include "gpu-freq.h" #include "debugfs.h" -#include "perf.h" static int perf_i915_open (int config,int group) {
overlay/gpu-perf.c +2 -1
@@ -34,7 +34,8 @@#include <fcntl.h> #include <errno.h> -#include "perf.h" +#include "igt_perf.h" +#include "gpu-perf.h" #include "debugfs.h"
overlay/gpu-top.c +2 -1
@@ -31,7 +31,8 @@#include <errno.h> #include <assert.h> -#include "perf.h" +#include "igt_perf.h" +#include "igfx.h" #include "gpu-top.h"
overlay/meson.build +1 -1
@@ -10,7 +10,6 @@ gpu_overlay_src = [ 'gpu-freq.c', 'igfx.c', 'overlay.c', - 'perf.c', 'power.c', 'rc6.c', ]
@@ -56,5 +55,6 @@ if xrandr.found() and cairo.found() include_directories : inc, c_args : gpu_overlay_cflags, dependencies : gpu_overlay_deps, + link_with : lib_igt_perf, install : true) endif
overlay/power.c +2 -1
@@ -31,7 +31,8 @@#include <time.h> #include <errno.h> -#include "perf.h" +#include "igt_perf.h" +#include "power.h" #include "debugfs.h"
overlay/rc6.c +2 -1
@@ -31,8 +31,9 @@#include <time.h> #include <errno.h> +#include "igt_perf.h" +#include "rc6.h" -#include "perf.h" static int perf_i915_open (int config,int group) {
Signature · 6 lines
2.14.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 2/9 intel-gpu-overlay: Consolidate perf PMU access to library
In reply to Tvrtko UrsulinFrom: Tvrtko Ursulin <[email protected]>
Various tool modules implement their owm PMU open wrapper which can be replaced by calling the library one.
v2:
* Remove extra newline. (Chris Wilson)
* Commit msg.
--- lib/igt_perf.c | 32 ++++++++++++++++++++++++++++++++ lib/igt_perf.h | 2 ++ overlay/gem-interrupts.c | 16 +--------------- overlay/gpu-freq.c | 22 ++-------------------- overlay/gpu-top.c | 32 ++++++++------------------------ overlay/power.c | 17 +---------------- overlay/rc6.c | 24 +++--------------------- 7 files changed, 49 insertions(+), 96 deletions(-)
lib/igt_perf.c +32 -0
@@ -2,6 +2,8 @@#include <fcntl.h> #include <unistd.h> #include <stdlib.h> +#include <string.h> +#include <errno.h> #include "igt_perf.h"
@@ -24,3 +26,33 @@ uint64_t i915_type_id(void)return strtoull (buf,0 ,0 ); } +static int _perf_open (int config,int group,int format) +{ +struct perf_event_attr attr; + +memset (&attr,0 ,sizeof (attr)); + + attr.type =i915_type_id (); +if (attr.type ==0 ) +return -ENOENT ; + + attr.config = config; + +if (group >=0 ) + format &= ~PERF_FORMAT_GROUP ; + + attr.read_format = format; + +return perf_event_open (&attr,-1 ,0 , group,0 ); +} + +int perf_i915_open (int config) +{ +return _perf_open (config,-1 ,PERF_FORMAT_TOTAL_TIME_ENABLED ); +} + +int perf_i915_open_group (int config,int group) +{ +return _perf_open (config, group, +PERF_FORMAT_TOTAL_TIME_ENABLED |PERF_FORMAT_GROUP ); +}
lib/igt_perf.h +2 -0
@@ -62,5 +62,7 @@ perf_event_open(struct perf_event_attr *attr, }uint64_t i915_type_id (void ); +int perf_i915_open (int config); +int perf_i915_open_group (int config,int group);#endif /* I915_PERF_H */
overlay/gem-interrupts.c +1 -15
@@ -36,20 +36,6 @@#include "gem-interrupts.h" #include "debugfs.h" -static int perf_open (void ) -{ -struct perf_event_attr attr; - -memset (&attr,0 ,sizeof (attr)); - - attr.type =i915_type_id (); -if (attr.type ==0 ) -return -ENOENT ; - attr.config =I915_PERF_INTERRUPTS ; - -return perf_event_open (&attr,-1 ,0 ,-1 ,0 ); -} -static long long debugfs_read (void ) {char buf[8192 ], *b;
@@ -127,7 +113,7 @@ int gem_interrupts_init(struct gem_interrupts *irqs) {memset (irqs,0 ,sizeof (*irqs)); - irqs->fd =perf_open (); + irqs->fd =perf_i915_open (I915_PERF_INTERRUPTS );if (irqs->fd <0 &&interrupts_read () <0 ) irqs->error =ENODEV ;
overlay/gpu-freq.c +2 -20
@@ -33,30 +33,12 @@#include "gpu-freq.h" #include "debugfs.h" -static int perf_i915_open (int config,int group) -{ -struct perf_event_attr attr; - -memset (&attr,0 ,sizeof (attr)); - - attr.type =i915_type_id (); -if (attr.type ==0 ) -return -ENOENT ; - attr.config = config; - - attr.read_format =PERF_FORMAT_TOTAL_TIME_ENABLED ; -if (group ==-1 ) - attr.read_format |=PERF_FORMAT_GROUP ; - -return perf_event_open (&attr,-1 ,0 , group,0 ); -} -static int perf_open (void ) {int fd; - fd =perf_i915_open (I915_PERF_ACTUAL_FREQUENCY ,-1 ); -if (perf_i915_open (I915_PERF_REQUESTED_FREQUENCY , fd) <0 ) { + fd =perf_i915_open_group (I915_PERF_ACTUAL_FREQUENCY ,-1 ); +if (perf_i915_open_group (I915_PERF_REQUESTED_FREQUENCY , fd) <0 ) {close (fd); fd =-1 ; }
overlay/gpu-top.c +8 -24
@@ -48,24 +48,6 @@#define I915_PERF_RING_WAIT (n) (__I915_PERF_RING(n) + 1)#define I915_PERF_RING_SEMA (n) (__I915_PERF_RING(n) + 2) -static int perf_i915_open (int config,int group) -{ -struct perf_event_attr attr; - -memset (&attr,0 ,sizeof (attr)); - - attr.type =i915_type_id (); -if (attr.type ==0 ) -return -ENOENT ; - attr.config = config; - - attr.read_format =PERF_FORMAT_TOTAL_TIME_ENABLED ; -if (group ==-1 ) - attr.read_format |=PERF_FORMAT_GROUP ; - -return perf_event_open (&attr,-1 ,0 , group,0 ); -} -static int perf_init (struct gpu_top *gt) {const char *names[] = {
@@ -77,27 +59,29 @@ static int perf_init(struct gpu_top *gt) };int n; - gt->fd =perf_i915_open (I915_PERF_RING_BUSY (0 ),-1 ); + gt->fd =perf_i915_open_group (I915_PERF_RING_BUSY (0 ),-1 );if (gt->fd <0 )return -1 ; -if (perf_i915_open (I915_PERF_RING_WAIT (0 ), gt->fd) >=0 ) +if (perf_i915_open_group (I915_PERF_RING_WAIT (0 ), gt->fd) >=0 ) gt->have_wait =1 ; -if (perf_i915_open (I915_PERF_RING_SEMA (0 ), gt->fd) >=0 ) +if (perf_i915_open_group (I915_PERF_RING_SEMA (0 ), gt->fd) >=0 ) gt->have_sema =1 ; gt->ring[0 ].name = names[0 ]; gt->num_rings =1 ;for (n =1 ; names[n]; n++) { -if (perf_i915_open (I915_PERF_RING_BUSY (n), gt->fd) >=0 ) { +if (perf_i915_open_group (I915_PERF_RING_BUSY (n), gt->fd) >=0 ) {if (gt->have_wait && -perf_i915_open (I915_PERF_RING_WAIT (n), gt->fd) <0 ) +perf_i915_open_group (I915_PERF_RING_WAIT (n), + gt->fd) <0 )return -1 ;if (gt->have_sema && -perf_i915_open (I915_PERF_RING_SEMA (n), gt->fd) <0 ) +perf_i915_open_group (I915_PERF_RING_SEMA (n), + gt->fd) <0 )return -1 ; gt->ring[gt->num_rings++].name = names[n];
overlay/power.c +1 -16
@@ -38,21 +38,6 @@/* XXX Is this exposed through RAPL? */ -static int perf_open (void ) -{ -struct perf_event_attr attr; - -memset (&attr,0 ,sizeof (attr)); - - attr.type =i915_type_id (); -if (attr.type ==0 ) -return -1 ; - attr.config =I915_PERF_ENERGY ; - - attr.read_format =PERF_FORMAT_TOTAL_TIME_ENABLED ; -return perf_event_open (&attr,-1 ,0 ,-1 ,0 ); -} -int power_init (struct power *power) {char buf[4096 ];
@@ -60,7 +45,7 @@ int power_init(struct power *power)memset (power,0 ,sizeof (*power)); - power->fd =perf_open (); + power->fd =perf_i915_open (I915_PERF_ENERGY );if (power->fd !=-1 )return 0 ;
overlay/rc6.c +3 -21
@@ -35,24 +35,6 @@#include "rc6.h" -static int perf_i915_open (int config,int group) -{ -struct perf_event_attr attr; - -memset (&attr,0 ,sizeof (attr)); - - attr.type =i915_type_id (); -if (attr.type ==0 ) -return -ENOENT ; - attr.config = config; - - attr.read_format =PERF_FORMAT_TOTAL_TIME_ENABLED ; -if (group ==-1 ) - attr.read_format |=PERF_FORMAT_GROUP ; - -return perf_event_open (&attr,-1 ,0 , group,0 ); -} -#define RC6 (1<<0)#define RC6p (1<<1)#define RC6pp (1<<2)
@@ -61,15 +43,15 @@ static int perf_open(unsigned *flags) {int fd; - fd =perf_i915_open (I915_PERF_RC6_RESIDENCY ,-1 ); + fd =perf_i915_open_group (I915_PERF_RC6_RESIDENCY ,-1 );if (fd <0 )return -1 ; *flags |=RC6 ; -if (perf_i915_open (I915_PERF_RC6p_RESIDENCY, fd) >=0 ) +if (perf_i915_open_group (I915_PERF_RC6p_RESIDENCY, fd) >=0 ) *flags |= RC6p; -if (perf_i915_open (I915_PERF_RC6pp_RESIDENCY, fd) >=0 ) +if (perf_i915_open_group (I915_PERF_RC6pp_RESIDENCY, fd) >=0 ) *flags |= RC6pp;return fd;
Signature · 6 lines
2.9.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH i-g-t 2/9] intel-gpu-overlay: Consolidate perf PMU access to library
Quoting Tvrtko Ursulin (2017-10-10 10:30:01)
Quoted 10 lines
From: Tvrtko Ursulin <[email protected]>
Various tool modules implement their owm PMU open wrapper which can be replaced by calling the library one.
v2:
* Remove extra newline. (Chris Wilson)
* Commit msg.Signed-off-by Tvrtko Ursulin <[email protected]>
-Chris
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 3/9 lib/perf: Fix data types and general tidy
In reply to Tvrtko UrsulinFrom: Tvrtko Ursulin <[email protected]>
Configuration and format are uint64_t in the perf API.
Tidy some other details as well.
--- lib/igt_perf.c | 40 +++++++++++++++++++--------------------- lib/igt_perf.h | 4 ++-- 2 files changed, 21 insertions(+), 23 deletions(-)
lib/igt_perf.c +19 -21
@@ -9,49 +9,47 @@uint64_t i915_type_id (void ) { -char buf[1024 ]; -int fd, n; - - fd =open ("/sys/bus/event_source/devices/i915/type" ,0 ); -if (fd <0 ) { - n =-1 ; - }else { - n =read (fd, buf,sizeof (buf)-1 ); -close (fd); - } -if (n <0 ) +char buf[64 ]; +ssize_t ret; +int fd; + + fd =open ("/sys/bus/event_source/devices/i915/type" ,O_RDONLY ); +if (fd <0 ) +return 0 ; + + ret =read (fd, buf,sizeof (buf) -1 ); +close (fd); +if (ret <1 )return 0 ; - buf[n] ='\0' ; -return strtoull (buf,0 ,0 ); + buf[ret] ='\0' ; + +return strtoull (buf,NULL ,0 ); } -static int _perf_open (int config,int group,int format) +static int _perf_open (uint64_t config,int group,uint64_t format) { -struct perf_event_attr attr; - -memset (&attr,0 ,sizeof (attr)); +struct perf_event_attr attr = { }; attr.type =i915_type_id ();if (attr.type ==0 )return -ENOENT ; - attr.config = config; -if (group >=0 ) format &= ~PERF_FORMAT_GROUP ; attr.read_format = format; + attr.config = config;return perf_event_open (&attr,-1 ,0 , group,0 ); } -int perf_i915_open (int config) +int perf_i915_open (uint64_t config) {return _perf_open (config,-1 ,PERF_FORMAT_TOTAL_TIME_ENABLED ); } -int perf_i915_open_group (int config,int group) +int perf_i915_open_group (uint64_t config,int group) {return _perf_open (config, group,PERF_FORMAT_TOTAL_TIME_ENABLED |PERF_FORMAT_GROUP );
lib/igt_perf.h +2 -2
@@ -62,7 +62,7 @@ perf_event_open(struct perf_event_attr *attr, }uint64_t i915_type_id (void ); -int perf_i915_open (int config); -int perf_i915_open_group (int config,int group); +int perf_i915_open (uint64_t config); +int perf_i915_open_group (uint64_t config,int group);#endif /* I915_PERF_H */
Signature · 6 lines
2.9.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH i-g-t 3/9] lib/perf: Fix data types and general tidy
Quoting Tvrtko Ursulin (2017-10-10 10:30:02)
Quoted 3 lines
From: Tvrtko Ursulin <[email protected]>
Configuration and format are
uint64_tin the perf API.
Planning for a busy few years? ;)
Quoted 3 lines
Tidy some other details as well.
Signed-off-by Tvrtko Ursulin <[email protected]>
-Chris
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 4/9 intel-gpu-overlay: Fix interrupts PMU readout
In reply to Tvrtko UrsulinFrom: Tvrtko Ursulin <[email protected]>
--- overlay/gem-interrupts.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
overlay/gem-interrupts.c +5 -1
@@ -136,8 +136,12 @@ int gem_interrupts_update(struct gem_interrupts *irqs)else val = ret; }else { -if (read (irqs->fd, &val,sizeof (val)) <0 ) +uint64_t data[2 ]; + +if (read (irqs->fd, &data,sizeof (data)) <0 )return irqs->error = errno; + + val = data[0 ]; } update = irqs->last_count ==0 ;
Signature · 6 lines
2.9.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH i-g-t 4/9] intel-gpu-overlay: Fix interrupts PMU readout
Quoting Tvrtko Ursulin (2017-10-10 10:30:03)
Quoted 12 lines
From: Tvrtko Ursulin <[email protected]>
Signed-off-by Tvrtko Ursulin <[email protected]>--- overlay/gem-interrupts.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)overlay/gem-interrupts.c +0
-0
overlay/gem-interrupts.c int gem_interrupts_update(struct gem_interrupts *irqs) · line 141
Quoted 7 lines
overlay/gem-interrupts.c +3
-1@@ -136,8 +136,12 @@ int gem_interrupts_update(struct gem_interrupts *irqs)else val = ret; }else { -if (read (irqs->fd, &val,sizeof (val)) <0 ) +uint64_t data[2 ]; + +if (read (irqs->fd, &data,sizeof (data)) <0 )
s/&data/data/
-Chris
_______________________________________________
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[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v2 4/9 intel-gpu-overlay: Fix interrupts PMU readout
From: Tvrtko Ursulin <[email protected]>
v2: Use correct address of. (Chris Wilson)
--- overlay/gem-interrupts.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
overlay/gem-interrupts.c +5 -1
@@ -136,8 +136,12 @@ int gem_interrupts_update(struct gem_interrupts *irqs)else val = ret; }else { -if (read (irqs->fd, &val,sizeof (val)) <0 ) +uint64_t data[2 ]; + +if (read (irqs->fd, data,sizeof (data)) <0 )return irqs->error = errno; + + val = data[0 ]; } update = irqs->last_count ==0 ;
Signature · 6 lines
2.9.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 5/9 intel-gpu-overlay: Catch-up to new i915 PMU
In reply to Tvrtko UrsulinFrom: Tvrtko Ursulin <[email protected]>
v2: Update for i915 changes.
v3: Use 1eN for large numbers. (Chris Wilson)
--- lib/igt_perf.h | 89 +++++++++++++++++++++++++++++++++--------------- overlay/gem-interrupts.c | 2 +- overlay/gpu-freq.c | 8 ++--- overlay/gpu-top.c | 68 ++++++++++++++++++++---------------- overlay/power.c | 4 +-- overlay/rc6.c | 20 +++++------ 6 files changed, 116 insertions(+), 75 deletions(-)
lib/igt_perf.h +62 -27
@@ -1,3 +1,27 @@ +/* +* Copyright © 2017 Intel Corporation +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice (including the next +* paragraph) shall be included in all copies or substantial portions of the +* Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +* IN THE SOFTWARE. +* +*/ +#ifndef I915_PERF_H #define I915_PERF_H
@@ -5,41 +29,52 @@#include <linux/perf_event.h> -#define I915_SAMPLE_BUSY 0 -#define I915_SAMPLE_WAIT 1 -#define I915_SAMPLE_SEMA 2 +enum drm_i915_gem_engine_class { +I915_ENGINE_CLASS_OTHER =0 , +I915_ENGINE_CLASS_RENDER =1 , +I915_ENGINE_CLASS_COPY =2 , +I915_ENGINE_CLASS_VIDEO =3 , +I915_ENGINE_CLASS_VIDEO_ENHANCE =4 , +I915_ENGINE_CLASS_MAX /* non-ABI */ +}; + +enum drm_i915_pmu_engine_sample { +I915_SAMPLE_BUSY =0 , +I915_SAMPLE_WAIT =1 , +I915_SAMPLE_SEMA =2 , +I915_ENGINE_SAMPLE_MAX /* non-ABI */ +}; -#define I915_SAMPLE_RCS 0 -#define I915_SAMPLE_VCS 1 -#define I915_SAMPLE_BCS 2 -#define I915_SAMPLE_VECS 3 +#define I915_PMU_SAMPLE_BITS (4) +#define I915_PMU_SAMPLE_MASK (0xf) +#define I915_PMU_SAMPLE_INSTANCE_BITS (8) +#define I915_PMU_CLASS_SHIFT \ + (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) -#define __I915_PERF_COUNT (ring, id) ((ring) << 4 | (id)) +#define __I915_PMU_ENGINE (class, instance, sample) \ + ((class) << I915_PMU_CLASS_SHIFT | \ + (instance) << I915_PMU_SAMPLE_BITS | \ + (sample)) -#define I915_PERF_COUNT_RCS_BUSY __I915_PERF_COUNT(I915_SAMPLE_RCS, I915_SAMPLE_BUSY) -#define I915_PERF_COUNT_RCS_WAIT __I915_PERF_COUNT(I915_SAMPLE_RCS, I915_SAMPLE_WAIT) -#define I915_PERF_COUNT_RCS_SEMA __I915_PERF_COUNT(I915_SAMPLE_RCS, I915_SAMPLE_SEMA) +#define I915_PMU_ENGINE_BUSY (class, instance) \ + __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) -#define I915_PERF_COUNT_VCS_BUSY __I915_PERF_COUNT(I915_SAMPLE_VCS, I915_SAMPLE_BUSY) -#define I915_PERF_COUNT_VCS_WAIT __I915_PERF_COUNT(I915_SAMPLE_VCS, I915_SAMPLE_WAIT) -#define I915_PERF_COUNT_VCS_SEMA __I915_PERF_COUNT(I915_SAMPLE_VCS, I915_SAMPLE_SEMA) +#define I915_PMU_ENGINE_WAIT (class, instance) \ + __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) -#define I915_PERF_COUNT_BCS_BUSY __I915_PERF_COUNT(I915_SAMPLE_BCS, I915_SAMPLE_BUSY) -#define I915_PERF_COUNT_BCS_WAIT __I915_PERF_COUNT(I915_SAMPLE_BCS, I915_SAMPLE_WAIT) -#define I915_PERF_COUNT_BCS_SEMA __I915_PERF_COUNT(I915_SAMPLE_BCS, I915_SAMPLE_SEMA) +#define I915_PMU_ENGINE_SEMA (class, instance) \ + __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) -#define I915_PERF_COUNT_VECS_BUSY __I915_PERF_COUNT(I915_SAMPLE_VECS, I915_SAMPLE_BUSY) -#define I915_PERF_COUNT_VECS_WAIT __I915_PERF_COUNT(I915_SAMPLE_VECS, I915_SAMPLE_WAIT) -#define I915_PERF_COUNT_VECS_SEMA __I915_PERF_COUNT(I915_SAMPLE_VECS, I915_SAMPLE_SEMA) +#define __I915_PMU_OTHER (x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) -#define I915_PERF_ACTUAL_FREQUENCY 32 -#define I915_PERF_REQUESTED_FREQUENCY 33 -#define I915_PERF_ENERGY 34 -#define I915_PERF_INTERRUPTS 35 +#define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) +#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) +#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) +#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) +#define I915_PMU_RC6p_RESIDENCY __I915_PMU_OTHER(4) +#define I915_PMU_RC6pp_RESIDENCY __I915_PMU_OTHER(5) -#define I915_PERF_RC6_RESIDENCY 40 -#define I915_PERF_RC6p_RESIDENCY 41 -#define I915_PERF_RC6pp_RESIDENCY 42 +#define I915_PMU_LAST I915_PMU_RC6pp_RESIDENCY static inline int perf_event_open(struct perf_event_attr *attr,
overlay/gem-interrupts.c +1 -1
@@ -113,7 +113,7 @@ int gem_interrupts_init(struct gem_interrupts *irqs) {memset (irqs,0 ,sizeof (*irqs)); - irqs->fd =perf_i915_open (I915_PERF_INTERRUPTS ); + irqs->fd =perf_i915_open (I915_PMU_INTERRUPTS );if (irqs->fd <0 &&interrupts_read () <0 ) irqs->error =ENODEV ;
overlay/gpu-freq.c +4 -4
@@ -37,8 +37,8 @@ static int perf_open(void) {int fd; - fd =perf_i915_open_group (I915_PERF_ACTUAL_FREQUENCY ,-1 ); -if (perf_i915_open_group (I915_PERF_REQUESTED_FREQUENCY , fd) <0 ) { + fd =perf_i915_open_group (I915_PMU_ACTUAL_FREQUENCY ,-1 ); +if (perf_i915_open_group (I915_PMU_REQUESTED_FREQUENCY , fd) <0 ) {close (fd); fd =-1 ; }
@@ -176,8 +176,8 @@ int gpu_freq_update(struct gpu_freq *gf)return EAGAIN ; } - gf->current = (s->act - d->act) / d_time; - gf->request = (s->req - d->req) / d_time; + gf->current = (s->act - d->act) *1e9 / d_time; + gf->request = (s->req - d->req) *1e9 / d_time; }return 0 ;
overlay/gpu-top.c +38 -30
87 lines not on this page · raw message
overlay/power.c +1 -3
@@ -45,9 +45,7 @@ int power_init(struct power *power)memset (power,0 ,sizeof (*power)); - power->fd =perf_i915_open (I915_PERF_ENERGY ); -if (power->fd !=-1 ) -return 0 ; + power->fd =-1 ;sprintf (buf,"%s/i915_energy_uJ" , debugfs_dri_path); fd =open (buf,0 );
overlay/rc6.c +10 -10
@@ -43,15 +43,15 @@ static int perf_open(unsigned *flags) {int fd; - fd =perf_i915_open_group (I915_PERF_RC6_RESIDENCY ,-1 ); + fd =perf_i915_open_group (I915_PMU_RC6_RESIDENCY ,-1 );if (fd <0 )return -1 ; *flags |=RC6 ; -if (perf_i915_open_group (I915_PERF_RC6p_RESIDENCY, fd) >=0 ) +if (perf_i915_open_group (I915_PMU_RC6p_RESIDENCY, fd) >=0 ) *flags |= RC6p; -if (perf_i915_open_group (I915_PERF_RC6pp_RESIDENCY, fd) >=0 ) +if (perf_i915_open_group (I915_PMU_RC6pp_RESIDENCY, fd) >=0 ) *flags |= RC6pp;return fd;
@@ -132,11 +132,11 @@ int rc6_update(struct rc6 *rc6) len =2 ;if (rc6->flags &RC6 ) - s->rc6_residency = data[len++]; + s->rc6_residency = data[len++] /1e6 ;if (rc6->flags & RC6p) - s->rc6p_residency = data[len++]; + s->rc6p_residency = data[len++] /1e6 ;if (rc6->flags & RC6pp) - s->rc6pp_residency = data[len++]; + s->rc6pp_residency = data[len++] /1e6 ; }if (rc6->count ==1 )
@@ -149,14 +149,14 @@ int rc6_update(struct rc6 *rc6) } d_rc6 = s->rc6_residency - d->rc6_residency; - rc6->rc6 = (100 * d_rc6 + d_time/2 ) / d_time; + rc6->rc6 =100 * d_rc6 / d_time; d_rc6p = s->rc6p_residency - d->rc6p_residency; - rc6->rc6p = (100 * d_rc6p + d_time/2 ) / d_time; + rc6->rc6p =100 * d_rc6p / d_time; d_rc6pp = s->rc6pp_residency - d->rc6pp_residency; - rc6->rc6pp = (100 * d_rc6pp + d_time/2 ) / d_time; + rc6->rc6pp =100 * d_rc6pp / d_time; - rc6->rc6_combined = (100 * (d_rc6 + d_rc6p + d_rc6pp) + d_time/2 ) / d_time; + rc6->rc6_combined =100 * (d_rc6 + d_rc6p + d_rc6pp) / d_time;return 0 ; }
Signature · 6 lines
2.9.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 5/9 intel-gpu-overlay: Catch-up to new i915 PMU
From: Tvrtko Ursulin <[email protected]>
v2: Update for i915 changes.
v3: Use 1eN for large numbers. (Chris Wilson)
v4: Update for upstream engine class enum.
--- lib/igt_perf.h | 89 +++++++++++++++++++++++++++++++++--------------- overlay/gem-interrupts.c | 2 +- overlay/gpu-freq.c | 8 ++--- overlay/gpu-top.c | 68 ++++++++++++++++++++---------------- overlay/power.c | 4 +-- overlay/rc6.c | 20 +++++------ 6 files changed, 116 insertions(+), 75 deletions(-)
lib/igt_perf.h +62 -27
@@ -1,3 +1,27 @@ +/* +* Copyright © 2017 Intel Corporation +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice (including the next +* paragraph) shall be included in all copies or substantial portions of the +* Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +* IN THE SOFTWARE. +* +*/ +#ifndef I915_PERF_H #define I915_PERF_H
@@ -5,41 +29,52 @@#include <linux/perf_event.h> -#define I915_SAMPLE_BUSY 0 -#define I915_SAMPLE_WAIT 1 -#define I915_SAMPLE_SEMA 2 +enum drm_i915_gem_engine_class { +I915_ENGINE_CLASS_RENDER =0 , +I915_ENGINE_CLASS_COPY =1 , +I915_ENGINE_CLASS_VIDEO =2 , +I915_ENGINE_CLASS_VIDEO_ENHANCE =3 , + +I915_ENGINE_CLASS_INVALID =-1 +}; + +enum drm_i915_pmu_engine_sample { +I915_SAMPLE_BUSY =0 , +I915_SAMPLE_WAIT =1 , +I915_SAMPLE_SEMA =2 , +I915_ENGINE_SAMPLE_MAX /* non-ABI */ +}; -#define I915_SAMPLE_RCS 0 -#define I915_SAMPLE_VCS 1 -#define I915_SAMPLE_BCS 2 -#define I915_SAMPLE_VECS 3 +#define I915_PMU_SAMPLE_BITS (4) +#define I915_PMU_SAMPLE_MASK (0xf) +#define I915_PMU_SAMPLE_INSTANCE_BITS (8) +#define I915_PMU_CLASS_SHIFT \ + (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) -#define __I915_PERF_COUNT (ring, id) ((ring) << 4 | (id)) +#define __I915_PMU_ENGINE (class, instance, sample) \ + ((class) << I915_PMU_CLASS_SHIFT | \ + (instance) << I915_PMU_SAMPLE_BITS | \ + (sample)) -#define I915_PERF_COUNT_RCS_BUSY __I915_PERF_COUNT(I915_SAMPLE_RCS, I915_SAMPLE_BUSY) -#define I915_PERF_COUNT_RCS_WAIT __I915_PERF_COUNT(I915_SAMPLE_RCS, I915_SAMPLE_WAIT) -#define I915_PERF_COUNT_RCS_SEMA __I915_PERF_COUNT(I915_SAMPLE_RCS, I915_SAMPLE_SEMA) +#define I915_PMU_ENGINE_BUSY (class, instance) \ + __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) -#define I915_PERF_COUNT_VCS_BUSY __I915_PERF_COUNT(I915_SAMPLE_VCS, I915_SAMPLE_BUSY) -#define I915_PERF_COUNT_VCS_WAIT __I915_PERF_COUNT(I915_SAMPLE_VCS, I915_SAMPLE_WAIT) -#define I915_PERF_COUNT_VCS_SEMA __I915_PERF_COUNT(I915_SAMPLE_VCS, I915_SAMPLE_SEMA) +#define I915_PMU_ENGINE_WAIT (class, instance) \ + __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) -#define I915_PERF_COUNT_BCS_BUSY __I915_PERF_COUNT(I915_SAMPLE_BCS, I915_SAMPLE_BUSY) -#define I915_PERF_COUNT_BCS_WAIT __I915_PERF_COUNT(I915_SAMPLE_BCS, I915_SAMPLE_WAIT) -#define I915_PERF_COUNT_BCS_SEMA __I915_PERF_COUNT(I915_SAMPLE_BCS, I915_SAMPLE_SEMA) +#define I915_PMU_ENGINE_SEMA (class, instance) \ + __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) -#define I915_PERF_COUNT_VECS_BUSY __I915_PERF_COUNT(I915_SAMPLE_VECS, I915_SAMPLE_BUSY) -#define I915_PERF_COUNT_VECS_WAIT __I915_PERF_COUNT(I915_SAMPLE_VECS, I915_SAMPLE_WAIT) -#define I915_PERF_COUNT_VECS_SEMA __I915_PERF_COUNT(I915_SAMPLE_VECS, I915_SAMPLE_SEMA) +#define __I915_PMU_OTHER (x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) -#define I915_PERF_ACTUAL_FREQUENCY 32 -#define I915_PERF_REQUESTED_FREQUENCY 33 -#define I915_PERF_ENERGY 34 -#define I915_PERF_INTERRUPTS 35 +#define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) +#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) +#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) +#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) +#define I915_PMU_RC6p_RESIDENCY __I915_PMU_OTHER(4) +#define I915_PMU_RC6pp_RESIDENCY __I915_PMU_OTHER(5) -#define I915_PERF_RC6_RESIDENCY 40 -#define I915_PERF_RC6p_RESIDENCY 41 -#define I915_PERF_RC6pp_RESIDENCY 42 +#define I915_PMU_LAST I915_PMU_RC6pp_RESIDENCY static inline int perf_event_open(struct perf_event_attr *attr,
overlay/gem-interrupts.c +1 -1
@@ -113,7 +113,7 @@ int gem_interrupts_init(struct gem_interrupts *irqs) {memset (irqs,0 ,sizeof (*irqs)); - irqs->fd =perf_i915_open (I915_PERF_INTERRUPTS ); + irqs->fd =perf_i915_open (I915_PMU_INTERRUPTS );if (irqs->fd <0 &&interrupts_read () <0 ) irqs->error =ENODEV ;
overlay/gpu-freq.c +4 -4
@@ -37,8 +37,8 @@ static int perf_open(void) {int fd; - fd =perf_i915_open_group (I915_PERF_ACTUAL_FREQUENCY ,-1 ); -if (perf_i915_open_group (I915_PERF_REQUESTED_FREQUENCY , fd) <0 ) { + fd =perf_i915_open_group (I915_PMU_ACTUAL_FREQUENCY ,-1 ); +if (perf_i915_open_group (I915_PMU_REQUESTED_FREQUENCY , fd) <0 ) {close (fd); fd =-1 ; }
@@ -176,8 +176,8 @@ int gpu_freq_update(struct gpu_freq *gf)return EAGAIN ; } - gf->current = (s->act - d->act) / d_time; - gf->request = (s->req - d->req) / d_time; + gf->current = (s->act - d->act) *1e9 / d_time; + gf->request = (s->req - d->req) *1e9 / d_time; }return 0 ;
overlay/gpu-top.c +38 -30
87 lines not on this page · raw message
overlay/power.c +1 -3
@@ -45,9 +45,7 @@ int power_init(struct power *power)memset (power,0 ,sizeof (*power)); - power->fd =perf_i915_open (I915_PERF_ENERGY ); -if (power->fd !=-1 ) -return 0 ; + power->fd =-1 ;sprintf (buf,"%s/i915_energy_uJ" , debugfs_dri_path); fd =open (buf,0 );
overlay/rc6.c +10 -10
@@ -43,15 +43,15 @@ static int perf_open(unsigned *flags) {int fd; - fd =perf_i915_open_group (I915_PERF_RC6_RESIDENCY ,-1 ); + fd =perf_i915_open_group (I915_PMU_RC6_RESIDENCY ,-1 );if (fd <0 )return -1 ; *flags |=RC6 ; -if (perf_i915_open_group (I915_PERF_RC6p_RESIDENCY, fd) >=0 ) +if (perf_i915_open_group (I915_PMU_RC6p_RESIDENCY, fd) >=0 ) *flags |= RC6p; -if (perf_i915_open_group (I915_PERF_RC6pp_RESIDENCY, fd) >=0 ) +if (perf_i915_open_group (I915_PMU_RC6pp_RESIDENCY, fd) >=0 ) *flags |= RC6pp;return fd;
@@ -132,11 +132,11 @@ int rc6_update(struct rc6 *rc6) len =2 ;if (rc6->flags &RC6 ) - s->rc6_residency = data[len++]; + s->rc6_residency = data[len++] /1e6 ;if (rc6->flags & RC6p) - s->rc6p_residency = data[len++]; + s->rc6p_residency = data[len++] /1e6 ;if (rc6->flags & RC6pp) - s->rc6pp_residency = data[len++]; + s->rc6pp_residency = data[len++] /1e6 ; }if (rc6->count ==1 )
@@ -149,14 +149,14 @@ int rc6_update(struct rc6 *rc6) } d_rc6 = s->rc6_residency - d->rc6_residency; - rc6->rc6 = (100 * d_rc6 + d_time/2 ) / d_time; + rc6->rc6 =100 * d_rc6 / d_time; d_rc6p = s->rc6p_residency - d->rc6p_residency; - rc6->rc6p = (100 * d_rc6p + d_time/2 ) / d_time; + rc6->rc6p =100 * d_rc6p / d_time; d_rc6pp = s->rc6pp_residency - d->rc6pp_residency; - rc6->rc6pp = (100 * d_rc6pp + d_time/2 ) / d_time; + rc6->rc6pp =100 * d_rc6pp / d_time; - rc6->rc6_combined = (100 * (d_rc6 + d_rc6p + d_rc6pp) + d_time/2 ) / d_time; + rc6->rc6_combined =100 * (d_rc6 + d_rc6p + d_rc6pp) / d_time;return 0 ; }
Signature · 6 lines
2.14.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 6/9 intel-gpu-overlay: Use RAPL PMU for power reading
In reply to Tvrtko UrsulinFrom: Tvrtko Ursulin <[email protected]>
Wire up to the RAPL PMU for GPU energy readings.
The only complication is that we have to add code to parse:
# cat /sys/devices/power/events/energy-gpu.scale 2.3283064365386962890625e-10
--- lib/igt_perf.c | 16 ++++-- lib/igt_perf.h | 1 + overlay/power.c | 156 ++++++++++++++++++++++++++++++++++++++++++-------------- overlay/power.h | 2 + 4 files changed, 133 insertions(+), 42 deletions(-)
lib/igt_perf.c +12 -4
@@ -27,11 +27,12 @@ uint64_t i915_type_id(void)return strtoull (buf,NULL ,0 ); } -static int _perf_open (uint64_t config,int group,uint64_t format) +static int +_perf_open (uint64_t type,uint64_t config,int group,uint64_t format) {struct perf_event_attr attr = { }; - attr.type =i915_type_id (); + attr.type = type;if (attr.type ==0 )return -ENOENT ;
@@ -46,11 +47,18 @@ static int _perf_open(uint64_t config, int group, uint64_t format)int perf_i915_open (uint64_t config) { -return _perf_open (config,-1 ,PERF_FORMAT_TOTAL_TIME_ENABLED ); +return _perf_open (i915_type_id (), config,-1 , +PERF_FORMAT_TOTAL_TIME_ENABLED ); }int perf_i915_open_group (uint64_t config,int group) { -return _perf_open (config, group, +return _perf_open (i915_type_id (), config, group,PERF_FORMAT_TOTAL_TIME_ENABLED |PERF_FORMAT_GROUP ); } + +int igt_perf_open (uint64_t type,uint64_t config) +{ +return _perf_open (type, config,-1 , +PERF_FORMAT_TOTAL_TIME_ENABLED ); +}
lib/igt_perf.h +1 -0
@@ -99,5 +99,6 @@ perf_event_open(struct perf_event_attr *attr,uint64_t i915_type_id (void );int perf_i915_open (uint64_t config);int perf_i915_open_group (uint64_t config,int group); +int igt_perf_open (uint64_t type,uint64_t config);#endif /* I915_PERF_H */
overlay/power.c +118 -38
215 lines not on this page · raw message
overlay/power.h +2 -0
@@ -39,6 +39,8 @@ struct power {int new_sample;uint64_t power_mW; + +double rapl_scale; };int power_init (struct power *power);
Signature · 6 lines
2.9.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v2 6/9 intel-gpu-overlay: Use RAPL PMU for power reading
From: Tvrtko Ursulin <[email protected]>
Wire up to the RAPL PMU for GPU energy readings.
The only complication is that we have to add code to parse:
# cat /sys/devices/power/events/energy-gpu.scale 2.3283064365386962890625e-10
v2: Link with -lm.
--- lib/igt_perf.c | 16 ++++-- lib/igt_perf.h | 1 + overlay/Makefile.am | 2 +- overlay/power.c | 156 +++++++++++++++++++++++++++++++++++++++------------- overlay/power.h | 2 + 5 files changed, 134 insertions(+), 43 deletions(-)
lib/igt_perf.c +12 -4
@@ -27,11 +27,12 @@ uint64_t i915_type_id(void)return strtoull (buf,NULL ,0 ); } -static int _perf_open (uint64_t config,int group,uint64_t format) +static int +_perf_open (uint64_t type,uint64_t config,int group,uint64_t format) {struct perf_event_attr attr = { }; - attr.type =i915_type_id (); + attr.type = type;if (attr.type ==0 )return -ENOENT ;
@@ -46,11 +47,18 @@ static int _perf_open(uint64_t config, int group, uint64_t format)int perf_i915_open (uint64_t config) { -return _perf_open (config,-1 ,PERF_FORMAT_TOTAL_TIME_ENABLED ); +return _perf_open (i915_type_id (), config,-1 , +PERF_FORMAT_TOTAL_TIME_ENABLED ); }int perf_i915_open_group (uint64_t config,int group) { -return _perf_open (config, group, +return _perf_open (i915_type_id (), config, group,PERF_FORMAT_TOTAL_TIME_ENABLED |PERF_FORMAT_GROUP ); } + +int igt_perf_open (uint64_t type,uint64_t config) +{ +return _perf_open (type, config,-1 , +PERF_FORMAT_TOTAL_TIME_ENABLED ); +}
lib/igt_perf.h +1 -0
@@ -99,5 +99,6 @@ perf_event_open(struct perf_event_attr *attr,uint64_t i915_type_id (void );int perf_i915_open (uint64_t config);int perf_i915_open_group (uint64_t config,int group); +int igt_perf_open (uint64_t type,uint64_t config);#endif /* I915_PERF_H */
overlay/Makefile.am +1 -1
@@ -63,7 +63,7 @@ intel_gpu_overlay_SOURCES += \ intel_gpu_overlay_SOURCES += $(both_x11_sources) -intel_gpu_overlay_LDADD = $(LDADD) -lrt +intel_gpu_overlay_LDADD = $(LDADD) -lrt -lm EXTRA_DIST= \ README \
overlay/power.c +118 -38
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overlay/power.h +2 -0
@@ -39,6 +39,8 @@ struct power {int new_sample;uint64_t power_mW; + +double rapl_scale; };int power_init (struct power *power);
Signature · 6 lines
2.9.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v3 6/9 intel-gpu-overlay: Use RAPL PMU for power reading
From: Tvrtko Ursulin <[email protected]>
Wire up to the RAPL PMU for GPU energy readings.
The only complication is that we have to add code to parse:
# cat /sys/devices/power/events/energy-gpu.scale 2.3283064365386962890625e-10
v2: Link with -lm.
v3: strtod can handle scientific notation, even though my initial
reading of the man page did not spot that. (Chris Wilson)
--- lib/igt_perf.c | 16 +++++-- lib/igt_perf.h | 1 + overlay/Makefile.am | 2 +- overlay/power.c | 127 ++++++++++++++++++++++++++++++++++++---------------- overlay/power.h | 2 + 5 files changed, 104 insertions(+), 44 deletions(-)
lib/igt_perf.c +12 -4
@@ -27,11 +27,12 @@ uint64_t i915_type_id(void)return strtoull (buf,NULL ,0 ); } -static int _perf_open (uint64_t config,int group,uint64_t format) +static int +_perf_open (uint64_t type,uint64_t config,int group,uint64_t format) {struct perf_event_attr attr = { }; - attr.type =i915_type_id (); + attr.type = type;if (attr.type ==0 )return -ENOENT ;
@@ -46,11 +47,18 @@ static int _perf_open(uint64_t config, int group, uint64_t format)int perf_i915_open (uint64_t config) { -return _perf_open (config,-1 ,PERF_FORMAT_TOTAL_TIME_ENABLED ); +return _perf_open (i915_type_id (), config,-1 , +PERF_FORMAT_TOTAL_TIME_ENABLED ); }int perf_i915_open_group (uint64_t config,int group) { -return _perf_open (config, group, +return _perf_open (i915_type_id (), config, group,PERF_FORMAT_TOTAL_TIME_ENABLED |PERF_FORMAT_GROUP ); } + +int igt_perf_open (uint64_t type,uint64_t config) +{ +return _perf_open (type, config,-1 , +PERF_FORMAT_TOTAL_TIME_ENABLED ); +}
lib/igt_perf.h +1 -0
@@ -99,5 +99,6 @@ perf_event_open(struct perf_event_attr *attr,uint64_t i915_type_id (void );int perf_i915_open (uint64_t config);int perf_i915_open_group (uint64_t config,int group); +int igt_perf_open (uint64_t type,uint64_t config);#endif /* I915_PERF_H */
overlay/Makefile.am +1 -1
@@ -63,7 +63,7 @@ intel_gpu_overlay_SOURCES += \ intel_gpu_overlay_SOURCES += $(both_x11_sources) -intel_gpu_overlay_LDADD = $(LDADD) -lrt +intel_gpu_overlay_LDADD = $(LDADD) -lrt -lm EXTRA_DIST= \ README \
overlay/power.c +88 -39
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overlay/power.h +2 -0
@@ -39,6 +39,8 @@ struct power {int new_sample;uint64_t power_mW; + +double rapl_scale; };int power_init (struct power *power);
Signature · 6 lines
2.9.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH i-g-t v3 6/9] intel-gpu-overlay: Use RAPL PMU for power reading
Quoting Tvrtko Ursulin (2017-10-10 13:05:40)
Quoted 6 lines
From: Tvrtko Ursulin <[email protected]>
Wire up to the RAPL PMU for GPU energy readings.
The only complication is that we have to add code to parse:
Quoted 8 lines
# cat /sys/devices/power/events/energy-gpu.scale 2.3283064365386962890625e-10v2: Link with -lm.
v3: strtod can handle scientific notation, even though my initial
reading of the man page did not spot that. (Chris Wilson)Signed-off-by Tvrtko Ursulin <[email protected]>
-Chris
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PATCH v4 6/9 intel-gpu-overlay: Use RAPL PMU for power reading
In reply to Tvrtko UrsulinFrom: Tvrtko Ursulin <[email protected]>
Wire up to the RAPL PMU for GPU energy readings.
The only complication is that we have to add code to parse:
# cat /sys/devices/power/events/energy-gpu.scale 2.3283064365386962890625e-10
v2: Link with -lm.
v3: strtod can handle scientific notation, even though my initial
reading of the man page did not spot that. (Chris Wilson)
v4: Meson fix.
--- lib/igt_perf.c | 16 +++++-- lib/igt_perf.h | 1 + overlay/Makefile.am | 2 +- overlay/meson.build | 2 +- overlay/power.c | 127 ++++++++++++++++++++++++++++++++++++---------------- overlay/power.h | 2 + 6 files changed, 105 insertions(+), 45 deletions(-)
lib/igt_perf.c +12 -4
@@ -27,11 +27,12 @@ uint64_t i915_type_id(void)return strtoull (buf,NULL ,0 ); } -static int _perf_open (uint64_t config,int group,uint64_t format) +static int +_perf_open (uint64_t type,uint64_t config,int group,uint64_t format) {struct perf_event_attr attr = { }; - attr.type =i915_type_id (); + attr.type = type;if (attr.type ==0 )return -ENOENT ;
@@ -46,11 +47,18 @@ static int _perf_open(uint64_t config, int group, uint64_t format)int perf_i915_open (uint64_t config) { -return _perf_open (config,-1 ,PERF_FORMAT_TOTAL_TIME_ENABLED ); +return _perf_open (i915_type_id (), config,-1 , +PERF_FORMAT_TOTAL_TIME_ENABLED ); }int perf_i915_open_group (uint64_t config,int group) { -return _perf_open (config, group, +return _perf_open (i915_type_id (), config, group,PERF_FORMAT_TOTAL_TIME_ENABLED |PERF_FORMAT_GROUP ); } + +int igt_perf_open (uint64_t type,uint64_t config) +{ +return _perf_open (type, config,-1 , +PERF_FORMAT_TOTAL_TIME_ENABLED ); +}
lib/igt_perf.h +1 -0
@@ -99,5 +99,6 @@ perf_event_open(struct perf_event_attr *attr,uint64_t i915_type_id (void );int perf_i915_open (uint64_t config);int perf_i915_open_group (uint64_t config,int group); +int igt_perf_open (uint64_t type,uint64_t config);#endif /* I915_PERF_H */
overlay/Makefile.am +1 -1
@@ -63,7 +63,7 @@ intel_gpu_overlay_SOURCES += \ intel_gpu_overlay_SOURCES += $(both_x11_sources) -intel_gpu_overlay_LDADD = $(LDADD) -lrt +intel_gpu_overlay_LDADD = $(LDADD) -lrt -lm EXTRA_DIST= \ README \
overlay/meson.build +1 -1
@@ -21,7 +21,7 @@ dri2proto = dependency('dri2proto', version : '>= 2.6', required : false) cairo_xlib = dependency('cairo-xlib', required : false) xrandr = dependency('xrandr', version : '>=1.3', required : false) -gpu_overlay_deps = [ realtime, cairo, pciaccess, libdrm, libdrm_intel ] +gpu_overlay_deps = [ realtime, math, cairo, pciaccess, libdrm, libdrm_intel ] both_x11_src = ''
overlay/power.c +88 -39
185 lines not on this page · raw message
overlay/power.h +2 -0
@@ -39,6 +39,8 @@ struct power {int new_sample;uint64_t power_mW; + +double rapl_scale; };int power_init (struct power *power);
Signature · 6 lines
2.14.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 7/9 tests/perf_pmu: Tests for i915 PMU API
In reply to Tvrtko UrsulinFrom: Tvrtko Ursulin <[email protected]>
A bunch of tests for the new i915 PMU feature.
Parts of the code were initialy sketched by Dmitry Rogozhkin.
v2: (Most suggestions by Chris Wilson)
* Add new class/instance based engine list.
* Add gem_has_engine/gem_require_engine to work with class/instance.
* Use the above two throughout the test.
* Shorten tests to 100ms busy batches, seems enough.
* Add queued counter sanity checks.
* Use igt_nsec_elapsed.
* Skip on perf -ENODEV in some tests instead of embedding knowledge locally.
* Fix multi ordering for busy accounting.
* Use new guranteed_usleep when sleep time is asserted on.
* Check for no queued when idle/busy.
* Add queued counter init test.
* Add queued tests.
* Consolidate and increase multiple busy engines tests to most-busy and all-busy tests.
* Guarantte interrupts by using fences.
* Test RC6 via forcewake.
v3:
* Tweak assert in interrupts subtest.
* Sprinkle of comments.
* Fix multi-client test which got broken in v2.
v4:
* Measured instead of guaranteed sleep.
* Missing sync in no_sema.
* Log busyness before asserts for debug.
* access(2) instead of open(2) to determine if cpu0 is hotpluggable.
* Test frequency reporting via min/max setting instead assuming. ^^ All above suggested by Chris Wilson. ^^
* Drop queued subtests to match i915.
* Use long batches with fences to ensure interrupts.
* Test render node as well.
v5:
* Add to meson build. (Petri Latvala)
* Use 1eN constants. (Chris Wilson)
* Add tests for semaphore and event waiting.
--- lib/igt_gt.c | 50 ++ lib/igt_gt.h | 38 ++ lib/igt_perf.h | 9 +- tests/Makefile.am | 1 + tests/Makefile.sources | 1 + tests/meson.build | 1 + tests/perf_pmu.c | 1238 ++++++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 1330 insertions(+), 8 deletions(-) create mode 100644 tests/perf_pmu.c
lib/igt_gt.c +50 -0
@@ -568,3 +568,53 @@ bool gem_can_store_dword(int fd, unsigned int engine)return true; } + +const struct intel_execution_engine2 intel_execution_engines2[] = { + {"rcs0" ,I915_ENGINE_CLASS_RENDER ,0 }, + {"bcs0" ,I915_ENGINE_CLASS_COPY ,0 }, + {"vcs0" ,I915_ENGINE_CLASS_VIDEO ,0 }, + {"vcs1" ,I915_ENGINE_CLASS_VIDEO ,1 }, + {"vecs0" ,I915_ENGINE_CLASS_VIDEO_ENHANCE ,0 }, +}; + +unsigned int +gem_class_instance_to_eb_flags (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance) +{ +if (class !=I915_ENGINE_CLASS_VIDEO ) +igt_assert (instance ==0 ); +else +igt_assert (instance >=0 && instance <=1 ); + +switch (class) { +case I915_ENGINE_CLASS_RENDER : +return I915_EXEC_RENDER ; +case I915_ENGINE_CLASS_COPY : +return I915_EXEC_BLT ; +case I915_ENGINE_CLASS_VIDEO : +if (instance ==0 ) { +if (gem_has_bsd2 (gem_fd)) +return I915_EXEC_BSD |I915_EXEC_BSD_RING1 ; +else +return I915_EXEC_BSD ; + + }else { +return I915_EXEC_BSD |I915_EXEC_BSD_RING2 ; + } +case I915_ENGINE_CLASS_VIDEO_ENHANCE : +return I915_EXEC_VEBOX ; +case I915_ENGINE_CLASS_OTHER : +default : +igt_assert (0 ); + }; +} + +bool gem_has_engine (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance) +{ +return gem_has_ring (gem_fd, +gem_class_instance_to_eb_flags (gem_fd, class, + instance)); +}
lib/igt_gt.h +38 -0
@@ -25,6 +25,7 @@#define IGT_GT_H #include "igt_debugfs.h" +#include "igt_core.h" void igt_require_hang_ring (int fd,int ring);
@@ -80,4 +81,41 @@ extern const struct intel_execution_engine {bool gem_can_store_dword (int fd,unsigned int engine); +extern const struct intel_execution_engine2 { +const char *name; +int class; +int instance; +} intel_execution_engines2[]; + +#define for_each_engine_class_instance (fd__, e__) \ + for ((e__) = intel_execution_engines2;\ + (e__)->name; \ + (e__)++) + +enum drm_i915_gem_engine_class { +I915_ENGINE_CLASS_OTHER =0 , +I915_ENGINE_CLASS_RENDER =1 , +I915_ENGINE_CLASS_COPY =2 , +I915_ENGINE_CLASS_VIDEO =3 , +I915_ENGINE_CLASS_VIDEO_ENHANCE =4 , +I915_ENGINE_CLASS_MAX /* non-ABI */ +}; + +unsigned int +gem_class_instance_to_eb_flags (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance); + +bool gem_has_engine (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance); + +static inline +void gem_require_engine (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance) +{ +igt_require (gem_has_engine (gem_fd, class, instance)); +} +#endif /* IGT_GT_H */
lib/igt_perf.h +1 -8
@@ -29,14 +29,7 @@#include <linux/perf_event.h> -enum drm_i915_gem_engine_class { -I915_ENGINE_CLASS_OTHER =0 , -I915_ENGINE_CLASS_RENDER =1 , -I915_ENGINE_CLASS_COPY =2 , -I915_ENGINE_CLASS_VIDEO =3 , -I915_ENGINE_CLASS_VIDEO_ENHANCE =4 , -I915_ENGINE_CLASS_MAX /* non-ABI */ -}; +#include "igt_gt.h" enum drm_i915_pmu_engine_sample {I915_SAMPLE_BUSY =0 ,
tests/Makefile.am +1 -0
@@ -131,6 +131,7 @@ gen7_forcewake_mt_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gen7_forcewake_mt_LDADD = $(LDADD) -lpthread gem_userptr_blits_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_userptr_blits_LDADD = $(LDADD) -lpthread +perf_pmu_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la gem_wait_LDADD = $(LDADD) -lrt kms_flip_LDADD = $(LDADD) -lrt -lpthread
tests/Makefile.sources +1 -0
@@ -217,6 +217,7 @@ TESTS_progs = \ kms_vblank \ meta_test \ perf \ + perf_pmu \ pm_backlight \ pm_lpsp \ pm_rc6_residency \
tests/meson.build +1 -0
@@ -197,6 +197,7 @@ test_progs = [ 'kms_vblank', 'meta_test', 'perf', + 'perf_pmu', 'pm_backlight', 'pm_lpsp', 'pm_rc6_residency',
tests/perf_pmu.c new file +1238 -0
1,238 lines not on this page · raw message
Signature · 6 lines
2.9.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH i-g-t 7/9] tests/perf_pmu: Tests for i915 PMU API
Quoting Tvrtko Ursulin (2017-10-10 10:30:06)
Quoted 13 lines
tests/perf_pmu.c new file +13
-0+static void +event_wait (int gem_fd,const struct intel_execution_engine2 *e) +{ +struct drm_i915_gem_exec_object2 obj = { }; +struct drm_i915_gem_execbuffer2 eb = { }; +data_t data; +igt_display_t *display = &data.display; +const uint32_t DERRMR =0x44050 ; +unsigned int valid_tests =0 ; +uint32_t batch[8 ], *b; +igt_output_t *output; +uint32_t bb_handle; +uint32_t reg;
tests/perf_pmu.c line 520
Quoted 10 lines
tests/perf_pmu.c new file +10
-0+enum pipe p; +int fd; + +igt_require (intel_gen (intel_get_drm_devid (gem_fd)) >=6 ); +igt_require (intel_register_access_init (intel_get_pci_device (), + false, gem_fd) ==0 ); + +/** +* We will use the display to render event forwarind so need to +* program the DERRMR register and restore it at exit.
DERRMR is always masked until we need it. If you really wanted to preserve the old value, SRM, LRM around the test. Not that fussed, just a general dislike of direct poking of registers.
Quoted 33 lines
tests/perf_pmu.c new file +32
-0+* +* We will emit a MI_WAIT_FOR_EVENT listening for vblank events, +* have a background helper to indirectly enable vblank irqs, and +* listen to the recorded time spent in engine wait state as reported +* by the PMU. +*/ + reg =intel_register_read (DERRMR ); + +kmstest_set_vt_graphics_mode (); +igt_display_init (&data.display, gem_fd); + + bb_handle =gem_create (gem_fd,4096 ); + + b = batch; + *b++ =MI_LOAD_REGISTER_IMM ; + *b++ =DERRMR ; + *b++ = reg & ~((1 <<3 ) | (1 <<11 ) | (1 <<21 )); + *b++ =MI_WAIT_FOR_EVENT |MI_WAIT_FOR_PIPE_A_VBLANK ; + *b++ =MI_LOAD_REGISTER_IMM ; + *b++ =DERRMR ; + *b++ = reg; + *b++ =MI_BATCH_BUFFER_END ; +static int chain_nop (int gem_fd,unsigned long sz,int in_fence,bool sync) +{ +struct drm_i915_gem_exec_object2 obj = {}; +struct drm_i915_gem_execbuffer2 eb = + { .buffer_count =1 , .buffers_ptr = (uintptr_t )&obj}; +const uint32_t bbe =0xa <<23 ; + + sz =ALIGN (sz,sizeof (uint32_t )); + + obj.handle =gem_create (gem_fd, sz);
tests/perf_pmu.c
Quoted 10 lines
tests/perf_pmu.c new file +10
-0+gem_write (gem_fd, obj.handle, sz -sizeof (bbe), &bbe,sizeof (bbe)); + + eb.flags =I915_EXEC_RENDER |I915_EXEC_FENCE_OUT ; + +if (in_fence >=0 ) { + eb.flags |=I915_EXEC_FENCE_IN ; + eb.rsvd2 = in_fence; + } + +gem_execbuf_wr (gem_fd, &eb);
On the same ctx/engine, this shouldn't be generating interrupts between the batches. The fence should be resolved to an i915 request and then we see that the requests are naturally ordered so the fence is elided.
tests/perf_pmu.c line 860
Quoted 3 lines
tests/perf_pmu.c new file +3
-0+ +if (sync) +gem_sync (gem_fd, obj.handle);
So it looks like this will remain the only interrupt generator.
If we exported the out-fence and then polled that, that is currently hooked up to an interrupt only path.
I don't have anything else to say! Afaict you have everything covered, so the only way to find what's not is by letting it go live!
Give or take more tuning of the interrupt test,
-Chris
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Re: [PATCH i-g-t 7/9] tests/perf_pmu: Tests for i915 PMU API
Quoted 20 lines · Chris Wilson
Quoting Tvrtko Ursulin (2017-10-10 10:30:06)
Quoted 19 lines
tests/perf_pmu.c new file +19
-0+static void +event_wait (int gem_fd,const struct intel_execution_engine2 *e) +{ +struct drm_i915_gem_exec_object2 obj = { }; +struct drm_i915_gem_execbuffer2 eb = { }; +data_t data; +igt_display_t *display = &data.display; +const uint32_t DERRMR =0x44050 ; +unsigned int valid_tests =0 ; +uint32_t batch[8 ], *b; +igt_output_t *output; +uint32_t bb_handle; +uint32_t reg; +enum pipe p; +int fd; + +igt_require (intel_gen (intel_get_drm_devid (gem_fd)) >=6 ); +igt_require (intel_register_access_init (intel_get_pci_device (), + false, gem_fd) ==0 );
Quoted 8 lines
tests/perf_pmu.c line 520
Quoted 4 lines
tests/perf_pmu.c new file +4
-0+ +/** +* We will use the display to render event forwarind so need to +* program the DERRMR register and restore it at exit. DERRMR is always masked until we need it. If you really wanted to preserve the old value, SRM, LRM around the test. Not that fussed, just a general dislike of direct poking of registers.
Thought I can get away with it since the handle is drm master and also there doesn't seem to be a patch in i915 which touches this register.
Quoted 47 lines
Quoted 33 lines
tests/perf_pmu.c new file +32
-0+* +* We will emit a MI_WAIT_FOR_EVENT listening for vblank events, +* have a background helper to indirectly enable vblank irqs, and +* listen to the recorded time spent in engine wait state as reported +* by the PMU. +*/ + reg =intel_register_read (DERRMR ); + +kmstest_set_vt_graphics_mode (); +igt_display_init (&data.display, gem_fd); + + bb_handle =gem_create (gem_fd,4096 ); + + b = batch; + *b++ =MI_LOAD_REGISTER_IMM ; + *b++ =DERRMR ; + *b++ = reg & ~((1 <<3 ) | (1 <<11 ) | (1 <<21 )); + *b++ =MI_WAIT_FOR_EVENT |MI_WAIT_FOR_PIPE_A_VBLANK ; + *b++ =MI_LOAD_REGISTER_IMM ; + *b++ =DERRMR ; + *b++ = reg; + *b++ =MI_BATCH_BUFFER_END ; +static int chain_nop (int gem_fd,unsigned long sz,int in_fence,bool sync) +{ +struct drm_i915_gem_exec_object2 obj = {}; +struct drm_i915_gem_execbuffer2 eb = + { .buffer_count =1 , .buffers_ptr = (uintptr_t )&obj}; +const uint32_t bbe =0xa <<23 ; + + sz =ALIGN (sz,sizeof (uint32_t )); + + obj.handle =gem_create (gem_fd, sz);tests/perf_pmu.c
Quoted 10 lines
tests/perf_pmu.c new file +10
-0+gem_write (gem_fd, obj.handle, sz -sizeof (bbe), &bbe,sizeof (bbe)); + + eb.flags =I915_EXEC_RENDER |I915_EXEC_FENCE_OUT ; + +if (in_fence >=0 ) { + eb.flags |=I915_EXEC_FENCE_IN ; + eb.rsvd2 = in_fence; + } + +gem_execbuf_wr (gem_fd, &eb);On the same ctx/engine, this shouldn't be generating interrupts between the batches. The fence should be resolved to an i915 request and then we see that the requests are naturally ordered so the fence is elided.
Quoted 8 lines
tests/perf_pmu.c line 860
Quoted 3 lines
tests/perf_pmu.c new file +3
-0+ +if (sync) +gem_sync (gem_fd, obj.handle);So it looks like this will remain the only interrupt generator.
If we exported the out-fence and then polled that, that is currently hooked up to an interrupt only path.
So you think I'm counting ctx switches and other stuff? Maybe we should have separate PMU counters for all the different interrupts. :)
What do you mean by exporting the out fence? Looping it through via something external to hide the source? Not sure how to do it. Dup the fd? Or create a swfence and merge the out fence to it? (Talking from memory here.)
P.S.
I did miss to subtract the previous count before the assert.
Regards,
Tvrtko
Quoted 5 lines
I don't have anything else to say! Afaict you have everything covered, so the only way to find what's not is by letting it go live!
Quoted 8 lines
Give or take more tuning of the interrupt test,
Reviewed-by Chris Wilson <[email protected]>-Chris
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Re: [PATCH i-g-t 7/9] tests/perf_pmu: Tests for i915 PMU API
Quoting Tvrtko Ursulin (2017-10-10 14:38:10)
Quoted 31 lines · Chris Wilson
Quoted 20 lines
Quoting Tvrtko Ursulin (2017-10-10 10:30:06)
Quoted 19 lines
tests/perf_pmu.c new file +19
-0+static void +event_wait (int gem_fd,const struct intel_execution_engine2 *e) +{ +struct drm_i915_gem_exec_object2 obj = { }; +struct drm_i915_gem_execbuffer2 eb = { }; +data_t data; +igt_display_t *display = &data.display; +const uint32_t DERRMR =0x44050 ; +unsigned int valid_tests =0 ; +uint32_t batch[8 ], *b; +igt_output_t *output; +uint32_t bb_handle; +uint32_t reg; +enum pipe p; +int fd; + +igt_require (intel_gen (intel_get_drm_devid (gem_fd)) >=6 ); +igt_require (intel_register_access_init (intel_get_pci_device (), + false, gem_fd) ==0 );Quoted 8 lines
tests/perf_pmu.c line 520
Quoted 4 lines
tests/perf_pmu.c new file +4
-0+ +/** +* We will use the display to render event forwarind so need to +* program the DERRMR register and restore it at exit. DERRMR is always masked until we need it. If you really wanted to preserve the old value, SRM, LRM around the test. Not that fussed, just a general dislike of direct poking of registers.
Quoted 2 lines
Thought I can get away with it since the handle is drm master and also there doesn't seem to be a patch in i915 which touches this register.
Oh, we used to set it around pageflips. Good point about drmMaster. That's worth a igt_require(igt_set_master()) to document the requirement that we need it here for SECURE dispatch.
I'm actually a bit concerned that DERRMR isn't ~0u by default. (Though maybe they only assert the bits that are connected to events).
Quoted 51 lines
Quoted 51 lines
Quoted 33 lines
tests/perf_pmu.c new file +32
-0+* +* We will emit a MI_WAIT_FOR_EVENT listening for vblank events, +* have a background helper to indirectly enable vblank irqs, and +* listen to the recorded time spent in engine wait state as reported +* by the PMU. +*/ + reg =intel_register_read (DERRMR ); + +kmstest_set_vt_graphics_mode (); +igt_display_init (&data.display, gem_fd); + + bb_handle =gem_create (gem_fd,4096 ); + + b = batch; + *b++ =MI_LOAD_REGISTER_IMM ; + *b++ =DERRMR ; + *b++ = reg & ~((1 <<3 ) | (1 <<11 ) | (1 <<21 )); + *b++ =MI_WAIT_FOR_EVENT |MI_WAIT_FOR_PIPE_A_VBLANK ; + *b++ =MI_LOAD_REGISTER_IMM ; + *b++ =DERRMR ; + *b++ = reg; + *b++ =MI_BATCH_BUFFER_END ; +static int chain_nop (int gem_fd,unsigned long sz,int in_fence,bool sync) +{ +struct drm_i915_gem_exec_object2 obj = {}; +struct drm_i915_gem_execbuffer2 eb = + { .buffer_count =1 , .buffers_ptr = (uintptr_t )&obj}; +const uint32_t bbe =0xa <<23 ; + + sz =ALIGN (sz,sizeof (uint32_t )); + + obj.handle =gem_create (gem_fd, sz);tests/perf_pmu.c
Quoted 10 lines
tests/perf_pmu.c new file +10
-0+gem_write (gem_fd, obj.handle, sz -sizeof (bbe), &bbe,sizeof (bbe)); + + eb.flags =I915_EXEC_RENDER |I915_EXEC_FENCE_OUT ; + +if (in_fence >=0 ) { + eb.flags |=I915_EXEC_FENCE_IN ; + eb.rsvd2 = in_fence; + } + +gem_execbuf_wr (gem_fd, &eb);On the same ctx/engine, this shouldn't be generating interrupts between the batches. The fence should be resolved to an i915 request and then we see that the requests are naturally ordered so the fence is elided.
Quoted 3 lines
tests/perf_pmu.c new file +3
-0+ +if (sync) +gem_sync (gem_fd, obj.handle);
Quoted 7 lines
Quoted 4 lines
So it looks like this will remain the only interrupt generator.
If we exported the out-fence and then polled that, that is currently hooked up to an interrupt only path.
So you think I'm counting ctx switches and other stuff? Maybe we should have separate PMU counters for all the different interrupts. :)
Yeah, each request will be generating a new lite-restore. Hmm, how about if we guarded that with i915_gem_request_started(). Interesting...
Quoted 4 lines
What do you mean by exporting the out fence? Looping it through via something external to hide the source? Not sure how to do it. Dup the fd? Or create a swfence and merge the out fence to it? (Talking from memory here.)
We can just use the poll((struct pfd){fd, POLLIN}, 1, -1). Instead of "exporting the out_fence" read "having exported the out_fence", i.e. the sync_file currently forces use of the interrupt (so long as it is not already completed!).
-Chris
_______________________________________________
Intel-gfx mailing list
[email protected]
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PATCH v6 7/9 tests/perf_pmu: Tests for i915 PMU API
From: Tvrtko Ursulin <[email protected]>
A bunch of tests for the new i915 PMU feature.
Parts of the code were initialy sketched by Dmitry Rogozhkin.
v2: (Most suggestions by Chris Wilson)
* Add new class/instance based engine list.
* Add gem_has_engine/gem_require_engine to work with class/instance.
* Use the above two throughout the test.
* Shorten tests to 100ms busy batches, seems enough.
* Add queued counter sanity checks.
* Use igt_nsec_elapsed.
* Skip on perf -ENODEV in some tests instead of embedding knowledge locally.
* Fix multi ordering for busy accounting.
* Use new guranteed_usleep when sleep time is asserted on.
* Check for no queued when idle/busy.
* Add queued counter init test.
* Add queued tests.
* Consolidate and increase multiple busy engines tests to most-busy and all-busy tests.
* Guarantte interrupts by using fences.
* Test RC6 via forcewake.
v3:
* Tweak assert in interrupts subtest.
* Sprinkle of comments.
* Fix multi-client test which got broken in v2.
v4:
* Measured instead of guaranteed sleep.
* Missing sync in no_sema.
* Log busyness before asserts for debug.
* access(2) instead of open(2) to determine if cpu0 is hotpluggable.
* Test frequency reporting via min/max setting instead assuming. ^^ All above suggested by Chris Wilson. ^^
* Drop queued subtests to match i915.
* Use long batches with fences to ensure interrupts.
* Test render node as well.
v5:
* Add to meson build. (Petri Latvala)
* Use 1eN constants. (Chris Wilson)
* Add tests for semaphore and event waiting.
v6:
* Fix interrupts subtest by polling the fence from the "outside". (Chris Wilson)
--- lib/igt_gt.c | 50 ++ lib/igt_gt.h | 38 ++ lib/igt_perf.h | 9 +- tests/Makefile.am | 1 + tests/Makefile.sources | 1 + tests/meson.build | 1 + tests/perf_pmu.c | 1238 ++++++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 1330 insertions(+), 8 deletions(-) create mode 100644 tests/perf_pmu.c
lib/igt_gt.c +50 -0
@@ -568,3 +568,53 @@ bool gem_can_store_dword(int fd, unsigned int engine)return true; } + +const struct intel_execution_engine2 intel_execution_engines2[] = { + {"rcs0" ,I915_ENGINE_CLASS_RENDER ,0 }, + {"bcs0" ,I915_ENGINE_CLASS_COPY ,0 }, + {"vcs0" ,I915_ENGINE_CLASS_VIDEO ,0 }, + {"vcs1" ,I915_ENGINE_CLASS_VIDEO ,1 }, + {"vecs0" ,I915_ENGINE_CLASS_VIDEO_ENHANCE ,0 }, +}; + +unsigned int +gem_class_instance_to_eb_flags (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance) +{ +if (class !=I915_ENGINE_CLASS_VIDEO ) +igt_assert (instance ==0 ); +else +igt_assert (instance >=0 && instance <=1 ); + +switch (class) { +case I915_ENGINE_CLASS_RENDER : +return I915_EXEC_RENDER ; +case I915_ENGINE_CLASS_COPY : +return I915_EXEC_BLT ; +case I915_ENGINE_CLASS_VIDEO : +if (instance ==0 ) { +if (gem_has_bsd2 (gem_fd)) +return I915_EXEC_BSD |I915_EXEC_BSD_RING1 ; +else +return I915_EXEC_BSD ; + + }else { +return I915_EXEC_BSD |I915_EXEC_BSD_RING2 ; + } +case I915_ENGINE_CLASS_VIDEO_ENHANCE : +return I915_EXEC_VEBOX ; +case I915_ENGINE_CLASS_OTHER : +default : +igt_assert (0 ); + }; +} + +bool gem_has_engine (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance) +{ +return gem_has_ring (gem_fd, +gem_class_instance_to_eb_flags (gem_fd, class, + instance)); +}
lib/igt_gt.h +38 -0
@@ -25,6 +25,7 @@#define IGT_GT_H #include "igt_debugfs.h" +#include "igt_core.h" void igt_require_hang_ring (int fd,int ring);
@@ -80,4 +81,41 @@ extern const struct intel_execution_engine {bool gem_can_store_dword (int fd,unsigned int engine); +extern const struct intel_execution_engine2 { +const char *name; +int class; +int instance; +} intel_execution_engines2[]; + +#define for_each_engine_class_instance (fd__, e__) \ + for ((e__) = intel_execution_engines2;\ + (e__)->name; \ + (e__)++) + +enum drm_i915_gem_engine_class { +I915_ENGINE_CLASS_OTHER =0 , +I915_ENGINE_CLASS_RENDER =1 , +I915_ENGINE_CLASS_COPY =2 , +I915_ENGINE_CLASS_VIDEO =3 , +I915_ENGINE_CLASS_VIDEO_ENHANCE =4 , +I915_ENGINE_CLASS_MAX /* non-ABI */ +}; + +unsigned int +gem_class_instance_to_eb_flags (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance); + +bool gem_has_engine (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance); + +static inline +void gem_require_engine (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance) +{ +igt_require (gem_has_engine (gem_fd, class, instance)); +} +#endif /* IGT_GT_H */
lib/igt_perf.h +1 -8
@@ -29,14 +29,7 @@#include <linux/perf_event.h> -enum drm_i915_gem_engine_class { -I915_ENGINE_CLASS_OTHER =0 , -I915_ENGINE_CLASS_RENDER =1 , -I915_ENGINE_CLASS_COPY =2 , -I915_ENGINE_CLASS_VIDEO =3 , -I915_ENGINE_CLASS_VIDEO_ENHANCE =4 , -I915_ENGINE_CLASS_MAX /* non-ABI */ -}; +#include "igt_gt.h" enum drm_i915_pmu_engine_sample {I915_SAMPLE_BUSY =0 ,
tests/Makefile.am +1 -0
@@ -131,6 +131,7 @@ gen7_forcewake_mt_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gen7_forcewake_mt_LDADD = $(LDADD) -lpthread gem_userptr_blits_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_userptr_blits_LDADD = $(LDADD) -lpthread +perf_pmu_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la gem_wait_LDADD = $(LDADD) -lrt kms_flip_LDADD = $(LDADD) -lrt -lpthread
tests/Makefile.sources +1 -0
@@ -217,6 +217,7 @@ TESTS_progs = \ kms_vblank \ meta_test \ perf \ + perf_pmu \ pm_backlight \ pm_lpsp \ pm_rc6_residency \
tests/meson.build +1 -0
@@ -197,6 +197,7 @@ test_progs = [ 'kms_vblank', 'meta_test', 'perf', + 'perf_pmu', 'pm_backlight', 'pm_lpsp', 'pm_rc6_residency',
tests/perf_pmu.c new file +1238 -0
1,238 lines not on this page · raw message
Signature · 6 lines
2.9.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH i-g-t v6 7/9] tests/perf_pmu: Tests for i915 PMU API
Quoting Tvrtko Ursulin (2017-10-10 15:17:54)
Quoted 12 lines
tests/perf_pmu.c new file +12
-0+static void +busy_check_all (int gem_fd,const struct intel_execution_engine2 *e, +const unsigned int num_engines) +{ +const struct intel_execution_engine2 *e_; +uint64_t val[num_engines]; +int fd[num_engines]; +igt_spin_t *spin; +unsigned int busy_idx, i; + + i =0 ; + fd[0 ] =-1 ;
tests/perf_pmu.c line 206
Quoted 10 lines
tests/perf_pmu.c new file +10
-0+for_each_engine_class_instance (fd, e_) { +if (!gem_has_engine (gem_fd, e_->class, e_->instance)) +continue ; +else if (e == e_) + busy_idx = i; + + fd[i++] =open_group (I915_PMU_ENGINE_BUSY (e_->class, + e_->instance), + fd[0 ]); + }
igt_assert(i == num_engines);
Feels like a bug waiting to happen; a trap.
Quoted 62 lines
tests/perf_pmu.c new file +62
-0+static void +test_frequency (int gem_fd) +{ +const uint64_t duration_ns =2e9 ; +uint32_t min_freq, max_freq, boost_freq; +uint64_t min[2 ], max[2 ], start[2 ]; +igt_spin_t *spin; +int fd, sysfs; + + sysfs =igt_sysfs_open (gem_fd,NULL ); +igt_require (sysfs >=0 ); + + min_freq =igt_sysfs_get_u32 (sysfs,"gt_RPn_freq_mhz" ); + max_freq =igt_sysfs_get_u32 (sysfs,"gt_RP0_freq_mhz" ); + boost_freq =igt_sysfs_get_u32 (sysfs,"gt_boost_freq_mhz" ); +igt_require (min_freq >0 && max_freq >0 && boost_freq >0 ); +igt_require (max_freq > min_freq); +igt_require (boost_freq > min_freq); + + fd =open_group (I915_PMU_REQUESTED_FREQUENCY ,-1 ); +open_group (I915_PMU_ACTUAL_FREQUENCY , fd); + +/* +* Set GPU to min frequency and read PMU counters. +*/ +igt_require (igt_sysfs_set_u32 (sysfs,"gt_max_freq_mhz" , min_freq)); +igt_require (igt_sysfs_get_u32 (sysfs,"gt_max_freq_mhz" ) == min_freq); +igt_require (igt_sysfs_set_u32 (sysfs,"gt_boost_freq_mhz" , min_freq)); +igt_require (igt_sysfs_get_u32 (sysfs,"gt_boost_freq_mhz" ) == min_freq); + +pmu_read_multi (fd,2 , start); + + spin =igt_spin_batch_new (gem_fd,0 ,I915_EXEC_RENDER ,0 ); +igt_spin_batch_set_timeout (spin, duration_ns); +gem_sync (gem_fd, spin->handle); + +pmu_read_multi (fd,2 , min); + min[0 ] -= start[0 ]; + min[1 ] -= start[1 ]; + +igt_spin_batch_free (gem_fd, spin); + +usleep (1e6 ); + +/* +* Set GPU to max frequency and read PMU counters. +*/ +igt_require (igt_sysfs_set_u32 (sysfs,"gt_max_freq_mhz" , max_freq)); +igt_require (igt_sysfs_get_u32 (sysfs,"gt_max_freq_mhz" ) == max_freq); +igt_require (igt_sysfs_set_u32 (sysfs,"gt_boost_freq_mhz" , boost_freq)); +igt_require (igt_sysfs_get_u32 (sysfs,"gt_boost_freq_mhz" ) == boost_freq); + +igt_require (igt_sysfs_set_u32 (sysfs,"gt_min_freq_mhz" , max_freq)); +igt_require (igt_sysfs_get_u32 (sysfs,"gt_min_freq_mhz" ) == max_freq); + +pmu_read_multi (fd,2 , start); + + spin =igt_spin_batch_new (gem_fd,0 ,I915_EXEC_RENDER ,0 ); +igt_spin_batch_set_timeout (spin, duration_ns); +gem_sync (gem_fd, spin->handle); + +pmu_read_multi (fd,2 , max);
tests/perf_pmu.c line 983
Quoted 10 lines
tests/perf_pmu.c new file +10
-0+ max[0 ] -= start[0 ]; + max[1 ] -= start[1 ]; + +igt_spin_batch_free (gem_fd, spin); + +/* +* Restore min/max. +*/ +igt_require (igt_sysfs_set_u32 (sysfs,"gt_min_freq_mhz" , min_freq)); +igt_require (igt_sysfs_get_u32 (sysfs,"gt_min_freq_mhz" ) == min_freq);
The test is done at this point, and you are just being neat and tidy for the next user. We don't need to do anything but warn:
igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz");
if (igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") != min_freq)
igt_warn("Unable to restore min frequency to save value [%d MHz], now %d MHz\n",
min_freq, igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz"));Review
Quoted 2 lines
(quoted diff) +2
-0+ + close(fd);
Add to the list of subtests that want a destructor (for clean error paths).
-Chris
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v7 7/9 tests/perf_pmu: Tests for i915 PMU API
From: Tvrtko Ursulin <[email protected]>
A bunch of tests for the new i915 PMU feature.
Parts of the code were initialy sketched by Dmitry Rogozhkin.
v2: (Most suggestions by Chris Wilson)
* Add new class/instance based engine list.
* Add gem_has_engine/gem_require_engine to work with class/instance.
* Use the above two throughout the test.
* Shorten tests to 100ms busy batches, seems enough.
* Add queued counter sanity checks.
* Use igt_nsec_elapsed.
* Skip on perf -ENODEV in some tests instead of embedding knowledge locally.
* Fix multi ordering for busy accounting.
* Use new guranteed_usleep when sleep time is asserted on.
* Check for no queued when idle/busy.
* Add queued counter init test.
* Add queued tests.
* Consolidate and increase multiple busy engines tests to most-busy and all-busy tests.
* Guarantte interrupts by using fences.
* Test RC6 via forcewake.
v3:
* Tweak assert in interrupts subtest.
* Sprinkle of comments.
* Fix multi-client test which got broken in v2.
v4:
* Measured instead of guaranteed sleep.
* Missing sync in no_sema.
* Log busyness before asserts for debug.
* access(2) instead of open(2) to determine if cpu0 is hotpluggable.
* Test frequency reporting via min/max setting instead assuming. ^^ All above suggested by Chris Wilson. ^^
* Drop queued subtests to match i915.
* Use long batches with fences to ensure interrupts.
* Test render node as well.
v5:
* Add to meson build. (Petri Latvala)
* Use 1eN constants. (Chris Wilson)
* Add tests for semaphore and event waiting.
v6:
* Fix interrupts subtest by polling the fence from the "outside". (Chris Wilson)
v7:
* Assert number of initialized engines matches the expectation. (Chris Wilson)
* Warn instead of skipping if we couldn't restore the initial frequency. (Chris Wilson)
* Move all asserts to after the test cleanup (just a tidy).
* More 1eN notation for timeouts.
* Bump the tolerance to 5% since I saw a few noisy runs with sampling counters.
* Always start the PMU before submitting batches to lower reliance on i915 doing the delayed engine busy stats disable.
--- lib/igt_gt.c | 50 ++ lib/igt_gt.h | 38 ++ lib/igt_perf.h | 9 +- tests/Makefile.am | 1 + tests/Makefile.sources | 1 + tests/meson.build | 1 + tests/perf_pmu.c | 1242 ++++++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 1334 insertions(+), 8 deletions(-) create mode 100644 tests/perf_pmu.c
lib/igt_gt.c +50 -0
@@ -568,3 +568,53 @@ bool gem_can_store_dword(int fd, unsigned int engine)return true; } + +const struct intel_execution_engine2 intel_execution_engines2[] = { + {"rcs0" ,I915_ENGINE_CLASS_RENDER ,0 }, + {"bcs0" ,I915_ENGINE_CLASS_COPY ,0 }, + {"vcs0" ,I915_ENGINE_CLASS_VIDEO ,0 }, + {"vcs1" ,I915_ENGINE_CLASS_VIDEO ,1 }, + {"vecs0" ,I915_ENGINE_CLASS_VIDEO_ENHANCE ,0 }, +}; + +unsigned int +gem_class_instance_to_eb_flags (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance) +{ +if (class !=I915_ENGINE_CLASS_VIDEO ) +igt_assert (instance ==0 ); +else +igt_assert (instance >=0 && instance <=1 ); + +switch (class) { +case I915_ENGINE_CLASS_RENDER : +return I915_EXEC_RENDER ; +case I915_ENGINE_CLASS_COPY : +return I915_EXEC_BLT ; +case I915_ENGINE_CLASS_VIDEO : +if (instance ==0 ) { +if (gem_has_bsd2 (gem_fd)) +return I915_EXEC_BSD |I915_EXEC_BSD_RING1 ; +else +return I915_EXEC_BSD ; + + }else { +return I915_EXEC_BSD |I915_EXEC_BSD_RING2 ; + } +case I915_ENGINE_CLASS_VIDEO_ENHANCE : +return I915_EXEC_VEBOX ; +case I915_ENGINE_CLASS_OTHER : +default : +igt_assert (0 ); + }; +} + +bool gem_has_engine (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance) +{ +return gem_has_ring (gem_fd, +gem_class_instance_to_eb_flags (gem_fd, class, + instance)); +}
lib/igt_gt.h +38 -0
@@ -25,6 +25,7 @@#define IGT_GT_H #include "igt_debugfs.h" +#include "igt_core.h" void igt_require_hang_ring (int fd,int ring);
@@ -80,4 +81,41 @@ extern const struct intel_execution_engine {bool gem_can_store_dword (int fd,unsigned int engine); +extern const struct intel_execution_engine2 { +const char *name; +int class; +int instance; +} intel_execution_engines2[]; + +#define for_each_engine_class_instance (fd__, e__) \ + for ((e__) = intel_execution_engines2;\ + (e__)->name; \ + (e__)++) + +enum drm_i915_gem_engine_class { +I915_ENGINE_CLASS_OTHER =0 , +I915_ENGINE_CLASS_RENDER =1 , +I915_ENGINE_CLASS_COPY =2 , +I915_ENGINE_CLASS_VIDEO =3 , +I915_ENGINE_CLASS_VIDEO_ENHANCE =4 , +I915_ENGINE_CLASS_MAX /* non-ABI */ +}; + +unsigned int +gem_class_instance_to_eb_flags (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance); + +bool gem_has_engine (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance); + +static inline +void gem_require_engine (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance) +{ +igt_require (gem_has_engine (gem_fd, class, instance)); +} +#endif /* IGT_GT_H */
lib/igt_perf.h +1 -8
@@ -29,14 +29,7 @@#include <linux/perf_event.h> -enum drm_i915_gem_engine_class { -I915_ENGINE_CLASS_OTHER =0 , -I915_ENGINE_CLASS_RENDER =1 , -I915_ENGINE_CLASS_COPY =2 , -I915_ENGINE_CLASS_VIDEO =3 , -I915_ENGINE_CLASS_VIDEO_ENHANCE =4 , -I915_ENGINE_CLASS_MAX /* non-ABI */ -}; +#include "igt_gt.h" enum drm_i915_pmu_engine_sample {I915_SAMPLE_BUSY =0 ,
tests/Makefile.am +1 -0
@@ -131,6 +131,7 @@ gen7_forcewake_mt_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gen7_forcewake_mt_LDADD = $(LDADD) -lpthread gem_userptr_blits_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_userptr_blits_LDADD = $(LDADD) -lpthread +perf_pmu_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la gem_wait_LDADD = $(LDADD) -lrt kms_flip_LDADD = $(LDADD) -lrt -lpthread
tests/Makefile.sources +1 -0
@@ -217,6 +217,7 @@ TESTS_progs = \ kms_vblank \ meta_test \ perf \ + perf_pmu \ pm_backlight \ pm_lpsp \ pm_rc6_residency \
tests/meson.build +1 -0
@@ -197,6 +197,7 @@ test_progs = [ 'kms_vblank', 'meta_test', 'perf', + 'perf_pmu', 'pm_backlight', 'pm_lpsp', 'pm_rc6_residency',
tests/perf_pmu.c new file +1242 -0
1,242 lines not on this page · raw message
Signature · 6 lines
2.9.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH i-g-t v7 7/9] tests/perf_pmu: Tests for i915 PMU API
Quoting Tvrtko Ursulin (2017-10-11 13:54:18)
Quoted 61 lines
From: Tvrtko Ursulin <[email protected]>
A bunch of tests for the new i915 PMU feature.
Parts of the code were initialy sketched by Dmitry Rogozhkin.
v2: (Most suggestions by Chris Wilson)
* Add new class/instance based engine list.
* Add gem_has_engine/gem_require_engine to work with class/instance.
* Use the above two throughout the test.
* Shorten tests to 100ms busy batches, seems enough.
* Add queued counter sanity checks.
* Useigt_nsec_elapsed.
* Skip on perf-ENODEVin some tests instead of embedding knowledge locally.
* Fix multi ordering for busy accounting.
* Use newguranteed_usleepwhen sleep time is asserted on.
* Check for no queued when idle/busy.
* Add queued counter init test.
* Add queued tests.
* Consolidate and increase multiple busy engines tests to most-busy and all-busy tests.
* Guarantte interrupts by using fences.
* Test RC6 via forcewake.v3:
* Tweak assert in interrupts subtest.
* Sprinkle of comments.
* Fix multi-client test which got broken in v2.v4:
* Measured instead of guaranteed sleep.
* Missing sync inno_sema.
* Log busyness before asserts for debug.
* access(2) instead of open(2) to determine if cpu0 is hotpluggable.
* Test frequency reporting via min/max setting instead assuming. ^^ All above suggested by Chris Wilson. ^^
* Drop queued subtests to match i915.
* Use long batches with fences to ensure interrupts.
* Test render node as well.v5:
* Add to meson build. (Petri Latvala)
* Use 1eN constants. (Chris Wilson)
* Add tests for semaphore and event waiting.v6:
* Fix interrupts subtest by polling the fence from the "outside". (Chris Wilson)v7:
* Assert number of initialized engines matches the expectation. (Chris Wilson)
* Warn instead of skipping if we couldn't restore the initial frequency. (Chris Wilson)
* Move all asserts to after the test cleanup (just a tidy).
* More 1eN notation for timeouts.
* Bump the tolerance to 5% since I saw a few noisy runs with sampling counters.
* Always start the PMU before submitting batches to lower reliance on i915 doing the delayed engine busy stats disable.
Quoted 4 lines
Signed-off-by Tvrtko Ursulin <[email protected]>Cc Chris Wilson <[email protected]>Cc Dmitry Rogozhkin <[email protected]>Reviewed-by Chris Wilson <[email protected]> (v6)
I think the proof of the pudding is in the eating...
-Chris
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Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v8 7/9 tests/perf_pmu: Tests for i915 PMU API
In reply to Tvrtko UrsulinFrom: Tvrtko Ursulin <[email protected]>
A bunch of tests for the new i915 PMU feature.
Parts of the code were initialy sketched by Dmitry Rogozhkin.
v2: (Most suggestions by Chris Wilson)
* Add new class/instance based engine list.
* Add gem_has_engine/gem_require_engine to work with class/instance.
* Use the above two throughout the test.
* Shorten tests to 100ms busy batches, seems enough.
* Add queued counter sanity checks.
* Use igt_nsec_elapsed.
* Skip on perf -ENODEV in some tests instead of embedding knowledge locally.
* Fix multi ordering for busy accounting.
* Use new guranteed_usleep when sleep time is asserted on.
* Check for no queued when idle/busy.
* Add queued counter init test.
* Add queued tests.
* Consolidate and increase multiple busy engines tests to most-busy and all-busy tests.
* Guarantte interrupts by using fences.
* Test RC6 via forcewake.
v3:
* Tweak assert in interrupts subtest.
* Sprinkle of comments.
* Fix multi-client test which got broken in v2.
v4:
* Measured instead of guaranteed sleep.
* Missing sync in no_sema.
* Log busyness before asserts for debug.
* access(2) instead of open(2) to determine if cpu0 is hotpluggable.
* Test frequency reporting via min/max setting instead assuming. ^^ All above suggested by Chris Wilson. ^^
* Drop queued subtests to match i915.
* Use long batches with fences to ensure interrupts.
* Test render node as well.
v5:
* Add to meson build. (Petri Latvala)
* Use 1eN constants. (Chris Wilson)
* Add tests for semaphore and event waiting.
v6:
* Fix interrupts subtest by polling the fence from the "outside". (Chris Wilson)
v7:
* Assert number of initialized engines matches the expectation. (Chris Wilson)
* Warn instead of skipping if we couldn't restore the initial frequency. (Chris Wilson)
* Move all asserts to after the test cleanup (just a tidy).
* More 1eN notation for timeouts.
* Bump the tolerance to 5% since I saw a few noisy runs with sampling counters.
* Always start the PMU before submitting batches to lower reliance on i915 doing the delayed engine busy stats disable.
v8:
* Update for upstream engine class enum.
--- lib/igt_gt.c | 50 ++ lib/igt_gt.h | 38 ++ lib/igt_perf.h | 9 +- tests/Makefile.am | 1 + tests/Makefile.sources | 1 + tests/meson.build | 1 + tests/perf_pmu.c | 1242 ++++++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 1334 insertions(+), 8 deletions(-) create mode 100644 tests/perf_pmu.c
lib/igt_gt.c +50 -0
@@ -608,3 +608,53 @@ bool gem_can_store_dword(int fd, unsigned int engine)return true; } + +const struct intel_execution_engine2 intel_execution_engines2[] = { + {"rcs0" ,I915_ENGINE_CLASS_RENDER ,0 }, + {"bcs0" ,I915_ENGINE_CLASS_COPY ,0 }, + {"vcs0" ,I915_ENGINE_CLASS_VIDEO ,0 }, + {"vcs1" ,I915_ENGINE_CLASS_VIDEO ,1 }, + {"vecs0" ,I915_ENGINE_CLASS_VIDEO_ENHANCE ,0 }, +}; + +unsigned int +gem_class_instance_to_eb_flags (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance) +{ +if (class !=I915_ENGINE_CLASS_VIDEO ) +igt_assert (instance ==0 ); +else +igt_assert (instance >=0 && instance <=1 ); + +switch (class) { +case I915_ENGINE_CLASS_RENDER : +return I915_EXEC_RENDER ; +case I915_ENGINE_CLASS_COPY : +return I915_EXEC_BLT ; +case I915_ENGINE_CLASS_VIDEO : +if (instance ==0 ) { +if (gem_has_bsd2 (gem_fd)) +return I915_EXEC_BSD |I915_EXEC_BSD_RING1 ; +else +return I915_EXEC_BSD ; + + }else { +return I915_EXEC_BSD |I915_EXEC_BSD_RING2 ; + } +case I915_ENGINE_CLASS_VIDEO_ENHANCE : +return I915_EXEC_VEBOX ; +case I915_ENGINE_CLASS_INVALID : +default : +igt_assert (0 ); + }; +} + +bool gem_has_engine (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance) +{ +return gem_has_ring (gem_fd, +gem_class_instance_to_eb_flags (gem_fd, class, + instance)); +}
lib/igt_gt.h +38 -0
@@ -25,6 +25,7 @@#define IGT_GT_H #include "igt_debugfs.h" +#include "igt_core.h" void igt_require_hang_ring (int fd,int ring);
@@ -80,4 +81,41 @@ extern const struct intel_execution_engine {bool gem_can_store_dword (int fd,unsigned int engine); +extern const struct intel_execution_engine2 { +const char *name; +int class; +int instance; +} intel_execution_engines2[]; + +#define for_each_engine_class_instance (fd__, e__) \ + for ((e__) = intel_execution_engines2;\ + (e__)->name; \ + (e__)++) + +enum drm_i915_gem_engine_class { +I915_ENGINE_CLASS_RENDER =0 , +I915_ENGINE_CLASS_COPY =1 , +I915_ENGINE_CLASS_VIDEO =2 , +I915_ENGINE_CLASS_VIDEO_ENHANCE =3 , + +I915_ENGINE_CLASS_INVALID =-1 +}; + +unsigned int +gem_class_instance_to_eb_flags (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance); + +bool gem_has_engine (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance); + +static inline +void gem_require_engine (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance) +{ +igt_require (gem_has_engine (gem_fd, class, instance)); +} +#endif /* IGT_GT_H */
lib/igt_perf.h +1 -8
@@ -29,14 +29,7 @@#include <linux/perf_event.h> -enum drm_i915_gem_engine_class { -I915_ENGINE_CLASS_RENDER =0 , -I915_ENGINE_CLASS_COPY =1 , -I915_ENGINE_CLASS_VIDEO =2 , -I915_ENGINE_CLASS_VIDEO_ENHANCE =3 , - -I915_ENGINE_CLASS_INVALID =-1 -}; +#include "igt_gt.h" enum drm_i915_pmu_engine_sample {I915_SAMPLE_BUSY =0 ,
tests/Makefile.am +1 -0
@@ -131,6 +131,7 @@ gen7_forcewake_mt_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gen7_forcewake_mt_LDADD = $(LDADD) -lpthread gem_userptr_blits_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_userptr_blits_LDADD = $(LDADD) -lpthread +perf_pmu_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la gem_wait_LDADD = $(LDADD) -lrt kms_flip_LDADD = $(LDADD) -lrt -lpthread
tests/Makefile.sources +1 -0
@@ -215,6 +215,7 @@ TESTS_progs = \ kms_vblank \ meta_test \ perf \ + perf_pmu \ pm_backlight \ pm_lpsp \ pm_rc6_residency \
tests/meson.build +1 -0
@@ -195,6 +195,7 @@ test_progs = [ 'kms_vblank', 'meta_test', 'perf', + 'perf_pmu', 'pm_backlight', 'pm_lpsp', 'pm_rc6_residency',
tests/perf_pmu.c new file +1242 -0
1,242 lines not on this page · raw message
Signature · 6 lines
2.14.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v9 7/9 tests/perf_pmu: Tests for i915 PMU API
From: Tvrtko Ursulin <[email protected]>
A bunch of tests for the new i915 PMU feature.
Parts of the code were initialy sketched by Dmitry Rogozhkin.
v2: (Most suggestions by Chris Wilson)
* Add new class/instance based engine list.
* Add gem_has_engine/gem_require_engine to work with class/instance.
* Use the above two throughout the test.
* Shorten tests to 100ms busy batches, seems enough.
* Add queued counter sanity checks.
* Use igt_nsec_elapsed.
* Skip on perf -ENODEV in some tests instead of embedding knowledge locally.
* Fix multi ordering for busy accounting.
* Use new guranteed_usleep when sleep time is asserted on.
* Check for no queued when idle/busy.
* Add queued counter init test.
* Add queued tests.
* Consolidate and increase multiple busy engines tests to most-busy and all-busy tests.
* Guarantte interrupts by using fences.
* Test RC6 via forcewake.
v3:
* Tweak assert in interrupts subtest.
* Sprinkle of comments.
* Fix multi-client test which got broken in v2.
v4:
* Measured instead of guaranteed sleep.
* Missing sync in no_sema.
* Log busyness before asserts for debug.
* access(2) instead of open(2) to determine if cpu0 is hotpluggable.
* Test frequency reporting via min/max setting instead assuming. ^^ All above suggested by Chris Wilson. ^^
* Drop queued subtests to match i915.
* Use long batches with fences to ensure interrupts.
* Test render node as well.
v5:
* Add to meson build. (Petri Latvala)
* Use 1eN constants. (Chris Wilson)
* Add tests for semaphore and event waiting.
v6:
* Fix interrupts subtest by polling the fence from the "outside". (Chris Wilson)
v7:
* Assert number of initialized engines matches the expectation. (Chris Wilson)
* Warn instead of skipping if we couldn't restore the initial frequency. (Chris Wilson)
* Move all asserts to after the test cleanup (just a tidy).
* More 1eN notation for timeouts.
* Bump the tolerance to 5% since I saw a few noisy runs with sampling counters.
* Always start the PMU before submitting batches to lower reliance on i915 doing the delayed engine busy stats disable.
v8:
* Update for upstream engine class enum.
v9:
* Add meson build support.
--- lib/igt_gt.c | 50 ++ lib/igt_gt.h | 38 ++ lib/igt_perf.h | 9 +- tests/Makefile.am | 1 + tests/Makefile.sources | 1 + tests/meson.build | 6 + tests/perf_pmu.c | 1242 ++++++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 1339 insertions(+), 8 deletions(-) create mode 100644 tests/perf_pmu.c
lib/igt_gt.c +50 -0
@@ -608,3 +608,53 @@ bool gem_can_store_dword(int fd, unsigned int engine)return true; } + +const struct intel_execution_engine2 intel_execution_engines2[] = { + {"rcs0" ,I915_ENGINE_CLASS_RENDER ,0 }, + {"bcs0" ,I915_ENGINE_CLASS_COPY ,0 }, + {"vcs0" ,I915_ENGINE_CLASS_VIDEO ,0 }, + {"vcs1" ,I915_ENGINE_CLASS_VIDEO ,1 }, + {"vecs0" ,I915_ENGINE_CLASS_VIDEO_ENHANCE ,0 }, +}; + +unsigned int +gem_class_instance_to_eb_flags (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance) +{ +if (class !=I915_ENGINE_CLASS_VIDEO ) +igt_assert (instance ==0 ); +else +igt_assert (instance >=0 && instance <=1 ); + +switch (class) { +case I915_ENGINE_CLASS_RENDER : +return I915_EXEC_RENDER ; +case I915_ENGINE_CLASS_COPY : +return I915_EXEC_BLT ; +case I915_ENGINE_CLASS_VIDEO : +if (instance ==0 ) { +if (gem_has_bsd2 (gem_fd)) +return I915_EXEC_BSD |I915_EXEC_BSD_RING1 ; +else +return I915_EXEC_BSD ; + + }else { +return I915_EXEC_BSD |I915_EXEC_BSD_RING2 ; + } +case I915_ENGINE_CLASS_VIDEO_ENHANCE : +return I915_EXEC_VEBOX ; +case I915_ENGINE_CLASS_INVALID : +default : +igt_assert (0 ); + }; +} + +bool gem_has_engine (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance) +{ +return gem_has_ring (gem_fd, +gem_class_instance_to_eb_flags (gem_fd, class, + instance)); +}
lib/igt_gt.h +38 -0
@@ -25,6 +25,7 @@#define IGT_GT_H #include "igt_debugfs.h" +#include "igt_core.h" void igt_require_hang_ring (int fd,int ring);
@@ -80,4 +81,41 @@ extern const struct intel_execution_engine {bool gem_can_store_dword (int fd,unsigned int engine); +extern const struct intel_execution_engine2 { +const char *name; +int class; +int instance; +} intel_execution_engines2[]; + +#define for_each_engine_class_instance (fd__, e__) \ + for ((e__) = intel_execution_engines2;\ + (e__)->name; \ + (e__)++) + +enum drm_i915_gem_engine_class { +I915_ENGINE_CLASS_RENDER =0 , +I915_ENGINE_CLASS_COPY =1 , +I915_ENGINE_CLASS_VIDEO =2 , +I915_ENGINE_CLASS_VIDEO_ENHANCE =3 , + +I915_ENGINE_CLASS_INVALID =-1 +}; + +unsigned int +gem_class_instance_to_eb_flags (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance); + +bool gem_has_engine (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance); + +static inline +void gem_require_engine (int gem_fd, +enum drm_i915_gem_engine_class class, +unsigned int instance) +{ +igt_require (gem_has_engine (gem_fd, class, instance)); +} +#endif /* IGT_GT_H */
lib/igt_perf.h +1 -8
@@ -29,14 +29,7 @@#include <linux/perf_event.h> -enum drm_i915_gem_engine_class { -I915_ENGINE_CLASS_RENDER =0 , -I915_ENGINE_CLASS_COPY =1 , -I915_ENGINE_CLASS_VIDEO =2 , -I915_ENGINE_CLASS_VIDEO_ENHANCE =3 , - -I915_ENGINE_CLASS_INVALID =-1 -}; +#include "igt_gt.h" enum drm_i915_pmu_engine_sample {I915_SAMPLE_BUSY =0 ,
tests/Makefile.am +1 -0
@@ -131,6 +131,7 @@ gen7_forcewake_mt_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gen7_forcewake_mt_LDADD = $(LDADD) -lpthread gem_userptr_blits_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_userptr_blits_LDADD = $(LDADD) -lpthread +perf_pmu_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la gem_wait_LDADD = $(LDADD) -lrt kms_flip_LDADD = $(LDADD) -lrt -lpthread
tests/Makefile.sources +1 -0
@@ -215,6 +215,7 @@ TESTS_progs = \ kms_vblank \ meta_test \ perf \ + perf_pmu \ pm_backlight \ pm_lpsp \ pm_rc6_residency \
tests/meson.build +6 -0
@@ -195,6 +195,7 @@ test_progs = [ 'kms_vblank', 'meta_test', 'perf', + 'perf_pmu', 'pm_backlight', 'pm_lpsp', 'pm_rc6_residency',
@@ -266,9 +267,14 @@ endif libexecdir = join_paths(get_option('prefix'), get_option('libexecdir'), 'intel-gpu-tools') foreach prog : test_progs + link = [] + if prog == 'perf_pmu' + link += lib_igt_perf + endif executable(prog, prog + '.c', dependencies : test_deps, install_dir : libexecdir, + link_with : link, install : true) endforeach
tests/perf_pmu.c new file +1242 -0
1,242 lines not on this page · raw message
Signature · 6 lines
2.14.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 8/9 gem_wsim: Busy stats balancers
In reply to Tvrtko UrsulinFrom: Tvrtko Ursulin <[email protected]>
Add busy and busy-avg balancers which make balancing decisions by looking at engine busyness via the i915 PMU.
And thus are able to make decisions on the actual instantaneous load of the system, and not use metrics that lag behind by a batch or two. In doing so, each client should be able to greedily maximise their own usage of the system, leading to improved load balancing even in the face of other uncooperative clients. On the other hand, we are only using the instantaneous load without coupling in the predictive factor for dispatch and execution length.
v2:
* Commit text. (Chris Wilson)
* Rename get_stats to get_pmu_stats. (Chris Wilson)
* Fix PMU readout in VCS remap mode.
--- benchmarks/Makefile.am | 2 +- benchmarks/gem_wsim.c | 142 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 143 insertions(+), 1 deletion(-)
benchmarks/Makefile.am +1 -1
@@ -21,7 +21,7 @@ gem_latency_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_latency_LDADD = $(LDADD) -lpthread gem_syslatency_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_syslatency_LDADD = $(LDADD) -lpthread -lrt -gem_wsim_LDADD = $(LDADD) -lpthread +gem_wsim_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la -lpthread EXTRA_DIST= \ README \
benchmarks/gem_wsim.c +142 -0
178 lines not on this page · raw message
Signature · 6 lines
2.9.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v3 8/9 gem_wsim: Busy stats balancers
From: Tvrtko Ursulin <[email protected]>
Add busy and busy-avg balancers which make balancing decisions by looking at engine busyness via the i915 PMU.
And thus are able to make decisions on the actual instantaneous load of the system, and not use metrics that lag behind by a batch or two. In doing so, each client should be able to greedily maximise their own usage of the system, leading to improved load balancing even in the face of other uncooperative clients. On the other hand, we are only using the instantaneous load without coupling in the predictive factor for dispatch and execution length.
v2:
* Commit text. (Chris Wilson)
* Rename get_stats to get_pmu_stats. (Chris Wilson)
* Fix PMU readout in VCS remap mode.
v3:
* Integrated Petri's meson build recipe.
--- benchmarks/Makefile.am | 2 +- benchmarks/gem_wsim.c | 142 +++++++++++++++++++++++++++++++++++++++++++++++++ benchmarks/meson.build | 7 ++- 3 files changed, 149 insertions(+), 2 deletions(-)
benchmarks/Makefile.am +1 -1
@@ -21,7 +21,7 @@ gem_latency_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_latency_LDADD = $(LDADD) -lpthread gem_syslatency_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_syslatency_LDADD = $(LDADD) -lpthread -lrt -gem_wsim_LDADD = $(LDADD) -lpthread +gem_wsim_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la -lpthread EXTRA_DIST= \ README \
benchmarks/gem_wsim.c +142 -0
178 lines not on this page · raw message
benchmarks/meson.build +6 -1
@@ -31,6 +31,11 @@ endif foreach prog : benchmark_progs # FIXME meson doesn't like binaries with the same name # meanwhile just suffix with _bench + link = [] + if prog == 'gem_wsim' + link += lib_igt_perf + endif executable(prog + '_bench', prog + '.c', - dependencies : test_deps) + link_with : link, + dependencies : test_deps) endforeach
Signature · 6 lines
2.14.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 9/9 media-bench.pl: Add busy balancers to the list
In reply to Tvrtko UrsulinFrom: Tvrtko Ursulin <[email protected]>
--- scripts/media-bench.pl | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
scripts/media-bench.pl +3 -2
@@ -47,8 +47,9 @@ my $nop; my %opts; my @balancers = ( 'rr', 'rand', 'qd', 'qdr', 'qdavg', 'rt', 'rtr', 'rtavg', - 'context' ); -my %bal_skip_H = ( 'rr' => 1, 'rand' => 1, 'context' => 1 ); + 'context', 'busy', 'busy-avg' ); +my %bal_skip_H = ( 'rr' => 1, 'rand' => 1, 'context' => 1, , 'busy' => 1, + 'busy-avg' => 1 ); my %bal_skip_R = ( 'context' => 1 ); my @workloads = (
Signature · 6 lines
2.9.5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH i-g-t 9/9] media-bench.pl: Add busy balancers to the list
Quoting Tvrtko Ursulin (2017-10-10 10:30:08)
Quoted 3 lines
From: Tvrtko Ursulin <[email protected]>
Signed-off-by Tvrtko Ursulin <[email protected]>
-Chris
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Patchwork
CI✗ Fi.CI.BAT: failure for IGT PMU support (rev7)
In reply to Tvrtko Ursulin== Series Details ==
== Series Details ==
Series: IGT PMU support (rev7)
URL : https://patchwork.freedesktop.org/series/28253/
State : failure
== Summary ==
IGT patchset build failed on latest successful build d7c88290ab6a8393dc341b30c7fb5e27d2952901 syncobj: Add a test for SYNCOBJ_CREATE_SIGNALED
make all-recursive
Making all in lib
make all-recursive
Making all in .
Making all in tests
make[4]: Nothing to be done for 'all'.
Making all in man
make[2]: Nothing to be done for 'all'.
Making all in tools
Making all in null_state_gen
make[3]: Nothing to be done for 'all'.
Making all in registers
make[3]: Nothing to be done for 'all'.
make[3]: Nothing to be done for 'all-am'.
Making all in scripts
make[2]: Nothing to be done for 'all'.
Making all in benchmarks
Making all in wsim
make[3]: Nothing to be done for 'all'.
Making all in ezbench.d
make[3]: Nothing to be done for 'all'.
make[3]: Nothing to be done for 'all-am'.
Making all in tests
Making all in intel-ci
make[3]: Nothing to be done for 'all'.
make[3]: Nothing to be done for 'all-am'.
Making all in assembler
make all-recursive
Making all in doc
make[4]: Nothing to be done for 'all'.
Making all in test
make[4]: Nothing to be done for 'all'.
make[4]: Nothing to be done for 'all-am'.
Making all in overlay
CCLD intel-gpu-overlay/usr/bin/ld: power.o: undefined reference to symbol 'llround@@GLIBC_2.2.5' //lib/x86_64-linux-gnu/libm.so.6: error adding symbols: DSO missing from command line
collect2: error: ld returned 1 exit status
Makefile:564: recipe for target 'intel-gpu-overlay' failed
make[2]: *** [intel-gpu-overlay] Error 1
Makefile:533: recipe for target 'all-recursive' failed
make[1]: *** [all-recursive] Error 1
Makefile:465: recipe for target 'all' failed
make: *** [all] Error 2
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Patchwork
CI✓ Fi.CI.BAT: success for IGT PMU support (rev8)
In reply to Tvrtko Ursulin== Series Details ==
== Series Details ==
Series: IGT PMU support (rev8)
URL : https://patchwork.freedesktop.org/series/28253/
State : success
== Summary ==
IGT patchset tested on top of latest successful build d7c88290ab6a8393dc341b30c7fb5e27d2952901 syncobj: Add a test for SYNCOBJ_CREATE_SIGNALED
with latest DRM-Tip kernel build CI_DRM_32026bcaf2275e52 drm-tip: 2017y-10m-10d-10h-57m-51s UTC integration manifest
Testlist changes:
+igt@perf_pmu@all-busy-check-all
+igt@perf_pmu@busy-bcs0
+igt@perf_pmu@busy-check-all-bcs0
+igt@perf_pmu@busy-check-all-rcs0
+igt@perf_pmu@busy-check-all-vcs0
+igt@perf_pmu@busy-check-all-vcs1
+igt@perf_pmu@busy-check-all-vecs0
+igt@perf_pmu@busy-no-semaphores-bcs0
+igt@perf_pmu@busy-no-semaphores-rcs0
+igt@perf_pmu@busy-no-semaphores-vcs0
+igt@perf_pmu@busy-no-semaphores-vcs1
+igt@perf_pmu@busy-no-semaphores-vecs0
+igt@perf_pmu@busy-rcs0
+igt@perf_pmu@busy-vcs0
+igt@perf_pmu@busy-vcs1
+igt@perf_pmu@busy-vecs0
+igt@perf_pmu@cpu-hotplug
+igt@perf_pmu@event-wait-rcs0
+igt@perf_pmu@frequency
+igt@perf_pmu@idle-bcs0
+igt@perf_pmu@idle-no-semaphores-bcs0
+igt@perf_pmu@idle-no-semaphores-rcs0
+igt@perf_pmu@idle-no-semaphores-vcs0
+igt@perf_pmu@idle-no-semaphores-vcs1
+igt@perf_pmu@idle-no-semaphores-vecs0
+igt@perf_pmu@idle-rcs0
+igt@perf_pmu@idle-vcs0
+igt@perf_pmu@idle-vcs1
+igt@perf_pmu@idle-vecs0
+igt@perf_pmu@init-busy-bcs0
+igt@perf_pmu@init-busy-rcs0
+igt@perf_pmu@init-busy-vcs0
+igt@perf_pmu@init-busy-vcs1
+igt@perf_pmu@init-busy-vecs0
+igt@perf_pmu@init-sema-bcs0
+igt@perf_pmu@init-sema-rcs0
+igt@perf_pmu@init-sema-vcs0
+igt@perf_pmu@init-sema-vcs1
+igt@perf_pmu@init-sema-vecs0
+igt@perf_pmu@init-wait-bcs0
+igt@perf_pmu@init-wait-rcs0
+igt@perf_pmu@init-wait-vcs0
+igt@perf_pmu@init-wait-vcs1
+igt@perf_pmu@init-wait-vecs0
+igt@perf_pmu@interrupts
+igt@perf_pmu@invalid-init
+igt@perf_pmu@most-busy-check-all-bcs0
+igt@perf_pmu@most-busy-check-all-rcs0
+igt@perf_pmu@most-busy-check-all-vcs0
+igt@perf_pmu@most-busy-check-all-vcs1
+igt@perf_pmu@most-busy-check-all-vecs0
+igt@perf_pmu@multi-client-bcs0
+igt@perf_pmu@multi-client-rcs0
+igt@perf_pmu@multi-client-vcs0
+igt@perf_pmu@multi-client-vcs1
+igt@perf_pmu@multi-client-vecs0
+igt@perf_pmu@other-init-0
+igt@perf_pmu@other-init-1
+igt@perf_pmu@other-init-2
+igt@perf_pmu@other-init-3
+igt@perf_pmu@other-init-4
+igt@perf_pmu@other-init-5
+igt@perf_pmu@other-init-6
+igt@perf_pmu@other-read-0
+igt@perf_pmu@other-read-1
+igt@perf_pmu@other-read-2
+igt@perf_pmu@other-read-3
+igt@perf_pmu@other-read-4
+igt@perf_pmu@other-read-5
+igt@perf_pmu@other-read-6
+igt@perf_pmu@rc6
+igt@perf_pmu@rc6p
+igt@perf_pmu@render-node-busy-bcs0
+igt@perf_pmu@render-node-busy-rcs0
+igt@perf_pmu@render-node-busy-vcs0
+igt@perf_pmu@render-node-busy-vcs1
+igt@perf_pmu@render-node-busy-vecs0
+igt@perf_pmu@semaphore-wait-bcs0
+igt@perf_pmu@semaphore-wait-rcs0
+igt@perf_pmu@semaphore-wait-vcs0
+igt@perf_pmu@semaphore-wait-vcs1
+igt@perf_pmu@semaphore-wait-vecs0
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (fi-byt-n2820) fdo#101705fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:461s fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:479s fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:396s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:570s fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:286s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:523s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:524s fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:534s fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:536s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:564s fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:634s fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:427s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:600s fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:445s fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:422s fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:466s fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:510s fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:478s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:500s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:584s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:490s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:589s fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:659s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:474s fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:660s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:540s fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:517s fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:475s fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:583s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:438s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_310/
_______________________________________________
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Patchwork
CI✓ Fi.CI.BAT: success for IGT PMU support (rev9)
In reply to Tvrtko Ursulin== Series Details ==
== Series Details ==
Series: IGT PMU support (rev9)
URL : https://patchwork.freedesktop.org/series/28253/
State : success
== Summary ==
IGT patchset tested on top of latest successful build d7c88290ab6a8393dc341b30c7fb5e27d2952901 syncobj: Add a test for SYNCOBJ_CREATE_SIGNALED
with latest DRM-Tip kernel build CI_DRM_32026bcaf2275e52 drm-tip: 2017y-10m-10d-10h-57m-51s UTC integration manifest
Testlist changes:
+igt@perf_pmu@all-busy-check-all
+igt@perf_pmu@busy-bcs0
+igt@perf_pmu@busy-check-all-bcs0
+igt@perf_pmu@busy-check-all-rcs0
+igt@perf_pmu@busy-check-all-vcs0
+igt@perf_pmu@busy-check-all-vcs1
+igt@perf_pmu@busy-check-all-vecs0
+igt@perf_pmu@busy-no-semaphores-bcs0
+igt@perf_pmu@busy-no-semaphores-rcs0
+igt@perf_pmu@busy-no-semaphores-vcs0
+igt@perf_pmu@busy-no-semaphores-vcs1
+igt@perf_pmu@busy-no-semaphores-vecs0
+igt@perf_pmu@busy-rcs0
+igt@perf_pmu@busy-vcs0
+igt@perf_pmu@busy-vcs1
+igt@perf_pmu@busy-vecs0
+igt@perf_pmu@cpu-hotplug
+igt@perf_pmu@event-wait-rcs0
+igt@perf_pmu@frequency
+igt@perf_pmu@idle-bcs0
+igt@perf_pmu@idle-no-semaphores-bcs0
+igt@perf_pmu@idle-no-semaphores-rcs0
+igt@perf_pmu@idle-no-semaphores-vcs0
+igt@perf_pmu@idle-no-semaphores-vcs1
+igt@perf_pmu@idle-no-semaphores-vecs0
+igt@perf_pmu@idle-rcs0
+igt@perf_pmu@idle-vcs0
+igt@perf_pmu@idle-vcs1
+igt@perf_pmu@idle-vecs0
+igt@perf_pmu@init-busy-bcs0
+igt@perf_pmu@init-busy-rcs0
+igt@perf_pmu@init-busy-vcs0
+igt@perf_pmu@init-busy-vcs1
+igt@perf_pmu@init-busy-vecs0
+igt@perf_pmu@init-sema-bcs0
+igt@perf_pmu@init-sema-rcs0
+igt@perf_pmu@init-sema-vcs0
+igt@perf_pmu@init-sema-vcs1
+igt@perf_pmu@init-sema-vecs0
+igt@perf_pmu@init-wait-bcs0
+igt@perf_pmu@init-wait-rcs0
+igt@perf_pmu@init-wait-vcs0
+igt@perf_pmu@init-wait-vcs1
+igt@perf_pmu@init-wait-vecs0
+igt@perf_pmu@interrupts
+igt@perf_pmu@invalid-init
+igt@perf_pmu@most-busy-check-all-bcs0
+igt@perf_pmu@most-busy-check-all-rcs0
+igt@perf_pmu@most-busy-check-all-vcs0
+igt@perf_pmu@most-busy-check-all-vcs1
+igt@perf_pmu@most-busy-check-all-vecs0
+igt@perf_pmu@multi-client-bcs0
+igt@perf_pmu@multi-client-rcs0
+igt@perf_pmu@multi-client-vcs0
+igt@perf_pmu@multi-client-vcs1
+igt@perf_pmu@multi-client-vecs0
+igt@perf_pmu@other-init-0
+igt@perf_pmu@other-init-1
+igt@perf_pmu@other-init-2
+igt@perf_pmu@other-init-3
+igt@perf_pmu@other-init-4
+igt@perf_pmu@other-init-5
+igt@perf_pmu@other-init-6
+igt@perf_pmu@other-read-0
+igt@perf_pmu@other-read-1
+igt@perf_pmu@other-read-2
+igt@perf_pmu@other-read-3
+igt@perf_pmu@other-read-4
+igt@perf_pmu@other-read-5
+igt@perf_pmu@other-read-6
+igt@perf_pmu@rc6
+igt@perf_pmu@rc6p
+igt@perf_pmu@render-node-busy-bcs0
+igt@perf_pmu@render-node-busy-rcs0
+igt@perf_pmu@render-node-busy-vcs0
+igt@perf_pmu@render-node-busy-vcs1
+igt@perf_pmu@render-node-busy-vecs0
+igt@perf_pmu@semaphore-wait-bcs0
+igt@perf_pmu@semaphore-wait-rcs0
+igt@perf_pmu@semaphore-wait-vcs0
+igt@perf_pmu@semaphore-wait-vcs1
+igt@perf_pmu@semaphore-wait-vecs0
Test gem_exec_suspend:
Subgroup basic-s3:
dmesg-warn -> PASS (fi-cfl-s) fdo#103026
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (fi-byt-n2820) fdo#101705fdo#103026 https://bugs.freedesktop.org/show_bug.cgi?id=103026
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:455s fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:475s fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:397s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:562s fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:286s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:523s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:528s fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:538s fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:528s fi-cfl-s total:289 pass:257 dwarn:0 dfail:0 fail:0 skip:32 time:570s fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:630s fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:438s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:599s fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:441s fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:416s fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:464s fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:510s fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:480s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:506s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:586s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:490s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:596s fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:660s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:467s fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:656s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:532s fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:522s fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:477s fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:585s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:435s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_311/
_______________________________________________
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Patchwork
CI✗ Fi.CI.IGT: failure for IGT PMU support (rev8)
In reply to Tvrtko Ursulin== Series Details ==
== Series Details ==
Series: IGT PMU support (rev8)
URL : https://patchwork.freedesktop.org/series/28253/
State : failure
== Summary ==
Test gem_eio:
Subgroup wait:
pass -> DMESG-WARN (shard-hsw) fdo#102886 +2
Test drv_module_reload:
Subgroup basic-no-display:
pass -> DMESG-WARN (shard-hsw) fdo#102707
Test kms_flip_tiling:
Subgroup flip-to-Yf-tiled:
skip -> INCOMPLETE (shard-hsw)fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707
shard-hsw total:2634 pass:1402 dwarn:7 dfail:0 fail:13 skip:1159 time:9342s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_310/shards.html
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Patchwork
CI✓ Fi.CI.BAT: success for IGT PMU support (rev11)
In reply to Tvrtko Ursulin== Series Details ==
== Series Details ==
Series: IGT PMU support (rev11)
URL : https://patchwork.freedesktop.org/series/28253/
State : success
== Summary ==
IGT patchset tested on top of latest successful build d7c88290ab6a8393dc341b30c7fb5e27d2952901 syncobj: Add a test for SYNCOBJ_CREATE_SIGNALED
with latest DRM-Tip kernel build CI_DRM_3206cc58e6d2bc38 drm-tip: 2017y-10m-10d-15h-40m-22s UTC integration manifest
Testlist changes:
+igt@perf_pmu@all-busy-check-all
+igt@perf_pmu@busy-bcs0
+igt@perf_pmu@busy-check-all-bcs0
+igt@perf_pmu@busy-check-all-rcs0
+igt@perf_pmu@busy-check-all-vcs0
+igt@perf_pmu@busy-check-all-vcs1
+igt@perf_pmu@busy-check-all-vecs0
+igt@perf_pmu@busy-no-semaphores-bcs0
+igt@perf_pmu@busy-no-semaphores-rcs0
+igt@perf_pmu@busy-no-semaphores-vcs0
+igt@perf_pmu@busy-no-semaphores-vcs1
+igt@perf_pmu@busy-no-semaphores-vecs0
+igt@perf_pmu@busy-rcs0
+igt@perf_pmu@busy-vcs0
+igt@perf_pmu@busy-vcs1
+igt@perf_pmu@busy-vecs0
+igt@perf_pmu@cpu-hotplug
+igt@perf_pmu@event-wait-rcs0
+igt@perf_pmu@frequency
+igt@perf_pmu@idle-bcs0
+igt@perf_pmu@idle-no-semaphores-bcs0
+igt@perf_pmu@idle-no-semaphores-rcs0
+igt@perf_pmu@idle-no-semaphores-vcs0
+igt@perf_pmu@idle-no-semaphores-vcs1
+igt@perf_pmu@idle-no-semaphores-vecs0
+igt@perf_pmu@idle-rcs0
+igt@perf_pmu@idle-vcs0
+igt@perf_pmu@idle-vcs1
+igt@perf_pmu@idle-vecs0
+igt@perf_pmu@init-busy-bcs0
+igt@perf_pmu@init-busy-rcs0
+igt@perf_pmu@init-busy-vcs0
+igt@perf_pmu@init-busy-vcs1
+igt@perf_pmu@init-busy-vecs0
+igt@perf_pmu@init-sema-bcs0
+igt@perf_pmu@init-sema-rcs0
+igt@perf_pmu@init-sema-vcs0
+igt@perf_pmu@init-sema-vcs1
+igt@perf_pmu@init-sema-vecs0
+igt@perf_pmu@init-wait-bcs0
+igt@perf_pmu@init-wait-rcs0
+igt@perf_pmu@init-wait-vcs0
+igt@perf_pmu@init-wait-vcs1
+igt@perf_pmu@init-wait-vecs0
+igt@perf_pmu@interrupts
+igt@perf_pmu@invalid-init
+igt@perf_pmu@most-busy-check-all-bcs0
+igt@perf_pmu@most-busy-check-all-rcs0
+igt@perf_pmu@most-busy-check-all-vcs0
+igt@perf_pmu@most-busy-check-all-vcs1
+igt@perf_pmu@most-busy-check-all-vecs0
+igt@perf_pmu@multi-client-bcs0
+igt@perf_pmu@multi-client-rcs0
+igt@perf_pmu@multi-client-vcs0
+igt@perf_pmu@multi-client-vcs1
+igt@perf_pmu@multi-client-vecs0
+igt@perf_pmu@other-init-0
+igt@perf_pmu@other-init-1
+igt@perf_pmu@other-init-2
+igt@perf_pmu@other-init-3
+igt@perf_pmu@other-init-4
+igt@perf_pmu@other-init-5
+igt@perf_pmu@other-init-6
+igt@perf_pmu@other-read-0
+igt@perf_pmu@other-read-1
+igt@perf_pmu@other-read-2
+igt@perf_pmu@other-read-3
+igt@perf_pmu@other-read-4
+igt@perf_pmu@other-read-5
+igt@perf_pmu@other-read-6
+igt@perf_pmu@rc6
+igt@perf_pmu@rc6p
+igt@perf_pmu@render-node-busy-bcs0
+igt@perf_pmu@render-node-busy-rcs0
+igt@perf_pmu@render-node-busy-vcs0
+igt@perf_pmu@render-node-busy-vcs1
+igt@perf_pmu@render-node-busy-vecs0
+igt@perf_pmu@semaphore-wait-bcs0
+igt@perf_pmu@semaphore-wait-rcs0
+igt@perf_pmu@semaphore-wait-vcs0
+igt@perf_pmu@semaphore-wait-vcs1
+igt@perf_pmu@semaphore-wait-vecs0
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS (fi-kbl-7560u) fdo#102846 +1
Test drv_module_reload:
Subgroup basic-reload-inject:
dmesg-warn -> INCOMPLETE (fi-cfl-s) fdo#103022fdo#102846 https://bugs.freedesktop.org/show_bug.cgi?id=102846
fdo#103022 https://bugs.freedesktop.org/show_bug.cgi?id=103022
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:458s fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:478s fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:396s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:578s fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:284s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:529s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:527s fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:537s fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:530s fi-cfl-s total:288 pass:253 dwarn:3 dfail:0 fail:0 skip:31 fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:634s fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:436s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:606s fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:440s fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:421s fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:464s fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:508s fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:476s fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:495s fi-kbl-7560u total:247 pass:230 dwarn:0 dfail:0 fail:0 skip:16 fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:486s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:589s fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:665s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:476s fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:664s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:535s fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:516s fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:471s fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:586s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:440s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_314/
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Patchwork
CI✓ Fi.CI.IGT: success for IGT PMU support (rev11)
In reply to Tvrtko Ursulin== Series Details ==
== Series Details ==
Series: IGT PMU support (rev11)
URL : https://patchwork.freedesktop.org/series/28253/
State : success
== Summary ==
Test kms_flip:
Subgroup flip-vs-fences-interruptible:
pass -> FAIL (shard-hsw) fdo#102946
Test drv_module_reload:
Subgroup basic-no-display:
pass -> DMESG-WARN (shard-hsw) fdo#102707
Test gem_eio:
Subgroup in-flight-contexts:
pass -> DMESG-WARN (shard-hsw) fdo#102886 +2
Test gem_flink_race:
Subgroup flink_close:
pass -> FAIL (shard-hsw) fdo#102655fdo#102946 https://bugs.freedesktop.org/show_bug.cgi?id=102946
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707
fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886
fdo#102655 https://bugs.freedesktop.org/show_bug.cgi?id=102655
shard-hsw total:2634 pass:1427 dwarn:7 dfail:0 fail:15 skip:1185 time:9631s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_314/shards.html
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Patchwork
CI✓ Fi.CI.BAT: success for IGT PMU support (rev12)
In reply to Tvrtko Ursulin== Series Details ==
== Series Details ==
Series: IGT PMU support (rev12)
URL : https://patchwork.freedesktop.org/series/28253/
State : success
== Summary ==
IGT patchset tested on top of latest successful build 136100c2f00b590bc9485100cce012282c1217cf igt/syncobj_wait: Don't close the timeline early in wait_snapshot
with latest DRM-Tip kernel build CI_DRM_321336e0e803d3d7 drm-tip: 2017y-10m-11d-11h-31m-33s UTC integration manifest
Testlist changes:
+igt@perf_pmu@all-busy-check-all
+igt@perf_pmu@busy-bcs0
+igt@perf_pmu@busy-check-all-bcs0
+igt@perf_pmu@busy-check-all-rcs0
+igt@perf_pmu@busy-check-all-vcs0
+igt@perf_pmu@busy-check-all-vcs1
+igt@perf_pmu@busy-check-all-vecs0
+igt@perf_pmu@busy-no-semaphores-bcs0
+igt@perf_pmu@busy-no-semaphores-rcs0
+igt@perf_pmu@busy-no-semaphores-vcs0
+igt@perf_pmu@busy-no-semaphores-vcs1
+igt@perf_pmu@busy-no-semaphores-vecs0
+igt@perf_pmu@busy-rcs0
+igt@perf_pmu@busy-vcs0
+igt@perf_pmu@busy-vcs1
+igt@perf_pmu@busy-vecs0
+igt@perf_pmu@cpu-hotplug
+igt@perf_pmu@event-wait-rcs0
+igt@perf_pmu@frequency
+igt@perf_pmu@idle-bcs0
+igt@perf_pmu@idle-no-semaphores-bcs0
+igt@perf_pmu@idle-no-semaphores-rcs0
+igt@perf_pmu@idle-no-semaphores-vcs0
+igt@perf_pmu@idle-no-semaphores-vcs1
+igt@perf_pmu@idle-no-semaphores-vecs0
+igt@perf_pmu@idle-rcs0
+igt@perf_pmu@idle-vcs0
+igt@perf_pmu@idle-vcs1
+igt@perf_pmu@idle-vecs0
+igt@perf_pmu@init-busy-bcs0
+igt@perf_pmu@init-busy-rcs0
+igt@perf_pmu@init-busy-vcs0
+igt@perf_pmu@init-busy-vcs1
+igt@perf_pmu@init-busy-vecs0
+igt@perf_pmu@init-sema-bcs0
+igt@perf_pmu@init-sema-rcs0
+igt@perf_pmu@init-sema-vcs0
+igt@perf_pmu@init-sema-vcs1
+igt@perf_pmu@init-sema-vecs0
+igt@perf_pmu@init-wait-bcs0
+igt@perf_pmu@init-wait-rcs0
+igt@perf_pmu@init-wait-vcs0
+igt@perf_pmu@init-wait-vcs1
+igt@perf_pmu@init-wait-vecs0
+igt@perf_pmu@interrupts
+igt@perf_pmu@invalid-init
+igt@perf_pmu@most-busy-check-all-bcs0
+igt@perf_pmu@most-busy-check-all-rcs0
+igt@perf_pmu@most-busy-check-all-vcs0
+igt@perf_pmu@most-busy-check-all-vcs1
+igt@perf_pmu@most-busy-check-all-vecs0
+igt@perf_pmu@multi-client-bcs0
+igt@perf_pmu@multi-client-rcs0
+igt@perf_pmu@multi-client-vcs0
+igt@perf_pmu@multi-client-vcs1
+igt@perf_pmu@multi-client-vecs0
+igt@perf_pmu@other-init-0
+igt@perf_pmu@other-init-1
+igt@perf_pmu@other-init-2
+igt@perf_pmu@other-init-3
+igt@perf_pmu@other-init-4
+igt@perf_pmu@other-init-5
+igt@perf_pmu@other-init-6
+igt@perf_pmu@other-read-0
+igt@perf_pmu@other-read-1
+igt@perf_pmu@other-read-2
+igt@perf_pmu@other-read-3
+igt@perf_pmu@other-read-4
+igt@perf_pmu@other-read-5
+igt@perf_pmu@other-read-6
+igt@perf_pmu@rc6
+igt@perf_pmu@rc6p
+igt@perf_pmu@render-node-busy-bcs0
+igt@perf_pmu@render-node-busy-rcs0
+igt@perf_pmu@render-node-busy-vcs0
+igt@perf_pmu@render-node-busy-vcs1
+igt@perf_pmu@render-node-busy-vecs0
+igt@perf_pmu@semaphore-wait-bcs0
+igt@perf_pmu@semaphore-wait-rcs0
+igt@perf_pmu@semaphore-wait-vcs0
+igt@perf_pmu@semaphore-wait-vcs1
+igt@perf_pmu@semaphore-wait-vecs0
Test chamelium:
Subgroup dp-crc-fast:
pass -> FAIL (fi-kbl-7500u) fdo#102514fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:455s fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:475s fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:389s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:574s fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:287s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:532s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:526s fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:537s fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:522s fi-cfl-s total:289 pass:253 dwarn:4 dfail:0 fail:0 skip:32 time:562s fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:633s fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:437s fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:274s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:597s fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:440s fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:475s fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:505s fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:474s fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:500s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:586s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:488s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:597s fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:661s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:474s fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:652s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:539s fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:512s fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:473s fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:583s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:429s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_329/
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Patchwork
CI✗ Fi.CI.IGT: failure for IGT PMU support (rev12)
In reply to Tvrtko Ursulin== Series Details ==
== Series Details ==
Series: IGT PMU support (rev12)
URL : https://patchwork.freedesktop.org/series/28253/
State : failure
== Summary ==
Test gem_eio:
Subgroup in-flight:
dmesg-warn -> PASS (shard-hsw) fdo#102886 +1
Test gem_tiled_swapping:
Subgroup non-threaded:
pass -> DMESG-WARN (shard-hsw)
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
Test kms_atomic:
Subgroup atomic_invalid_params:
pass -> SKIP (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-indfb-fliptrack:
pass -> SKIP (shard-hsw)
Test kms_chv_cursor_fail:
Subgroup pipe-C-64x64-bottom-edge:
pass -> SKIP (shard-hsw)
Test gem_flink_race:
Subgroup flink_close:
pass -> FAIL (shard-hsw) fdo#102655
Test gem_exec_store:
Subgroup pages-render:
pass -> FAIL (shard-hsw)
Test kms_flip:
Subgroup flip-vs-rmfb:
pass -> DMESG-WARN (shard-hsw)fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102655 https://bugs.freedesktop.org/show_bug.cgi?id=102655
shard-hsw total:2581 pass:1396 dwarn:7 dfail:0 fail:10 skip:1168 time:9317s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_329/shards.html
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Patchwork
CI✓ Fi.CI.BAT: success for IGT PMU support (rev18)
In reply to Tvrtko Ursulin== Series Details ==
== Series Details ==
Series: IGT PMU support (rev18)
URL : https://patchwork.freedesktop.org/series/28253/
State : success
== Summary ==
IGT patchset tested on top of latest successful build f8f6db9ced0061229018fa658cf1c80c56464686 tools/intel_watermark: Try not to dump nonexistent planes on SKL+
with latest DRM-Tip kernel build CI_DRM_3371d8251dc669fe drm-tip: 2017y-11m-22d-10h-27m-38s UTC integration manifest
Testlist changes:
+igt@perf_pmu@all-busy-check-all
+igt@perf_pmu@busy-bcs0
+igt@perf_pmu@busy-check-all-bcs0
+igt@perf_pmu@busy-check-all-rcs0
+igt@perf_pmu@busy-check-all-vcs0
+igt@perf_pmu@busy-check-all-vcs1
+igt@perf_pmu@busy-check-all-vecs0
+igt@perf_pmu@busy-no-semaphores-bcs0
+igt@perf_pmu@busy-no-semaphores-rcs0
+igt@perf_pmu@busy-no-semaphores-vcs0
+igt@perf_pmu@busy-no-semaphores-vcs1
+igt@perf_pmu@busy-no-semaphores-vecs0
+igt@perf_pmu@busy-rcs0
+igt@perf_pmu@busy-vcs0
+igt@perf_pmu@busy-vcs1
+igt@perf_pmu@busy-vecs0
+igt@perf_pmu@cpu-hotplug
+igt@perf_pmu@event-wait-rcs0
+igt@perf_pmu@frequency
+igt@perf_pmu@idle-bcs0
+igt@perf_pmu@idle-no-semaphores-bcs0
+igt@perf_pmu@idle-no-semaphores-rcs0
+igt@perf_pmu@idle-no-semaphores-vcs0
+igt@perf_pmu@idle-no-semaphores-vcs1
+igt@perf_pmu@idle-no-semaphores-vecs0
+igt@perf_pmu@idle-rcs0
+igt@perf_pmu@idle-vcs0
+igt@perf_pmu@idle-vcs1
+igt@perf_pmu@idle-vecs0
+igt@perf_pmu@init-busy-bcs0
+igt@perf_pmu@init-busy-rcs0
+igt@perf_pmu@init-busy-vcs0
+igt@perf_pmu@init-busy-vcs1
+igt@perf_pmu@init-busy-vecs0
+igt@perf_pmu@init-sema-bcs0
+igt@perf_pmu@init-sema-rcs0
+igt@perf_pmu@init-sema-vcs0
+igt@perf_pmu@init-sema-vcs1
+igt@perf_pmu@init-sema-vecs0
+igt@perf_pmu@init-wait-bcs0
+igt@perf_pmu@init-wait-rcs0
+igt@perf_pmu@init-wait-vcs0
+igt@perf_pmu@init-wait-vcs1
+igt@perf_pmu@init-wait-vecs0
+igt@perf_pmu@interrupts
+igt@perf_pmu@invalid-init
+igt@perf_pmu@most-busy-check-all-bcs0
+igt@perf_pmu@most-busy-check-all-rcs0
+igt@perf_pmu@most-busy-check-all-vcs0
+igt@perf_pmu@most-busy-check-all-vcs1
+igt@perf_pmu@most-busy-check-all-vecs0
+igt@perf_pmu@multi-client-bcs0
+igt@perf_pmu@multi-client-rcs0
+igt@perf_pmu@multi-client-vcs0
+igt@perf_pmu@multi-client-vcs1
+igt@perf_pmu@multi-client-vecs0
+igt@perf_pmu@other-init-0
+igt@perf_pmu@other-init-1
+igt@perf_pmu@other-init-2
+igt@perf_pmu@other-init-3
+igt@perf_pmu@other-init-4
+igt@perf_pmu@other-init-5
+igt@perf_pmu@other-init-6
+igt@perf_pmu@other-read-0
+igt@perf_pmu@other-read-1
+igt@perf_pmu@other-read-2
+igt@perf_pmu@other-read-3
+igt@perf_pmu@other-read-4
+igt@perf_pmu@other-read-5
+igt@perf_pmu@other-read-6
+igt@perf_pmu@rc6
+igt@perf_pmu@rc6p
+igt@perf_pmu@render-node-busy-bcs0
+igt@perf_pmu@render-node-busy-rcs0
+igt@perf_pmu@render-node-busy-vcs0
+igt@perf_pmu@render-node-busy-vcs1
+igt@perf_pmu@render-node-busy-vecs0
+igt@perf_pmu@semaphore-wait-bcs0
+igt@perf_pmu@semaphore-wait-rcs0
+igt@perf_pmu@semaphore-wait-vcs0
+igt@perf_pmu@semaphore-wait-vcs1
+igt@perf_pmu@semaphore-wait-vecs0
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS (fi-snb-2520m) fdo#103713fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:452s fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:455s fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:385s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:546s fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:280s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:512s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:512s fi-byt-n2820 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:497s fi-cfl-s2 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:607s fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:431s fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:265s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:543s fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:430s fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:440s fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:432s fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:490s fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:464s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:480s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:534s fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:476s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:538s fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:581s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:456s fi-skl-6600u total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:546s fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:572s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:523s fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:495s fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:468s fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:562s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:435s Blacklisted hosts: fi-cnl-y total:253 pass:227 dwarn:0 dfail:0 fail:0 skip:25 fi-glk-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:506s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_520/
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Re: ✓ Fi.CI.BAT: success for IGT PMU support (rev18)
Hi guys,
On 22/11/2017 11:41, Patchwork wrote:
[snip]
Quoted 73 lines
Testlist changes:
(quoted diff) +72
-0+igt@perf_pmu@all-busy-check-all +igt@perf_pmu@busy-bcs0 +igt@perf_pmu@busy-check-all-bcs0 +igt@perf_pmu@busy-check-all-rcs0 +igt@perf_pmu@busy-check-all-vcs0 +igt@perf_pmu@busy-check-all-vcs1 +igt@perf_pmu@busy-check-all-vecs0 +igt@perf_pmu@busy-no-semaphores-bcs0 +igt@perf_pmu@busy-no-semaphores-rcs0 +igt@perf_pmu@busy-no-semaphores-vcs0 +igt@perf_pmu@busy-no-semaphores-vcs1 +igt@perf_pmu@busy-no-semaphores-vecs0 +igt@perf_pmu@busy-rcs0 +igt@perf_pmu@busy-vcs0 +igt@perf_pmu@busy-vcs1 +igt@perf_pmu@busy-vecs0 +igt@perf_pmu@cpu-hotplug +igt@perf_pmu@event-wait-rcs0 +igt@perf_pmu@frequency +igt@perf_pmu@idle-bcs0 +igt@perf_pmu@idle-no-semaphores-bcs0 +igt@perf_pmu@idle-no-semaphores-rcs0 +igt@perf_pmu@idle-no-semaphores-vcs0 +igt@perf_pmu@idle-no-semaphores-vcs1 +igt@perf_pmu@idle-no-semaphores-vecs0 +igt@perf_pmu@idle-rcs0 +igt@perf_pmu@idle-vcs0 +igt@perf_pmu@idle-vcs1 +igt@perf_pmu@idle-vecs0 +igt@perf_pmu@init-busy-bcs0 +igt@perf_pmu@init-busy-rcs0 +igt@perf_pmu@init-busy-vcs0 +igt@perf_pmu@init-busy-vcs1 +igt@perf_pmu@init-busy-vecs0 +igt@perf_pmu@init-sema-bcs0 +igt@perf_pmu@init-sema-rcs0 +igt@perf_pmu@init-sema-vcs0 +igt@perf_pmu@init-sema-vcs1 +igt@perf_pmu@init-sema-vecs0 +igt@perf_pmu@init-wait-bcs0 +igt@perf_pmu@init-wait-rcs0 +igt@perf_pmu@init-wait-vcs0 +igt@perf_pmu@init-wait-vcs1 +igt@perf_pmu@init-wait-vecs0 +igt@perf_pmu@interrupts +igt@perf_pmu@invalid-init +igt@perf_pmu@most-busy-check-all-bcs0 +igt@perf_pmu@most-busy-check-all-rcs0 +igt@perf_pmu@most-busy-check-all-vcs0 +igt@perf_pmu@most-busy-check-all-vcs1 +igt@perf_pmu@most-busy-check-all-vecs0 +igt@perf_pmu@multi-client-bcs0 +igt@perf_pmu@multi-client-rcs0 +igt@perf_pmu@multi-client-vcs0 +igt@perf_pmu@multi-client-vcs1 +igt@perf_pmu@multi-client-vecs0 +igt@perf_pmu@other-init-0 +igt@perf_pmu@other-init-1 +igt@perf_pmu@other-init-2 +igt@perf_pmu@other-init-3 +igt@perf_pmu@other-init-4 +igt@perf_pmu@other-init-5 +igt@perf_pmu@other-init-6 +igt@perf_pmu@other-read-0 +igt@perf_pmu@other-read-1 +igt@perf_pmu@other-read-2 +igt@perf_pmu@other-read-3 +igt@perf_pmu@other-read-4 +igt@perf_pmu@other-read-5 +igt@perf_pmu@other-read-6 +igt@perf_pmu@rc6 +igt@perf_pmu@rc6p
Review
Quoted 10 lines
(quoted diff) +10
-0+igt@perf_pmu@render-node-busy-bcs0 +igt@perf_pmu@render-node-busy-rcs0 +igt@perf_pmu@render-node-busy-vcs0 +igt@perf_pmu@render-node-busy-vcs1 +igt@perf_pmu@render-node-busy-vecs0 +igt@perf_pmu@semaphore-wait-bcs0 +igt@perf_pmu@semaphore-wait-rcs0 +igt@perf_pmu@semaphore-wait-vcs0 +igt@perf_pmu@semaphore-wait-vcs1 +igt@perf_pmu@semaphore-wait-vecs0
Would it be possible to have a test run of these new tests on the shards?
If successful then we can add it to the testlist. Total runtime should be up to 30 seconds.
But I wouldn't be surprised if there will be issues since I was only able to test on SKL during development.
Regards,
Tvrtko
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Re: ✓ Fi.CI.BAT: success for IGT PMU support (rev18)
Quoted 84 lines · Tvrtko Ursulin
Hi guys,
On 22/11/2017 11:41, Patchwork wrote:
[snip]
Quoted 77 lines
Testlist changes:
(quoted diff) +76
-0+igt@perf_pmu@all-busy-check-all +igt@perf_pmu@busy-bcs0 +igt@perf_pmu@busy-check-all-bcs0 +igt@perf_pmu@busy-check-all-rcs0 +igt@perf_pmu@busy-check-all-vcs0 +igt@perf_pmu@busy-check-all-vcs1 +igt@perf_pmu@busy-check-all-vecs0 +igt@perf_pmu@busy-no-semaphores-bcs0 +igt@perf_pmu@busy-no-semaphores-rcs0 +igt@perf_pmu@busy-no-semaphores-vcs0 +igt@perf_pmu@busy-no-semaphores-vcs1 +igt@perf_pmu@busy-no-semaphores-vecs0 +igt@perf_pmu@busy-rcs0 +igt@perf_pmu@busy-vcs0 +igt@perf_pmu@busy-vcs1 +igt@perf_pmu@busy-vecs0 +igt@perf_pmu@cpu-hotplug +igt@perf_pmu@event-wait-rcs0 +igt@perf_pmu@frequency +igt@perf_pmu@idle-bcs0 +igt@perf_pmu@idle-no-semaphores-bcs0 +igt@perf_pmu@idle-no-semaphores-rcs0 +igt@perf_pmu@idle-no-semaphores-vcs0 +igt@perf_pmu@idle-no-semaphores-vcs1 +igt@perf_pmu@idle-no-semaphores-vecs0 +igt@perf_pmu@idle-rcs0 +igt@perf_pmu@idle-vcs0 +igt@perf_pmu@idle-vcs1 +igt@perf_pmu@idle-vecs0 +igt@perf_pmu@init-busy-bcs0 +igt@perf_pmu@init-busy-rcs0 +igt@perf_pmu@init-busy-vcs0 +igt@perf_pmu@init-busy-vcs1 +igt@perf_pmu@init-busy-vecs0 +igt@perf_pmu@init-sema-bcs0 +igt@perf_pmu@init-sema-rcs0 +igt@perf_pmu@init-sema-vcs0 +igt@perf_pmu@init-sema-vcs1 +igt@perf_pmu@init-sema-vecs0 +igt@perf_pmu@init-wait-bcs0 +igt@perf_pmu@init-wait-rcs0 +igt@perf_pmu@init-wait-vcs0 +igt@perf_pmu@init-wait-vcs1 +igt@perf_pmu@init-wait-vecs0 +igt@perf_pmu@interrupts +igt@perf_pmu@invalid-init +igt@perf_pmu@most-busy-check-all-bcs0 +igt@perf_pmu@most-busy-check-all-rcs0 +igt@perf_pmu@most-busy-check-all-vcs0 +igt@perf_pmu@most-busy-check-all-vcs1 +igt@perf_pmu@most-busy-check-all-vecs0 +igt@perf_pmu@multi-client-bcs0 +igt@perf_pmu@multi-client-rcs0 +igt@perf_pmu@multi-client-vcs0 +igt@perf_pmu@multi-client-vcs1 +igt@perf_pmu@multi-client-vecs0 +igt@perf_pmu@other-init-0 +igt@perf_pmu@other-init-1 +igt@perf_pmu@other-init-2 +igt@perf_pmu@other-init-3 +igt@perf_pmu@other-init-4 +igt@perf_pmu@other-init-5 +igt@perf_pmu@other-init-6 +igt@perf_pmu@other-read-0 +igt@perf_pmu@other-read-1 +igt@perf_pmu@other-read-2 +igt@perf_pmu@other-read-3 +igt@perf_pmu@other-read-4 +igt@perf_pmu@other-read-5 +igt@perf_pmu@other-read-6 +igt@perf_pmu@rc6 +igt@perf_pmu@rc6p +igt@perf_pmu@render-node-busy-bcs0 +igt@perf_pmu@render-node-busy-rcs0 +igt@perf_pmu@render-node-busy-vcs0 +igt@perf_pmu@render-node-busy-vcs1
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Review
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(quoted diff) +6
-0+igt@perf_pmu@render-node-busy-vecs0 +igt@perf_pmu@semaphore-wait-bcs0 +igt@perf_pmu@semaphore-wait-rcs0 +igt@perf_pmu@semaphore-wait-vcs0 +igt@perf_pmu@semaphore-wait-vcs1 +igt@perf_pmu@semaphore-wait-vecs0Would it be possible to have a test run of these new tests on the shards?
The shard run will run them automatically, you just have to check the results manually, and look at shards-all.html instead of shards.html
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Petri Latvala _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Patchwork
CI✓ Fi.CI.IGT: success for IGT PMU support (rev18)
In reply to Tvrtko Ursulin== Series Details ==
== Series Details ==
Series: IGT PMU support (rev18)
URL : https://patchwork.freedesktop.org/series/28253/
State : success
== Summary ==
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
pass -> FAIL (shard-hsw) fdo#100368fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
shard-hsw total:2667 pass:1473 dwarn:2 dfail:0 fail:11 skip:1181 time:9509s shard-snb total:2649 pass:1241 dwarn:1 dfail:0 fail:11 skip:1395 time:7972s
Blacklisted hosts:
shard-apl total:2631 pass:1591 dwarn:2 dfail:0 fail:24 skip:1012 time:12761s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_520/shards.html
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Re: ✓ Fi.CI.IGT: success for IGT PMU support (rev18)
Quoted 11 lines · Patchwork
== Series Details ==
Series: IGT PMU support (rev18)
URL : https://patchwork.freedesktop.org/series/28253/
State : success== Summary ==
Test
kms_flip:Subgroup plain-flip-fb-recreate-interruptible: pass -> FAIL (shard-hsw) fdo#100368
Tomi, why doesn't this diff show igt@drv_selftest@live_hangcheck pass -> incomplete on snb?
Quoted 11 lines
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
shard-hsw total:2667 pass:1473 dwarn:2 dfail:0 fail:11 skip:1181 time:9509s shard-snb total:2649 pass:1241 dwarn:1 dfail:0 fail:11 skip:1395 time:7972sBlacklisted hosts:
shard-apl total:2631 pass:1591 dwarn:2 dfail:0 fail:24 skip:1012 time:12761s== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_520/shards.html
shards-all.html shows perf_pmu tests getting a SKIP across the board, on SNB, HSW and APL. igt@perf_pmu@multi-client-vcs1 on APL being the only exception but that's just a notrun (due to a hang earlier in that particular shard).
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Petri Latvala _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: ✓ Fi.CI.IGT: success for IGT PMU support (rev18)
Quoted 9 lines · Petri Latvala
Quoted 8 lines · Patchwork
== Series Details ==
Series: IGT PMU support (rev18)
URL : https://patchwork.freedesktop.org/series/28253/
State : success== Summary ==
Quoted 7 lines
Quoted 3 lines
Test
kms_flip:Subgroup plain-flip-fb-recreate-interruptible: pass -> FAIL (shard-hsw) fdo#100368Tomi, why doesn't this diff show igt@drv_selftest@live_hangcheck pass -> incomplete on snb?
Mystery solved, cibuglog has that test suppressed.
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Petri Latvala _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: ✓ Fi.CI.IGT: success for IGT PMU support (rev18)
In reply to Petri LatvalaQuoted 1 line · Petri Latvala
On Wed, Nov 22, 2017 at 02:31:08PM +0000, Patchwork wrote:
[snip]
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fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
shard-hsw total:2667 pass:1473 dwarn:2 dfail:0 fail:11 skip:1181 time:9509s shard-snb total:2649 pass:1241 dwarn:1 dfail:0 fail:11 skip:1395 time:7972sBlacklisted hosts:
shard-apl total:2631 pass:1591 dwarn:2 dfail:0 fail:24 skip:1012 time:12761s== Logs ==
Quoted 7 lines
Quoted 1 line
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_520/shards.html
shards-all.html shows
perf_pmutests getting a SKIP across the board, on SNB, HSW and APL. igt@perf_pmu@multi-client-vcs1 on APL being the only exception but that's just a notrun (due to a hang earlier in that particular shard).
After some head scratching Chris suggested that drm-tip at the time when this run did not yet contain the PMU patches.
However on a subsequent runs some lockdep issue surfaced so its not like all is good after all.
Regards,
Tvrtko
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