Skip to contentSkip to conversation

ARM: dts: imx6ul-14x14-evk: switch lcdif pixel clock to video pll

PATCH New Philipp Zabel 3 participants 3 messages Oct 12, 2017 – Oct 14, 2017

Subsystems (2)
Device tree bindings Arm i.MX and Layerscape
lore
Share & tools
lore

Philipp Zabel

author
#0 lore raw

PATCH 1/1 ARM: dts: imx6ul-14x14-evk: switch lcdif pixel clock to video pll

By default, the lcdif_pre_sel mux is switched to the pll3_pfd1_540m PFD source. If this mux is allowed to propagate rate changes to its parent, setting the LCDIF pixel clock rate to 9 MHz, as required by the LCD panel, will cause the pll3_pfd1_540m PFD to be switched away from its nominal rate to 288 MHz.
This has no negative side effects, as there are no other children to this PFD. Still, to avoid surprises, it might be preferrable to switch to the designated video PLL (pll5_video_div) as clock source for the LCDIF pixel clock.

Signed-off-by Philipp Zabel <[email protected]>
---
 arch/arm/boot/dts/imx6ul-14x14-evk.dts | 2 ++
 1 file changed, 2 insertions(+)
arch/arm/boot/dts/imx6ul-14x14-evk.dts +2 -0
index 9c23e017d86ad..e5d3ef88be608 100644
@@ -147,6 +147,8 @@
 
 
 &lcdif {
+	assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
+	assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lcdif_dat
 		     &pinctrl_lcdif_ctrl>;
Signature · 1 line
2.11.0
reviewer
#1 lore raw

PATCH 1/1 ARM: dts: imx6ul-14x14-evk: switch lcdif pixel clock to video pll

Quoted 11 lines · Philipp Zabel

By default, the lcdif_pre_sel mux is switched to the pll3_pfd1_540m PFD source. If this mux is allowed to propagate rate changes to its parent, setting the LCDIF pixel clock rate to 9 MHz, as required by the LCD panel, will cause the pll3_pfd1_540m PFD to be switched away from its nominal rate to 288 MHz.
This has no negative side effects, as there are no other children to this PFD. Still, to avoid surprises, it might be preferrable to switch to the designated video PLL (pll5_video_div) as clock source for the LCDIF pixel clock.

Signed-off-by Philipp Zabel <[email protected]>

Makes sense:

Reviewed-by Fabio Estevam <[email protected]>
Applied
#2 lore raw

PATCH 1/1 ARM: dts: imx6ul-14x14-evk: switch lcdif pixel clock to video pll

In reply to Philipp Zabel
Quoted 11 lines · Philipp Zabel

By default, the lcdif_pre_sel mux is switched to the pll3_pfd1_540m PFD source. If this mux is allowed to propagate rate changes to its parent, setting the LCDIF pixel clock rate to 9 MHz, as required by the LCD panel, will cause the pll3_pfd1_540m PFD to be switched away from its nominal rate to 288 MHz.
This has no negative side effects, as there are no other children to this PFD. Still, to avoid surprises, it might be preferrable to switch to the designated video PLL (pll5_video_div) as clock source for the LCDIF pixel clock.

Signed-off-by Philipp Zabel <[email protected]>

Applied, thanks.