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sunxi: video: add DE2 LCD and ANX6345 drivers

PATCH New Vasily Khoruzhick 2 participants 18 messages Sep 21, 2017 – Oct 27, 2017

Subsystems (4)
Arm (32-bit) Arm sub-architectures Framebuffer layer Arm/Allwinner sunXi SoC support
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Vasily Khoruzhick

author
#0 lore raw

v2 cover sunxi: video: add DE2 LCD and ANX6345 drivers

This series adds drivers that are necessary to get LCD working on Pinebook:
- ANX6345 eDP bridge driver that allows to connect eDP panels to SoCs that have parallel LCD interface
- DE2 LCD driver for Allwinner A64. Similar hardware is present in V3s and R40, but is not supported by this driver yet.

Whole combination (along with PWM driver which is sent in another series) is tested on Pinebook which is based on Allwiner A64 SoC.

Please see https://github.com/anarsoul/u-boot-pine64/ if you want to test it.

author
#1 lore raw

PATCH v2 1/5 dm: video: bridge: add operation to read EDID

Add an operation to read EDID, since bridge may have ability to read EDID from the panel that is connected to it, for example LCD<->eDP bridge.

Signed-off-by Vasily Khoruzhick <[email protected]>

---
v2: - no changes

 drivers/video/bridge/video-bridge-uclass.c | 10 ++++++++++
 include/video_bridge.h                     | 20 ++++++++++++++++++++
 2 files changed, 30 insertions(+)
drivers/video/bridge/video-bridge-uclass.c +10 -0
index 07270bac9e..79facd02a6 100644
@@ -8,6 +8,7 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
+#include <edid.h>
 #include <video_bridge.h>
 
 int video_bridge_set_backlight(struct udevice *dev, int percent)

@@ -45,6 +46,15 @@ int video_bridge_check_attached(struct udevice *dev)
 	return ops->check_attached(dev);
 }
 
+int video_bridge_read_edid(struct udevice *dev, u8 *buf, int buf_size)
+{
+	struct video_bridge_ops *ops = video_bridge_get_ops(dev);
+
+	if (!ops || !ops->read_edid)
+		return -ENOSYS;
+	return ops->read_edid(dev, buf, buf_size);
+}
+
 static int video_bridge_pre_probe(struct udevice *dev)
 {
 	struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
include/video_bridge.h +20 -0
index c7b8681849..0699a8dda8 100644
@@ -53,6 +53,16 @@ struct video_bridge_ops {
 	 * @return 0 if OK, -ve on error
 	 */
 	int (*set_backlight)(struct udevice *dev, int percent);
+
+	/**
+	 * read_edid() - Read information from EDID
+	 *
+	 * @dev:	Device to read from
+	 * @buf:	Buffer to read into
+	 * @buf_size:	Buffer size
+	 * @return number of bytes read, <=0 for error
+	 */
+	int (*read_edid)(struct udevice *dev, u8 *buf, int buf_size);
 };
 
 #define video_bridge_get_ops(dev) \

@@ -89,4 +99,14 @@ int video_bridge_set_active(struct udevice *dev, bool active);
  */
 int video_bridge_check_attached(struct udevice *dev);
 
+/**
+ * video_bridge_read_edid() - Read information from EDID
+ *
+ * @dev:	Device to read from
+ * @buf:	Buffer to read into
+ * @buf_size:	Buffer size
+ * @return number of bytes read, <=0 for error
+ */
+int video_bridge_read_edid(struct udevice *dev, u8 *buf, int buf_size);
+
 #endif
Signature · 1 line
2.14.1
#2 lore raw

PATCH v2 1/5 dm: video: bridge: add operation to read EDID

Quoted 10 lines · On Wed, 20 Sep 2017 23:29:07 -0700 Vasily Khoruzhick anarsoul at gmail.com…

Add an operation to read EDID, since bridge may have ability to read EDID from the panel that is connected to it, for example LCD<->eDP bridge.

Signed-off-by Vasily Khoruzhick <[email protected]>

---
v2: - no changes

 drivers/video/bridge/video-bridge-uclass.c | 10 ++++++++++
 include/video_bridge.h                     | 20 ++++++++++++++++++++
 2 files changed, 30 insertions(+)

Applied to u-boot-video/master, thanks!

--
Anatolij

author
#3 lore raw

PATCH v2 2/5 video: anx9804: split out registers definitions into a separate header

In reply to Vasily Khoruzhick

This header will be used in anx6345 driver

Signed-off-by Vasily Khoruzhick <[email protected]>

---
v2: - no changes

 drivers/video/anx9804.c | 54 +--------------------------
 include/anx98xx-edp.h   | 98 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 99 insertions(+), 53 deletions(-)
 create mode 100644 include/anx98xx-edp.h
drivers/video/anx9804.c +1 -53
index 37ad69a039..67f7da7d18 100755
@@ -12,61 +12,9 @@
 
 #include <common.h>
 #include <i2c.h>
+#include <anx98xx-edp.h>
 #include "anx9804.h"
 
-/* Registers at i2c address 0x38 */
-
-#define ANX9804_HDCP_CONTROL_0_REG				0x01
-
-#define ANX9804_SYS_CTRL2_REG					0x81
-#define ANX9804_SYS_CTRL2_CHA_STA				0x04
-
-#define ANX9804_SYS_CTRL3_REG					0x82
-#define ANX9804_SYS_CTRL3_VALID_CTRL				BIT(0)
-#define ANX9804_SYS_CTRL3_F_VALID				BIT(1)
-#define ANX9804_SYS_CTRL3_HPD_CTRL				BIT(4)
-#define ANX9804_SYS_CTRL3_F_HPD					BIT(5)
-
-#define ANX9804_LINK_BW_SET_REG					0xa0
-#define ANX9804_LANE_COUNT_SET_REG				0xa1
-#define ANX9804_TRAINING_PTN_SET_REG				0xa2
-#define ANX9804_TRAINING_LANE0_SET_REG				0xa3
-#define ANX9804_TRAINING_LANE1_SET_REG				0xa4
-#define ANX9804_TRAINING_LANE2_SET_REG				0xa5
-#define ANX9804_TRAINING_LANE3_SET_REG				0xa6
-
-#define ANX9804_LINK_TRAINING_CTRL_REG				0xa8
-#define ANX9804_LINK_TRAINING_CTRL_EN				BIT(0)
-
-#define ANX9804_LINK_DEBUG_REG					0xb8
-#define ANX9804_PLL_CTRL_REG					0xc7	
-#define ANX9804_ANALOG_POWER_DOWN_REG				0xc8
-
-/* Registers at i2c address 0x39 */
-
-#define ANX9804_DEV_IDH_REG					0x03
-
-#define ANX9804_POWERD_CTRL_REG					0x05
-#define ANX9804_POWERD_AUDIO					BIT(4)
-
-#define ANX9804_RST_CTRL_REG					0x06
-
-#define ANX9804_RST_CTRL2_REG					0x07
-#define ANX9804_RST_CTRL2_AUX					BIT(2)
-#define ANX9804_RST_CTRL2_AC_MODE				BIT(6)
-
-#define ANX9804_VID_CTRL1_REG					0x08
-#define ANX9804_VID_CTRL1_VID_EN				BIT(7)
-#define ANX9804_VID_CTRL1_EDGE					BIT(0)
-
-#define ANX9804_VID_CTRL2_REG					0x09
-#define ANX9804_ANALOG_DEBUG_REG1				0xdc
-#define ANX9804_ANALOG_DEBUG_REG3				0xde
-#define ANX9804_PLL_FILTER_CTRL1				0xdf
-#define ANX9804_PLL_FILTER_CTRL3				0xe1
-#define ANX9804_PLL_FILTER_CTRL					0xe2
-#define ANX9804_PLL_CTRL3					0xe6
-
 /**
  * anx9804_init() - Init anx9804 parallel lcd to edp bridge chip
  *
include/anx98xx-edp.h new file +98 -0

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Signature · 1 line
2.14.1
#4 lore raw

PATCH v3 2/5 video: anx9804: split out registers definitions into a separate header

From: Vasily Khoruzhick <[email protected]>

This header will be used in anx6345 driver

Signed-off-by Vasily Khoruzhick <[email protected]>
Signed-off-by Anatolij Gustschin <[email protected]>

---
v3: - moved header to drivers/video
v2: - no changes

 drivers/video/anx9804.c     | 54 +------------------------
 drivers/video/anx98xx-edp.h | 98 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 99 insertions(+), 53 deletions(-)
 create mode 100644 drivers/video/anx98xx-edp.h
drivers/video/anx9804.c +1 -53
index 37ad69a039..3910458bf1 100755
@@ -12,61 +12,9 @@
 
 #include <common.h>
 #include <i2c.h>
+#include "anx98xx-edp.h"
 #include "anx9804.h"
 
-/* Registers at i2c address 0x38 */
-
-#define ANX9804_HDCP_CONTROL_0_REG				0x01
-
-#define ANX9804_SYS_CTRL2_REG					0x81
-#define ANX9804_SYS_CTRL2_CHA_STA				0x04
-
-#define ANX9804_SYS_CTRL3_REG					0x82
-#define ANX9804_SYS_CTRL3_VALID_CTRL				BIT(0)
-#define ANX9804_SYS_CTRL3_F_VALID				BIT(1)
-#define ANX9804_SYS_CTRL3_HPD_CTRL				BIT(4)
-#define ANX9804_SYS_CTRL3_F_HPD					BIT(5)
-
-#define ANX9804_LINK_BW_SET_REG					0xa0
-#define ANX9804_LANE_COUNT_SET_REG				0xa1
-#define ANX9804_TRAINING_PTN_SET_REG				0xa2
-#define ANX9804_TRAINING_LANE0_SET_REG				0xa3
-#define ANX9804_TRAINING_LANE1_SET_REG				0xa4
-#define ANX9804_TRAINING_LANE2_SET_REG				0xa5
-#define ANX9804_TRAINING_LANE3_SET_REG				0xa6
-
-#define ANX9804_LINK_TRAINING_CTRL_REG				0xa8
-#define ANX9804_LINK_TRAINING_CTRL_EN				BIT(0)
-
-#define ANX9804_LINK_DEBUG_REG					0xb8
-#define ANX9804_PLL_CTRL_REG					0xc7	
-#define ANX9804_ANALOG_POWER_DOWN_REG				0xc8
-
-/* Registers at i2c address 0x39 */
-
-#define ANX9804_DEV_IDH_REG					0x03
-
-#define ANX9804_POWERD_CTRL_REG					0x05
-#define ANX9804_POWERD_AUDIO					BIT(4)
-
-#define ANX9804_RST_CTRL_REG					0x06
-
-#define ANX9804_RST_CTRL2_REG					0x07
-#define ANX9804_RST_CTRL2_AUX					BIT(2)
-#define ANX9804_RST_CTRL2_AC_MODE				BIT(6)
-
-#define ANX9804_VID_CTRL1_REG					0x08
-#define ANX9804_VID_CTRL1_VID_EN				BIT(7)
-#define ANX9804_VID_CTRL1_EDGE					BIT(0)
-
-#define ANX9804_VID_CTRL2_REG					0x09
-#define ANX9804_ANALOG_DEBUG_REG1				0xdc
-#define ANX9804_ANALOG_DEBUG_REG3				0xde
-#define ANX9804_PLL_FILTER_CTRL1				0xdf
-#define ANX9804_PLL_FILTER_CTRL3				0xe1
-#define ANX9804_PLL_FILTER_CTRL					0xe2
-#define ANX9804_PLL_CTRL3					0xe6
-
 /**
  * anx9804_init() - Init anx9804 parallel lcd to edp bridge chip
  *
drivers/video/anx98xx-edp.h new file +98 -0

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Signature · 1 line
2.11.0
#5 lore raw

PATCH v3 2/5 video: anx9804: split out registers definitions into a separate header

Quoted 6 lines · On Thu, 26 Oct 2017 18:26:43 +0200 Anatolij Gustschin agust at denx.de wrote:

From: Vasily Khoruzhick <[email protected]>

This header will be used in anx6345 driver

Signed-off-by Vasily Khoruzhick <[email protected]>
Signed-off-by Anatolij Gustschin <[email protected]>
Quoted 8 lines

---
v3: - moved header to drivers/video
v2: - no changes

 drivers/video/anx9804.c     | 54 +------------------------
 drivers/video/anx98xx-edp.h | 98 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 99 insertions(+), 53 deletions(-)
 create mode 100644 drivers/video/anx98xx-edp.h

Applied to u-boot-video/master, thanks!

--
Anatolij

#6 lore raw

PATCH v3 3/5 video: add anx6345 DM driver

In reply to Vasily Khoruzhick

From: Vasily Khoruzhick <[email protected]>

This is a eDP bridge similar to ANX9804, it allows to connect eDP panels to the chips that can output only parallel signal

Signed-off-by Vasily Khoruzhick <[email protected]>
Signed-off-by Anatolij Gustschin <[email protected]>

---
v3: - fixed checkpatch errors/warnings
v2: - no changes

 drivers/video/bridge/Kconfig   |   8 +
 drivers/video/bridge/Makefile  |   1 +
 drivers/video/bridge/anx6345.c | 426 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 435 insertions(+)
 create mode 100644 drivers/video/bridge/anx6345.c
drivers/video/bridge/Kconfig +8 -0
index 2a3b6c4bee..765f7380b8 100644
@@ -25,3 +25,11 @@ config VIDEO_BRIDGE_NXP_PTN3460
 	  signalling) converter. It enables an LVDS LCD panel to be connected
 	  to an eDP output device such as an SoC that lacks LVDS capability,
 	  or where LVDS requires too many signals to route on the PCB.
+
+config VIDEO_BRIDGE_ANALOGIX_ANX6345
+	bool "Support Analogix ANX6345 RGB->DP bridge"
+	depends on VIDEO_BRIDGE
+	select DM_I2C
+	help
+	 The Analogix ANX6345 is RGB-to-DP converter. It enables an eDP LCD
+	 panel to be connected to an parallel LCD interface.
drivers/video/bridge/Makefile +1 -0
index ce731fa4ca..2a746c6f8b 100644
@@ -7,3 +7,4 @@
 obj-$(CONFIG_VIDEO_BRIDGE) += video-bridge-uclass.o
 obj-$(CONFIG_VIDEO_BRIDGE_PARADE_PS862X) += ps862x.o
 obj-$(CONFIG_VIDEO_BRIDGE_NXP_PTN3460) += ptn3460.o
+obj-$(CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345) += anx6345.o
drivers/video/bridge/anx6345.c new file +426 -0

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Signature · 1 line
2.11.0
#7 lore raw

PATCH v3 3/5 video: add anx6345 DM driver

Quoted 11 lines · On Thu, 26 Oct 2017 18:29:39 +0200 Anatolij Gustschin agust at denx.de wrote:

From: Vasily Khoruzhick <[email protected]>

This is a eDP bridge similar to ANX9804, it allows to connect eDP panels to the chips that can output only parallel signal

Signed-off-by Vasily Khoruzhick <[email protected]>
Signed-off-by Anatolij Gustschin <[email protected]>

---
v3: - fixed checkpatch errors/warnings
v2: - no changes

Quoted 5 lines
 drivers/video/bridge/Kconfig   |   8 +
 drivers/video/bridge/Makefile  |   1 +
 drivers/video/bridge/anx6345.c | 426 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 435 insertions(+)
 create mode 100644 drivers/video/bridge/anx6345.c

Applied to u-boot-video/master, thanks!

--
Anatolij

author
#8 lore raw

PATCH v2 3/5 video: add anx6345 DM driver

In reply to Vasily Khoruzhick

This is a eDP bridge similar to ANX9804, it allows to connect eDP panels to the chips that can output only parallel signal

Signed-off-by Vasily Khoruzhick <[email protected]>

---
v2: - no changes

 drivers/video/bridge/Kconfig   |   8 +
 drivers/video/bridge/Makefile  |   1 +
 drivers/video/bridge/anx6345.c | 419 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 428 insertions(+)
 create mode 100644 drivers/video/bridge/anx6345.c
drivers/video/bridge/Kconfig +8 -0
index 2a3b6c4bee..765f7380b8 100644
@@ -25,3 +25,11 @@ config VIDEO_BRIDGE_NXP_PTN3460
 	  signalling) converter. It enables an LVDS LCD panel to be connected
 	  to an eDP output device such as an SoC that lacks LVDS capability,
 	  or where LVDS requires too many signals to route on the PCB.
+
+config VIDEO_BRIDGE_ANALOGIX_ANX6345
+	bool "Support Analogix ANX6345 RGB->DP bridge"
+	depends on VIDEO_BRIDGE
+	select DM_I2C
+	help
+	 The Analogix ANX6345 is RGB-to-DP converter. It enables an eDP LCD
+	 panel to be connected to an parallel LCD interface.
drivers/video/bridge/Makefile +1 -0
index ce731fa4ca..2a746c6f8b 100644
@@ -7,3 +7,4 @@
 obj-$(CONFIG_VIDEO_BRIDGE) += video-bridge-uclass.o
 obj-$(CONFIG_VIDEO_BRIDGE_PARADE_PS862X) += ps862x.o
 obj-$(CONFIG_VIDEO_BRIDGE_NXP_PTN3460) += ptn3460.o
+obj-$(CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345) += anx6345.o
drivers/video/bridge/anx6345.c new file +419 -0

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2.14.1
author
#9 lore raw

PATCH v2 4/5 sunxi: video: split out PLL configuration code

In reply to Vasily Khoruzhick

It will be reused in new DM LCD driver.

Signed-off-by Vasily Khoruzhick <[email protected]>

---
v2: - no changes

 arch/arm/include/asm/arch-sunxi/lcdc.h |   2 +
 drivers/video/sunxi/lcdc.c             | 117 ++++++++++++++++++++++++++++++-
 drivers/video/sunxi/sunxi_display.c    | 121 ++-------------------------------
 3 files changed, 124 insertions(+), 116 deletions(-)
arch/arm/include/asm/arch-sunxi/lcdc.h +2 -0
index a751698b4f..5d9253aaa5 100644
@@ -124,5 +124,7 @@ void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
 void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
 			 const struct display_timing *mode,
 			 bool ext_hvsync, bool is_composite);
+void lcdc_pll_set(struct sunxi_ccm_reg * const ccm, int tcon,
+		  int dotclock, int *clk_div, int *clk_double);
 
 #endif /* _LCDC_H */
drivers/video/sunxi/lcdc.c +116 -1

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drivers/video/sunxi/sunxi_display.c +6 -115

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Signature · 1 line
2.14.1
#10 lore raw

PATCH v2 4/5 sunxi: video: split out PLL configuration code

Quoted 10 lines · On Wed, 20 Sep 2017 23:29:10 -0700 Vasily Khoruzhick anarsoul at gmail.com…

It will be reused in new DM LCD driver.

Signed-off-by Vasily Khoruzhick <[email protected]>

---
v2: - no changes

 arch/arm/include/asm/arch-sunxi/lcdc.h |   2 +
 drivers/video/sunxi/lcdc.c             | 117 ++++++++++++++++++++++++++++++-
 drivers/video/sunxi/sunxi_display.c    | 121 ++-------------------------------
 3 files changed, 124 insertions(+), 116 deletions(-)

This patch breaks building for many sunxi boards, please see build logs here:

https://travis-ci.org/vdsao/u-boot-video/jobs/293307123
https://travis-ci.org/vdsao/u-boot-video/jobs/293307125
https://travis-ci.org/vdsao/u-boot-video/jobs/293307128
https://travis-ci.org/vdsao/u-boot-video/jobs/293307131

--
Anatolij

author
#11 lore raw

PATCH v2 4/5 sunxi: video: split out PLL configuration code

Hi Anatolij,

I'll look into it tonight.

Regards,
Vasily

Quoted 24 lines · Anatolij Gustschin
Quoted 10 lines · On Wed, 20 Sep 2017 23:29:10 -0700 Vasily Khoruzhick anarsoul at gmail.com…

It will be reused in new DM LCD driver.

Signed-off-by Vasily Khoruzhick <[email protected]>

---
v2: - no changes

 arch/arm/include/asm/arch-sunxi/lcdc.h |   2 +
 drivers/video/sunxi/lcdc.c             | 117 ++++++++++++++++++++++++++++++-
 drivers/video/sunxi/sunxi_display.c    | 121 ++-------------------------------
 3 files changed, 124 insertions(+), 116 deletions(-)

This patch breaks building for many sunxi boards, please see build logs here:

https://travis-ci.org/vdsao/u-boot-video/jobs/293307123
https://travis-ci.org/vdsao/u-boot-video/jobs/293307125
https://travis-ci.org/vdsao/u-boot-video/jobs/293307128
https://travis-ci.org/vdsao/u-boot-video/jobs/293307131

--
Anatolij

author
#12 lore raw

PATCH v4 4/5 sunxi: video: split out PLL configuration code

It will be reused in new DM LCD driver.

Signed-off-by Vasily Khoruzhick <[email protected]>

---
v2-v3: no changes
v4: - fix compilation for boards that use sunxi_display.c
- rebased and fixed checkpatch errors

 arch/arm/include/asm/arch-sunxi/lcdc.h |   3 +
 drivers/video/sunxi/lcdc.c             | 122 +++++++++++++++++++++++++++++++-
 drivers/video/sunxi/sunxi_display.c    | 123 +++------------------------------
 3 files changed, 132 insertions(+), 116 deletions(-)
arch/arm/include/asm/arch-sunxi/lcdc.h +3 -0
index a751698b4f..132c480106 100644
@@ -124,5 +124,8 @@ void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
 void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
 			 const struct display_timing *mode,
 			 bool ext_hvsync, bool is_composite);
+void lcdc_pll_set(struct sunxi_ccm_reg * const ccm, int tcon,
+		  int dotclock, int *clk_div, int *clk_double,
+		  bool is_composite);
 
 #endif /* _LCDC_H */
drivers/video/sunxi/lcdc.c +121 -1

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drivers/video/sunxi/sunxi_display.c +8 -115

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Signature · 1 line
2.14.3
author
#13 lore raw

PATCH v4 5/5 sunxi: video: add LCD support to DE2 driver

Extend DE2 driver with LCD support. Tested on Pinebook which is based on A64 and has ANX6345 eDP bridge with eDP panel connected to it.

Signed-off-by Vasily Khoruzhick <[email protected]>

---
v4: - adapted to v4 changes in patch 4/5
v3: - rebased and fixed checkpatch errors/warnings

v2: - drop redundant clock_set_pll10() call
- fallback to timings from DT if reading EDID from bridge failed
- read panel_bpp from DT

 arch/arm/mach-sunxi/Kconfig     |   2 +-
 drivers/video/sunxi/Makefile    |   2 +-
 drivers/video/sunxi/sunxi_de2.c |  17 +++++
 drivers/video/sunxi/sunxi_lcd.c | 152 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 171 insertions(+), 2 deletions(-)
 create mode 100644 drivers/video/sunxi/sunxi_lcd.c
arch/arm/mach-sunxi/Kconfig +1 -1
index 2309f59999..06d697e3a7 100644
@@ -680,7 +680,7 @@ config VIDEO_LCD_MODE
 
 config VIDEO_LCD_DCLK_PHASE
 	int "LCD panel display clock phase"
-	depends on VIDEO
+	depends on VIDEO || DM_VIDEO
 	default 1
 	---help---
 	Select LCD panel display clock phase shift, range 0-3.
drivers/video/sunxi/Makefile +1 -1
index 0d64c2021f..8c91766c24 100644
@@ -6,4 +6,4 @@
 #
 
 obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o tve_common.o ../videomodes.o
-obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o
+obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o sunxi_lcd.o
drivers/video/sunxi/sunxi_de2.c +17 -0
index ee67764ac5..49c36b8d73 100644
@@ -232,6 +232,23 @@ static int sunxi_de2_probe(struct udevice *dev)
 	if (!(gd->flags & GD_FLG_RELOC))
 		return 0;
 
+	ret = uclass_find_device_by_name(UCLASS_DISPLAY,
+					 "sunxi_lcd", &disp);
+	if (!ret) {
+		int mux;
+
+		mux = 0;
+
+		ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
+				     false);
+		if (!ret) {
+			video_set_flush_dcache(dev, 1);
+			return 0;
+		}
+	}
+
+	debug("%s: lcd display not found (ret=%d)\n", __func__, ret);
+
 	ret = uclass_find_device_by_name(UCLASS_DISPLAY,
 					 "sunxi_dw_hdmi", &disp);
 	if (!ret) {
drivers/video/sunxi/sunxi_lcd.c new file +152 -0

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2.14.3
#14 lore raw

PATCH v4 5/5 sunxi: video: add LCD support to DE2 driver

Quoted 11 lines · On Thu, 26 Oct 2017 21:51:52 -0700 Vasily Khoruzhick anarsoul at gmail.com…

Extend DE2 driver with LCD support. Tested on Pinebook which is based on A64 and has ANX6345 eDP bridge with eDP panel connected to it.

Signed-off-by Vasily Khoruzhick <[email protected]>

---
v4: - adapted to v4 changes in patch 4/5
v3: - rebased and fixed checkpatch errors/warnings

v2: - drop redundant clock_set_pll10() call
- fallback to timings from DT if reading EDID from bridge failed
- read panel_bpp from DT

Quoted 6 lines
 arch/arm/mach-sunxi/Kconfig     |   2 +-
 drivers/video/sunxi/Makefile    |   2 +-
 drivers/video/sunxi/sunxi_de2.c |  17 +++++
 drivers/video/sunxi/sunxi_lcd.c | 152 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 171 insertions(+), 2 deletions(-)
 create mode 100644 drivers/video/sunxi/sunxi_lcd.c

Applied to u-boot-video/master, thanks!

--
Anatolij

#15 lore raw

PATCH v4 4/5 sunxi: video: split out PLL configuration code

In reply to Vasily Khoruzhick
Quoted 8 lines · On Thu, 26 Oct 2017 21:51:51 -0700 Vasily Khoruzhick anarsoul at gmail.com…

It will be reused in new DM LCD driver.

Signed-off-by Vasily Khoruzhick <[email protected]>

---
v2-v3: no changes
v4: - fix compilation for boards that use sunxi_display.c
- rebased and fixed checkpatch errors

Quoted 4 lines
 arch/arm/include/asm/arch-sunxi/lcdc.h |   3 +
 drivers/video/sunxi/lcdc.c             | 122 +++++++++++++++++++++++++++++++-
 drivers/video/sunxi/sunxi_display.c    | 123 +++------------------------------
 3 files changed, 132 insertions(+), 116 deletions(-)

Applied to u-boot-video/master, thanks!

--
Anatolij

author
#16 lore raw

PATCH v2 5/5 sunxi: video: add LCD support to DE2 driver

In reply to Vasily Khoruzhick

Extend DE2 driver with LCD support. Tested on Pinebook which is based on A64 and has ANX6345 eDP bridge with eDP panel connected to it.

Signed-off-by Vasily Khoruzhick <[email protected]>

---
v2: - drop redundant clock_set_pll10() call
- fallback to timings from DT if reading EDID from bridge failed
- read panel_bpp from DT

 arch/arm/mach-sunxi/Kconfig     |   2 +-
 drivers/video/sunxi/Makefile    |   2 +-
 drivers/video/sunxi/sunxi_de2.c |  17 +++++
 drivers/video/sunxi/sunxi_lcd.c | 149 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 168 insertions(+), 2 deletions(-)
 create mode 100644 drivers/video/sunxi/sunxi_lcd.c
arch/arm/mach-sunxi/Kconfig +1 -1
index 2309f59999..06d697e3a7 100644
@@ -680,7 +680,7 @@ config VIDEO_LCD_MODE
 
 config VIDEO_LCD_DCLK_PHASE
 	int "LCD panel display clock phase"
-	depends on VIDEO
+	depends on VIDEO || DM_VIDEO
 	default 1
 	---help---
 	Select LCD panel display clock phase shift, range 0-3.
drivers/video/sunxi/Makefile +1 -1
index 0d64c2021f..8c91766c24 100644
@@ -6,4 +6,4 @@
 #
 
 obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o tve_common.o ../videomodes.o
-obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o
+obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o sunxi_lcd.o
drivers/video/sunxi/sunxi_de2.c +17 -0
index ee67764ac5..a838bbacd1 100644
@@ -232,6 +232,23 @@ static int sunxi_de2_probe(struct udevice *dev)
 	if (!(gd->flags & GD_FLG_RELOC))
 		return 0;
 
+	ret = uclass_find_device_by_name(UCLASS_DISPLAY,
+					 "sunxi_lcd", &disp);
+	if (!ret) {
+		int mux;
+
+		mux = 0;
+
+		ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
+		                     false);
+		if (!ret) {
+			video_set_flush_dcache(dev, 1);
+			return 0;
+		}
+	}
+
+	debug("%s: lcd display not found (ret=%d)\n", __func__, ret);
+
 	ret = uclass_find_device_by_name(UCLASS_DISPLAY,
 					 "sunxi_dw_hdmi", &disp);
 	if (!ret) {
drivers/video/sunxi/sunxi_lcd.c new file +149 -0

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2.14.1
#17 lore raw

PATCH v3 5/5 sunxi: video: add LCD support to DE2 driver

From: Vasily Khoruzhick <[email protected]>

Extend DE2 driver with LCD support. Tested on Pinebook which is based on A64 and has ANX6345 eDP bridge with eDP panel connected to it.

Signed-off-by Vasily Khoruzhick <[email protected]>
Signed-off-by Anatolij Gustschin <[email protected]>

---
v3: - rebased and fixed checkpatch errors/warnings

v2: - drop redundant clock_set_pll10() call
- fallback to timings from DT if reading EDID from bridge failed
- read panel_bpp from DT

 arch/arm/mach-sunxi/Kconfig     |   2 +-
 drivers/video/sunxi/Makefile    |   2 +-
 drivers/video/sunxi/sunxi_de2.c |  17 +++++
 drivers/video/sunxi/sunxi_lcd.c | 151 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 170 insertions(+), 2 deletions(-)
 create mode 100644 drivers/video/sunxi/sunxi_lcd.c
arch/arm/mach-sunxi/Kconfig +1 -1
index bb57d4ff81..09cfec6f57 100644
@@ -682,7 +682,7 @@ config VIDEO_LCD_MODE
 
 config VIDEO_LCD_DCLK_PHASE
 	int "LCD panel display clock phase"
-	depends on VIDEO_SUNXI
+	depends on VIDEO_SUNXI || DM_VIDEO
 	default 1
 	---help---
 	Select LCD panel display clock phase shift, range 0-3.
drivers/video/sunxi/Makefile +1 -1
index aec32b79b9..fa12d43029 100644
@@ -6,4 +6,4 @@
 #
 
 obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o simplefb_common.o lcdc.o tve_common.o ../videomodes.o
-obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o simplefb_common.o lcdc.o ../dw_hdmi.o
+obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o simplefb_common.o lcdc.o ../dw_hdmi.o sunxi_lcd.o
drivers/video/sunxi/sunxi_de2.c +17 -0
index 67b937098c..e8903400ec 100644
@@ -236,6 +236,23 @@ static int sunxi_de2_probe(struct udevice *dev)
 		return 0;
 
 	ret = uclass_find_device_by_name(UCLASS_DISPLAY,
+					 "sunxi_lcd", &disp);
+	if (!ret) {
+		int mux;
+
+		mux = 0;
+
+		ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
+				     false);
+		if (!ret) {
+			video_set_flush_dcache(dev, 1);
+			return 0;
+		}
+	}
+
+	debug("%s: lcd display not found (ret=%d)\n", __func__, ret);
+
+	ret = uclass_find_device_by_name(UCLASS_DISPLAY,
 					 "sunxi_dw_hdmi", &disp);
 	if (!ret) {
 		int mux;
drivers/video/sunxi/sunxi_lcd.c new file +151 -0

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2.11.0