SMP and CPU hotplug support for Meson8/Meson8b

PATCH Superseded Martin Blumenstingl 4 participants 17 messages Sep 17, 2017 – Oct 29, 2017

Subsystems (4)

Device tree bindings Arm (32-bit) Arm sub-architectures Arm/Amlogic Meson SoC support

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Martin Blumenstingl

author reviewer

2017-09-17 16:45 UTC #0 lore raw

v7 cover SMP and CPU hotplug support for Meson8/Meson8b

This patchset adds support for booting the secondary CPU cores (and taking them offline again) on Amlogic Meson8 and Meson8b SoCs. It is based on an earlier version from Carlo Caione - this helped me a lot to get a better understanding of how SMP/CPU hotplug works (compared to the code found in Amlogic's GPL kernel sources from year 2015).

Changes since v6 from [6]:
- rebased on top of v4.14-rc1 (which only corrected some line numbers in the SCU patches)

Changes since v5 from [5]:
- dropped dependency on another patch series (for the clock controller's embedded reset controller, which is needed to boot the secondary CPUs) from the cover-letter as that series is now merged
- fix incorrect documentation of scu_cpu_power_enable (thanks to Russell King for spotting these). removed the paragraph about preemption, cache coherency and interrupts as we're powering on a CPU core (the text was copied from the original scu_power_mode but simply not adjusted). also changed "Set the executing CPUs" to "Set the given (logical) CPU's" as we're not modifying the current CPU. this affects only patch #2
- extended the commit message of patch #3 with a short sentence about why SCU_CPU_STATUS_MASK was introduced

Changes since v4 from [4]:
- use __pa_symbol(secondary_startup) instead of virt_to_phys(secondary_startup) as suggested by Florian Fainelli (affects patch #4)
- (cover-letter) removed dependency on my other patch "ARM: dts: meson: add a node which describes the SRAM" [2] as that was merged into Kevin's Amlogic repo today
- dropped patch #5 ("clk: meson: meson8b: export the CPU soft reset lines") again because the reset controller series exposes the preprocessor macros now directly, see [1]
- refreshed the .dts patches so they now include the new header for the reset line preprocessor macros

Changes since v3 from [3]:
- added Rob's ACK to patch #1
- replaced a msleep(10) with usleep_range(10000, 15000) in patch #4
- removed all "pen" code from patch #4 as that code was not needed at all (it was left-over while trying to fix Meson8 secondary CPU boot - which turned out to have nothing to do with this "pen" code)
- removed all memory barrier operations as they were added based on the code in the Amlogic GPL kernel tree (while trying to fix the Meson8 secondary CPU boot - just like the "pen" code). Everything still works fine with these on my Meson8m2 and Meson8b boards.
- added PATCH #5 as we now have to export the reset identifiers (just like we do it with the clock identifiers / preprocessor macros) - this is the result of a change in the reset controller patch in version 2, see [1]
- use the reset line preprocessor macros (from patch #5) in patches #6 and #7

Changes since v2 from [0]:
- added support for Meson8 (which requires a slightly different enable-method)
- implemented CPU hotplug support which allows taking a CPU core offline for both, Meson8 and Meson8b
- add a function to smp_scu.c which allows enabling a CPU core from a different CPU (previously only the power mode for the current CPU could be changed). Without this the CPU cores on Meson8 won't come up (Amlogic's vendor GPL kernel sources also enable power through SCU as very first step for Meson8b as well)
- add a function to smp_scu.c to get the power status of a CPU core (which is needed because the code in .cpu_kill needs to wait until the core is actually powered off)
- dropped patch "ARM: DTS: meson8b: Extend L2 cache controller node" as it is already applied (for both, Meson8 and Meson8b)
- dropped the patches which implement the reset controller which is built into the clock-controller, these are a separate series: [1]
- moved the enable-method property to each CPU node

[0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390355.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004456.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004282.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004297.html
[4] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004354.html
[5] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004460.html
[6] http://lists.infradead.org/pipermail/linux-amlogic/2017-August/004588.html

Carlo Caione (2):
dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation
ARM: dts: meson8b: add support for booting the secondary CPU cores

Martin Blumenstingl (4):
ARM: smp_scu: add a helper for powering on a specific CPU
ARM: smp_scu: allow the platform code to read the SCU CPU status
ARM: meson: Add SMP bringup code for Meson8 and Meson8b
ARM: dts: meson8: add support for booting the secondary CPU cores

 .../devicetree/bindings/arm/amlogic/pmu.txt        |  18 +
 .../devicetree/bindings/arm/amlogic/smp-sram.txt   |  32 ++
 Documentation/devicetree/bindings/arm/cpus.txt     |   2 +
 arch/arm/Makefile                                  |   1 +
 arch/arm/boot/dts/meson8.dtsi                      |  21 +
 arch/arm/boot/dts/meson8b.dtsi                     |  21 +
 arch/arm/include/asm/smp_scu.h                     |  12 +
 arch/arm/kernel/smp_scu.c                          |  43 +-
 arch/arm/mach-meson/Kconfig                        |   1 +
 arch/arm/mach-meson/Makefile                       |   1 +
 arch/arm/mach-meson/platsmp.c                      | 440 +++++++++++++++++++++
 11 files changed, 586 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/amlogic/pmu.txt
 create mode 100644 Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt
 create mode 100644 arch/arm/mach-meson/platsmp.c

Signature · 1 line

2.14.1

Martin Blumenstingl

author reviewer

2017-09-17 16:45 UTC #1 lore raw

PATCH v7 1/6 dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation

From: Carlo Caione <[email protected]>

With this patch we add documentation for:

* power-management-unit: the PMU is used to bring up the cores during SMP operations
* sram: among other things the sram is used to store the first code executed by the core when it is powered up
* cpu-enable-method: the CPU enable method used by Amlogic Meson8 and Meson8b SoCs

Signed-off-by Carlo Caione <[email protected]>

[also add Meson8 to the documentation]

Signed-off-by Martin Blumenstingl <[email protected]>

Acked-by Rob Herring <[email protected]>

---
 .../devicetree/bindings/arm/amlogic/pmu.txt        | 18 ++++++++++++
 .../devicetree/bindings/arm/amlogic/smp-sram.txt   | 32 ++++++++++++++++++++++
 Documentation/devicetree/bindings/arm/cpus.txt     |  2 ++
 3 files changed, 52 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/amlogic/pmu.txt
 create mode 100644 Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt

Documentation/devicetree/bindings/arm/amlogic/pmu.txt new file +18 -0

new file mode 100644
index 000000000000..72f8d08198b6
@@ -0,0 +1,18 @@
+Amlogic Meson8 and Meson8b power-management-unit:
+-------------------------------------------------
+
+The pmu is used to turn off and on different power domains of the SoCs
+This includes the power to the CPU cores.
+
+Required node properties:
+- compatible value : depending on the SoC this should be one of:
+			"amlogic,meson8-pmu"
+			"amlogic,meson8b-pmu"
+- reg : physical base address and the size of the registers window
+
+Example:
+
+	pmu at c81000e4 {
+		compatible = "amlogic,meson8b-pmu", "syscon";
+		reg = <0xc81000e0 0x18>;
+	};

Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt new file +32 -0

new file mode 100644
index 000000000000..3473ddaadfac
@@ -0,0 +1,32 @@
+Amlogic Meson8 and Meson8b SRAM for smp bringup:
+------------------------------------------------
+
+Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
+Once the core gets powered up it executes the code that is residing at a
+specific location.
+
+Therefore a reserved section sub-node has to be added to the mmio-sram
+declaration.
+
+Required sub-node properties:
+- compatible : depending on the SoC this should be one of:
+		"amlogic,meson8-smp-sram"
+		"amlogic,meson8b-smp-sram"
+
+The rest of the properties should follow the generic mmio-sram discription
+found in ../../misc/sram.txt
+
+Example:
+
+	sram: sram at d9000000 {
+		compatible = "mmio-sram";
+		reg = <0xd9000000 0x20000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xd9000000 0x20000>;
+
+		smp-sram at 1ff80 {
+			compatible = "amlogic,meson8b-smp-sram";
+			reg = <0x1ff80 0x8>;
+		};
+	};

Documentation/devicetree/bindings/arm/cpus.txt +2 -0

index b92f12bd5244..a0009b72e9be 100644
@@ -197,6 +197,8 @@ described below.
 			    "actions,s500-smp"
 			    "allwinner,sun6i-a31"
 			    "allwinner,sun8i-a23"
+			    "amlogic,meson8-smp"
+			    "amlogic,meson8b-smp"
 			    "arm,realview-smp"
 			    "brcm,bcm11351-cpu-method"
 			    "brcm,bcm23550"

Signature · 1 line

2.14.1

Martin Blumenstingl

author reviewer

2017-09-17 16:45 UTC #2 lore raw

PATCH v7 2/6 ARM: smp_scu: add a helper for powering on a specific CPU

In reply to Martin Blumenstingl

To boot the secondary CPUs on the Amlogic Meson8/Meson8m2 (Cortex-A9) and Meson8b (Cortex-A5) SoCs we have to enable SCU mode SCU_PM_NORMAL, otherwise the secondary cores will not start.
This patch adds a scu_cpu_power_enable() function which can be used to enable SCU_PM_NORMAL for a specific (logical) CPU. An internal helper function is also created, to avoid code duplication with scu_power_mode().

Signed-off-by Martin Blumenstingl <[email protected]>

---
 arch/arm/include/asm/smp_scu.h |  6 ++++++
 arch/arm/kernel/smp_scu.c      | 35 +++++++++++++++++++++++++----------
 2 files changed, 31 insertions(+), 10 deletions(-)

arch/arm/include/asm/smp_scu.h +6 -0

index 5983f6bc62d5..4c47bdfd4f61 100644
@@ -27,6 +27,7 @@ static inline unsigned long scu_a9_get_base(void)
 #ifdef CONFIG_HAVE_ARM_SCU
 unsigned int scu_get_core_count(void __iomem *);
 int scu_power_mode(void __iomem *, unsigned int);
+int scu_cpu_power_enable(void __iomem *, unsigned int);
 #else
 static inline unsigned int scu_get_core_count(void __iomem *scu_base)
 {

@@ -36,6 +37,11 @@ static inline int scu_power_mode(void __iomem *scu_base, unsigned int mode)
 {
 	return -EINVAL;
 }
+static inline int scu_cpu_power_enable(void __iomem *scu_base,
+				       unsigned int mode)
+{
+	return -EINVAL;
+}
 #endif
 
 #if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU)

arch/arm/kernel/smp_scu.c +25 ~~-10~~

index 72f9241ad5db..1d549c16b5fc 100644
@@ -72,18 +72,12 @@ void scu_enable(void __iomem *scu_base)
 }
 #endif
 
-/*
- * Set the executing CPUs power mode as defined.  This will be in
- * preparation for it executing a WFI instruction.
- *
- * This function must be called with preemption disabled, and as it
- * has the side effect of disabling coherency, caches must have been
- * flushed.  Interrupts must also have been disabled.
- */
-int scu_power_mode(void __iomem *scu_base, unsigned int mode)
+static int scu_set_power_mode_internal(void __iomem *scu_base,
+				       unsigned int logical_cpu,
+				       unsigned int mode)
 {
 	unsigned int val;
-	int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
+	int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0);
 
 	if (mode > 3 || mode == 1 || cpu > 3)
 		return -EINVAL;

@@ -94,3 +88,24 @@ int scu_power_mode(void __iomem *scu_base, unsigned int mode)
 
 	return 0;
 }
+
+/*
+ * Set the executing CPUs power mode as defined.  This will be in
+ * preparation for it executing a WFI instruction.
+ *
+ * This function must be called with preemption disabled, and as it
+ * has the side effect of disabling coherency, caches must have been
+ * flushed.  Interrupts must also have been disabled.
+ */
+int scu_power_mode(void __iomem *scu_base, unsigned int mode)
+{
+	return scu_set_power_mode_internal(scu_base, smp_processor_id(), mode);
+}
+
+/*
+ * Set the given (logical) CPU's power mode to SCU_PM_NORMAL.
+ */
+int scu_cpu_power_enable(void __iomem *scu_base, unsigned int cpu)
+{
+	return scu_set_power_mode_internal(scu_base, cpu, SCU_PM_NORMAL);
+}

Signature · 1 line

2.14.1

Russell King - ARM Linux

maintainer

2017-10-23 09:51 UTC #3 lore raw

PATCH v7 2/6 ARM: smp_scu: add a helper for powering on a specific CPU

Quoted 9 lines · Martin Blumenstingl

To boot the secondary CPUs on the Amlogic Meson8/Meson8m2 (Cortex-A9) and Meson8b (Cortex-A5) SoCs we have to enable SCU mode SCU_PM_NORMAL, otherwise the secondary cores will not start.
This patch adds a scu_cpu_power_enable() function which can be used to enable SCU_PM_NORMAL for a specific (logical) CPU. An internal helper function is also created, to avoid code duplication with scu_power_mode().
Signed-off-by Martin Blumenstingl <[email protected]>

Acked-by Russell King <[email protected]>

Signature · 3 lines

RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
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Martin Blumenstingl

author reviewer

2017-09-17 16:45 UTC #4 lore raw

PATCH v7 3/6 ARM: smp_scu: allow the platform code to read the SCU CPU status

In reply to Martin Blumenstingl

On Amlogic Meson8 / Meson8m2 (both Cortex-A9) and Meson8b (Cortex-A5) the CPU hotplug code needs to wait until the SCU status of the CPU that is being taken offline is SCU_PM_POWEROFF.
Provide a utility function (which can be invoked for example from .cpu_kill()) which allows reading the SCU status of a CPU.

While here, replace the magic number 0x3 with a preprocessor macro (SCU_CPU_STATUS_MASK) so we don't have to duplicate this magic number in the new function.

Signed-off-by Martin Blumenstingl <[email protected]>

---
 arch/arm/include/asm/smp_scu.h |  6 ++++++
 arch/arm/kernel/smp_scu.c      | 18 +++++++++++++++++-
 2 files changed, 23 insertions(+), 1 deletion(-)

arch/arm/include/asm/smp_scu.h +6 -0

index 4c47bdfd4f61..1529d1ae2f8d 100644
@@ -28,6 +28,7 @@ static inline unsigned long scu_a9_get_base(void)
 unsigned int scu_get_core_count(void __iomem *);
 int scu_power_mode(void __iomem *, unsigned int);
 int scu_cpu_power_enable(void __iomem *, unsigned int);
+int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu);
 #else
 static inline unsigned int scu_get_core_count(void __iomem *scu_base)
 {

@@ -42,6 +43,11 @@ static inline int scu_cpu_power_enable(void __iomem *scu_base,
 {
 	return -EINVAL;
 }
+static inline int scu_get_cpu_power_mode(void __iomem *scu_base,
+					 unsigned int logical_cpu)
+{
+	return -EINVAL;
+}
 #endif
 
 #if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU)

arch/arm/kernel/smp_scu.c +17 -1

index 1d549c16b5fc..c6b33074c393 100644
@@ -21,6 +21,7 @@
 #define SCU_STANDBY_ENABLE	(1 << 5)
 #define SCU_CONFIG		0x04
 #define SCU_CPU_STATUS		0x08
+#define SCU_CPU_STATUS_MASK	GENMASK(1, 0)
 #define SCU_INVALIDATE		0x0c
 #define SCU_FPGA_REVISION	0x10

@@ -82,7 +83,8 @@ static int scu_set_power_mode_internal(void __iomem *scu_base,
 	if (mode > 3 || mode == 1 || cpu > 3)
 		return -EINVAL;
 
-	val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
+	val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
+	val &= ~SCU_CPU_STATUS_MASK;
 	val |= mode;
 	writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);

@@ -109,3 +111,17 @@ int scu_cpu_power_enable(void __iomem *scu_base, unsigned int cpu)
 {
 	return scu_set_power_mode_internal(scu_base, cpu, SCU_PM_NORMAL);
 }
+
+int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu)
+{
+	unsigned int val;
+	int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0);
+
+	if (cpu > 3)
+		return -EINVAL;
+
+	val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
+	val &= SCU_CPU_STATUS_MASK;
+
+	return val;
+}

Signature · 1 line

2.14.1

Russell King - ARM Linux

maintainer

2017-10-23 09:54 UTC #5 lore raw

PATCH v7 3/6 ARM: smp_scu: allow the platform code to read the SCU CPU status

Quoted 11 lines · Martin Blumenstingl

On Amlogic Meson8 / Meson8m2 (both Cortex-A9) and Meson8b (Cortex-A5) the CPU hotplug code needs to wait until the SCU status of the CPU that is being taken offline is SCU_PM_POWEROFF.
Provide a utility function (which can be invoked for example from .cpu_kill()) which allows reading the SCU status of a CPU.
While here, replace the magic number 0x3 with a preprocessor macro (SCU_CPU_STATUS_MASK) so we don't have to duplicate this magic number in the new function.
Signed-off-by Martin Blumenstingl <[email protected]>

Acked-by Russell King <[email protected]>

Quoted 72 lines

---
 arch/arm/include/asm/smp_scu.h |  6 ++++++
 arch/arm/kernel/smp_scu.c      | 18 +++++++++++++++++-
 2 files changed, 23 insertions(+), 1 deletion(-)

arch/arm/include/asm/smp_scu.h +6 -0

index 4c47bdfd4f61..1529d1ae2f8d 100644
@@ -28,6 +28,7 @@ static inline unsigned long scu_a9_get_base(void)
 unsigned int scu_get_core_count(void __iomem *);
 int scu_power_mode(void __iomem *, unsigned int);
 int scu_cpu_power_enable(void __iomem *, unsigned int);
+int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu);
 #else
 static inline unsigned int scu_get_core_count(void __iomem *scu_base)
 {

@@ -42,6 +43,11 @@ static inline int scu_cpu_power_enable(void __iomem *scu_base,
 {
 	return -EINVAL;
 }
+static inline int scu_get_cpu_power_mode(void __iomem *scu_base,
+					 unsigned int logical_cpu)
+{
+	return -EINVAL;
+}
 #endif
 
 #if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU)

arch/arm/kernel/smp_scu.c +17 -1

index 1d549c16b5fc..c6b33074c393 100644
@@ -21,6 +21,7 @@
 #define SCU_STANDBY_ENABLE	(1 << 5)
 #define SCU_CONFIG		0x04
 #define SCU_CPU_STATUS		0x08
+#define SCU_CPU_STATUS_MASK	GENMASK(1, 0)
 #define SCU_INVALIDATE		0x0c
 #define SCU_FPGA_REVISION	0x10

@@ -82,7 +83,8 @@ static int scu_set_power_mode_internal(void __iomem *scu_base,
 	if (mode > 3 || mode == 1 || cpu > 3)
 		return -EINVAL;
 
-	val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
+	val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
+	val &= ~SCU_CPU_STATUS_MASK;
 	val |= mode;
 	writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);

@@ -109,3 +111,17 @@ int scu_cpu_power_enable(void __iomem *scu_base, unsigned int cpu)
 {
 	return scu_set_power_mode_internal(scu_base, cpu, SCU_PM_NORMAL);
 }
+
+int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu)
+{
+	unsigned int val;
+	int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0);
+
+	if (cpu > 3)
+		return -EINVAL;
+
+	val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
+	val &= SCU_CPU_STATUS_MASK;
+
+	return val;
+}

Signature · 1 line

2.14.1

Signature · 3 lines

RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up

Martin Blumenstingl

author reviewer

2017-09-17 16:45 UTC #6 lore raw

PATCH v7 4/6 ARM: meson: Add SMP bringup code for Meson8 and Meson8b

In reply to Martin Blumenstingl

This adds the necessary SMP-operations and startup code to use the additional cores on the Amlogic Meson8/Meson8m2 (both are using the same sequence) and Meson8b (using a slightly difference sequence) SoCs.

Signed-off-by Carlo Caione <[email protected]>

[add Meson8/Meson8m2 support and allow taking CPU cores offline as well]

Signed-off-by Martin Blumenstingl <[email protected]>

---
 arch/arm/Makefile             |   1 +
 arch/arm/mach-meson/Kconfig   |   1 +
 arch/arm/mach-meson/Makefile  |   1 +
 arch/arm/mach-meson/platsmp.c | 440 ++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 443 insertions(+)
 create mode 100644 arch/arm/mach-meson/platsmp.c

arch/arm/Makefile +1 -0

index 47d3a1ab08d2..82faa958ab88 100644
@@ -147,6 +147,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000
 endif
 textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
 textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
+textofs-$(CONFIG_ARCH_MESON) := 0x00208000
 textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
 
 # Machine directory name.  This list is sorted alphanumerically

arch/arm/mach-meson/Kconfig +1 -0

index ee30511849ca..a0c64762d961 100644
@@ -9,6 +9,7 @@ menuconfig ARCH_MESON
 	select PINCTRL_MESON
 	select COMMON_CLK
 	select COMMON_CLK_AMLOGIC
+	select HAVE_ARM_SCU if SMP
 
 if ARCH_MESON

arch/arm/mach-meson/Makefile +1 -0

index 9d7380eeeedd..bc26c85a7e8f 100644
@@ -1 +1,2 @@
 obj-$(CONFIG_ARCH_MESON) += meson.o
+obj-$(CONFIG_SMP) += platsmp.o

arch/arm/mach-meson/platsmp.c new file +440 -0

440 lines not on this page · raw message

Signature · 1 line

2.14.1

Linus Lüssing

2017-10-28 21:08 UTC #7 lore raw

PATCH v7 4/6 ARM: meson: Add SMP bringup code for Meson8 and Meson8b

arch/arm/Makefile textofs-$(CONFIG_SA1111) := 0x00208000 · line 153

Quoted 12 lines

arch/arm/Makefile +1 -0

index 47d3a1ab08d2..82faa958ab88 100644
@@ -147,6 +147,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000
 endif
 textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
 textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
+textofs-$(CONFIG_ARCH_MESON) := 0x00208000
 textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
 
 # Machine directory name.  This list is sorted alphanumerically

Due to the observations made/explained here [0], would it make
sense to put this diff into an extra patch? With a
"Fixes: 4a69fcd3a108 ("ARM: meson: Add DTS for Odroid-C1 and Tronfy MXQ boards")" and "Reported-by: Emiliano Ingrassia <[email protected]>" maybe?

Regards, Linus

[0]: https://lkml.org/lkml/2017/10/28/148

Martin Blumenstingl

author reviewer

2017-09-17 16:45 UTC #8 lore raw

PATCH v7 5/6 ARM: dts: meson8: add support for booting the secondary CPU cores

In reply to Martin Blumenstingl

Booting the secondary CPU cores involves the following nodes/devices:
- SCU (Snoop-Control-Unit, for which we already have a DT node)
- a reset line for each CPU core, provided by the reset-controller which is built into the clock-controller
- the PMU (power management unit) which controls the power of the CPU cores
- a range in the SRAM specifically reserved for booting secondary CPU cores
- the "enable-method" which activates booting the secondary CPU cores

This adds all required nodes and properties to boot the secondary CPU cores.

Signed-off-by Martin Blumenstingl <[email protected]>

---
 arch/arm/boot/dts/meson8.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

arch/arm/boot/dts/meson8.dtsi +21 -0

index b98d44fde6b6..bf572fb45fe0 100644
@@ -45,6 +45,7 @@
 
 #include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8-gpio.h>
+#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
 #include "meson.dtsi"
 
 / {

@@ -60,6 +61,8 @@
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
 			reg = <0x200>;
+			enable-method = "amlogic,meson8-smp";
+			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
 		};
 
 		cpu at 201 {

@@ -67,6 +70,8 @@
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
 			reg = <0x201>;
+			enable-method = "amlogic,meson8-smp";
+			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
 		};
 
 		cpu at 202 {

@@ -74,6 +79,8 @@
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
 			reg = <0x202>;
+			enable-method = "amlogic,meson8-smp";
+			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
 		};
 
 		cpu at 203 {

@@ -81,6 +88,8 @@
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
 			reg = <0x203>;
+			enable-method = "amlogic,meson8-smp";
+			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
 		};
 	};

@@ -118,6 +127,11 @@
 }; /* end of / */
 
 &aobus {
+	pmu: pmu at e0 {
+		compatible = "amlogic,meson8-pmu", "syscon";
+		reg = <0xe0 0x8>;
+	};
+
 	pinctrl_aobus: pinctrl at 84 {
 		compatible = "amlogic,meson8-aobus-pinctrl";
 		reg = <0x84 0xc>;

@@ -249,6 +263,13 @@
 	};
 };
 
+&ahb_sram {
+	smp-sram at 1ff80 {
+		compatible = "amlogic,meson8-smp-sram";
+		reg = <0x1ff80 0x8>;
+	};
+};
+
 &ethmac {
 	clocks = <&clkc CLKID_ETH>;
 	clock-names = "stmmaceth";

Signature · 1 line

2.14.1

Martin Blumenstingl

author reviewer

2017-09-17 16:45 UTC #9 lore raw

PATCH v7 6/6 ARM: dts: meson8b: add support for booting the secondary CPU cores

In reply to Martin Blumenstingl

From: Carlo Caione <[email protected]>

This adds all required nodes and properties to boot the secondary CPU cores.

Signed-off-by Carlo Caione <[email protected]>

Signed-off-by Martin Blumenstingl <[email protected]>

---
 arch/arm/boot/dts/meson8b.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

arch/arm/boot/dts/meson8b.dtsi +21 -0

index bc278da7df0d..aaebfcce9073 100644
@@ -47,6 +47,7 @@
 #include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8b-gpio.h>
 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
+#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
 #include "meson.dtsi"
 
 / {

@@ -59,6 +60,8 @@
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x200>;
+			enable-method = "amlogic,meson8b-smp";
+			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
 		};
 
 		cpu at 201 {

@@ -66,6 +69,8 @@
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x201>;
+			enable-method = "amlogic,meson8b-smp";
+			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
 		};
 
 		cpu at 202 {

@@ -73,6 +78,8 @@
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x202>;
+			enable-method = "amlogic,meson8b-smp";
+			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
 		};
 
 		cpu at 203 {

@@ -80,6 +87,8 @@
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x203>;
+			enable-method = "amlogic,meson8b-smp";
+			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
 		};
 	};

@@ -90,6 +99,11 @@
 }; /* end of / */
 
 &aobus {
+	pmu: pmu at e0 {
+		compatible = "amlogic,meson8b-pmu", "syscon";
+		reg = <0xe0 0x18>;
+	};
+
 	pinctrl_aobus: pinctrl at 84 {
 		compatible = "amlogic,meson8b-aobus-pinctrl";
 		reg = <0x84 0xc>;

@@ -157,6 +171,13 @@
 	};
 };
 
+&ahb_sram {
+	smp-sram at 1ff80 {
+		compatible = "amlogic,meson8b-smp-sram";
+		reg = <0x1ff80 0x8>;
+	};
+};
+
 &ethmac {
 	clocks = <&clkc CLKID_ETH>;
 	clock-names = "stmmaceth";

Signature · 1 line

2.14.1

Linus Lüssing

2017-09-29 11:29 UTC #10 lore raw

PATCH v7 6/6 ARM: dts: meson8b: add support for booting the secondary CPU cores

A five hours test run with the stress-ng tool worked fine for this patchset for me.

stress-ng command:

$ stress-ng -v --sequential 0 -t 120s --exclude sysfs,opcode --metrics

Logfile (6.3MB):
http://metameute.de/~tux/linux/amlogic/stress-ng-odroidc1%2b-with-resmem%2bsmp-log.txt

Tested device:
- Odroid C1+

Tested OS:
- Debian stable (stress-ng 0.07.16)

Tested kernel: v4.14-rc1 plus this patchset plus:
- "ARM: dts: meson: fixing USB support on Meson6, Meson8 and Meson8b"
https://patchwork.kernel.org/patch/9965871/
- "ARM: dts: meson: enabling the USB Host controller on Odroid-C1/C1+ board"
https://patchwork.kernel.org/patch/9961565/
- "[RFC] ARM: dts: meson8b: add reserved memory zones"
https://patchwork.kernel.org/patch/9977479/

Tested kernel config:
- multi_v7_defconfig, except CONFIG_DRM_TEGRA=n (build error otherwise)

I had to exclude the sysfs and opcode tests though. The former created an unhandled kernel paging request. And the latter a silent freeze after some seconds.

Those two issues seem unrelated to this patchset though, therefore

Tested-by Linus L?ssing <[email protected]>

Martin Blumenstingl

author reviewer

2017-10-01 12:19 UTC #11 lore raw

v7 cover SMP and CPU hotplug support for Meson8/Meson8b

In reply to Martin Blumenstingl

Hello Russel, Hi Kevin,

Quoted 10 lines · Martin Blumenstingl

This patchset adds support for booting the secondary CPU cores (and taking them offline again) on Amlogic Meson8 and Meson8b SoCs. It is based on an earlier version from Carlo Caione - this helped me a lot to get a better understanding of how SMP/CPU hotplug works (compared to the code found in Amlogic's GPL kernel sources from year 2015).
Changes since v6 from [6]:
- rebased on top of v4.14-rc1 (which only corrected some line numbers in the SCU patches)

it's been two weeks since v6 and since then Linus L?ssing has confirmed that this works fine on his Odroid-C1 as well (many thanks for testing!): [7]

Quoted 77 lines

Changes since v5 from [5]:
- dropped dependency on another patch series (for the clock controller's embedded reset controller, which is needed to boot the secondary CPUs) from the cover-letter as that series is now merged
- fix incorrect documentation of scu_cpu_power_enable (thanks to Russell King for spotting these). removed the paragraph about preemption, cache coherency and interrupts as we're powering on a CPU core (the text was copied from the original scu_power_mode but simply not adjusted). also changed "Set the executing CPUs" to "Set the given (logical) CPU's" as we're not modifying the current CPU. this affects only patch #2
- extended the commit message of patch #3 with a short sentence about why SCU_CPU_STATUS_MASK was introduced
Changes since v4 from [4]:
- use __pa_symbol(secondary_startup) instead of virt_to_phys(secondary_startup) as suggested by Florian Fainelli (affects patch #4)
- (cover-letter) removed dependency on my other patch "ARM: dts: meson: add a node which describes the SRAM" [2] as that was merged into Kevin's Amlogic repo today
- dropped patch #5 ("clk: meson: meson8b: export the CPU soft reset lines") again because the reset controller series exposes the preprocessor macros now directly, see [1]
- refreshed the .dts patches so they now include the new header for the reset line preprocessor macros
Changes since v3 from [3]:
- added Rob's ACK to patch #1
- replaced a msleep(10) with usleep_range(10000, 15000) in patch #4
- removed all "pen" code from patch #4 as that code was not needed at all (it was left-over while trying to fix Meson8 secondary CPU boot - which turned out to have nothing to do with this "pen" code)
- removed all memory barrier operations as they were added based on the code in the Amlogic GPL kernel tree (while trying to fix the Meson8 secondary CPU boot - just like the "pen" code). Everything still works fine with these on my Meson8m2 and Meson8b boards.
- added PATCH #5 as we now have to export the reset identifiers (just like we do it with the clock identifiers / preprocessor macros) - this is the result of a change in the reset controller patch in version 2, see [1]
- use the reset line preprocessor macros (from patch #5) in patches #6 and #7
Changes since v2 from [0]:
- added support for Meson8 (which requires a slightly different enable-method)
- implemented CPU hotplug support which allows taking a CPU core offline for both, Meson8 and Meson8b
- add a function to smp_scu.c which allows enabling a CPU core from a different CPU (previously only the power mode for the current CPU could be changed). Without this the CPU cores on Meson8 won't come up (Amlogic's vendor GPL kernel sources also enable power through SCU as very first step for Meson8b as well)
- add a function to smp_scu.c to get the power status of a CPU core (which is needed because the code in .cpu_kill needs to wait until the core is actually powered off)
- dropped patch "ARM: DTS: meson8b: Extend L2 cache controller node" as it is already applied (for both, Meson8 and Meson8b)
- dropped the patches which implement the reset controller which is built into the clock-controller, these are a separate series: [1]
- moved the enable-method property to each CPU node
[0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390355.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004456.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004282.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004297.html
[4] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004354.html
[5] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004460.html
[6] http://lists.infradead.org/pipermail/linux-amlogic/2017-August/004588.html
Carlo Caione (2):
dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation
ARM: dts: meson8b: add support for booting the secondary CPU cores

Quoted 5 lines

Martin Blumenstingl (4):
ARM: smp_scu: add a helper for powering on a specific CPU
ARM: smp_scu: allow the platform code to read the SCU CPU status
ARM: meson: Add SMP bringup code for Meson8 and Meson8b
ARM: dts: meson8: add support for booting the secondary CPU cores

@Russel: should Kevin take all patches including the two smp_scu ones? or do you want to take them through your own tree?

Quoted 16 lines

 .../devicetree/bindings/arm/amlogic/pmu.txt        |  18 +
 .../devicetree/bindings/arm/amlogic/smp-sram.txt   |  32 ++
 Documentation/devicetree/bindings/arm/cpus.txt     |   2 +
 arch/arm/Makefile                                  |   1 +
 arch/arm/boot/dts/meson8.dtsi                      |  21 +
 arch/arm/boot/dts/meson8b.dtsi                     |  21 +
 arch/arm/include/asm/smp_scu.h                     |  12 +
 arch/arm/kernel/smp_scu.c                          |  43 +-
 arch/arm/mach-meson/Kconfig                        |   1 +
 arch/arm/mach-meson/Makefile                       |   1 +
 arch/arm/mach-meson/platsmp.c                      | 440 +++++++++++++++++++++
 11 files changed, 586 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/amlogic/pmu.txt
 create mode 100644 Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt
 create mode 100644 arch/arm/mach-meson/platsmp.c

Quoted 3 lines

--
2.14.1

Regards,
Martin

[7] http://lists.infradead.org/pipermail/linux-amlogic/2017-September/004813.html

Kevin Hilman

maintainer

2017-10-06 21:30 UTC #12 lore raw

v7 cover SMP and CPU hotplug support for Meson8/Meson8b

Quoted 95 lines · Martin Blumenstingl

Hello Russel, Hi Kevin,
Quoted 10 lines · Martin Blumenstingl
This patchset adds support for booting the secondary CPU cores (and taking them offline again) on Amlogic Meson8 and Meson8b SoCs. It is based on an earlier version from Carlo Caione - this helped me a lot to get a better understanding of how SMP/CPU hotplug works (compared to the code found in Amlogic's GPL kernel sources from year 2015).
Changes since v6 from [6]:
- rebased on top of v4.14-rc1 (which only corrected some line numbers in the SCU patches)
it's been two weeks since v6 and since then Linus L?ssing has confirmed that this works fine on his Odroid-C1 as well (many thanks for testing!): [7]
Quoted 77 lines
Changes since v5 from [5]:
- dropped dependency on another patch series (for the clock controller's embedded reset controller, which is needed to boot the secondary CPUs) from the cover-letter as that series is now merged
- fix incorrect documentation of scu_cpu_power_enable (thanks to Russell King for spotting these). removed the paragraph about preemption, cache coherency and interrupts as we're powering on a CPU core (the text was copied from the original scu_power_mode but simply not adjusted). also changed "Set the executing CPUs" to "Set the given (logical) CPU's" as we're not modifying the current CPU. this affects only patch #2
- extended the commit message of patch #3 with a short sentence about why SCU_CPU_STATUS_MASK was introduced
Changes since v4 from [4]:
- use __pa_symbol(secondary_startup) instead of virt_to_phys(secondary_startup) as suggested by Florian Fainelli (affects patch #4)
- (cover-letter) removed dependency on my other patch "ARM: dts: meson: add a node which describes the SRAM" [2] as that was merged into Kevin's Amlogic repo today
- dropped patch #5 ("clk: meson: meson8b: export the CPU soft reset lines") again because the reset controller series exposes the preprocessor macros now directly, see [1]
- refreshed the .dts patches so they now include the new header for the reset line preprocessor macros
Changes since v3 from [3]:
- added Rob's ACK to patch #1
- replaced a msleep(10) with usleep_range(10000, 15000) in patch #4
- removed all "pen" code from patch #4 as that code was not needed at all (it was left-over while trying to fix Meson8 secondary CPU boot - which turned out to have nothing to do with this "pen" code)
- removed all memory barrier operations as they were added based on the code in the Amlogic GPL kernel tree (while trying to fix the Meson8 secondary CPU boot - just like the "pen" code). Everything still works fine with these on my Meson8m2 and Meson8b boards.
- added PATCH #5 as we now have to export the reset identifiers (just like we do it with the clock identifiers / preprocessor macros) - this is the result of a change in the reset controller patch in version 2, see [1]
- use the reset line preprocessor macros (from patch #5) in patches #6 and #7
Changes since v2 from [0]:
- added support for Meson8 (which requires a slightly different enable-method)
- implemented CPU hotplug support which allows taking a CPU core offline for both, Meson8 and Meson8b
- add a function to smp_scu.c which allows enabling a CPU core from a different CPU (previously only the power mode for the current CPU could be changed). Without this the CPU cores on Meson8 won't come up (Amlogic's vendor GPL kernel sources also enable power through SCU as very first step for Meson8b as well)
- add a function to smp_scu.c to get the power status of a CPU core (which is needed because the code in .cpu_kill needs to wait until the core is actually powered off)
- dropped patch "ARM: DTS: meson8b: Extend L2 cache controller node" as it is already applied (for both, Meson8 and Meson8b)
- dropped the patches which implement the reset controller which is built into the clock-controller, these are a separate series: [1]
- moved the enable-method property to each CPU node
[0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390355.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004456.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004282.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004297.html
[4] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004354.html
[5] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004460.html
[6] http://lists.infradead.org/pipermail/linux-amlogic/2017-August/004588.html
Carlo Caione (2):
dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation
ARM: dts: meson8b: add support for booting the secondary CPU cores

Quoted 7 lines

Quoted 5 lines
Martin Blumenstingl (4):
ARM: smp_scu: add a helper for powering on a specific CPU
ARM: smp_scu: allow the platform code to read the SCU CPU status
ARM: meson: Add SMP bringup code for Meson8 and Meson8b
ARM: dts: meson8: add support for booting the secondary CPU cores
@Russel: should Kevin take all patches including the two smp_scu ones? or do you want to take them through your own tree?

With Russell's ack, I can take the series via the amlogic tree. But I'm also fine if Russell wants to take the arch/arm/* via his tree, and I will just queue up the DT.

Kevin

Martin Blumenstingl

author reviewer

2017-10-20 22:14 UTC #13 lore raw

v7 cover SMP and CPU hotplug support for Meson8/Meson8b

Hi Russel,

Quoted 93 lines · Kevin Hilman

Quoted 91 lines · Martin Blumenstingl
Hello Russel, Hi Kevin,
Quoted 10 lines · Martin Blumenstingl
This patchset adds support for booting the secondary CPU cores (and taking them offline again) on Amlogic Meson8 and Meson8b SoCs. It is based on an earlier version from Carlo Caione - this helped me a lot to get a better understanding of how SMP/CPU hotplug works (compared to the code found in Amlogic's GPL kernel sources from year 2015).
Changes since v6 from [6]:
- rebased on top of v4.14-rc1 (which only corrected some line numbers in the SCU patches)
it's been two weeks since v6 and since then Linus L?ssing has confirmed that this works fine on his Odroid-C1 as well (many thanks for testing!): [7]
Quoted 73 lines
Changes since v5 from [5]:
- dropped dependency on another patch series (for the clock controller's embedded reset controller, which is needed to boot the secondary CPUs) from the cover-letter as that series is now merged
- fix incorrect documentation of scu_cpu_power_enable (thanks to Russell King for spotting these). removed the paragraph about preemption, cache coherency and interrupts as we're powering on a CPU core (the text was copied from the original scu_power_mode but simply not adjusted). also changed "Set the executing CPUs" to "Set the given (logical) CPU's" as we're not modifying the current CPU. this affects only patch #2
- extended the commit message of patch #3 with a short sentence about why SCU_CPU_STATUS_MASK was introduced
Changes since v4 from [4]:
- use __pa_symbol(secondary_startup) instead of virt_to_phys(secondary_startup) as suggested by Florian Fainelli (affects patch #4)
- (cover-letter) removed dependency on my other patch "ARM: dts: meson: add a node which describes the SRAM" [2] as that was merged into Kevin's Amlogic repo today
- dropped patch #5 ("clk: meson: meson8b: export the CPU soft reset lines") again because the reset controller series exposes the preprocessor macros now directly, see [1]
- refreshed the .dts patches so they now include the new header for the reset line preprocessor macros
Changes since v3 from [3]:
- added Rob's ACK to patch #1
- replaced a msleep(10) with usleep_range(10000, 15000) in patch #4
- removed all "pen" code from patch #4 as that code was not needed at all (it was left-over while trying to fix Meson8 secondary CPU boot - which turned out to have nothing to do with this "pen" code)
- removed all memory barrier operations as they were added based on the code in the Amlogic GPL kernel tree (while trying to fix the Meson8 secondary CPU boot - just like the "pen" code). Everything still works fine with these on my Meson8m2 and Meson8b boards.
- added PATCH #5 as we now have to export the reset identifiers (just like we do it with the clock identifiers / preprocessor macros) - this is the result of a change in the reset controller patch in version 2, see [1]
- use the reset line preprocessor macros (from patch #5) in patches #6 and #7
Changes since v2 from [0]:
- added support for Meson8 (which requires a slightly different enable-method)
- implemented CPU hotplug support which allows taking a CPU core offline for both, Meson8 and Meson8b
- add a function to smp_scu.c which allows enabling a CPU core from a different CPU (previously only the power mode for the current CPU could be changed). Without this the CPU cores on Meson8 won't come up (Amlogic's vendor GPL kernel sources also enable power through SCU as very first step for Meson8b as well)
- add a function to smp_scu.c to get the power status of a CPU core (which is needed because the code in .cpu_kill needs to wait until the core is actually powered off)
- dropped patch "ARM: DTS: meson8b: Extend L2 cache controller node" as it is already applied (for both, Meson8 and Meson8b)
- dropped the patches which implement the reset controller which is built into the clock-controller, these are a separate series: [1]
- moved the enable-method property to each CPU node
[0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390355.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004456.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004282.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004297.html
[4] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004354.html
[5] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004460.html
[6] http://lists.infradead.org/pipermail/linux-amlogic/2017-August/004588.html

Quoted 7 lines

Quoted 7 lines
Quoted 7 lines
Carlo Caione (2):
dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation
ARM: dts: meson8b: add support for booting the secondary CPU cores
Martin Blumenstingl (4):
ARM: smp_scu: add a helper for powering on a specific CPU
ARM: smp_scu: allow the platform code to read the SCU CPU status

could you please have a look at these two patches? it would be great if you could give feedback on these, because they are needed for SMP support on the Amlogic Meson8 and Meson8b platforms

Quoted 8 lines

Quoted 4 lines
Quoted 2 lines
ARM: meson: Add SMP bringup code for Meson8 and Meson8b
ARM: dts: meson8: add support for booting the secondary CPU cores
@Russel: should Kevin take all patches including the two smp_scu ones? or do you want to take them through your own tree?
With Russell's ack, I can take the series via the amlogic tree. But I'm also fine if Russell wants to take the arch/arm/* via his tree, and I will just queue up the DT.

please also let Kevin know if you would like him to take these patches through the amlogic tree

thank you in advance!

Regards
Martin

Russell King - ARM Linux

maintainer

2017-10-23 09:49 UTC #14 lore raw

v7 cover SMP and CPU hotplug support for Meson8/Meson8b

Quoted 109 lines · Martin Blumenstingl

Hi Russel,
Quoted 93 lines · Kevin Hilman
Quoted 91 lines · Martin Blumenstingl
Hello Russel, Hi Kevin,
Quoted 10 lines · Martin Blumenstingl
This patchset adds support for booting the secondary CPU cores (and taking them offline again) on Amlogic Meson8 and Meson8b SoCs. It is based on an earlier version from Carlo Caione - this helped me a lot to get a better understanding of how SMP/CPU hotplug works (compared to the code found in Amlogic's GPL kernel sources from year 2015).
Changes since v6 from [6]:
- rebased on top of v4.14-rc1 (which only corrected some line numbers in the SCU patches)
it's been two weeks since v6 and since then Linus L?ssing has confirmed that this works fine on his Odroid-C1 as well (many thanks for testing!): [7]
Quoted 73 lines
Changes since v5 from [5]:
- dropped dependency on another patch series (for the clock controller's embedded reset controller, which is needed to boot the secondary CPUs) from the cover-letter as that series is now merged
- fix incorrect documentation of scu_cpu_power_enable (thanks to Russell King for spotting these). removed the paragraph about preemption, cache coherency and interrupts as we're powering on a CPU core (the text was copied from the original scu_power_mode but simply not adjusted). also changed "Set the executing CPUs" to "Set the given (logical) CPU's" as we're not modifying the current CPU. this affects only patch #2
- extended the commit message of patch #3 with a short sentence about why SCU_CPU_STATUS_MASK was introduced
Changes since v4 from [4]:
- use __pa_symbol(secondary_startup) instead of virt_to_phys(secondary_startup) as suggested by Florian Fainelli (affects patch #4)
- (cover-letter) removed dependency on my other patch "ARM: dts: meson: add a node which describes the SRAM" [2] as that was merged into Kevin's Amlogic repo today
- dropped patch #5 ("clk: meson: meson8b: export the CPU soft reset lines") again because the reset controller series exposes the preprocessor macros now directly, see [1]
- refreshed the .dts patches so they now include the new header for the reset line preprocessor macros
Changes since v3 from [3]:
- added Rob's ACK to patch #1
- replaced a msleep(10) with usleep_range(10000, 15000) in patch #4
- removed all "pen" code from patch #4 as that code was not needed at all (it was left-over while trying to fix Meson8 secondary CPU boot - which turned out to have nothing to do with this "pen" code)
- removed all memory barrier operations as they were added based on the code in the Amlogic GPL kernel tree (while trying to fix the Meson8 secondary CPU boot - just like the "pen" code). Everything still works fine with these on my Meson8m2 and Meson8b boards.
- added PATCH #5 as we now have to export the reset identifiers (just like we do it with the clock identifiers / preprocessor macros) - this is the result of a change in the reset controller patch in version 2, see [1]
- use the reset line preprocessor macros (from patch #5) in patches #6 and #7
Changes since v2 from [0]:
- added support for Meson8 (which requires a slightly different enable-method)
- implemented CPU hotplug support which allows taking a CPU core offline for both, Meson8 and Meson8b
- add a function to smp_scu.c which allows enabling a CPU core from a different CPU (previously only the power mode for the current CPU could be changed). Without this the CPU cores on Meson8 won't come up (Amlogic's vendor GPL kernel sources also enable power through SCU as very first step for Meson8b as well)
- add a function to smp_scu.c to get the power status of a CPU core (which is needed because the code in .cpu_kill needs to wait until the core is actually powered off)
- dropped patch "ARM: DTS: meson8b: Extend L2 cache controller node" as it is already applied (for both, Meson8 and Meson8b)
- dropped the patches which implement the reset controller which is built into the clock-controller, these are a separate series: [1]
- moved the enable-method property to each CPU node
[0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390355.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004456.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004282.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004297.html
[4] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004354.html
[5] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004460.html
[6] http://lists.infradead.org/pipermail/linux-amlogic/2017-August/004588.html
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Carlo Caione (2):
dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation
ARM: dts: meson8b: add support for booting the secondary CPU cores
Martin Blumenstingl (4):
ARM: smp_scu: add a helper for powering on a specific CPU
ARM: smp_scu: allow the platform code to read the SCU CPU status
could you please have a look at these two patches? it would be great if you could give feedback on these, because they are needed for SMP support on the Amlogic Meson8 and Meson8b platforms
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ARM: meson: Add SMP bringup code for Meson8 and Meson8b
ARM: dts: meson8: add support for booting the secondary CPU cores

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@Russel: should Kevin take all patches including the two smp_scu ones? or do you want to take them through your own tree?
With Russell's ack, I can take the series via the amlogic tree. But I'm also fine if Russell wants to take the arch/arm/* via his tree, and I will just queue up the DT.
please also let Kevin know if you would like him to take these patches through the amlogic tree

Stuff in this thread seems to be sent either over the weekend, or late on Friday, which means it gets buried by Monday. I'll look at it now.

Signature · 3 lines

RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
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Martin Blumenstingl

author reviewer

2017-10-25 21:05 UTC #15 lore raw

v7 cover SMP and CPU hotplug support for Meson8/Meson8b

Hi Russel,

Quoted 113 lines · Russell King - ARM Linux

Quoted 112 lines · Martin Blumenstingl
Hi Russel,
Quoted 93 lines · Kevin Hilman
Quoted 91 lines · Martin Blumenstingl
Hello Russel, Hi Kevin,
Quoted 10 lines · Martin Blumenstingl
This patchset adds support for booting the secondary CPU cores (and taking them offline again) on Amlogic Meson8 and Meson8b SoCs. It is based on an earlier version from Carlo Caione - this helped me a lot to get a better understanding of how SMP/CPU hotplug works (compared to the code found in Amlogic's GPL kernel sources from year 2015).
Changes since v6 from [6]:
- rebased on top of v4.14-rc1 (which only corrected some line numbers in the SCU patches)
it's been two weeks since v6 and since then Linus L?ssing has confirmed that this works fine on his Odroid-C1 as well (many thanks for testing!): [7]
Quoted 73 lines
Changes since v5 from [5]:
- dropped dependency on another patch series (for the clock controller's embedded reset controller, which is needed to boot the secondary CPUs) from the cover-letter as that series is now merged
- fix incorrect documentation of scu_cpu_power_enable (thanks to Russell King for spotting these). removed the paragraph about preemption, cache coherency and interrupts as we're powering on a CPU core (the text was copied from the original scu_power_mode but simply not adjusted). also changed "Set the executing CPUs" to "Set the given (logical) CPU's" as we're not modifying the current CPU. this affects only patch #2
- extended the commit message of patch #3 with a short sentence about why SCU_CPU_STATUS_MASK was introduced
Changes since v4 from [4]:
- use __pa_symbol(secondary_startup) instead of virt_to_phys(secondary_startup) as suggested by Florian Fainelli (affects patch #4)
- (cover-letter) removed dependency on my other patch "ARM: dts: meson: add a node which describes the SRAM" [2] as that was merged into Kevin's Amlogic repo today
- dropped patch #5 ("clk: meson: meson8b: export the CPU soft reset lines") again because the reset controller series exposes the preprocessor macros now directly, see [1]
- refreshed the .dts patches so they now include the new header for the reset line preprocessor macros
Changes since v3 from [3]:
- added Rob's ACK to patch #1
- replaced a msleep(10) with usleep_range(10000, 15000) in patch #4
- removed all "pen" code from patch #4 as that code was not needed at all (it was left-over while trying to fix Meson8 secondary CPU boot - which turned out to have nothing to do with this "pen" code)
- removed all memory barrier operations as they were added based on the code in the Amlogic GPL kernel tree (while trying to fix the Meson8 secondary CPU boot - just like the "pen" code). Everything still works fine with these on my Meson8m2 and Meson8b boards.
- added PATCH #5 as we now have to export the reset identifiers (just like we do it with the clock identifiers / preprocessor macros) - this is the result of a change in the reset controller patch in version 2, see [1]
- use the reset line preprocessor macros (from patch #5) in patches #6 and #7
Changes since v2 from [0]:
- added support for Meson8 (which requires a slightly different enable-method)
- implemented CPU hotplug support which allows taking a CPU core offline for both, Meson8 and Meson8b
- add a function to smp_scu.c which allows enabling a CPU core from a different CPU (previously only the power mode for the current CPU could be changed). Without this the CPU cores on Meson8 won't come up (Amlogic's vendor GPL kernel sources also enable power through SCU as very first step for Meson8b as well)
- add a function to smp_scu.c to get the power status of a CPU core (which is needed because the code in .cpu_kill needs to wait until the core is actually powered off)
- dropped patch "ARM: DTS: meson8b: Extend L2 cache controller node" as it is already applied (for both, Meson8 and Meson8b)
- dropped the patches which implement the reset controller which is built into the clock-controller, these are a separate series: [1]
- moved the enable-method property to each CPU node
[0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390355.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004456.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004282.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004297.html
[4] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004354.html
[5] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004460.html
[6] http://lists.infradead.org/pipermail/linux-amlogic/2017-August/004588.html
Quoted 7 lines
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Carlo Caione (2):
dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation
ARM: dts: meson8b: add support for booting the secondary CPU cores
Martin Blumenstingl (4):
ARM: smp_scu: add a helper for powering on a specific CPU
ARM: smp_scu: allow the platform code to read the SCU CPU status
could you please have a look at these two patches? it would be great if you could give feedback on these, because they are needed for SMP support on the Amlogic Meson8 and Meson8b platforms
Quoted 5 lines
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ARM: meson: Add SMP bringup code for Meson8 and Meson8b
ARM: dts: meson8: add support for booting the secondary CPU cores
@Russel: should Kevin take all patches including the two smp_scu ones? or do you want to take them through your own tree?

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With Russell's ack, I can take the series via the amlogic tree. But I'm also fine if Russell wants to take the arch/arm/* via his tree, and I will just queue up the DT.
please also let Kevin know if you would like him to take these patches through the amlogic tree
Stuff in this thread seems to be sent either over the weekend, or late on Friday, which means it gets buried by Monday. I'll look at it now.

thank you for reviewing my patches!

I do this in my spare time - so I typically end up having all bugs fixed at some point during the weekend
however, you still found my patches - problem solved. :)

Thank you!
Regards
Martin

Kevin Hilman

maintainer Applied

2017-10-29 15:31 UTC #16 lore raw

v7 cover SMP and CPU hotplug support for Meson8/Meson8b

In reply to Martin Blumenstingl

Quoted 6 lines · Martin Blumenstingl

This patchset adds support for booting the secondary CPU cores (and taking them offline again) on Amlogic Meson8 and Meson8b SoCs. It is based on an earlier version from Carlo Caione - this helped me a lot to get a better understanding of how SMP/CPU hotplug works (compared to the code found in Amlogic's GPL kernel sources from year 2015).

[...]

Quoted 3 lines

Carlo Caione (2):
dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation
ARM: dts: meson8b: add support for booting the secondary CPU cores

Applied to v4.15/dt...

Quoted 5 lines

Martin Blumenstingl (4):
ARM: smp_scu: add a helper for powering on a specific CPU
ARM: smp_scu: allow the platform code to read the SCU CPU status
ARM: meson: Add SMP bringup code for Meson8 and Meson8b
ARM: dts: meson8: add support for booting the secondary CPU cores

Applied to v4.15/soc with Russell's ack.

Thanks,

Kevin