Add support for GE PPD

Add missing parts for i.MX53 PWM support

Acked-by Nandor Han <[email protected]>

Signed-off-by Martyn Welch <[email protected]>

Cc Stefano Babic <[email protected]>

---
 arch/arm/include/asm/arch-mx5/imx-regs.h | 19 +++++++++++++++++++
 drivers/pwm/pwm-imx-util.c               |  2 ++
 2 files changed, 21 insertions(+)

arch/arm/include/asm/arch-mx5/imx-regs.h +0 -0

index 3e79fa3..c2ff798 100644

arch/arm/include/asm/arch-mx5/imx-regs.h +18 -0

+#define PWMCR_PRESCALER(x)	(((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN		(1 << 24)
+#define PWMCR_WAITEN		(1 << 23)
+#define PWMCR_DBGEN		(1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH	(2 << 16)
+#define PWMCR_CLKSRC_IPG	(1 << 16)
+#define PWMCR_EN		(1 << 0)
+
+struct pwm_regs {
+	u32	cr;
+	u32	sr;
+	u32	ir;
+	u32	sar;
+	u32	pr;
+	u32	cnr;
+};
+#endif
+
 #endif /* __ASSEMBLER__*/
 
 #endif				/* __ASM_ARCH_MX5_IMX_REGS_H__ */

drivers/pwm/pwm-imx-util.c +0 -0

index 534dd8e..97ac0c8 100644
@@ -23,10 +23,12 @@ struct pwm_regs *pwm_id_to_reg(int pwm_id)
 		return (struct pwm_regs *)PWM1_BASE_ADDR;
 	case 1:

Quoted 18 lines · Martyn Welch

Add missing parts for i.MX53 PWM support

Acked-by Nandor Han <[email protected]>

Signed-off-by Martyn Welch <[email protected]>

Cc Stefano Babic <[email protected]>

---
 arch/arm/include/asm/arch-mx5/imx-regs.h | 19 +++++++++++++++++++
 drivers/pwm/pwm-imx-util.c               |  2 ++
 2 files changed, 21 insertions(+)

arch/arm/include/asm/arch-mx5/imx-regs.h +0 -0

index 3e79fa3..c2ff798 100644
@@ -508,6 +508,25 @@ struct fuse_bank4_regs {
 };
 #endif
 

arch/arm/include/asm/arch-mx5/imx-regs.h struct fuse_bank4_regs { · line 511

Quoted 1 line

arch/arm/include/asm/arch-mx5/imx-regs.h +1 -0

+#if defined(CONFIG_MX53)

It looks to me this is not MX53 specific. You are already changing a MX5 file. As far as I see, this is valid at least for MX51. Do we need the #ifdef ?

Quoted 29 lines

arch/arm/include/asm/arch-mx5/imx-regs.h +18 -0

+#define PWMCR_PRESCALER(x)	(((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN		(1 << 24)
+#define PWMCR_WAITEN		(1 << 23)
+#define PWMCR_DBGEN		(1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH	(2 << 16)
+#define PWMCR_CLKSRC_IPG	(1 << 16)
+#define PWMCR_EN		(1 << 0)
+
+struct pwm_regs {
+	u32	cr;
+	u32	sr;
+	u32	ir;
+	u32	sar;
+	u32	pr;
+	u32	cnr;
+};
+#endif
+
 #endif /* __ASSEMBLER__*/
 
 #endif				/* __ASM_ARCH_MX5_IMX_REGS_H__ */

drivers/pwm/pwm-imx-util.c +0 -0

index 534dd8e..97ac0c8 100644
@@ -23,10 +23,12 @@ struct pwm_regs *pwm_id_to_reg(int pwm_id)
 		return (struct pwm_regs *)PWM1_BASE_ADDR;
 	case 1:

drivers/pwm/pwm-imx-util.c struct pwm_regs *pwm_id_to_reg(int pwm_id) · line 34

Quoted 10 lines

drivers/pwm/pwm-imx-util.c +2 -0

 		return (struct pwm_regs *)PWM2_BASE_ADDR;
+#ifdef CONFIG_MX6
 	case 2:
 		return (struct pwm_regs *)PWM3_BASE_ADDR;
 	case 3:
 		return (struct pwm_regs *)PWM4_BASE_ADDR;
+#endif
 #ifdef CONFIG_MX6SX
 	case 4:
 		return (struct pwm_regs *)PWM5_BASE_ADDR;

Best regards,
Stefano Babic

Quoted 19 lines · Stefano Babic

Quoted 18 lines · Martyn Welch

Add missing parts for i.MX53 PWM support

Acked-by Nandor Han <[email protected]>

Signed-off-by Martyn Welch <[email protected]>

Cc Stefano Babic <[email protected]>

---
 arch/arm/include/asm/arch-mx5/imx-regs.h | 19 +++++++++++++++++++
 drivers/pwm/pwm-imx-util.c               |  2 ++
 2 files changed, 21 insertions(+)

arch/arm/include/asm/arch-mx5/imx-regs.h +0 -0

index 3e79fa3..c2ff798 100644
@@ -508,6 +508,25 @@ struct fuse_bank4_regs {
 };
 #endif
 

Quoted 6 lines

arch/arm/include/asm/arch-mx5/imx-regs.h struct fuse_bank4_regs { · line 511

Quoted 1 line

arch/arm/include/asm/arch-mx5/imx-regs.h +1 -0

+#if defined(CONFIG_MX53)

It looks to me this is not MX53 specific. You are already changing a MX5 file. As far as I see, this is valid at least for MX51. Do we need the #ifdef ?

I only have access to an MX53, I'm not familiar with the rest of the MX5 family and was thus playing it safe.

Quoted 45 lines

Quoted 30 lines

arch/arm/include/asm/arch-mx5/imx-regs.h +18 -0

+#define PWMCR_PRESCALER(x)	(((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN		(1 << 24)
+#define PWMCR_WAITEN		(1 << 23)
+#define PWMCR_DBGEN		(1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH	(2 << 16)
+#define PWMCR_CLKSRC_IPG	(1 << 16)
+#define PWMCR_EN		(1 << 0)
+
+struct pwm_regs {
+	u32	cr;
+	u32	sr;
+	u32	ir;
+	u32	sar;
+	u32	pr;
+	u32	cnr;
+};
+#endif
+
 #endif /* __ASSEMBLER__*/
 
 #endif				/* __ASM_ARCH_MX5_IMX_REGS_H__ */

drivers/pwm/pwm-imx-util.c +0 -0

index 534dd8e..97ac0c8 100644
@@ -23,10 +23,12 @@ struct pwm_regs *pwm_id_to_reg(int pwm_id)
 		return (struct pwm_regs *)PWM1_BASE_ADDR;
 	case 1:

drivers/pwm/pwm-imx-util.c struct pwm_regs *pwm_id_to_reg(int pwm_id) · line 34

Quoted 10 lines

drivers/pwm/pwm-imx-util.c +2 -0

 		return (struct pwm_regs *)PWM2_BASE_ADDR;
+#ifdef CONFIG_MX6
 	case 2:
 		return (struct pwm_regs *)PWM3_BASE_ADDR;
 	case 3:
 		return (struct pwm_regs *)PWM4_BASE_ADDR;
+#endif
 #ifdef CONFIG_MX6SX
 	case 4:
 		return (struct pwm_regs *)PWM5_BASE_ADDR;

Best regards,
Stefano Babic

Add register definitions require for video configuration.

Signed-off-by Nandor Han <[email protected]>

Signed-off-by Martyn Welch <[email protected]>

Cc Stefano Babic <[email protected]>

---
 arch/arm/include/asm/arch-mx5/crm_regs.h |  9 +++++++++
 arch/arm/include/asm/arch-mx5/imx-regs.h | 28 ++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+)

arch/arm/include/asm/arch-mx5/crm_regs.h +9 -0

index b61c7b9..c0af832 100644
@@ -210,6 +210,15 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL		(0x1 << 1)
 #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL		0x1
 
+/* Define the bits in register CSCMR2 */
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_OFFSET		26
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK		(0x7 << 26)
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL(v)		(((v) & 0x7) << 26)
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_RD(r)	(((r) >> 26) & 0x7)
+
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK 5
+
+
 /* Define the bits in register CSCDR2 */
 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET		25
 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK		(0x7 << 25)

arch/arm/include/asm/arch-mx5/imx-regs.h +21 -0

index c2ff798..60c1bb9 100644
@@ -416,6 +416,34 @@ struct iomuxc {
 };
 #endif
 
+
+#define IOMUXC_GPR2_BITMAP_SPWG	0
+#define IOMUXC_GPR2_BITMAP_JEIDA	1
+
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET		6
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK		(1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA		(IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG		(IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+
+#define IOMUXC_GPR2_DATA_WIDTH_18	0
+#define IOMUXC_GPR2_DATA_WIDTH_24	1
+
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET		5
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK			(1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT		(IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT		(IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+
+#define IOMUXC_GPR2_MODE_DISABLED	0
+#define IOMUXC_GPR2_MODE_ENABLED_DI0	1
+#define IOMUXC_GPR2_MODE_ENABLED_DI1	3
+

From: Ian Ray <[email protected]>

Add support for bootcounter on an EXT filesystem.
Sync configuration whitelist.

Signed-off-by Ian Ray <[email protected]>

Signed-off-by Martyn Welch <[email protected]>

From: Ian Ray <[email protected]>

Add support for bootcounter on an EXT filesystem.
Sync configuration whitelist.

Signed-off-by Ian Ray <[email protected]>

Signed-off-by Martyn Welch <[email protected]>

---
Changes for v2:
- Adding Kconfig for EXT bootcount.

Changes for v3:
- Add over-arching BOOTCOUNT Kconfig entry.

 README                            |  7 +++++
 drivers/Kconfig                   |  2 ++
 drivers/bootcount/Kconfig         | 57 +++++++++++++++++++++++++++++++++++++
 drivers/bootcount/Makefile        |  1 +
 drivers/bootcount/bootcount_ext.c | 59 +++++++++++++++++++++++++++++++++++++++
 5 files changed, 126 insertions(+)
 create mode 100644 drivers/bootcount/Kconfig
 create mode 100644 drivers/bootcount/bootcount_ext.c

README +7 -0

index f288176..6336c5c 100644
@@ -2362,6 +2362,13 @@ The following options need to be configured:
 			CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for
 						    the bootcounter.
 			CONFIG_BOOTCOUNT_ALEN = address len
+		CONFIG_BOOTCOUNT_EXT
+		enable support for the bootcounter in EXT filesystem
+			CONFIG_SYS_BOOTCOUNT_ADDR = RAM address used for read
+                                                    and write.
+			CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE = interface
+			CONFIG_SYS_BOOTCOUNT_EXT_DEVPART = device and part
+			CONFIG_SYS_BOOTCOUNT_EXT_NAME = filename
 
 - Show boot progress:
 		CONFIG_SHOW_BOOT_PROGRESS

drivers/Kconfig +2 -0

index 613e602..c2e813f 100644
@@ -10,6 +10,8 @@ source "drivers/ata/Kconfig"
 
 source "drivers/block/Kconfig"
 
+source "drivers/bootcount/Kconfig"
+
 source "drivers/clk/Kconfig"
 
 source "drivers/cpu/Kconfig"

drivers/bootcount/Kconfig new file +57 -0

new file mode 100644
index 0000000..acffbcf
@@ -0,0 +1,57 @@
+#
+# Boot count configuration
+#
+
+menu "Boot count support"
+
+config BOOTCOUNT
+	bool "Enable Boot count support"
+	help
+	  Enable boot count support, which provides the ability to store the
+	  number of times the board has booted on a number of different
+	  persistent storage mediums.
+
+if BOOTCOUNT
+
+config BOOTCOUNT_EXT
+	bool "Boot counter on EXT filesystem"
+	help
+	  Add support for bootcounter on an EXT filesystem.
+
+if BOOTCOUNT_EXT
+
+config SYS_BOOTCOUNT_EXT_INTERFACE
+	string "Interface on which to find boot counter EXT filesystem"
+	default "mmc"
+	depends on BOOTCOUNT_EXT
+	help
+	  Set the interface to use when locating the filesystem to use for the
+	  boot counter.
+
+config SYS_BOOTCOUNT_EXT_DEVPART
+	string "Partition of the boot counter EXT filesystem"
+	default "0:1"
+	depends on BOOTCOUNT_EXT
+	help
+	  Set the partition to use when locating the filesystem to use for the
+	  boot counter.
+
+config SYS_BOOTCOUNT_EXT_NAME
+	string "Path and filename of the EXT filesystem based boot counter"
+	default "/boot/failures"
+	depends on BOOTCOUNT_EXT
+	help
+	  Set the filename and path of the file used to store the boot counter.
+
+config SYS_BOOTCOUNT_ADDR
+	hex "RAM address used for reading and writing the boot counter"
+	default 0x7000A000
+	depends on BOOTCOUNT_EXT
+	help
+	  Set the address used for reading and writing the boot counter.
+
+endif
+
+endif
+
+endmenu

drivers/bootcount/Makefile +1 -0

index ed9659a..45445d2 100644
@@ -9,3 +9,4 @@ obj-$(CONFIG_BOOTCOUNT_AM33XX)	+= bootcount_davinci.o
 obj-$(CONFIG_BOOTCOUNT_RAM)	+= bootcount_ram.o
 obj-$(CONFIG_BOOTCOUNT_ENV)	+= bootcount_env.o
 obj-$(CONFIG_BOOTCOUNT_I2C)	+= bootcount_i2c.o
+obj-$(CONFIG_BOOTCOUNT_EXT)	+= bootcount_ext.o

drivers/bootcount/bootcount_ext.c new file +49 -0

new file mode 100644
index 0000000..d36bb0e
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2017 General Electric Company. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <bootcount.h>
+#include <fs.h>
+#include <mapmem.h>
+
+#define BC_MAGIC	0xbc
+
+void bootcount_store(ulong a)
+{
+	uint8_t *buf;
+	loff_t len;
+	int ret;
+
+	if (fs_set_blk_dev(CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE, CONFIG_SYS_BOOTCOUNT_EXT_DEVPART, FS_TYPE_EXT)) {
+		puts("Error selecting device\n");
+		return;
+	}
+
+	buf = map_sysmem(CONFIG_SYS_BOOTCOUNT_ADDR, 2);
+	buf[0] = BC_MAGIC;
+	buf[1] = (a & 0xff);
+	unmap_sysmem(buf);
+
+	ret = fs_write(CONFIG_SYS_BOOTCOUNT_EXT_NAME, CONFIG_SYS_BOOTCOUNT_ADDR, 0, 2, &len);
+	if (ret != 0) {
+		puts("Error storing bootcount\n");
+	}
+}
+
+ulong bootcount_load(void)
+{
+	uint8_t *buf;
+	loff_t len_read;
+	int ret;
+
+	if (fs_set_blk_dev(CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE, CONFIG_SYS_BOOTCOUNT_EXT_DEVPART, FS_TYPE_EXT)) {
+		puts("Error selecting device\n");
+		return 0;
+	}
+
+	ret = fs_read(CONFIG_SYS_BOOTCOUNT_EXT_NAME, CONFIG_SYS_BOOTCOUNT_ADDR, 0, 2, &len_read);
+	if (ret != 0 || len_read != 2) {
+		puts("Error loading bootcount\n");
+		return 0;

Hi Martin, Ian,

Quoted 11 lines · Martyn Welch

From: Ian Ray <[email protected]>

Add support for bootcounter on an EXT filesystem.
Sync configuration whitelist.

Signed-off-by Ian Ray <[email protected]>

Signed-off-by Martyn Welch <[email protected]>

---
Changes for v2:
- Adding Kconfig for EXT bootcount.

Quoted 3 lines

Changes for v3:
- Add over-arching BOOTCOUNT Kconfig entry.

Should we better split this into two ? The patch patch does more as commit message suggests. First, it moves bootcounter to Kconfig (first topic). Second, it adds EXT support.

From: Peter Senna Tschudin <[email protected]>

Create board support for GE PPD, based on mx53loco.

Use mx53ppd_defconfig make target to configure for this board.

Signed-off-by Peter Senna Tschudin <[email protected]>

Signed-off-by Ian Ray <[email protected]>

Signed-off-by Nandor Han <[email protected]>

Signed-off-by Martyn Welch <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2:
- Replacing boot count related defines with default config.

Changes for v3:
- Update config due to BOOTCOUNT Kconfig addition.

 arch/arm/include/asm/mach-types.h       |   1 +
 arch/arm/mach-imx/mx5/Kconfig           |   5 +
 board/freescale/mx53ppd/Kconfig         |  17 ++
 board/freescale/mx53ppd/MAINTAINERS     |   7 +
 board/freescale/mx53ppd/Makefile        |  12 +
 board/freescale/mx53ppd/imximage.cfg    |  87 ++++++
 board/freescale/mx53ppd/mx53ppd.c       | 487 ++++++++++++++++++++++++++++++++
 board/freescale/mx53ppd/mx53ppd_video.c | 123 ++++++++
 board/freescale/mx53ppd/ppd_gpio.h      |  96 +++++++
 board/freescale/mx53ppd/vpd_reader.c    | 230 +++++++++++++++
 board/freescale/mx53ppd/vpd_reader.h    |  25 ++
 configs/mx53ppd_defconfig               |  39 +++
 include/configs/mx53ppd.h               | 246 ++++++++++++++++
 13 files changed, 1375 insertions(+)
 create mode 100644 board/freescale/mx53ppd/Kconfig
 create mode 100644 board/freescale/mx53ppd/MAINTAINERS
 create mode 100644 board/freescale/mx53ppd/Makefile
 create mode 100644 board/freescale/mx53ppd/imximage.cfg
 create mode 100644 board/freescale/mx53ppd/mx53ppd.c
 create mode 100644 board/freescale/mx53ppd/mx53ppd_video.c
 create mode 100644 board/freescale/mx53ppd/ppd_gpio.h
 create mode 100644 board/freescale/mx53ppd/vpd_reader.c
 create mode 100644 board/freescale/mx53ppd/vpd_reader.h
 create mode 100644 configs/mx53ppd_defconfig
 create mode 100644 include/configs/mx53ppd.h

arch/arm/include/asm/mach-types.h +0 -0

index 9f82efe..2a257cc 100644

arch/arm/include/asm/mach-types.h +0 -0

 #endif

arch/arm/mach-imx/mx5/Kconfig +5 -0

index ef37c35..330101d 100644
@@ -45,6 +45,10 @@ config TARGET_MX53LOCO
 	select BOARD_LATE_INIT
 	select MX53
 
+config TARGET_MX53PPD
+	bool "Support mx53ppd"
+	select MX53
+
 config TARGET_MX53SMD
 	bool "Support mx53smd"
 	select MX53

@@ -69,6 +73,7 @@ source "board/freescale/mx51evk/Kconfig"
 source "board/freescale/mx53ard/Kconfig"
 source "board/freescale/mx53evk/Kconfig"
 source "board/freescale/mx53loco/Kconfig"
+source "board/freescale/mx53ppd/Kconfig"
 source "board/freescale/mx53smd/Kconfig"
 source "board/inversepath/usbarmory/Kconfig"
 source "board/technologic/ts4800/Kconfig"

board/freescale/mx53ppd/Kconfig new file +17 -0

new file mode 100644
index 0000000..c66d6a7
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier:	GPL-2.0+
+
+if TARGET_MX53PPD
+
+config SYS_BOARD
+	default "mx53ppd"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "mx5"
+
+config SYS_CONFIG_NAME
+	default "mx53ppd"
+
+endif

board/freescale/mx53ppd/MAINTAINERS new file +7 -0

new file mode 100644
index 0000000..9b64b5d
@@ -0,0 +1,7 @@
+MX53PPD BOARD
+M:	Antti Mäentausta <[email protected]>
+M:	Martyn Welch <[email protected]>
+S:	Maintained
+F:	board/freescale/mx53ppd/
+F:	include/configs/mx53ppd.h
+F:	configs/mx53ppd_defconfig

board/freescale/mx53ppd/Makefile new file +12 -0

new file mode 100644
index 0000000..df6c61f
@@ -0,0 +1,12 @@
+# Copyright 2017 General Electric Company
+#
+# Based on board/freescale/mx53loco/Makefile:
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+# Jason Liu <[email protected]>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y			+= mx53ppd.o vpd_reader.o
+obj-$(CONFIG_VIDEO)	+= mx53ppd_video.o

board/freescale/mx53ppd/imximage.cfg new file +87 -0

new file mode 100644
index 0000000..83ff4b8
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2017 General Electric Company
+ *
+ * Based on board/freescale/mx53loco/imximage.cfg:
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x53fa8004 0x00194005
+DATA 4 0x53fa8554 0x00300000
+DATA 4 0x53fa8558 0x00300040
+DATA 4 0x53fa8560 0x00300000
+DATA 4 0x53fa8564 0x00300040
+DATA 4 0x53fa8568 0x00300040
+DATA 4 0x53fa8570 0x00300000
+DATA 4 0x53fa8574 0x00300000
+DATA 4 0x53fa8578 0x00300000
+DATA 4 0x53fa857c 0x00300040
+DATA 4 0x53fa8580 0x00300040
+DATA 4 0x53fa8584 0x00300000
+DATA 4 0x53fa8588 0x00300000
+DATA 4 0x53fa8590 0x00300040
+DATA 4 0x53fa8594 0x00300000
+DATA 4 0x53fa86f0 0x00300000
+DATA 4 0x53fa86f4 0x00000000
+DATA 4 0x53fa86fc 0x00000000
+DATA 4 0x53fa8714 0x00000000
+DATA 4 0x53fa8718 0x00300000
+DATA 4 0x53fa871c 0x00300000
+DATA 4 0x53fa8720 0x00300000
+DATA 4 0x53fa8728 0x00300000
+DATA 4 0x53fa872c 0x00300000
+DATA 4 0x63fd9088 0x35343535
+DATA 4 0x63fd9090 0x4d444c44
+DATA 4 0x63fd907c 0x01370138
+DATA 4 0x63fd9080 0x013b013c
+DATA 4 0x63fd9018 0x00111740
+DATA 4 0x63fd9000 0x85190000
+DATA 4 0x63fd900c 0x8b8f52e3
+DATA 4 0x63fd9010 0xb68e8a63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x008f0e21
+DATA 4 0x63fd9008 0x09333030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00468031
+DATA 4 0x63fd901c 0x052080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x05208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00005800
+DATA 4 0x63fd9040 0x05380003
+DATA 4 0x63fd9058 0x00011110
+DATA 4 0x63fd901c 0x00000000

board/freescale/mx53ppd/mx53ppd.c new file +400 -0

new file mode 100644
index 0000000..8c26f27
@@ -0,0 +1,487 @@
+/*
+ * Copyright 2017 General Electric Company
+ *
+ * Based on board/freescale/mx53loco/mx53loco.c:
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/arch/clock.h>
+#include <linux/errno.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/mx5_video.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/gpio.h>
+#include <power/pmic.h>
+#include <dialog_pmic.h>
+#include <fsl_pmic.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <watchdog.h>
+#include "ppd_gpio.h"
+#include <stdlib.h>
+#include "vpd_reader.h"
+#include <rtc.h>
+
+#define MX53PPD_LCD_POWER		IMX_GPIO_NR(3, 24)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Index of I2C1, SEGMENT 1 (see CONFIG_SYS_I2C_BUSES). */
+#define VPD_EEPROM_BUS 2
+
+/* Address of 24C08 EEPROM. */
+#define VPD_EEPROM_ADDR		0x50
+#define VPD_EEPROM_ADDR_LEN	1
+
+static uint32_t mx53_dram_size[2];
+
+phys_size_t get_effective_memsize(void)
+{
+	/*
+	 * WARNING: We must override get_effective_memsize() function here
+	 * to report only the size of the first DRAM bank. This is to make
+	 * U-Boot relocator place U-Boot into valid memory, that is, at the
+	 * end of the first DRAM bank. If we did not override this function
+	 * like so, U-Boot would be placed at the address of the first DRAM
+	 * bank + total DRAM size - sizeof(uboot), which in the setup where
+	 * each DRAM bank contains 512MiB of DRAM would result in placing
+	 * U-Boot into invalid memory area close to the end of the first
+	 * DRAM bank.
+	 */
+	return mx53_dram_size[0];
+}
+
+int dram_init(void)
+{
+	mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+	mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
+
+	gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = mx53_dram_size[0];
+
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = mx53_dram_size[1];
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	struct fuse_bank *bank = &iim->bank[0];
+	struct fuse_bank0_regs *fuse =
+		(struct fuse_bank0_regs *)bank->fuse_regs;
+
+	int rev = readl(&fuse->gp[6]);
+
+	rev = 0;
+
+	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+#ifdef CONFIG_USB_EHCI_MX5
+int board_ehci_hcd_init(int port)
+{
+	/* request VBUS power enable pin, GPIO7_8 */
+	imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
+	gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
+	return 0;
+}
+#endif
+
+static void setup_iomux_fec(void)
+{
+	static const iomux_v3_cfg_t fec_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+	{MMC_SDHC3_BASE_ADDR},
+	{MMC_SDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+
+#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(bd_t *bis)
+{
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
+				SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
+		MX53_PAD_EIM_DA11__GPIO3_11,
+	};
+
+	static const iomux_v3_cfg_t sd2_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+		MX53_PAD_EIM_DA13__GPIO3_13,
+	};
+
+	u32 index;
+	int ret;
+
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
+		switch (index) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(sd1_pads,
+							 ARRAY_SIZE(sd1_pads));
+			break;
+		case 1:
+			imx_iomux_v3_setup_multiple_pads(sd2_pads,
+							 ARRAY_SIZE(sd2_pads));
+			break;
+		default:
+			printf("Warning: you configured more ESDHC controller"
+				"(%d) as supported by the board(2)\n",
+				CONFIG_SYS_FSL_ESDHC_NUM);
+			return -EINVAL;
+		}
+		ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+#endif
+
+#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+static void setup_iomux_i2c(void)
+{
+	static const iomux_v3_cfg_t i2c1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
+}
+
+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX53_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
+		.gpio_mode = MX53_PAD_EIM_D28__GPIO3_28 | I2C_PAD,
+		.gp = IMX_GPIO_NR(3, 28)
+	},
+	.sda = {
+		.i2c_mode = MX53_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
+		.gpio_mode = MX53_PAD_EIM_D21__GPIO3_21 | I2C_PAD,
+		.gp = IMX_GPIO_NR(3, 21)
+	}
+};
+
+static void clock_1GHz(void)
+{
+	int ret;
+	u32 ref_clk = MXC_HCLK;
+	/*
+	 * After increasing voltage to 1.25V, we can switch
+	 * CPU clock to 1GHz and DDR to 400MHz safely
+	 */
+	ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
+	if (ret)
+		printf("CPU:   Switch CPU clock to 1GHZ failed\n");
+
+	ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+	ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+	if (ret)
+		printf("CPU:   Switch DDR clock to 400MHz failed\n");
+}
+
+void ppd_gpio_init(void)
+{
+	int i;
+	imx_iomux_v3_setup_multiple_pads(ppd_pads, ARRAY_SIZE(ppd_pads));
+	for (i = 0; i < ARRAY_SIZE(ppd_gpios); ++i) {
+		gpio_direction_output(ppd_gpios[i].gpio, ppd_gpios[i].value);
+	}
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_fec();
+	setup_iomux_lcd();
+	ppd_gpio_init();
+
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+#define VPD_TYPE_INVALID 0x00
+#define VPD_BLOCK_NETWORK 0x20
+#define VPD_BLOCK_HWID 0x44
+#define VPD_PRODUCT_PPD 4
+#define VPD_HAS_MAC1 0x1
+#define VPD_MAC_ADDRESS_LENGTH 6
+
+struct vpd_cache {
+	uint8_t product_id;
+	uint8_t has;
+	unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
+};
+
+/*
+ * Extracts MAC and product information from the VPD.
+ */
+static int vpd_callback(
+	void *userdata,
+	uint8_t id,
+	uint8_t version,
+	uint8_t type,
+	size_t size,
+	uint8_t const *data)
+{
+	struct vpd_cache *vpd = (struct vpd_cache *)userdata;
+
+	if (   id == VPD_BLOCK_HWID
+	    && version == 1
+	    && type != VPD_TYPE_INVALID
+	    && size >= 1) {
+		vpd->product_id = data[0];
+
+	} else if (   id == VPD_BLOCK_NETWORK
+		   && version == 1
+		   && type != VPD_TYPE_INVALID) {
+		if (size >= 6) {
+			vpd->has |= VPD_HAS_MAC1;
+			memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
+		}
+	}
+
+	return 0;
+}
+
+static void process_vpd(struct vpd_cache *vpd)
+{
+	int fec_index = -1;
+
+	switch (vpd->product_id)
+	{
+	case VPD_PRODUCT_PPD:
+		fec_index = 0;
+		break;
+	}
+
+	if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1)) {
+		eth_env_set_enetaddr("ethaddr", vpd->mac1);
+	}
+}
+
+static int read_vpd(uint eeprom_bus)
+{
+	struct vpd_cache vpd;
+	int res;
+	int size = 1024;
+	uint8_t *data;
+	unsigned int current_i2c_bus = i2c_get_bus_num();
+
+	res = i2c_set_bus_num(eeprom_bus);
+	if (res < 0)
+		return res;
+
+	data = (uint8_t *)malloc(size);
+	if (!data)
+		return -ENOMEM;
+
+	res = i2c_read(VPD_EEPROM_ADDR, 0,
+			VPD_EEPROM_ADDR_LEN, data, size);
+
+	if (res == 0) {
+		memset(&vpd, 0, sizeof(vpd));
+		vpd_reader(size, data, &vpd, vpd_callback);
+		process_vpd(&vpd);
+	}
+
+	free(data);
+
+	i2c_set_bus_num(current_i2c_bus);
+	return res;
+}
+
+void check_time(void)
+{
+	int ret, i;
+	struct rtc_time tm;
+	u8 retry = 3;
+
+	unsigned int current_i2c_bus = i2c_get_bus_num();
+
+	ret = i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM);
+	if (ret < 0)
+		return;
+
+	rtc_init();
+
+	for (i = 0; i < retry; i++) {
+		ret = rtc_get(&tm);
+		if(!ret || ret == -EINVAL) {
+			break;
+		}
+	}
+
+	if (ret < 0) {
+		env_set("rtc_status", "RTC_ERROR");

board/freescale/mx53ppd/mx53ppd.c new file +62 -0

+
+		for (i = 0; i < retry; i++) {
+			ret = rtc_set(&tm);
+			if(!ret) {
+				break;
+			}
+		}
+
+		if (ret < 0)
+			env_set("rtc_status", "RTC_ERROR");
+	}
+
+	i2c_set_bus_num(current_i2c_bus);
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	mxc_set_sata_internal_clock();
+	setup_iomux_i2c();
+
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	const char *cause;
+
+	/* We care about WDOG only, treating everything else as
+	 * a power-on-reset.
+	 */
+	if (get_imx_reset_cause() & 0x0010) {
+		cause = "WDOG";
+	} else {
+		cause = "POR";
+	}
+
+	env_set("bootcause", cause);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	read_vpd(VPD_EEPROM_BUS);
+
+	clock_1GHz();
+	print_cpuinfo();
+	hw_watchdog_init();
+
+	check_time();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: GE PPD\n");
+

board/freescale/mx53ppd/mx53ppd.c new file +5 -0

+U_BOOT_CMD(
+	ppd_lcd_enable,	1,	1,	do_lcd_enable,
+	"enable PPD LCD",
+	"no parameters"
+);

board/freescale/mx53ppd/mx53ppd_video.c new file +123 -0

new file mode 100644
index 0000000..338f00f
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2017 General Electric Company
+ *
+ * Based on board/freescale/mx53loco/mx53loco_video.c:
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Fabio Estevam <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/list.h>
+#include <asm/gpio.h>
+#include <asm/arch/iomux-mx53.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+#include <pwm.h>
+#include "ppd_gpio.h"
+
+#define MX53PPD_LCD_POWER		IMX_GPIO_NR(3, 24)
+
+static struct fb_videomode const nv_spwg = {
+	.name		= "NV-SPWGRGB888",
+	.refresh	= 60,
+	.xres		= 800,
+	.yres		= 480,
+	.pixclock	= 15384,
+	.left_margin	= 16,
+	.right_margin	= 210,
+	.upper_margin	= 10,
+	.lower_margin	= 22,
+	.hsync_len	= 30,
+	.vsync_len	= 13,
+	.sync		= FB_SYNC_EXT,
+	.vmode		= FB_VMODE_NONINTERLACED
+};
+
+
+void setup_iomux_lcd(void)
+{
+	static const iomux_v3_cfg_t lcd_pads[] = {
+		MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
+		MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
+		MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
+		MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
+		MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
+		MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
+		MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
+		MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
+		MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
+		MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
+		MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
+		MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
+		MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
+		MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
+		MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
+		MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
+		MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
+		MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
+		MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
+		MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
+		MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
+		MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
+		MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
+		MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
+		MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
+		MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
+		MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
+		MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+}
+
+void lcd_enable(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* Set LDB_DI0 as clock source for IPU_DI0 */
+	clrsetbits_le32(&mxc_ccm->cscmr2,
+		MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK,
+		MXC_CCM_CSCMR2_DI0_CLK_SEL(MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK));
+
+	/* Turn on IPU LDB DI0 clocks */
+	setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_LDB_DI0(3));
+
+	/* Turn on IPU DI0 clocks */
+	setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_IPU_DI0(3));
+
+	/* Configure LDB */
+	writel(IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+		IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
+		IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
+		&iomux->gpr[2]);
+
+	/* Enable backlights  */
+	pwm_init(1, 0, 0);
+
+	/* duty cycle 5000000ns, period: 5000000ns */
+	pwm_config(1, 5000000, 5000000);
+
+	/* Backlight Power */
+	gpio_direction_output(BACKLIGHT_ENABLE, 1);
+
+	pwm_enable(1);
+}
+
+
+int board_video_skip(void)
+{
+	int ret;
+
+	ret = ipuv3_fb_init(&nv_spwg, 0, IPU_PIX_FMT_RGB24);
+	if (ret)
+		printf("Display cannot be configured: %d\n", ret);
+
+	return ret;
+}

board/freescale/mx53ppd/ppd_gpio.h new file +96 -0

new file mode 100644
index 0000000..a722435
@@ -0,0 +1,96 @@
+/*
+ * (C) Copyright 2015 General Electric Company
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PPD_GPIO_H_
+#define __PPD_GPIO_H_
+
+#include <asm/arch/iomux-mx53.h>
+#include <asm/gpio.h>
+
+#define PPD_UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH |	\
+			   PAD_CTL_PUS_100K_UP)
+
+static const iomux_v3_cfg_t ppd_pads[] = {
+	/* FEC */
+	MX53_PAD_EIM_A22__GPIO2_16,
+	/* UART */
+	NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, PPD_UART_PAD_CTRL),
+	NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, PPD_UART_PAD_CTRL),
+	/* Video */
+	MX53_PAD_CSI0_DATA_EN__GPIO5_20, /* LR_SCAN_CTRL */
+	MX53_PAD_CSI0_VSYNC__GPIO5_21,	 /* UD_SCAN_CTRL */
+	MX53_PAD_CSI0_DAT10__GPIO5_28,	 /* DATA_WIDTH_CTRL */
+	MX53_PAD_CSI0_PIXCLK__GPIO5_18,	 /* HOST_CONTROLLED_RESET_TO_LCD_N */
+	MX53_PAD_EIM_DA2__GPIO3_2,	 /* LVDS1_MUX_CTRL */
+	MX53_PAD_EIM_DA3__GPIO3_3,	 /* LVDS0_MUX_CTRL */
+	MX53_PAD_EIM_A21__GPIO2_17,	 /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */
+	MX53_PAD_CSI0_DAT11__GPIO5_29,	 /* BACKLIGHT_ENABLE */
+	MX53_PAD_DISP0_DAT9__PWM2_PWMO,	 /* IMX535_PWM2_TO_LCD_CONNECTOR */
+	/* I2C */
+	MX53_PAD_EIM_A20__GPIO2_18,	 /* RESET_I2C1_BUS_SEGMENT_MUX_N */
+
+	/* SPI */
+	MX53_PAD_DISP0_DAT23__GPIO5_17,
+	MX53_PAD_KEY_COL2__GPIO4_10,
+	MX53_PAD_KEY_ROW2__GPIO4_11,
+	MX53_PAD_KEY_COL3__GPIO4_12,
+};
+
+struct gpio_cfg {
+	unsigned gpio;
+	int value;
+};
+
+#define RESET_IMX535_ETHERNET_PHY_N IMX_GPIO_NR(2, 16)
+#define UD_SCAN_CTRL IMX_GPIO_NR(5, 21)
+#define LR_SCAN_CTRL IMX_GPIO_NR(5, 20)
+#define LVDS0_MUX_CTRL IMX_GPIO_NR(3, 3)
+#define LVDS1_MUX_CTRL IMX_GPIO_NR(3, 2)
+#define HOST_CONTROLLED_RESET_TO_LCD_N IMX_GPIO_NR(5, 18)
+#define DATA_WIDTH_CTRL IMX_GPIO_NR(5, 28)
+#define RESET_DP0_TRANSMITTER_N IMX_GPIO_NR(2, 28)
+#define RESET_DP1_TRANSMITTER_N IMX_GPIO_NR(2, 29)
+#define POWER_DOWN_LVDS0_DESERIALIZER_N IMX_GPIO_NR(2, 22)
+#define POWER_DOWN_LVDS1_DESERIALIZER_N IMX_GPIO_NR(2, 27)
+#define ENABLE_PWR_TO_LCD_AND_UI_INTERFACE IMX_GPIO_NR(2, 17)
+#define BACKLIGHT_ENABLE IMX_GPIO_NR(5, 29)
+#define RESET_I2C1_BUS_SEGMENT_MUX_N IMX_GPIO_NR(2, 18)
+#define ECSPI1_CS0 IMX_GPIO_NR(5, 17)
+#define ECSPI1_CS1 IMX_GPIO_NR(4, 10)
+#define ECSPI1_CS2 IMX_GPIO_NR(4, 11)
+#define ECSPI1_CS3 IMX_GPIO_NR(4, 12)
+
+static const struct gpio_cfg ppd_gpios[] = {
+	/* FEC */
+	/* Drive Low as GPIO output for 25ms per Eth Phy IX spec */
+	/* Then Drive High as GPIO output to bring Eth Phy IC out of reset */
+	{ RESET_IMX535_ETHERNET_PHY_N, 0 },
+	{ RESET_IMX535_ETHERNET_PHY_N, 1 },
+	/* Video */
+	{ UD_SCAN_CTRL, 0 },
+	{ LR_SCAN_CTRL, 1 },
+#ifdef PROPRIETARY_CHANGES
+	{ LVDS0_MUX_CTRL, 1 },
+#else
+	{ LVDS0_MUX_CTRL, 0 },
+#endif
+	{ LVDS1_MUX_CTRL, 1 },
+	{ HOST_CONTROLLED_RESET_TO_LCD_N, 1 },
+	{ DATA_WIDTH_CTRL, 0 },
+	{ RESET_DP0_TRANSMITTER_N, 1 },
+	{ RESET_DP1_TRANSMITTER_N, 1 },
+	{ POWER_DOWN_LVDS0_DESERIALIZER_N, 1 },
+	{ POWER_DOWN_LVDS1_DESERIALIZER_N, 1 },
+	{ ENABLE_PWR_TO_LCD_AND_UI_INTERFACE, 1 },
+	{ BACKLIGHT_ENABLE, 0 },
+	{ RESET_I2C1_BUS_SEGMENT_MUX_N, 1 },
+	{ ECSPI1_CS0, 1 },
+	{ ECSPI1_CS1, 1 },
+	{ ECSPI1_CS2, 1 },
+	{ ECSPI1_CS3, 1 },
+};
+
+#endif /* __PPD_GPIO_H_ */

board/freescale/mx53ppd/vpd_reader.c new file +39 -0

new file mode 100644
index 0000000..ea6daf7
@@ -0,0 +1,230 @@
+/*
+ * Copyright 2016 General Electric Company
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "vpd_reader.h"
+
+#include <linux/bch.h>
+#include <stdlib.h>
+#include <errno.h>
+
+
+/* BCH configuration */
+
+const struct {
+	int header_ecc_capability_bits;
+	int data_ecc_capability_bits;
+	unsigned int prim_poly;
+	struct {
+		int min;
+		int max;
+	} galois_field_order;
+} bch_configuration = {
+	.header_ecc_capability_bits = 4,
+	.data_ecc_capability_bits = 16,
+	.prim_poly = 0,
+	.galois_field_order = {
+		.min = 5,
+		.max = 15,
+	},
+};
+
+static int calculate_galois_field_order(size_t source_length)
+{
+	int gfo = bch_configuration.galois_field_order.min;
+
+	for (; gfo < bch_configuration.galois_field_order.max &&
+	     ((((1 << gfo) - 1) - ((int)source_length * 8)) < 0);

board/freescale/mx53ppd/vpd_reader.c new file +181 -0

+static int verify_bch(int ecc_bits, unsigned int prim_poly,
+	uint8_t * data, size_t data_length,
+	const uint8_t * ecc, size_t ecc_length)
+{
+	int gfo = calculate_galois_field_order(data_length);
+	if (gfo < 0) {
+		return -1;
+	}
+
+	struct bch_control * bch = init_bch(gfo, ecc_bits, prim_poly);
+	if (!bch) {
+		return -1;
+	}
+
+	if (bch->ecc_bytes != ecc_length) {
+		free_bch(bch);
+		return -1;
+	}
+
+	unsigned * errloc = (unsigned *)calloc(data_length, sizeof(unsigned));
+	int errors = decode_bch(
+			bch, data, data_length, ecc, NULL, NULL, errloc);
+	free_bch(bch);
+	if (errors < 0) {
+		free(errloc);
+		return -1;
+	}
+
+	if (errors > 0) {
+		int n;
+		for (n = 0; n < errors; n++) {
+			if (errloc[n] >= 8 * data_length) {
+				/* n-th error located in ecc (no need for data correction) */
+			} else {
+				/* n-th error located in data */
+				data[errloc[n] / 8] ^= 1 << (errloc[n] % 8);
+			}
+		}
+	}
+
+	free(errloc);
+	return 0;
+}
+
+
+static const int ID = 0;
+static const int LEN = 1;
+static const int VER = 2;
+static const int TYP = 3;
+static const int BLOCK_SIZE = 4;
+
+static const uint8_t HEADER_BLOCK_ID = 0x00;
+static const uint8_t HEADER_BLOCK_LEN = 18;
+static const uint32_t HEADER_BLOCK_MAGIC = 0xca53ca53;
+static const size_t HEADER_BLOCK_VERIFY_LEN = 14;
+static const size_t HEADER_BLOCK_ECC_OFF = 14;
+static const size_t HEADER_BLOCK_ECC_LEN = 4;
+
+static const uint8_t ECC_BLOCK_ID = 0xFF;
+
+int vpd_reader(
+	size_t size,
+	uint8_t * data,
+	void * userdata,
+	int (*fn)(
+	    void * userdata,
+	    uint8_t id,
+	    uint8_t version,
+	    uint8_t type,
+	    size_t size,
+	    uint8_t const * data))
+{
+	if (   size < HEADER_BLOCK_LEN
+	    || data == NULL
+	    || fn == NULL) {
+		return -EINVAL;
+	}
+
+	/*
+	 * +--------------------+--------------------+--//--+--------------------+
+	 * | header block       | data block         | ...  | ecc block          |
+	 * +--------------------+--------------------+--//--+--------------------+
+	 * :                    :                           :
+	 * +------+-------+-----+                           +------+-------------+
+	 * | id   | magic | ecc |                           | ...  | ecc         |
+	 * | len  | off   |     |                           +------+-------------+
+	 * | ver  | size  |     |                           :
+	 * | type |       |     |                           :
+	 * +------+-------+-----+                           :
+	 * :              :     :                           :
+	 * <----- [1] ---->     <----------- [2] ----------->
+	 *
+	 * Repair (if necessary) the contents of header block [1] by using a
+	 * 4 byte ECC located at the end of the header block.  A successful
+	 * return value means that we can trust the header.
+	 */
+	int ret = verify_bch(
+		bch_configuration.header_ecc_capability_bits,
+		bch_configuration.prim_poly,
+		data,
+		HEADER_BLOCK_VERIFY_LEN,
+		&data[HEADER_BLOCK_ECC_OFF],
+		HEADER_BLOCK_ECC_LEN);
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* Validate header block { id, length, version, type }. */
+	if (   data[ID] != HEADER_BLOCK_ID
+	    || data[LEN] != HEADER_BLOCK_LEN
+	    || data[VER] != 0
+	    || data[TYP] != 0
+	    || ntohl(*(uint32_t *)(&data[4])) != HEADER_BLOCK_MAGIC) {
+		return -EINVAL;
+	}
+
+	uint32_t offset = ntohl(*(uint32_t *)(&data[8]));
+	uint16_t size_bits = ntohs(*(uint16_t *)(&data[12]));
+
+	/* Check that ECC header fits. */
+	if (offset + 3 >= size) {
+		return -EINVAL;
+	}
+
+	/* Validate ECC block. */
+	uint8_t * ecc = &data[offset];
+	if (   ecc[ID] != ECC_BLOCK_ID
+	    || ecc[LEN] < BLOCK_SIZE
+	    || ecc[LEN] + offset > size
+	    || ecc[LEN] - BLOCK_SIZE != size_bits / 8
+	    || ecc[VER] != 1
+	    || ecc[TYP] != 1) {
+		return -EINVAL;
+	}
+
+	/*
+	 * Use the header block to locate the ECC block and verify the data
+	 * blocks [2] against the ecc block ECC.
+	 */
+	ret = verify_bch(
+		bch_configuration.data_ecc_capability_bits,
+		bch_configuration.prim_poly,
+		&data[data[LEN]],
+		offset - data[LEN],
+		&data[offset + BLOCK_SIZE],
+		ecc[LEN] - BLOCK_SIZE);
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* Stop after ECC.  Ignore possible zero padding. */
+	size = offset;
+
+	for (;;) {
+		/* Move to next block. */
+		size -= data[LEN];
+		data += data[LEN];
+
+		if (size == 0) {
+			/* Finished iterating through blocks. */
+			return 0;
+		}
+
+		if (   size < BLOCK_SIZE
+		    || data[LEN] < BLOCK_SIZE) {
+			/* Not enough data for a header, or short header. */
+			return -EINVAL;
+		}
+
+		ret = fn(
+			userdata,
+			data[ID],
+			data[VER],
+			data[TYP],
+			data[LEN] - BLOCK_SIZE,
+			&data[BLOCK_SIZE]);
+		if (ret) {
+			return ret;
+		}
+	}
+}

board/freescale/mx53ppd/vpd_reader.h new file +25 -0

new file mode 100644
index 0000000..efa172a
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2016 General Electric Company
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "common.h"
+
+/*
+ * Read VPD from given data, verify content, and call callback
+ * for each vital product data block.
+ *
+ * Returns Non-zero on error.  Negative numbers encode errno.
+ */
 
 
+int vpd_reader(
+	size_t size,
+	uint8_t * data,
+	void * userdata,
+	int (*fn)(
+	    void * userdata,
+	    uint8_t id,
+	    uint8_t version,
+	    uint8_t type,
+	    size_t size,
+	    uint8_t const * data));

configs/mx53ppd_defconfig new file +39 -0

new file mode 100644
index 0000000..1cc3578
@@ -0,0 +1,39 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
+CONFIG_TARGET_MX53PPD=y
+CONFIG_FIT=y
+CONFIG_BOOTCOUNT=y
+CONFIG_BOOTCOUNT_EXT=y
+CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE="mmc"
+CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="0:5"
+CONFIG_SYS_BOOTCOUNT_EXT_NAME="/boot/failures"
+CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
+CONFIG_NETDEVICES=y
+CONFIG_VIDEO=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ppd/imximage.cfg"
+CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_I2C=y
+CONFIG_RTC_S35392A=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
+
+CONFIG_MMC=y

include/configs/mx53ppd.h new file +236 -0

new file mode 100644
index 0000000..59cc527
@@ -0,0 +1,246 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <[email protected]>
+ *
+ * Configuration settings for Freescale MX53 low cost board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX53_PPD
+
+#include <asm/arch/imx-regs.h>
+
+#define CONSOLE_DEV	"ttymxc0"
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SYS_FSL_CLK
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_IMX_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_GPIO
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	2
+
+#define CONFIG_SUPPORT_RAW_INITRD	/* bootz raw initrd support */
+
+/* Eth Configs */
+#define CONFIG_MII
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR	0x1F
+
+/* USB Configs */
+#define CONFIG_USB_EHCI_MX5
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+#define CONFIG_SYS_RTC_BUS_NUM		2
+#define CONFIG_SYS_I2C_RTC_ADDR	0x30
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+
+/* PMIC Controller */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_DIALOG_POWER
+#define CONFIG_POWER_FSL
+#define CONFIG_POWER_FSL_MC13892
+#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR	0x48
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x8
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+#define CONFIG_SUPPORT_RAW_INITRD
+
+
+#define CONFIG_ETHPRIME		"FEC0"
+
+#define CONFIG_LOADADDR		0x72000000	/* loadaddr env var */
+#define CONFIG_SYS_TEXT_BASE    0x77800000
+
+#define PPD_CONFIG_NFS \
+	"nfsserver=192.168.252.95\0" \
+	"gatewayip=192.168.252.95\0" \
+	"netmask=255.255.255.0\0" \
+	"ipaddr=192.168.252.99\0" \
+	"kernsize=0x2000\0" \
+	"use_dhcp=0\0" \
+	"nfsroot=/opt/springdale/rd\0" \
+	"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs ${kern_ipconf} nfsroot=${nfsserver}:${nfsroot},v3,tcp rw\0" \
+	"choose_ip=if test $use_dhcp = 1; then set kern_ipconf ip=dhcp; set getcmd dhcp; else set kern_ipconf ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off; set getcmd tftp; fi\0" \
+	"nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} ${nfsserver}:${image}; bootm ${loadaddr}\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	PPD_CONFIG_NFS \
+	"bootlimit=10\0" \
+	"image=/boot/fitImage\0" \
+	"fdt_high=0xffffffff\0" \
+	"dev=mmc\0" \
+	"devnum=0\0" \
+	"rootdev=mmcblk0p\0" \
+	"quiet=quiet loglevel=0\0" \
+	"console=" CONSOLE_DEV "\0" \
+	"lvds=ldb\0" \
+	"setargs=setenv bootargs ${lvds} jtag=on mem=2G vt.global_cursor_default=0 " \
+		"bootcause=${bootcause} " \
+		"${quiet} console=${console} ${rtc_status}" \
+		"\0" \
+	"bootargs_emmc=setenv bootargs root=/dev/${rootdev}${partnum} " \
+		"ro rootwait ${bootargs}\0" \
+	"doquiet=" \
+		"if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; then setenv quiet; fi\0" \
+	"hasfirstboot=" \
+		"ext2load ${dev} ${devnum}:${partnum} 0x7000A000 /boot/bootcause/firstboot\0" \
+	"swappartitions=" \
+		"setexpr partnum 3 - ${partnum}\0" \
+	"failbootcmd=" \
+		"ppd_lcd_enable; " \
+		"msg=\"Monitor failed to start.  Try again, or contact GE Service for support.\"; " \
+		"echo $msg; " \
+		"setenv stdout vga; " \
+		"echo \"\n\n\n\n    \" $msg; " \
+		"setenv stdout serial; " \
+		"mw.b 0x7000A000 0xbc; " \
+		"mw.b 0x7000A001 0x00; " \
+		"ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
+	"altbootcmd=" \
+		"run doquiet; " \
+		"setenv partnum 1; run hasfirstboot || setenv partnum 2; run hasfirstboot || setenv partnum 0; " \
+		"if test ${partnum} != 0; then " \
+			"setenv bootcause REVERT; " \
+			"run swappartitions loadimage doboot; " \
+		"fi; " \
+		"run failbootcmd\0" \
+	"loadimage=" \
+		"ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
+	"doboot=" \
+		"echo Booting from ${dev}:${devnum}:${partnum} ...; " \
+		"run setargs; " \
+		"run bootargs_emmc; " \
+		"bootm ${loadaddr}\0" \
+	"tryboot=" \
+		"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
+		"run loadimage || run swappartitions && run loadimage || setenv partnum 0 && echo MISSING IMAGE;" \
+		"run doboot; " \
+		"run failbootcmd\0" \
+	"video-mode=" \
+		"lcd:800x480-24 at 60,monitor=lcd\0" \
+
+
+#define CONFIG_MMCBOOTCOMMAND \
+	"if mmc dev ${devnum}; then " \
+		"run doquiet; " \
+		"run tryboot; " \
+	"fi; " \
+
+#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+
+#define CONFIG_SYS_MAXARGS	48	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START       0x70000000
+#define CONFIG_SYS_MEMTEST_END         0x70010000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS	2
+#define PHYS_SDRAM_1			CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE		(gd->bd->bi_dram[0].size)
+#define PHYS_SDRAM_2			CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE		(gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_SIZE			(gd->ram_size)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_CMD_FUSE
+#define CONFIG_FSL_IIM
+
+#define CONFIG_SYS_I2C_SPEED	100000
+
+/* I2C1 */
+#define CONFIG_SYS_NUM_I2C_BUSES	9
+#define CONFIG_SYS_I2C_MAX_HOPS		1
+#define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
+				}
+
+#define CONFIG_BCH
+
+#define CONFIG_BOOTCOUNT_LIMIT
+

Hi Martyn, Peter,

Quoted 44 lines · Martyn Welch

From: Peter Senna Tschudin <[email protected]>

Create board support for GE PPD, based on mx53loco.

Use mx53ppd_defconfig make target to configure for this board.

Signed-off-by Peter Senna Tschudin <[email protected]>

Signed-off-by Ian Ray <[email protected]>

Signed-off-by Nandor Han <[email protected]>

Signed-off-by Martyn Welch <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2:
- Replacing boot count related defines with default config.

Changes for v3:
- Update config due to BOOTCOUNT Kconfig addition.

 arch/arm/include/asm/mach-types.h       |   1 +
 arch/arm/mach-imx/mx5/Kconfig           |   5 +
 board/freescale/mx53ppd/Kconfig         |  17 ++
 board/freescale/mx53ppd/MAINTAINERS     |   7 +
 board/freescale/mx53ppd/Makefile        |  12 +
 board/freescale/mx53ppd/imximage.cfg    |  87 ++++++
 board/freescale/mx53ppd/mx53ppd.c       | 487 ++++++++++++++++++++++++++++++++
 board/freescale/mx53ppd/mx53ppd_video.c | 123 ++++++++
 board/freescale/mx53ppd/ppd_gpio.h      |  96 +++++++
 board/freescale/mx53ppd/vpd_reader.c    | 230 +++++++++++++++
 board/freescale/mx53ppd/vpd_reader.h    |  25 ++
 configs/mx53ppd_defconfig               |  39 +++
 include/configs/mx53ppd.h               | 246 ++++++++++++++++
 13 files changed, 1375 insertions(+)
 create mode 100644 board/freescale/mx53ppd/Kconfig
 create mode 100644 board/freescale/mx53ppd/MAINTAINERS
 create mode 100644 board/freescale/mx53ppd/Makefile
 create mode 100644 board/freescale/mx53ppd/imximage.cfg
 create mode 100644 board/freescale/mx53ppd/mx53ppd.c
 create mode 100644 board/freescale/mx53ppd/mx53ppd_video.c
 create mode 100644 board/freescale/mx53ppd/ppd_gpio.h
 create mode 100644 board/freescale/mx53ppd/vpd_reader.c
 create mode 100644 board/freescale/mx53ppd/vpd_reader.h
 create mode 100644 configs/mx53ppd_defconfig
 create mode 100644 include/configs/mx53ppd.h

arch/arm/include/asm/mach-types.h line 5060

Quoted 9 lines

arch/arm/include/asm/mach-types.h +1 -0

index 9f82efe..2a257cc 100644
@@ -5057,4 +5057,5 @@
 #define MACH_TYPE_NASM25               5112
 #define MACH_TYPE_TOMATO               5113
 #define MACH_TYPE_OMAP3_MRC3D          5114
+#define MACH_TYPE_MX53_PPD             5134

Ouch..still an ancient Kernel ? 2.6.35, maybe ?

Even in that case, we agreed to not touch anymore mach-types.h. The value should go into the board configuration file,

	 #define CONFIG_MACH_TYPE   5134

Quoted 29 lines

arch/arm/include/asm/mach-types.h +29 -0

+void check_time(void)
+{
+	int ret, i;
+	struct rtc_time tm;
+	u8 retry = 3;
+
+	unsigned int current_i2c_bus = i2c_get_bus_num();
+
+	ret = i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM);
+	if (ret < 0)
+		return;
+
+	rtc_init();
+
+	for (i = 0; i < retry; i++) {
+		ret = rtc_get(&tm);
+		if(!ret || ret == -EINVAL) {
+			break;
+		}
+	}
+
+	if (ret < 0) {
+		env_set("rtc_status", "RTC_ERROR");
+	}
+
+	if (tm.tm_year > 2037) {
+		tm.tm_sec  = 0;
+		tm.tm_min  = 0;
+		tm.tm_hour = 0;

arch/arm/include/asm/mach-types.h

Quoted 4 lines

arch/arm/include/asm/mach-types.h +4 -0

+		tm.tm_mday = 1;
+		tm.tm_wday = 2;
+		tm.tm_mon  = 1;
+		tm.tm_year = 2036;

Agree this will be a problem in 2037, but I guess setting the time back is not the right solution. I am missing the reason, apart to convince kernel that time does not go by.

arch/arm/include/asm/mach-types.h

Quoted 8 lines

arch/arm/include/asm/mach-types.h +8 -0

+
+static int do_lcd_enable(cmd_tbl_t *cmdtp, int flag, int argc,
+			char * const argv[])
+{
+	lcd_enable();
+	return 0;
+}
+

If this is related to LCD, why the function is not in mx53ppd_video.c ?

Quoted 5 lines

arch/arm/include/asm/mach-types.h +5 -0

+U_BOOT_CMD(
+	ppd_lcd_enable,	1,	1,	do_lcd_enable,
+	"enable PPD LCD",
+	"no parameters"
+);

Quoted 45 lines

board/freescale/mx53ppd/vpd_reader.c new file +39 -0

new file mode 100644
index 0000000..ea6daf7
@@ -0,0 +1,230 @@
+/*
+ * Copyright 2016 General Electric Company
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "vpd_reader.h"
+
+#include <linux/bch.h>
+#include <stdlib.h>
+#include <errno.h>
+
+
+/* BCH configuration */
+
+const struct {
+	int header_ecc_capability_bits;
+	int data_ecc_capability_bits;
+	unsigned int prim_poly;
+	struct {
+		int min;
+		int max;
+	} galois_field_order;
+} bch_configuration = {
+	.header_ecc_capability_bits = 4,
+	.data_ecc_capability_bits = 16,
+	.prim_poly = 0,
+	.galois_field_order = {
+		.min = 5,
+		.max = 15,
+	},
+};
+
+static int calculate_galois_field_order(size_t source_length)
+{
+	int gfo = bch_configuration.galois_field_order.min;
+
+	for (; gfo < bch_configuration.galois_field_order.max &&
+	     ((((1 << gfo) - 1) - ((int)source_length * 8)) < 0);

board/freescale/mx53ppd/vpd_reader.c line 49

Quoted 10 lines

board/freescale/mx53ppd/vpd_reader.c new file +10 -0

+	     gfo++) {
+	}
+
+	if (gfo == bch_configuration.galois_field_order.max) {
+		return -1;
+	}
+
+	return gfo + 1;
+}
+

mmmhhh....I do not like this. You have already a handling for VPD header (your custom header) for the bx50v3 board. You duplicate here a lot of code, and I am missing what is different and what is identical.

I think you should move code in a common directory (as freescale boards do), like in ge/common, and the same code is reused by all your board instead of duplicating it each time.