dt-bindings: clock: tegra: Add sor1_out clock

PATCH Applied Thierry Reding 2 participants 10 messages Sep 1, 2017 – Nov 3, 2017

Subsystems (4)

Device tree bindings Common clk Tegra architecture support Tegra clock driver

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Thierry Reding

author

2017-09-01 14:53 UTC #0 lore raw

PATCH 1/4 dt-bindings: clock: tegra: Add sor1_out clock

From: Thierry Reding <[email protected]>

The sor1_src clock implemented on Tegra210 is modelled the wrong way around, which causes some issues with HDMI and DP support. This clock implementation is provided by BPMP on Tegra186, which models this in a more correct way. Since this introduces incompatibilities between the two SoC generations which we want to avoid, the Tegra210 will be fixed in subsequent patches.

This change adds sor1_out as an alias for sor1_src.

Signed-off-by Thierry Reding <[email protected]>

---
 include/dt-bindings/clock/tegra210-car.h | 1 +
 1 file changed, 1 insertion(+)

include/dt-bindings/clock/tegra210-car.h +1 -0

index 46689cd3750b..43c4a8407333 100644
@@ -309,6 +309,7 @@
 #define TEGRA210_CLK_BLINK 280
 /* 281 */
 #define TEGRA210_CLK_SOR1_SRC 282
+#define TEGRA210_CLK_SOR1_OUT 282
 /* 283 */
 #define TEGRA210_CLK_XUSB_HOST_SRC 284
 #define TEGRA210_CLK_XUSB_FALCON_SRC 285

Signature · 1 line

2.13.3

Thierry Reding

author

2017-09-01 14:53 UTC #1 lore raw

PATCH 2/4 clk: tegra: Add peripheral clock registration helper

From: Thierry Reding <[email protected]>

There is a common pattern that registers individual peripheral clocks from an initialization table. Add a common implementation to remove the duplication from various call sites.

Signed-off-by Thierry Reding <[email protected]>

---
 drivers/clk/tegra/clk-periph.c | 8 ++++++++
 drivers/clk/tegra/clk.h        | 3 +++
 2 files changed, 11 insertions(+)

drivers/clk/tegra/clk-periph.c +8 -0

index cf80831de79d..9475c00b7cf9 100644
@@ -203,3 +203,11 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
 	return _tegra_clk_register_periph(name, parent_names, num_parents,
 			periph, clk_base, offset, CLK_SET_RATE_PARENT);
 }
+
+struct clk *tegra_clk_register_periph_data(void __iomem *clk_base,
+					   struct tegra_periph_init_data *init)
+{
+	return _tegra_clk_register_periph(init->name, init->p.parent_names,
+					  init->num_parents, &init->periph,
+					  clk_base, init->offset, init->flags);
+}

drivers/clk/tegra/clk.h +3 -0

index 872f1189ad7f..3b2763df51c2 100644
@@ -662,6 +662,9 @@ struct tegra_periph_init_data {
 			_clk_num, _gate_flags, _clk_id,\
 			NULL, 0, NULL)
 
+struct clk *tegra_clk_register_periph_data(void __iomem *clk_base,
+					   struct tegra_periph_init_data *init);
+
 /**
  * struct clk_super_mux - super clock
  *

Signature · 1 line

2.13.3

Stephen Boyd

Applied

2017-11-02 08:16 UTC #2 lore raw

Re: [PATCH 2/4] clk: tegra: Add peripheral clock registration helper

Quoted 8 lines · Thierry Reding

From: Thierry Reding <[email protected]>
There is a common pattern that registers individual peripheral clocks from an initialization table. Add a common implementation to remove the duplication from various call sites.
Signed-off-by Thierry Reding <[email protected]>
---

Applied to clk-next

Signature · 2 lines

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Thierry Reding

author

2017-09-01 14:53 UTC #3 lore raw

PATCH 3/4 clk: tegra: Use tegra_clk_register_periph_data()

In reply to Thierry Reding

From: Thierry Reding <[email protected]>

Instead of open-coding the same pattern repeatedly, reuse the newly introduced tegra_clk_register_periph_data() helper that will unpack the initialization structure.

Signed-off-by Thierry Reding <[email protected]>

---
 drivers/clk/tegra/clk-tegra-periph.c | 5 +----
 drivers/clk/tegra/clk-tegra114.c     | 4 +---
 drivers/clk/tegra/clk-tegra20.c      | 4 +---
 drivers/clk/tegra/clk-tegra30.c      | 4 +---
 4 files changed, 4 insertions(+), 13 deletions(-)

drivers/clk/tegra/clk-tegra-periph.c +1 -4

index 848255cc0209..090a5d792341 100644
@@ -927,10 +927,7 @@ static void __init periph_clk_init(void __iomem *clk_base,
 			continue;
 
 		data->periph.gate.regs = bank;
-		clk = tegra_clk_register_periph(data->name,
-			data->p.parent_names, data->num_parents,
-			&data->periph, clk_base, data->offset,
-			data->flags);
+		clk = tegra_clk_register_periph_data(clk_base, data);
 		*dt_clk = clk;
 	}
 }

drivers/clk/tegra/clk-tegra114.c +1 -3

index fd1a99c05c2d..63087d17c3e2 100644
@@ -1092,9 +1092,7 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
 
 	for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
 		data = &tegra_periph_clk_list[i];
-		clk = tegra_clk_register_periph(data->name,
-			data->p.parent_names, data->num_parents,
-			&data->periph, clk_base, data->offset, data->flags);
+		clk = tegra_clk_register_periph_data(clk_base, data);
 		clks[data->clk_id] = clk;
 	}

drivers/clk/tegra/clk-tegra20.c +1 -3

index 837e5cbd60e9..2b839cb24436 100644
@@ -850,9 +850,7 @@ static void __init tegra20_periph_clk_init(void)
 
 	for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
 		data = &tegra_periph_clk_list[i];
-		clk = tegra_clk_register_periph(data->name, data->p.parent_names,
-				data->num_parents, &data->periph,
-				clk_base, data->offset, data->flags);
+		clk = tegra_clk_register_periph_data(clk_base, data);
 		clks[data->clk_id] = clk;
 	}

drivers/clk/tegra/clk-tegra30.c +1 -3

index a2d163f759b4..98e8a55e4e1c 100644
@@ -1079,9 +1079,7 @@ static void __init tegra30_periph_clk_init(void)
 
 	for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
 		data = &tegra_periph_clk_list[i];
-		clk = tegra_clk_register_periph(data->name, data->p.parent_names,
-				data->num_parents, &data->periph,
-				clk_base, data->offset, data->flags);
+		clk = tegra_clk_register_periph_data(clk_base, data);
 		clks[data->clk_id] = clk;
 	}

Signature · 1 line

2.13.3

Stephen Boyd

Applied

2017-11-02 08:16 UTC #4 lore raw

Re: [PATCH 3/4] clk: tegra: Use tegra_clk_register_periph_data()

Quoted 8 lines · Thierry Reding

From: Thierry Reding <[email protected]>
Instead of open-coding the same pattern repeatedly, reuse the newly introduced tegra_clk_register_periph_data() helper that will unpack the initialization structure.
Signed-off-by Thierry Reding <[email protected]>
---

Applied to clk-next

Signature · 2 lines

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Thierry Reding

author

2017-09-01 14:53 UTC #5 lore raw

PATCH 4/4 clk: tegra: Fix sor1_out clock implementation

In reply to Thierry Reding

From: Thierry Reding <[email protected]>

This clock was previously called sor1_src and was modelled as an input to the sor1 module clock. However, it's really an output clock that can be fed either from the safe, the sor1_pad_clkout or the sor1 module clocks. sor1 itself can take input from either of the display PLLs.

The same implementation for the sor1_out clock is used on Tegra186, so this nicely lines up both SoC generations to deal with this clock in a uniform way.

Signed-off-by Thierry Reding <[email protected]>

---
 drivers/clk/tegra/clk-tegra-periph.c | 16 ------------
 drivers/clk/tegra/clk-tegra210.c     | 47 ++++++++++++++++++++++++++++++++++++
 2 files changed, 47 insertions(+), 16 deletions(-)

drivers/clk/tegra/clk-tegra-periph.c +0 ~~-16~~

index 090a5d792341..c7694205573f 100644
@@ -129,7 +129,6 @@
 #define CLK_SOURCE_NVDEC 0x698
 #define CLK_SOURCE_NVJPG 0x69c
 #define CLK_SOURCE_APE 0x6c0
-#define CLK_SOURCE_SOR1 0x410
 #define CLK_SOURCE_SDMMC_LEGACY 0x694
 #define CLK_SOURCE_QSPI 0x6c4
 #define CLK_SOURCE_VI_I2C 0x6c8

@@ -278,7 +277,6 @@ static DEFINE_SPINLOCK(PLLP_OUTA_lock);
 static DEFINE_SPINLOCK(PLLP_OUTB_lock);
 static DEFINE_SPINLOCK(PLLP_OUTC_lock);
 static DEFINE_SPINLOCK(sor0_lock);
-static DEFINE_SPINLOCK(sor1_lock);
 
 #define MUX_I2S_SPDIF(_id)						\
 static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \

@@ -604,18 +602,6 @@ static u32 mux_pllp_plld_plld2_clkm_idx[] = {
 	[0] = 0, [1] = 2, [2] = 5, [3] = 6
 };
 
-static const char *mux_sor_safe_sor1_brick_sor1_src[] = {
-	/*
-	 * Bit 0 of the mux selects sor1_brick, irrespective of bit 1, so the
-	 * sor1_brick parent appears twice in the list below. This is merely
-	 * to support clk_get_parent() if firmware happened to set these bits
-	 * to 0b11. While not an invalid setting, code should always set the
-	 * bits to 0b01 to select sor1_brick.
-	 */
-	"sor_safe", "sor1_brick", "sor1_src", "sor1_brick"
-};
-#define mux_sor_safe_sor1_brick_sor1_src_idx NULL
-
 static const char *mux_pllp_pllre_clkm[] = {
 	"pll_p", "pll_re_out1", "clk_m"
 };

@@ -804,8 +790,6 @@ static struct tegra_periph_init_data periph_clks[] = {
 	MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec),
 	MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg),
 	MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),
-	MUX8_NOGATE_LOCK("sor1_src", mux_pllp_plld_plld2_clkm, CLK_SOURCE_SOR1, tegra_clk_sor1_src, &sor1_lock),
-	NODIV("sor1", mux_sor_safe_sor1_brick_sor1_src, CLK_SOURCE_SOR1, 14, MASK(2), 183, 0, tegra_clk_sor1, &sor1_lock),
 	MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy),
 	MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi),
 	I2C("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c),

drivers/clk/tegra/clk-tegra210.c +47 -0

81 lines not on this page · raw message

Signature · 1 line

2.13.3

Stephen Boyd

Applied

2017-11-02 08:16 UTC #6 lore raw

Re: [PATCH 4/4] clk: tegra: Fix sor1_out clock implementation

Quoted 7 lines · Thierry Reding

From: Thierry Reding <[email protected]>
This clock was previously called sor1_src and was modelled as an input to the sor1 module clock. However, it's really an output clock that can be fed either from the safe, the sor1_pad_clkout or the sor1 module clocks. sor1 itself can take input from either of the display PLLs.

Quoted 6 lines

The same implementation for the sor1_out clock is used on Tegra186, so this nicely lines up both SoC generations to deal with this clock in a uniform way.
Signed-off-by Thierry Reding <[email protected]>
---

Applied to clk-next

Signature · 2 lines

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Stephen Boyd

Applied

2017-11-02 08:16 UTC #7 lore raw

In reply to Thierry Reding

Quoted 9 lines · Thierry Reding

From: Thierry Reding <[email protected]>
The sor1_src clock implemented on Tegra210 is modelled the wrong way around, which causes some issues with HDMI and DP support. This clock implementation is provided by BPMP on Tegra186, which models this in a more correct way. Since this introduces incompatibilities between the two SoC generations which we want to avoid, the Tegra210 will be fixed in subsequent patches.

Quoted 4 lines

This change adds sor1_out as an alias for sor1_src.
Signed-off-by Thierry Reding <[email protected]>
---

Applied to clk-next

Signature · 2 lines

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Thierry Reding

author

2017-11-02 08:46 UTC #8 lore raw

Quoted 10 lines · Stephen Boyd

Quoted 9 lines · Thierry Reding
From: Thierry Reding <[email protected]>
The sor1_src clock implemented on Tegra210 is modelled the wrong way around, which causes some issues with HDMI and DP support. This clock implementation is provided by BPMP on Tegra186, which models this in a more correct way. Since this introduces incompatibilities between the two SoC generations which we want to avoid, the Tegra210 will be fixed in subsequent patches.

Quoted 6 lines

Quoted 4 lines
This change adds sor1_out as an alias for sor1_src.
Signed-off-by Thierry Reding <[email protected]>
---
Applied to clk-next

Hi Stephen,

sorry for not having been clear about this. This patch and the 2-4 are part of the pull request I sent out earlier (and for which I have an updated one to fix the regression I mentioned last week). I'd prefer to send this to you via pull request because there is a dependency on this from the ARM SoC tree (for a DT change).

Any chance you could back this out?

Thierry

Stephen Boyd

2017-11-03 15:16 UTC #9 lore raw

Quoted 18 lines · Thierry Reding

Quoted 10 lines · Stephen Boyd
Quoted 9 lines · Thierry Reding
From: Thierry Reding <[email protected]>
The sor1_src clock implemented on Tegra210 is modelled the wrong way around, which causes some issues with HDMI and DP support. This clock implementation is provided by BPMP on Tegra186, which models this in a more correct way. Since this introduces incompatibilities between the two SoC generations which we want to avoid, the Tegra210 will be fixed in subsequent patches.
Quoted 6 lines
Quoted 4 lines
This change adds sor1_out as an alias for sor1_src.
Signed-off-by Thierry Reding <[email protected]>
---
Applied to clk-next

Quoted 8 lines

Hi Stephen,
sorry for not having been clear about this. This patch and the 2-4 are part of the pull request I sent out earlier (and for which I have an updated one to fix the regression I mentioned last week). I'd prefer to send this to you via pull request because there is a dependency on this from the ARM SoC tree (for a DT change).

Sure I can back out the changes. Next time please indicate your merge path/strategy in some sort of cover letter so I can ignore changes in the review queue. Also, if you pick up a patch from the list please send a note that you applied it to your tree so I know to wait for a PR later.

Is the PR coming soon? I forgot about it because we were waiting for the second one.

Signature · 2 lines

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project