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amdgpu/dc: fix indentation warning from smatch.

PATCH In review Dave Airlie 3 participants 3 messages Nov 6, 2017 – Nov 7, 2017 1 message not in the archive

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DRM drivers Radeon and amdgpu DRM drivers AMD display core
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Dave Airlie

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#0 lore raw

PATCH 1/1 amdgpu/dc: fix indentation warning from smatch.

From: Dave Airlie <[email protected]>

This fixes all the current smatch:
warn: inconsistent indenting

Signed-off-by Dave Airlie <[email protected]>
---
 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c |  2 +-
 .../gpu/drm/amd/display/dc/bios/command_table2.c   | 18 ++++++-------
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |  2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c    |  4 +--
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c     | 26 +++++++++----------
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c      | 16 ++++++------
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 30 +++++++++++-----------
 .../display/dc/dce120/dce120_timing_generator.c    |  7 +++--
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c    |  2 +-
 .../dc/i2caux/dce110/i2c_hw_engine_dce110.c        | 30 +++++++++++-----------
 10 files changed, 68 insertions(+), 69 deletions(-)
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +1 -1
index 43e9a99..1ee1717 100644
@@ -1373,7 +1373,7 @@ static enum bp_result get_firmware_info_v3_1(
 				bp->cmd_tbl.get_smu_clock_info(bp) * 10;
 	}
 
-	 return BP_RESULT_OK;
+	return BP_RESULT_OK;
 }
 
 static enum bp_result bios_parser_get_encoder_cap_info(
drivers/gpu/drm/amd/display/dc/bios/command_table2.c +9 -9
index 64eab35..ba68693 100644
@@ -373,15 +373,15 @@ static void init_set_crtc_timing(struct bios_parser *bp)
 	uint32_t dtd_version =
 			BIOS_CMD_TABLE_PARA_REVISION(setcrtc_usingdtdtiming);
 
-		switch (dtd_version) {
-		case 3:
-			bp->cmd_tbl.set_crtc_timing =
-					set_crtc_using_dtd_timing_v3;
-			break;
-		default:
-			bp->cmd_tbl.set_crtc_timing = NULL;
-			break;
-		}
+	switch (dtd_version) {
+	case 3:
+		bp->cmd_tbl.set_crtc_timing =
+			set_crtc_using_dtd_timing_v3;
+		break;
+	default:
+		bp->cmd_tbl.set_crtc_timing = NULL;
+		break;
+	}
 }
 
 static enum bp_result set_crtc_using_dtd_timing_v3(
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +1 -1
index e151523..3dce35e 100644
@@ -1155,7 +1155,7 @@ static unsigned int dcn_find_normalized_clock_vdd_Level(
 			unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
 
 			if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {
-			vdd_level = dcn_bw_v_max0p91;
+				vdd_level = dcn_bw_v_max0p91;
 				BREAK_TO_DEBUGGER();
 			} else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {
 				vdd_level = dcn_bw_v_max0p9;
drivers/gpu/drm/amd/display/dc/core/dc_stream.c +2 -2
index 572b885..de04b95 100644
@@ -182,11 +182,11 @@ bool dc_stream_set_cursor_attributes(
 
 	if (NULL == stream) {
 		dm_error("DC: dc_stream is NULL!\n");
-			return false;
+		return false;
 	}
 	if (NULL == attributes) {
 		dm_error("DC: attributes is NULL!\n");
-			return false;
+		return false;
 	}
 
 	if (attributes->address.quad_part == 0) {
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +13 -13
index 526ec5c..d882adf 100644
@@ -179,19 +179,19 @@ static void check_audio_bandwidth_hdmi(
 	/* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number
 	 * of Audio samples per line multiplied by 10 - Layout 1)
 	 */
-	 samples /= 32;
-	 samples *= crtc_info->v_active;
-	 /*Number of samples multiplied by 10, per second */
-	 samples *= crtc_info->refresh_rate;
-	 /*Number of Audio samples per second */
-	 samples /= 10;
-
-	 /* @todo do it after deep color is implemented
-	  * 8xx - deep color bandwidth scaling
-	  * Extra bandwidth is avaliable in deep color b/c link runs faster than
-	  * pixel rate. This has the effect of allowing more tmds characters to
-	  * be transmitted during blank
-	  */
+	samples /= 32;
+	samples *= crtc_info->v_active;
+	/*Number of samples multiplied by 10, per second */
+	samples *= crtc_info->refresh_rate;
+	/*Number of Audio samples per second */
+	samples /= 10;
+
+	/* @todo do it after deep color is implemented
+	 * 8xx - deep color bandwidth scaling
+	 * Extra bandwidth is avaliable in deep color b/c link runs faster than
+	 * pixel rate. This has the effect of allowing more tmds characters to
+	 * be transmitted during blank
+	 */
 
 	switch (crtc_info->color_depth) {
 	case COLOR_DEPTH_888:
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +8 -8
index 3691c74..fd77df5 100644
@@ -130,14 +130,14 @@ static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
 	if (wait == true) {
 		for (retryCount = 0; retryCount <= 100; retryCount++) {
 			dce_get_dmcu_psr_state(dmcu, &psr_state);
-				if (enable) {
-					if (psr_state != 0)
-						break;
-				} else {
-					if (psr_state == 0)
-						break;
-				}
-				udelay(10);
+			if (enable) {
+				if (psr_state != 0)
+					break;
+			} else {
+				if (psr_state == 0)
+					break;
+			}
+			udelay(10);
 		}
 	}
 }
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +15 -15
index 399a598..1229a33 100644
@@ -775,8 +775,8 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 	 * connect DIG back_end to front_end while enable_stream and
 	 * disconnect them during disable_stream
 	 * BY this, it is logic clean to separate stream and link */
-	 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
-			pipe_ctx->stream_res.stream_enc->id, true);
+	link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
+						    pipe_ctx->stream_res.stream_enc->id, true);
 
 }
 

@@ -1306,7 +1306,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
 		stream->timing.display_color_depth,
 		pipe_ctx->stream->signal);
 
-	pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
+		pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
 			pipe_ctx->stream_res.opp,
 			&stream->bit_depth_params,
 			&stream->clamping);

@@ -2594,21 +2594,21 @@ uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
 	uint8_t j;
 	uint32_t min_vertical_blank_time = -1;
 
-		for (j = 0; j < context->stream_count; j++) {
-			struct dc_stream_state *stream = context->streams[j];
-			uint32_t vertical_blank_in_pixels = 0;
-			uint32_t vertical_blank_time = 0;
+	for (j = 0; j < context->stream_count; j++) {
+		struct dc_stream_state *stream = context->streams[j];
+		uint32_t vertical_blank_in_pixels = 0;
+		uint32_t vertical_blank_time = 0;
 
-			vertical_blank_in_pixels = stream->timing.h_total *
-				(stream->timing.v_total
-					- stream->timing.v_addressable);
+		vertical_blank_in_pixels = stream->timing.h_total *
+			(stream->timing.v_total
+			 - stream->timing.v_addressable);
 
-			vertical_blank_time = vertical_blank_in_pixels
-				* 1000 / stream->timing.pix_clk_khz;
+		vertical_blank_time = vertical_blank_in_pixels
+			* 1000 / stream->timing.pix_clk_khz;
 
-			if (min_vertical_blank_time > vertical_blank_time)
-				min_vertical_blank_time = vertical_blank_time;
-		}
+		if (min_vertical_blank_time > vertical_blank_time)
+			min_vertical_blank_time = vertical_blank_time;
+	}
 
 	return min_vertical_blank_time;
 }
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +3 -4
index 95d871b..2502182 100644
@@ -293,10 +293,9 @@ void dce120_timing_generator_tear_down_global_swap_lock(
 			FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE), 0,
 			FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING), 0);
 
-		CRTC_REG_SET_2(
-			CRTC0_CRTC_GSL_CONTROL,
-			CRTC_GSL_CHECK_LINE_NUM, 0,
-			CRTC_GSL_FORCE_DELAY, 0x2); /*TODO Why this value here ?*/
+	CRTC_REG_SET_2(CRTC0_CRTC_GSL_CONTROL,
+		       CRTC_GSL_CHECK_LINE_NUM, 0,
+		       CRTC_GSL_FORCE_DELAY, 0x2); /*TODO Why this value here ?*/
 }
 
 /* Reset slave controllers on master VSync */
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +1 -1
index 7784001..40627c2 100644
@@ -124,7 +124,7 @@ static void program_gamut_remap(
 		const uint16_t *regval,
 		enum gamut_remap_select select)
 {
-	 uint16_t selection = 0;
+	uint16_t selection = 0;
 	struct color_matrices_reg gam_regs;
 
 	if (regval == NULL || select == GAMUT_REMAP_BYPASS) {
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c +15 -15
index 1a5b3f7..56e25b3 100644
@@ -133,13 +133,13 @@ static void release_engine(
 		safe_to_reset = (i2c_sw_status == 1);
 	}
 
-		if (safe_to_reset)
-			REG_UPDATE_2(
-					DC_I2C_CONTROL,
-					DC_I2C_SOFT_RESET, 1,
-					DC_I2C_SW_STATUS_RESET, 1);
-		else
-			REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1);
+	if (safe_to_reset)
+		REG_UPDATE_2(
+			DC_I2C_CONTROL,
+			DC_I2C_SOFT_RESET, 1,
+			DC_I2C_SW_STATUS_RESET, 1);
+	else
+		REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1);
 
 	/* HW I2c engine - clock gating feature */
 	if (!hw_engine->engine_keep_power_up_count)

@@ -301,16 +301,16 @@ static bool process_transaction(
 	 * For an I2C send operation, the LSB must be programmed to 0;
 	 * for I2C receive operation, the LSB must be programmed to 1. */
 	if (hw_engine->transaction_count == 0) {
-			value = REG_SET_4(DC_I2C_DATA, 0,
-						DC_I2C_DATA_RW, false,
-						DC_I2C_DATA, request->address,
-						DC_I2C_INDEX, 0,
-						DC_I2C_INDEX_WRITE, 1);
+		value = REG_SET_4(DC_I2C_DATA, 0,
+				  DC_I2C_DATA_RW, false,
+				  DC_I2C_DATA, request->address,
+				  DC_I2C_INDEX, 0,
+				  DC_I2C_INDEX_WRITE, 1);
 		hw_engine->buffer_used_write = 0;
 	} else
-			value = REG_SET_2(DC_I2C_DATA, 0,
-						DC_I2C_DATA_RW, false,
-						DC_I2C_DATA, request->address);
+		value = REG_SET_2(DC_I2C_DATA, 0,
+				  DC_I2C_DATA_RW, false,
+				  DC_I2C_DATA, request->address);
 
 	hw_engine->buffer_used_write++;
Signature · 6 lines
2.9.5

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A message that is not in the archive (sent off-list or not yet received): 20171106193047.31275-1-airlied-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org

Reviewed-by
#2 lore raw
Reviewed-by Andrey Grodzovsky <[email protected]>
Quoted 285 lines · Dave Airlie

From: Dave Airlie <[email protected]>

This fixes all the current smatch:
warn: inconsistent indenting

Signed-off-by Dave Airlie <[email protected]>
---
  drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c |  2 +-
  .../gpu/drm/amd/display/dc/bios/command_table2.c   | 18 ++++++-------
  drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |  2 +-
  drivers/gpu/drm/amd/display/dc/core/dc_stream.c    |  4 +--
  drivers/gpu/drm/amd/display/dc/dce/dce_audio.c     | 26 +++++++++----------
  drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c      | 16 ++++++------
  .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 30 +++++++++++-----------
  .../display/dc/dce120/dce120_timing_generator.c    |  7 +++--
  .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c    |  2 +-
  .../dc/i2caux/dce110/i2c_hw_engine_dce110.c        | 30 +++++++++++-----------
  10 files changed, 68 insertions(+), 69 deletions(-)
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +1 -1
index 43e9a99..1ee1717 100644
@@ -1373,7 +1373,7 @@ static enum bp_result get_firmware_info_v3_1(
  				bp->cmd_tbl.get_smu_clock_info(bp) * 10;
  	}
 
-	 return BP_RESULT_OK;
+	return BP_RESULT_OK;
  }
 
  static enum bp_result bios_parser_get_encoder_cap_info(
drivers/gpu/drm/amd/display/dc/bios/command_table2.c +9 -9
index 64eab35..ba68693 100644
@@ -373,15 +373,15 @@ static void init_set_crtc_timing(struct bios_parser *bp)
  	uint32_t dtd_version =
  			BIOS_CMD_TABLE_PARA_REVISION(setcrtc_usingdtdtiming);
 
-		switch (dtd_version) {
-		case 3:
-			bp->cmd_tbl.set_crtc_timing =
-					set_crtc_using_dtd_timing_v3;
-			break;
-		default:
-			bp->cmd_tbl.set_crtc_timing = NULL;
-			break;
-		}
+	switch (dtd_version) {
+	case 3:
+		bp->cmd_tbl.set_crtc_timing =
+			set_crtc_using_dtd_timing_v3;
+		break;
+	default:
+		bp->cmd_tbl.set_crtc_timing = NULL;
+		break;
+	}
  }
 
  static enum bp_result set_crtc_using_dtd_timing_v3(
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +1 -1
index e151523..3dce35e 100644
@@ -1155,7 +1155,7 @@ static unsigned int dcn_find_normalized_clock_vdd_Level(
  			unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
 
  			if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {
-			vdd_level = dcn_bw_v_max0p91;
+				vdd_level = dcn_bw_v_max0p91;
  				BREAK_TO_DEBUGGER();
  			} else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {
  				vdd_level = dcn_bw_v_max0p9;
drivers/gpu/drm/amd/display/dc/core/dc_stream.c +2 -2
index 572b885..de04b95 100644
@@ -182,11 +182,11 @@ bool dc_stream_set_cursor_attributes(
 
  	if (NULL == stream) {
  		dm_error("DC: dc_stream is NULL!\n");
-			return false;
+		return false;
  	}
  	if (NULL == attributes) {
  		dm_error("DC: attributes is NULL!\n");
-			return false;
+		return false;
  	}
 
  	if (attributes->address.quad_part == 0) {
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +13 -13
index 526ec5c..d882adf 100644
@@ -179,19 +179,19 @@ static void check_audio_bandwidth_hdmi(
  	/* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number
  	 * of Audio samples per line multiplied by 10 - Layout 1)
  	 */
-	 samples /= 32;
-	 samples *= crtc_info->v_active;
-	 /*Number of samples multiplied by 10, per second */
-	 samples *= crtc_info->refresh_rate;
-	 /*Number of Audio samples per second */
-	 samples /= 10;
-
-	 /* @todo do it after deep color is implemented
-	  * 8xx - deep color bandwidth scaling
-	  * Extra bandwidth is avaliable in deep color b/c link runs faster than
-	  * pixel rate. This has the effect of allowing more tmds characters to
-	  * be transmitted during blank
-	  */
+	samples /= 32;
+	samples *= crtc_info->v_active;
+	/*Number of samples multiplied by 10, per second */
+	samples *= crtc_info->refresh_rate;
+	/*Number of Audio samples per second */
+	samples /= 10;
+
+	/* @todo do it after deep color is implemented
+	 * 8xx - deep color bandwidth scaling
+	 * Extra bandwidth is avaliable in deep color b/c link runs faster than
+	 * pixel rate. This has the effect of allowing more tmds characters to
+	 * be transmitted during blank
+	 */
 
  	switch (crtc_info->color_depth) {
  	case COLOR_DEPTH_888:
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +8 -8
index 3691c74..fd77df5 100644
@@ -130,14 +130,14 @@ static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
  	if (wait == true) {
  		for (retryCount = 0; retryCount <= 100; retryCount++) {
  			dce_get_dmcu_psr_state(dmcu, &psr_state);
-				if (enable) {
-					if (psr_state != 0)
-						break;
-				} else {
-					if (psr_state == 0)
-						break;
-				}
-				udelay(10);
+			if (enable) {
+				if (psr_state != 0)
+					break;
+			} else {
+				if (psr_state == 0)
+					break;
+			}
+			udelay(10);
  		}
  	}
  }
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +15 -15
index 399a598..1229a33 100644
@@ -775,8 +775,8 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
  	 * connect DIG back_end to front_end while enable_stream and
  	 * disconnect them during disable_stream
  	 * BY this, it is logic clean to separate stream and link */
-	 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
-			pipe_ctx->stream_res.stream_enc->id, true);
+	link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
+						    pipe_ctx->stream_res.stream_enc->id, true);
 
  }
 

@@ -1306,7 +1306,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
  		stream->timing.display_color_depth,
  		pipe_ctx->stream->signal);
 
-	pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
+		pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
  			pipe_ctx->stream_res.opp,
  			&stream->bit_depth_params,
  			&stream->clamping);

@@ -2594,21 +2594,21 @@ uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
  	uint8_t j;
  	uint32_t min_vertical_blank_time = -1;
 
-		for (j = 0; j < context->stream_count; j++) {
-			struct dc_stream_state *stream = context->streams[j];
-			uint32_t vertical_blank_in_pixels = 0;
-			uint32_t vertical_blank_time = 0;
+	for (j = 0; j < context->stream_count; j++) {
+		struct dc_stream_state *stream = context->streams[j];
+		uint32_t vertical_blank_in_pixels = 0;
+		uint32_t vertical_blank_time = 0;
 
-			vertical_blank_in_pixels = stream->timing.h_total *
-				(stream->timing.v_total
-					- stream->timing.v_addressable);
+		vertical_blank_in_pixels = stream->timing.h_total *
+			(stream->timing.v_total
+			 - stream->timing.v_addressable);
 
-			vertical_blank_time = vertical_blank_in_pixels
-				* 1000 / stream->timing.pix_clk_khz;
+		vertical_blank_time = vertical_blank_in_pixels
+			* 1000 / stream->timing.pix_clk_khz;
 
-			if (min_vertical_blank_time > vertical_blank_time)
-				min_vertical_blank_time = vertical_blank_time;
-		}
+		if (min_vertical_blank_time > vertical_blank_time)
+			min_vertical_blank_time = vertical_blank_time;
+	}
 
  	return min_vertical_blank_time;
  }
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +3 -4
index 95d871b..2502182 100644
@@ -293,10 +293,9 @@ void dce120_timing_generator_tear_down_global_swap_lock(
  			FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE), 0,
  			FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING), 0);
 
-		CRTC_REG_SET_2(
-			CRTC0_CRTC_GSL_CONTROL,
-			CRTC_GSL_CHECK_LINE_NUM, 0,
-			CRTC_GSL_FORCE_DELAY, 0x2); /*TODO Why this value here ?*/
+	CRTC_REG_SET_2(CRTC0_CRTC_GSL_CONTROL,
+		       CRTC_GSL_CHECK_LINE_NUM, 0,
+		       CRTC_GSL_FORCE_DELAY, 0x2); /*TODO Why this value here ?*/
  }
 
  /* Reset slave controllers on master VSync */
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +1 -1
index 7784001..40627c2 100644
@@ -124,7 +124,7 @@ static void program_gamut_remap(
  		const uint16_t *regval,
  		enum gamut_remap_select select)
  {
-	 uint16_t selection = 0;
+	uint16_t selection = 0;
  	struct color_matrices_reg gam_regs;
 
  	if (regval == NULL || select == GAMUT_REMAP_BYPASS) {
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c +12 -12
index 1a5b3f7..56e25b3 100644
@@ -133,13 +133,13 @@ static void release_engine(
  		safe_to_reset = (i2c_sw_status == 1);
  	}
 
-		if (safe_to_reset)
-			REG_UPDATE_2(
-					DC_I2C_CONTROL,
-					DC_I2C_SOFT_RESET, 1,
-					DC_I2C_SW_STATUS_RESET, 1);
-		else
-			REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1);
+	if (safe_to_reset)
+		REG_UPDATE_2(
+			DC_I2C_CONTROL,
+			DC_I2C_SOFT_RESET, 1,
+			DC_I2C_SW_STATUS_RESET, 1);
+	else
+		REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1);
 
  	/* HW I2c engine - clock gating feature */
  	if (!hw_engine->engine_keep_power_up_count)

@@ -301,16 +301,16 @@ static bool process_transaction(
  	 * For an I2C send operation, the LSB must be programmed to 0;
  	 * for I2C receive operation, the LSB must be programmed to 1. */
  	if (hw_engine->transaction_count == 0) {
-			value = REG_SET_4(DC_I2C_DATA, 0,
-						DC_I2C_DATA_RW, false,
-						DC_I2C_DATA, request->address,
-						DC_I2C_INDEX, 0,
-						DC_I2C_INDEX_WRITE, 1);
+		value = REG_SET_4(DC_I2C_DATA, 0,
+				  DC_I2C_DATA_RW, false,
+				  DC_I2C_DATA, request->address,
+				  DC_I2C_INDEX, 0,
+				  DC_I2C_INDEX_WRITE, 1);
  		hw_engine->buffer_used_write = 0;

drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c static bool process_transaction( · line 316

Quoted 10 lines
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c +3 -3
  	} else
-			value = REG_SET_2(DC_I2C_DATA, 0,
-						DC_I2C_DATA_RW, false,
-						DC_I2C_DATA, request->address);
+		value = REG_SET_2(DC_I2C_DATA, 0,
+				  DC_I2C_DATA_RW, false,
+				  DC_I2C_DATA, request->address);
 
  	hw_engine->buffer_used_write++;

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Reviewed-by
#3 lore raw
In reply to a message not in the archive
Quoted 6 lines · Dave Airlie

From: Dave Airlie <[email protected]>

This fixes all the current smatch:
warn: inconsistent indenting

Signed-off-by Dave Airlie <[email protected]>
Reviewed-by Harry Wentland <[email protected]>

Harry

Quoted 280 lines
---
 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c |  2 +-
 .../gpu/drm/amd/display/dc/bios/command_table2.c   | 18 ++++++-------
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |  2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c    |  4 +--
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c     | 26 +++++++++----------
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c      | 16 ++++++------
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 30 +++++++++++-----------
 .../display/dc/dce120/dce120_timing_generator.c    |  7 +++--
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c    |  2 +-
 .../dc/i2caux/dce110/i2c_hw_engine_dce110.c        | 30 +++++++++++-----------
 10 files changed, 68 insertions(+), 69 deletions(-)
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +1 -1
index 43e9a99..1ee1717 100644
@@ -1373,7 +1373,7 @@ static enum bp_result get_firmware_info_v3_1(
 				bp->cmd_tbl.get_smu_clock_info(bp) * 10;
 	}
 
-	 return BP_RESULT_OK;
+	return BP_RESULT_OK;
 }
 
 static enum bp_result bios_parser_get_encoder_cap_info(
drivers/gpu/drm/amd/display/dc/bios/command_table2.c +9 -9
index 64eab35..ba68693 100644
@@ -373,15 +373,15 @@ static void init_set_crtc_timing(struct bios_parser *bp)
 	uint32_t dtd_version =
 			BIOS_CMD_TABLE_PARA_REVISION(setcrtc_usingdtdtiming);
 
-		switch (dtd_version) {
-		case 3:
-			bp->cmd_tbl.set_crtc_timing =
-					set_crtc_using_dtd_timing_v3;
-			break;
-		default:
-			bp->cmd_tbl.set_crtc_timing = NULL;
-			break;
-		}
+	switch (dtd_version) {
+	case 3:
+		bp->cmd_tbl.set_crtc_timing =
+			set_crtc_using_dtd_timing_v3;
+		break;
+	default:
+		bp->cmd_tbl.set_crtc_timing = NULL;
+		break;
+	}
 }
 
 static enum bp_result set_crtc_using_dtd_timing_v3(
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +1 -1
index e151523..3dce35e 100644
@@ -1155,7 +1155,7 @@ static unsigned int dcn_find_normalized_clock_vdd_Level(
 			unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
 
 			if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {
-			vdd_level = dcn_bw_v_max0p91;
+				vdd_level = dcn_bw_v_max0p91;
 				BREAK_TO_DEBUGGER();
 			} else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {
 				vdd_level = dcn_bw_v_max0p9;
drivers/gpu/drm/amd/display/dc/core/dc_stream.c +2 -2
index 572b885..de04b95 100644
@@ -182,11 +182,11 @@ bool dc_stream_set_cursor_attributes(
 
 	if (NULL == stream) {
 		dm_error("DC: dc_stream is NULL!\n");
-			return false;
+		return false;
 	}
 	if (NULL == attributes) {
 		dm_error("DC: attributes is NULL!\n");
-			return false;
+		return false;
 	}
 
 	if (attributes->address.quad_part == 0) {
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +13 -13
index 526ec5c..d882adf 100644
@@ -179,19 +179,19 @@ static void check_audio_bandwidth_hdmi(
 	/* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number
 	 * of Audio samples per line multiplied by 10 - Layout 1)
 	 */
-	 samples /= 32;
-	 samples *= crtc_info->v_active;
-	 /*Number of samples multiplied by 10, per second */
-	 samples *= crtc_info->refresh_rate;
-	 /*Number of Audio samples per second */
-	 samples /= 10;
-
-	 /* @todo do it after deep color is implemented
-	  * 8xx - deep color bandwidth scaling
-	  * Extra bandwidth is avaliable in deep color b/c link runs faster than
-	  * pixel rate. This has the effect of allowing more tmds characters to
-	  * be transmitted during blank
-	  */
+	samples /= 32;
+	samples *= crtc_info->v_active;
+	/*Number of samples multiplied by 10, per second */
+	samples *= crtc_info->refresh_rate;
+	/*Number of Audio samples per second */
+	samples /= 10;
+
+	/* @todo do it after deep color is implemented
+	 * 8xx - deep color bandwidth scaling
+	 * Extra bandwidth is avaliable in deep color b/c link runs faster than
+	 * pixel rate. This has the effect of allowing more tmds characters to
+	 * be transmitted during blank
+	 */
 
 	switch (crtc_info->color_depth) {
 	case COLOR_DEPTH_888:
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +8 -8
index 3691c74..fd77df5 100644
@@ -130,14 +130,14 @@ static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
 	if (wait == true) {
 		for (retryCount = 0; retryCount <= 100; retryCount++) {
 			dce_get_dmcu_psr_state(dmcu, &psr_state);
-				if (enable) {
-					if (psr_state != 0)
-						break;
-				} else {
-					if (psr_state == 0)
-						break;
-				}
-				udelay(10);
+			if (enable) {
+				if (psr_state != 0)
+					break;
+			} else {
+				if (psr_state == 0)
+					break;
+			}
+			udelay(10);
 		}
 	}
 }
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +15 -15
index 399a598..1229a33 100644
@@ -775,8 +775,8 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 	 * connect DIG back_end to front_end while enable_stream and
 	 * disconnect them during disable_stream
 	 * BY this, it is logic clean to separate stream and link */
-	 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
-			pipe_ctx->stream_res.stream_enc->id, true);
+	link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
+						    pipe_ctx->stream_res.stream_enc->id, true);
 
 }
 

@@ -1306,7 +1306,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
 		stream->timing.display_color_depth,
 		pipe_ctx->stream->signal);
 
-	pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
+		pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
 			pipe_ctx->stream_res.opp,
 			&stream->bit_depth_params,
 			&stream->clamping);

@@ -2594,21 +2594,21 @@ uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
 	uint8_t j;
 	uint32_t min_vertical_blank_time = -1;
 
-		for (j = 0; j < context->stream_count; j++) {
-			struct dc_stream_state *stream = context->streams[j];
-			uint32_t vertical_blank_in_pixels = 0;
-			uint32_t vertical_blank_time = 0;
+	for (j = 0; j < context->stream_count; j++) {
+		struct dc_stream_state *stream = context->streams[j];
+		uint32_t vertical_blank_in_pixels = 0;
+		uint32_t vertical_blank_time = 0;
 
-			vertical_blank_in_pixels = stream->timing.h_total *
-				(stream->timing.v_total
-					- stream->timing.v_addressable);
+		vertical_blank_in_pixels = stream->timing.h_total *
+			(stream->timing.v_total
+			 - stream->timing.v_addressable);
 
-			vertical_blank_time = vertical_blank_in_pixels
-				* 1000 / stream->timing.pix_clk_khz;
+		vertical_blank_time = vertical_blank_in_pixels
+			* 1000 / stream->timing.pix_clk_khz;
 
-			if (min_vertical_blank_time > vertical_blank_time)
-				min_vertical_blank_time = vertical_blank_time;
-		}
+		if (min_vertical_blank_time > vertical_blank_time)
+			min_vertical_blank_time = vertical_blank_time;
+	}
 
 	return min_vertical_blank_time;
 }
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +3 -4
index 95d871b..2502182 100644
@@ -293,10 +293,9 @@ void dce120_timing_generator_tear_down_global_swap_lock(
 			FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE), 0,
 			FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING), 0);
 
-		CRTC_REG_SET_2(
-			CRTC0_CRTC_GSL_CONTROL,
-			CRTC_GSL_CHECK_LINE_NUM, 0,
-			CRTC_GSL_FORCE_DELAY, 0x2); /*TODO Why this value here ?*/
+	CRTC_REG_SET_2(CRTC0_CRTC_GSL_CONTROL,
+		       CRTC_GSL_CHECK_LINE_NUM, 0,
+		       CRTC_GSL_FORCE_DELAY, 0x2); /*TODO Why this value here ?*/
 }
 
 /* Reset slave controllers on master VSync */
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +1 -1
index 7784001..40627c2 100644
@@ -124,7 +124,7 @@ static void program_gamut_remap(
 		const uint16_t *regval,
 		enum gamut_remap_select select)
 {
-	 uint16_t selection = 0;
+	uint16_t selection = 0;
 	struct color_matrices_reg gam_regs;
 
 	if (regval == NULL || select == GAMUT_REMAP_BYPASS) {
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c +12 -12
index 1a5b3f7..56e25b3 100644
@@ -133,13 +133,13 @@ static void release_engine(
 		safe_to_reset = (i2c_sw_status == 1);
 	}
 
-		if (safe_to_reset)
-			REG_UPDATE_2(
-					DC_I2C_CONTROL,
-					DC_I2C_SOFT_RESET, 1,
-					DC_I2C_SW_STATUS_RESET, 1);
-		else
-			REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1);
+	if (safe_to_reset)
+		REG_UPDATE_2(
+			DC_I2C_CONTROL,
+			DC_I2C_SOFT_RESET, 1,
+			DC_I2C_SW_STATUS_RESET, 1);
+	else
+		REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1);
 
 	/* HW I2c engine - clock gating feature */
 	if (!hw_engine->engine_keep_power_up_count)

@@ -301,16 +301,16 @@ static bool process_transaction(
 	 * For an I2C send operation, the LSB must be programmed to 0;
 	 * for I2C receive operation, the LSB must be programmed to 1. */
 	if (hw_engine->transaction_count == 0) {
-			value = REG_SET_4(DC_I2C_DATA, 0,
-						DC_I2C_DATA_RW, false,
-						DC_I2C_DATA, request->address,
-						DC_I2C_INDEX, 0,
-						DC_I2C_INDEX_WRITE, 1);
+		value = REG_SET_4(DC_I2C_DATA, 0,
+				  DC_I2C_DATA_RW, false,
+				  DC_I2C_DATA, request->address,
+				  DC_I2C_INDEX, 0,
+				  DC_I2C_INDEX_WRITE, 1);
 		hw_engine->buffer_used_write = 0;

drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c static bool process_transaction( · line 316

Quoted 10 lines
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c +3 -3
 	} else
-			value = REG_SET_2(DC_I2C_DATA, 0,
-						DC_I2C_DATA_RW, false,
-						DC_I2C_DATA, request->address);
+		value = REG_SET_2(DC_I2C_DATA, 0,
+				  DC_I2C_DATA_RW, false,
+				  DC_I2C_DATA, request->address);
 
 	hw_engine->buffer_used_write++;

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