drm/amd/amdgpu: fix UVD mc offsets

PATCH Superseded Piotr Redlewski 2 participants 4 messages Nov 10, 2017 3 messages not in the archive

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DRM drivers Radeon and amdgpu DRM drivers

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Piotr Redlewski

author

2017-11-10 11:34 UTC #0 lore raw

PATCH 1/1 drm/amd/amdgpu: fix UVD mc offsets

When UVD bo is created, its size is based on the information from firmware header (ucode_size_bytes). The same value should be be used when programming UVD mc controller offsets, otherwise it can happen that (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will point AMDGPU_GPU_PAGE_SIZE bytes after the UVD bo end.

Second issue is that when programming the mmUVD_VCPU_CACHE_SIZE0 register, AMDGPU_UVD_FIRMWARE_OFFSET should be taken into account. If it isn't, (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will always point AMDGPU_UVD_FIRMWARE_OFFSET bytes after the UVD bo end.

Signed-off-by Piotr Redlewski <[email protected]>

---
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 5 ++++-
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 5 ++++-
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 5 ++++-
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 7 ++++++-
 4 files changed, 18 insertions(+), 4 deletions(-)

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +4 -1

index 15771a53038e..aa171464f203 100644
@@ -560,10 +560,13 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
 {
 	uint64_t addr;
 	uint32_t size;
+	const struct common_firmware_header *hdr;
 
 	/* programm the VCPU memory controller bits 0-27 */
 	addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
-	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3;
+	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+	size = (AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) -
+		AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
 	WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
 	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +4 -1

index 3b29aaba783a..7daf4e92aa8b 100644
@@ -250,6 +250,7 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
 {
 	uint64_t offset;
 	uint32_t size;
+	const struct common_firmware_header *hdr;
 
 	/* programm memory controller bits 0-27 */
 	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

@@ -258,7 +259,9 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
 			upper_32_bits(adev->uvd.gpu_addr));
 
 	offset = AMDGPU_UVD_FIRMWARE_OFFSET;
-	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
+	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) -
+	       AMDGPU_UVD_FIRMWARE_OFFSET;
 	WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
 	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +4 -1

index 0c01825a8b9e..7c510aed7a1b 100644
@@ -595,6 +595,7 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
 {
 	uint64_t offset;
 	uint32_t size;
+	const struct common_firmware_header *hdr;
 
 	/* programm memory controller bits 0-27 */
 	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

@@ -603,7 +604,9 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
 			upper_32_bits(adev->uvd.gpu_addr));
 
 	offset = AMDGPU_UVD_FIRMWARE_OFFSET;
-	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
+	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) -
+	       AMDGPU_UVD_FIRMWARE_OFFSET;
 	WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
 	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +6 -1

index 7b77339feb1a..b015cfd5067d 100644
@@ -616,8 +616,13 @@ static int uvd_v7_0_resume(void *handle)
  */
 static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
 {
-	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
+	uint32_t size;
 	uint32_t offset;
+	const struct common_firmware_header *hdr;
+
+	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) -
+	       AMDGPU_UVD_FIRMWARE_OFFSET;
 
 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

Signature · 6 lines

2.15.0

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Christian König

2017-11-10 11:55 UTC #2 lore raw

Am 10.11.2017 um 12:34 schrieb Piotr Redlewski:

Quoted 10 lines

When UVD bo is created, its size is based on the information from firmware header (ucode_size_bytes). The same value should be be used when programming UVD mc controller offsets, otherwise it can happen that (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will point AMDGPU_GPU_PAGE_SIZE bytes after the UVD bo end.
Second issue is that when programming the mmUVD_VCPU_CACHE_SIZE0 register, AMDGPU_UVD_FIRMWARE_OFFSET should be taken into account. If it isn't, (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will always point AMDGPU_UVD_FIRMWARE_OFFSET bytes after the UVD bo end.

Good catch, a few notes inside.

Quoted 14 lines

Signed-off-by Piotr Redlewski <[email protected]>

---
  drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 5 ++++-
  drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 5 ++++-
  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 5 ++++-
  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 7 ++++++-
  4 files changed, 18 insertions(+), 4 deletions(-)

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +0 -0

index 15771a53038e..aa171464f203 100644

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) · line 563

Quoted 4 lines

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +1 -0

@@ -560,10 +560,13 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
  {
  	uint64_t addr;
  	uint32_t size;
+	const struct common_firmware_header *hdr;

Coding style says reverse tree order. In other words longest line first.

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) · line 569

Quoted 7 lines

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +3 -1

  	/* programm the VCPU memory controller bits 0-27 */
  	addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
-	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3;
+	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+	size = (AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) -
+		AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;

Instead of repeating the code multiple times please add a define for this into amdgpu_uvd.h. E.g. something like this:

#define AMDGPU_UVD_FIRMWARE_SIZE(adev)    \
    (((const struct common_firmware_header *)(adev)->uvd.fw->data)->ucode_size_bytes + \
    8 - AMDGPU_UVD_FIRMWARE_OFFSET)

Regards,
Christian.

Quoted 58 lines

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +0 -0

  	WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
  	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +4 -1

index 3b29aaba783a..7daf4e92aa8b 100644
@@ -250,6 +250,7 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
  {
  	uint64_t offset;
  	uint32_t size;
+	const struct common_firmware_header *hdr;
 
  	/* programm memory controller bits 0-27 */
  	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

@@ -258,7 +259,9 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
  			upper_32_bits(adev->uvd.gpu_addr));
 
  	offset = AMDGPU_UVD_FIRMWARE_OFFSET;
-	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
+	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) -
+	       AMDGPU_UVD_FIRMWARE_OFFSET;
  	WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
  	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +4 -1

index 0c01825a8b9e..7c510aed7a1b 100644
@@ -595,6 +595,7 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
  {
  	uint64_t offset;
  	uint32_t size;
+	const struct common_firmware_header *hdr;
 
  	/* programm memory controller bits 0-27 */
  	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

@@ -603,7 +604,9 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
  			upper_32_bits(adev->uvd.gpu_addr));
 
  	offset = AMDGPU_UVD_FIRMWARE_OFFSET;
-	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
+	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) -
+	       AMDGPU_UVD_FIRMWARE_OFFSET;
  	WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
  	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +0 -1

index 7b77339feb1a..b015cfd5067d 100644
@@ -616,8 +616,13 @@ static int uvd_v7_0_resume(void *handle)
   */
  static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
  {
-	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c static int uvd_v7_0_resume(void *handle) · line 628

Quoted 10 lines

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +6 -0

+	uint32_t size;
  	uint32_t offset;
+	const struct common_firmware_header *hdr;
+
+	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) -
+	       AMDGPU_UVD_FIRMWARE_OFFSET;
 
  	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
  		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

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Piotr Redlewski

author

2017-11-10 14:50 UTC #4 lore raw

Quoted 7 lines · Christian König

Am 10.11.2017 um 12:34 schrieb Piotr Redlewski:
Quoted 6 lines
When UVD bo is created, its size is based on the information from firmware header (ucode_size_bytes). The same value should be be used when programming UVD mc controller offsets, otherwise it can happen that (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will point AMDGPU_GPU_PAGE_SIZE bytes after the UVD bo end.

Quoted 6 lines

Quoted 4 lines
Second issue is that when programming the mmUVD_VCPU_CACHE_SIZE0 register, AMDGPU_UVD_FIRMWARE_OFFSET should be taken into account. If it isn't, (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will always point AMDGPU_UVD_FIRMWARE_OFFSET bytes after the UVD bo end.
Good catch, a few notes inside.

Thanks for comments, I've already sent v2 of the patch.

Quoted 32 lines

Quoted 15 lines
Signed-off-by Piotr Redlewski <[email protected]>
---
  drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 5 ++++-
  drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 5 ++++-
  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 5 ++++-
  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 7 ++++++-
  4 files changed, 18 insertions(+), 4 deletions(-)
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +0 -0
index 15771a53038e..aa171464f203 100644
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) · line 563
Quoted 4 lines
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +1 -0
@@ -560,10 +560,13 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
  {
  	uint64_t addr;
  	uint32_t size;
+	const struct common_firmware_header *hdr;
Coding style says reverse tree order. In other words longest line first.
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) · line 569
Quoted 6 lines
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +3 -1
  	/* programm the VCPU memory controller bits 0-27 */
  	addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
-	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3;
+	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+	size = (AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) -
+		AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
Instead of repeating the code multiple times please add a define for this into amdgpu_uvd.h. E.g. something like this:

Quoted 4 lines

#define AMDGPU_UVD_FIRMWARE_SIZE(adev)    \
    (((const struct common_firmware_header
*)(adev)->uvd.fw->data)->ucode_size_bytes + \
    8 - AMDGPU_UVD_FIRMWARE_OFFSET)

I probably miss something, but this get me wondering - when calculating the size of the UVD bo, firmware size is aligned to the page size. Is there a reason for that? If not, maybe similar change could be done in amdgpu_uvd_sw_init.

Regards,
Piotr

Quoted 62 lines

Regards,
Christian.

Quoted 58 lines

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +0 -0

  	WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
  	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +4 -1

index 3b29aaba783a..7daf4e92aa8b 100644
@@ -250,6 +250,7 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
  {
  	uint64_t offset;
  	uint32_t size;
+	const struct common_firmware_header *hdr;
  	/* programm memory controller bits 0-27 */
  	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

@@ -258,7 +259,9 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
  			upper_32_bits(adev->uvd.gpu_addr));
  	offset = AMDGPU_UVD_FIRMWARE_OFFSET;
-	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
+	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) -
+	       AMDGPU_UVD_FIRMWARE_OFFSET;
  	WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
  	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +4 -1

index 0c01825a8b9e..7c510aed7a1b 100644
@@ -595,6 +595,7 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
  {
  	uint64_t offset;
  	uint32_t size;
+	const struct common_firmware_header *hdr;
  	/* programm memory controller bits 0-27 */
  	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

@@ -603,7 +604,9 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
  			upper_32_bits(adev->uvd.gpu_addr));
  	offset = AMDGPU_UVD_FIRMWARE_OFFSET;
-	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
+	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) -
+	       AMDGPU_UVD_FIRMWARE_OFFSET;
  	WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
  	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +6 -1

index 7b77339feb1a..b015cfd5067d 100644
@@ -616,8 +616,13 @@ static int uvd_v7_0_resume(void *handle)
   */
  static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
  {
-	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
+	uint32_t size;
  	uint32_t offset;
+	const struct common_firmware_header *hdr;
+
+	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) -
+	       AMDGPU_UVD_FIRMWARE_OFFSET;

Quoted 8 lines

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c static int uvd_v7_0_resume(void *handle) · line 628
Quoted 2 lines
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +0 -0
  	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
  		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
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Piotr Redlewski

author

2017-11-10 18:41 UTC #6 lore raw

Quoted 48 lines · Piotr Redlewski

Quoted 7 lines · Christian König
Am 10.11.2017 um 12:34 schrieb Piotr Redlewski:
Quoted 6 lines
When UVD bo is created, its size is based on the information from firmware header (ucode_size_bytes). The same value should be be used when programming UVD mc controller offsets, otherwise it can happen that (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will point AMDGPU_GPU_PAGE_SIZE bytes after the UVD bo end.
Quoted 6 lines
Quoted 4 lines
Second issue is that when programming the mmUVD_VCPU_CACHE_SIZE0 register, AMDGPU_UVD_FIRMWARE_OFFSET should be taken into account. If it isn't, (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will always point AMDGPU_UVD_FIRMWARE_OFFSET bytes after the UVD bo end.
Good catch, a few notes inside.
Thanks for comments, I've already sent v2 of the patch.
Quoted 32 lines
Quoted 15 lines
Signed-off-by Piotr Redlewski <[email protected]>
---
  drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 5 ++++-
  drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 5 ++++-
  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 5 ++++-
  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 7 ++++++-
  4 files changed, 18 insertions(+), 4 deletions(-)
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +0 -0
index 15771a53038e..aa171464f203 100644
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) · line 563
Quoted 4 lines
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +1 -0
@@ -560,10 +560,13 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
  {
  	uint64_t addr;
  	uint32_t size;
+	const struct common_firmware_header *hdr;
Coding style says reverse tree order. In other words longest line first.
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) · line 569
Quoted 6 lines
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +3 -1
  	/* programm the VCPU memory controller bits 0-27 */
  	addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
-	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3;
+	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+	size = (AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) -
+		AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
Instead of repeating the code multiple times please add a define for this into amdgpu_uvd.h. E.g. something like this:

Quoted 8 lines

Quoted 4 lines
#define AMDGPU_UVD_FIRMWARE_SIZE(adev)    \
    (((const struct common_firmware_header
*)(adev)->uvd.fw->data)->ucode_size_bytes + \
    8 - AMDGPU_UVD_FIRMWARE_OFFSET)
I probably miss something, but this get me wondering - when calculating the size of the UVD bo, firmware size is aligned to the page size. Is there a reason for that? If not, maybe similar change could be done in amdgpu_uvd_sw_init.

Nevermind, I've answered myself this question with v3 of this patch.

Regards,
Piotr

Quoted 73 lines

Regards,
Piotr

Quoted 62 lines

Regards,
Christian.

Quoted 58 lines

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +0 -0

  	WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
  	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +4 -1

index 3b29aaba783a..7daf4e92aa8b 100644
@@ -250,6 +250,7 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
  {
  	uint64_t offset;
  	uint32_t size;
+	const struct common_firmware_header *hdr;
  	/* programm memory controller bits 0-27 */
  	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

@@ -258,7 +259,9 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
  			upper_32_bits(adev->uvd.gpu_addr));
  	offset = AMDGPU_UVD_FIRMWARE_OFFSET;
-	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
+	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) -
+	       AMDGPU_UVD_FIRMWARE_OFFSET;
  	WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
  	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +4 -1

index 0c01825a8b9e..7c510aed7a1b 100644
@@ -595,6 +595,7 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
  {
  	uint64_t offset;
  	uint32_t size;
+	const struct common_firmware_header *hdr;
  	/* programm memory controller bits 0-27 */
  	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

@@ -603,7 +604,9 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
  			upper_32_bits(adev->uvd.gpu_addr));
  	offset = AMDGPU_UVD_FIRMWARE_OFFSET;
-	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
+	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) -
+	       AMDGPU_UVD_FIRMWARE_OFFSET;
  	WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
  	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +6 -1

index 7b77339feb1a..b015cfd5067d 100644
@@ -616,8 +616,13 @@ static int uvd_v7_0_resume(void *handle)
   */
  static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
  {
-	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
+	uint32_t size;
  	uint32_t offset;
+	const struct common_firmware_header *hdr;
+
+	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) -
+	       AMDGPU_UVD_FIRMWARE_OFFSET;

Quoted 8 lines

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c static int uvd_v7_0_resume(void *handle) · line 628
Quoted 2 lines
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +0 -0
  	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
  		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
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Quoted 4 lines

_______________________________________________
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[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx