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ARM: dts: aspeed: quanta: add i2cmux for frus

PATCH In review Patrick Venture 2 participants 3 messages Nov 27, 2017 – Dec 8, 2017

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Device tree bindings Arm/Aspeed machine support
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Patrick Venture

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#0 lore raw

PATCH 1/1 ARM: dts: aspeed: quanta: add i2cmux for frus

The memory riser frus on the board are controlled
by a gpio mux.

Signed-off-by Patrick Venture <[email protected]>
---
 arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 93 +++++++++++++++++++++-------
 1 file changed, 69 insertions(+), 24 deletions(-)
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +69 -24
index 42b1d8007316..b93b29191960 100644
@@ -119,6 +119,75 @@
 			<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
 			<&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>;
 	};
+
+	i2cmux@1 {
+		compatible = "i2c-mux-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mux-gpios = <&sgpio 10 GPIO_ACTIVE_HIGH>;
+		i2c-parent = <&i2c1>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Memory Riser 1 FRU */
+			eeprom@50 {
+				compatible = "atmel,24c02";
+				reg = <0x50>;
+			};
+
+			/* Memory Riser 2 FRU */
+			eeprom@51 {
+				compatible = "atmel,24c02";
+				reg = <0x51>;
+			};
+
+			/* Memory Riser 3 FRU */
+			eeprom@52 {
+				compatible = "atmel,24c02";
+				reg = <0x52>;
+			};
+
+			/* Memory Riser 4 FRU */
+			eeprom@53 {
+				compatible = "atmel,24c02";
+				reg = <0x53>;
+			};
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Memory Riser 5 FRU */
+			eeprom@50 {
+				compatible = "atmel,24c02";
+				reg = <0x50>;
+			};
+
+			/* Memory Riser 6 FRU */
+			eeprom@51 {
+				compatible = "atmel,24c02";
+				reg = <0x51>;
+			};
+
+			/* Memory Riser 7 FRU */
+			eeprom@52 {
+				compatible = "atmel,24c02";
+				reg = <0x52>;
+			};
+
+			/* Memory Riser 8 FRU */
+			eeprom@53 {
+				compatible = "atmel,24c02";
+				reg = <0x53>;
+			};
+		};
+	};
 };
 
 &fmc {

@@ -196,30 +265,6 @@
 		reg = <0x4f>;
 	};
 
-	/* Memory Riser 1/5 FRU */
-	eeprom@50 {
-		compatible = "atmel,24c02";
-		reg = <0x50>;
-	};
-
-	/* Memory Riser 2/6 FRU */
-	eeprom@51 {
-		compatible = "atmel,24c02";
-		reg = <0x51>;
-	};
-
-	/* Memory Riser 3/7 FRU */
-	eeprom@52 {
-		compatible = "atmel,24c02";
-		reg = <0x52>;
-	};
-
-	/* Memory Riser 4/8 FRU */
-	eeprom@53 {
-		compatible = "atmel,24c02";
-		reg = <0x53>;
-	};
-
 	/* Baseboard FRU */
 	eeprom@54 {
 		compatible = "atmel,24c64";
Signature · 1 line
2.15.0.417.g466bffb3ac-goog
maintainer
#1 lore raw
Quoted 13 lines · Patrick Venture

The memory riser frus on the board are controlled
by a gpio mux.

Signed-off-by Patrick Venture <[email protected]>
---
 arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 93 +++++++++++++++++++++-------
 1 file changed, 69 insertions(+), 24 deletions(-)
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +0 -0
index 42b1d8007316..b93b29191960 100644

arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts line 123

Quoted 5 lines
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +2 -0
@@ -119,6 +119,75 @@
                        <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
                        <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>;
        };
+
+       i2cmux@1 {

When you stick a unit name on a node, it is supposed to have a matching reg property. We don't have a reg property here, so we shouldn't have the number. This matches what the i2c-mux-gpio bindings describe.

I dropped the '@1' for you when applying. It's in dev-4.10 now.

Cheers,

Joel

Quoted 3 lines
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +3 -0
+               compatible = "i2c-mux-gpio";
+               #address-cells = <1>;
+               #size-cells = <0>;
author
#2 lore raw

Thanks. I added the @1 from reading another device-tree that used this not super commonly used node. But your explanation makes perfect sense.

Patrick

Quoted 34 lines · Joel Stanley
Quoted 13 lines · Patrick Venture

The memory riser frus on the board are controlled
by a gpio mux.

Signed-off-by Patrick Venture <[email protected]>
---
 arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 93 +++++++++++++++++++++-------
 1 file changed, 69 insertions(+), 24 deletions(-)
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +0 -0
index 42b1d8007316..b93b29191960 100644

arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts line 123

Quoted 5 lines
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +2 -0
@@ -119,6 +119,75 @@
                        <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
                        <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>;
        };
+
+       i2cmux@1 {

When you stick a unit name on a node, it is supposed to have a matching reg property. We don't have a reg property here, so we shouldn't have the number. This matches what the i2c-mux-gpio bindings describe.

I dropped the '@1' for you when applying. It's in dev-4.10 now.

Cheers,

Joel

Quoted 3 lines
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +3 -0
+               compatible = "i2c-mux-gpio";
+               #address-cells = <1>;
+               #size-cells = <0>;