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ARM: dts: introduce Compulab IoT Gateway

PATCH In review [email protected] 2 participants 19 messages Nov 30, 2017 – Dec 5, 2017

Subsystems (4)
Device tree bindings Arm i.MX and Layerscape PCI Arm and arm64 SoC sub-architectures (common parts)
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[email protected]

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#0 lore raw

cover ARM: dts: introduce Compulab IoT Gateway

From: Tyler Baker <[email protected]>

The Compulab IoT Gateway is based on an NXP i.MX7D, dual core Cortex-A7 clocking at 1GHz. It supports up to 2GB of DDR3, and 32GB of eMMC flash. Onboard, there are two gigabit ethernet controllers, 4 x USB2, RS485, and CAN.

It uses the same SoM as the cl-som-imx7, but includes a baseboard with additional I/O.

Compulab has provided patches for this platform based on v4.1. I've used these patches as reference to get things working on tip.

The entire series is based on v4.15-rc1.

Tyler Baker (8):
ARM: dts: imx7d-sbc-iot: add initial iot gateway dts
ARM: dts: imx7: build imx7d-sbc-iot-imx7 dtb
ARM: dts: imx7d-cl-som: add nodes for usbh, and usbotg2
ARM: dts: imx7s: add dma support
ARM: dts: imx7s: add node and supplies for vdd1p2
ARM: dts: imx7d-sbc-iot: enable PCIe peripheral
ARM: dts: imx7s: add usb hsic phy domain
PCIe: imx6: imx7d: add support for phy refclk source

 arch/arm/boot/dts/Makefile               |   1 +
 arch/arm/boot/dts/imx7d-cl-som-imx7.dts  |  36 ++++-
 arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts | 252 +++++++++++++++++++++++++++++++
 arch/arm/boot/dts/imx7s.dtsi             |  29 +++-
 drivers/pci/dwc/pci-imx6.c               |   8 +-
 5 files changed, 316 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts
Signature · 1 line
2.9.3
author
#1 lore raw

PATCH 1/8 ARM: dts: imx7d-sbc-iot: add initial iot gateway dts

From: Tyler Baker <[email protected]>

The Compulab IoT Gateway is based on an NXP i.MX7D, dual core Cortex-A7 clocking at 1GHz. It supports up to 2GB of DDR3, and 32GB of eMMC flash. Onboard, there are two gigabit ethernet controllers, 4 x USB2, RS485, and CAN.

This platform is based on the imx7d-cl-som-imx7 module but includes a baseboard with additional peripherals which is what this device tree is meant to describe.

This work has been derrived from the Compulab Linux sources based on v4.1.

Signed-off-by Tyler Baker <[email protected]>
Signed-off-by Ilya Ledvich <[email protected]>
---
 arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts | 238 +++++++++++++++++++++++++++++++
 1 file changed, 238 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts
arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts new file +238 -0
new file mode 100644
index 0000000..50dfdd3
@@ -0,0 +1,238 @@
+/*
+ * Support for CompuLab SBC-IOT-iMX7 Single Board Computer
+ *
+ * Copyright (C) 2017 CompuLab Ltd. - http://www.compulab.co.il/
+ * Author: Ilya Ledvich <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx7d-cl-som-imx7.dts"
+
+/ {
+	model = "CompuLab SBC-IOT-iMX7";
+	compatible = "compulab,sbc-iot-imx7", "compulab,cl-som-imx7", "fsl,imx7d";
+
+	aliases {
+		lcdif = &lcdif;
+	};
+};
+
+&ecspi3 {
+	fsl,spi-num-chipselects = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
+	cs-gpios = <&gpio4 11 0>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	status = "okay";
+
+	eeprom_iot at 54 {
+		compatible = "atmel,24c08";
+		reg = <0x54>;
+		pagesize = <16>;
+	};
+
+	dvicape at 39 {
+		compatible = "sil164_simple";
+		reg = <0x39>;
+	};
+};
+
+&iomuxc {
+	pinctrl_xpen: xpengrp {
+		fsl,pins = <
+			MX7D_PAD_LCD_DATA13__GPIO3_IO18		0x34 /* P7-4 - gpio82 */
+			MX7D_PAD_LCD_DATA12__GPIO3_IO17		0x34 /* P7-5 - gpio81 */
+		>;
+	};
+
+	pinctrl_ecspi3: ecspi3grp {
+		fsl,pins = <
+			MX7D_PAD_I2C1_SDA__ECSPI3_MOSI		0xf /* P7-8 */
+			MX7D_PAD_I2C1_SCL__ECSPI3_MISO		0xf /* P7-7 */
+			MX7D_PAD_I2C2_SCL__ECSPI3_SCLK		0xf /* P7-6 */
+		>;
+	};
+
+	pinctrl_ecspi3_cs: ecspi3_cs_grp {
+		fsl,pins = <
+			MX7D_PAD_I2C2_SDA__GPIO4_IO11		0x34 /* P7-9 */
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX7D_PAD_GPIO1_IO09__I2C3_SDA		0x4000000f /* P7-3 */
+			MX7D_PAD_GPIO1_IO08__I2C3_SCL		0x4000000f /* P7-2 */
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX7D_PAD_GPIO1_IO11__I2C4_SDA		0x4000000f
+			MX7D_PAD_GPIO1_IO10__I2C4_SCL		0x4000000f
+		>;
+	};
+
+	pinctrl_lcdif_dat: lcdifdatgrp {
+		fsl,pins = <
+			MX7D_PAD_LCD_DATA00__LCD_DATA0		0x79
+			MX7D_PAD_LCD_DATA01__LCD_DATA1		0x79
+			MX7D_PAD_LCD_DATA02__LCD_DATA2		0x79
+			MX7D_PAD_LCD_DATA03__LCD_DATA3		0x79
+			MX7D_PAD_EPDC_DATA04__LCD_DATA4		0x79
+			MX7D_PAD_EPDC_DATA05__LCD_DATA5		0x79
+			MX7D_PAD_EPDC_DATA06__LCD_DATA6		0x79
+			MX7D_PAD_EPDC_DATA07__LCD_DATA7		0x79
+			MX7D_PAD_EPDC_DATA08__LCD_DATA8		0x79
+			MX7D_PAD_EPDC_DATA09__LCD_DATA9		0x79
+			MX7D_PAD_EPDC_DATA10__LCD_DATA10	0x79
+			MX7D_PAD_EPDC_DATA11__LCD_DATA11	0x79
+			MX7D_PAD_EPDC_DATA12__LCD_DATA12	0x79
+			MX7D_PAD_EPDC_DATA13__LCD_DATA13	0x79
+			MX7D_PAD_EPDC_DATA14__LCD_DATA14	0x79
+			MX7D_PAD_EPDC_DATA15__LCD_DATA15	0x79
+			MX7D_PAD_LCD_DATA16__LCD_DATA16		0x79
+			MX7D_PAD_LCD_DATA17__LCD_DATA17		0x79
+			MX7D_PAD_LCD_DATA18__LCD_DATA18		0x79
+			MX7D_PAD_LCD_DATA19__LCD_DATA19		0x79
+			MX7D_PAD_LCD_DATA20__LCD_DATA20		0x79
+			MX7D_PAD_LCD_DATA21__LCD_DATA21		0x79
+			MX7D_PAD_LCD_DATA22__LCD_DATA22		0x79
+			MX7D_PAD_LCD_DATA23__LCD_DATA23		0x79
+		>;
+	};
+
+	pinctrl_lcdif_ctrl: lcdifctrlgrp {
+		fsl,pins = <
+			MX7D_PAD_EPDC_DATA00__LCD_CLK		0x79
+			MX7D_PAD_EPDC_DATA01__LCD_ENABLE	0x79
+			MX7D_PAD_EPDC_DATA02__LCD_VSYNC		0x79
+			MX7D_PAD_EPDC_DATA03__LCD_HSYNC		0x79
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX7D_PAD_LCD_ENABLE__UART2_DCE_TX	0x79 /* P7-12 */
+			MX7D_PAD_LCD_CLK__UART2_DCE_RX		0x79 /* P7-13 */
+			MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS	0x79 /* P7-11 */
+			MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS	0x79 /* P7-10 */
+		>;
+	};
+
+	pinctrl_uart5: uart5grp {
+		fsl,pins = <
+			MX7D_PAD_I2C4_SDA__UART5_DCE_TX		0x79 /* RS232-TX */
+			MX7D_PAD_I2C4_SCL__UART5_DCE_RX		0x79 /* RS232-RX */
+			MX7D_PAD_I2C3_SDA__UART5_DCE_RTS	0x79 /* RS232-RTS */
+			MX7D_PAD_I2C3_SCL__UART5_DCE_CTS	0x79 /* RS232-CTS */
+		>;
+	};
+
+	pinctrl_uart7: uart7grp {
+		fsl,pins = <
+			MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX	0x79 /* R485-TX */
+			MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX	0x79 /* R485-RX */
+			MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS	0x79 /* R485-CTS */
+			MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS	0x79 /* R485-TTS */
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX7D_PAD_SD1_CMD__SD1_CMD		0x59
+			MX7D_PAD_SD1_CLK__SD1_CLK		0x19
+			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
+			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
+			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
+			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
+			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x59 /* CD */
+		>;
+	};
+};
+
+&lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_dat
+		     &pinctrl_lcdif_ctrl>;
+	display = <&display0>;
+	status = "okay";
+
+	display0: display {
+		bits-per-pixel = <24>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: dvi {
+				/* 1024x768p60 */
+				clock-frequency = <65000000>;
+				hactive = <1024>;
+				hfront-porch = <40>;
+				hback-porch = <220>;
+				hsync-len = <60>;
+				vactive = <768>;
+				vfront-porch = <7>;
+				vback-porch = <21>;
+				vsync-len = <10>;
+
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+	fsl,uart-has-rtscts;
+	status = "okay";
+};
+
+&uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart5>;
+	assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+	fsl,uart-has-rtscts;
+	status = "okay";
+};
+
+&uart7 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart7>;
+	assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+	fsl,uart-has-rtscts;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+	enable-sdio-wakeup;
+	status = "okay";
+};
Signature · 1 line
2.9.3
reviewer
#2 lore raw

Re: [PATCH 1/8] ARM: dts: imx7d-sbc-iot: add initial iot gateway dts

Quoted 2 lines · On Thu, Nov 30, 2017 at 6:14 PM, <[email protected]> wrote:

+&ecspi3 {
+ fsl,spi-num-chipselects = <1>;

Please remove this property. It is no longer used.

arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts line 51

Quoted 2 lines
arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts new file +2 -0
+       dvicape at 39 {
+               compatible = "sil164_simple";

This compatible string does not exist.

Quoted 19 lines

+&lcdif {

arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts new file +18 -0
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lcdif_dat
+                    &pinctrl_lcdif_ctrl>;
+       display = <&display0>;
+       status = "okay";
+
+       display0: display {
+               bits-per-pixel = <24>;
+               bus-width = <24>;
+
+               display-timings {
+                       native-mode = <&timing0>;
+                       timing0: dvi {
+                               /* 1024x768p60 */
+                               clock-frequency = <65000000>;
+                               hactive = <1024>;
+                               hfront-porch = <40>;
+                               hback-porch = <220>;

arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts line 198

Quoted 10 lines
arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts new file +10 -0
+                               hsync-len = <60>;
+                               vactive = <768>;
+                               vfront-porch = <7>;
+                               vback-porch = <21>;
+                               vsync-len = <10>;
+
+                               hsync-active = <0>;
+                               vsync-active = <0>;
+                               de-active = <1>;
+                               pixelclk-active = <0>;

Which panel is this? Could you use a simple panel driver compatible string instead?

arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts line 209

Quoted 11 lines
arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts new file +11 -0
+                       };
+               };
+       };
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2>;
+       assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
+       assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+       fsl,uart-has-rtscts;

Please use 'uart-has-rtscts' instead.

arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts line 218

Quoted 9 lines
arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts new file +9 -0
+       status = "okay";
+};
+
+&uart5 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart5>;
+       assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
+       assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+       fsl,uart-has-rtscts;

Ditto.

arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts line 227

Quoted 9 lines
arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts new file +9 -0
+       status = "okay";
+};
+
+&uart7 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart7>;
+       assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
+       assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+       fsl,uart-has-rtscts;

Ditto

author
#3 lore raw

Re: [PATCH 1/8] ARM: dts: imx7d-sbc-iot: add initial iot gateway dts

Quoted 6 lines · Fabio Estevam
Quoted 2 lines · On Thu, Nov 30, 2017 at 6:14 PM, <[email protected]> wrote:

+&ecspi3 {
+ fsl,spi-num-chipselects = <1>;

Please remove this property. It is no longer used.

Ack.

Quoted 6 lines

arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts line 51

Quoted 4 lines
arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts new file +2 -0
+       dvicape at 39 {
+               compatible = "sil164_simple";

This compatible string does not exist.

I'm going to drop this, and address the display hardware it in a later series.

Quoted 27 lines
Quoted 27 lines

+&lcdif {

arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts new file +23 -0
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lcdif_dat
+                    &pinctrl_lcdif_ctrl>;
+       display = <&display0>;
+       status = "okay";
+
+       display0: display {
+               bits-per-pixel = <24>;
+               bus-width = <24>;
+
+               display-timings {
+                       native-mode = <&timing0>;
+                       timing0: dvi {
+                               /* 1024x768p60 */
+                               clock-frequency = <65000000>;
+                               hactive = <1024>;
+                               hfront-porch = <40>;
+                               hback-porch = <220>;
+                               hsync-len = <60>;
+                               vactive = <768>;
+                               vfront-porch = <7>;
+                               vback-porch = <21>;
+                               vsync-len = <10>;
Quoted 8 lines

arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts line 198

Quoted 5 lines
arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts new file +5 -0
+
+                               hsync-active = <0>;
+                               vsync-active = <0>;
+                               de-active = <1>;
+                               pixelclk-active = <0>;

Which panel is this? Could you use a simple panel driver compatible string instead?

I'll switch to a simple panel driver and do some more testing. Will submit a follow up series to address the LCD panel and dvi cape.

Quoted 15 lines

arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts line 209

Quoted 13 lines
arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts new file +11 -0
+                       };
+               };
+       };
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2>;
+       assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
+       assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+       fsl,uart-has-rtscts;

Please use 'uart-has-rtscts' instead.

Ack.

Quoted 12 lines

arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts line 218

Quoted 10 lines
arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts new file +9 -0
+       status = "okay";
+};
+
+&uart5 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart5>;
+       assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
+       assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+       fsl,uart-has-rtscts;

Ditto.

Ack.

Quoted 12 lines

arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts line 227

Quoted 10 lines
arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts new file +9 -0
+       status = "okay";
+};
+
+&uart7 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart7>;
+       assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
+       assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+       fsl,uart-has-rtscts;

Ditto

Ack.

author
#4 lore raw

PATCH 2/8 ARM: dts: imx7: build imx7d-sbc-iot-imx7 dtb

In reply to [email protected]

From: Tyler Baker <[email protected]>

Build the imx7d-sbc-iot-imx7 device tree blob.

Signed-off-by Tyler Baker <[email protected]>
---
 arch/arm/boot/dts/Makefile | 1 +
 1 file changed, 1 insertion(+)
arch/arm/boot/dts/Makefile +1 -0
index d0381e9..0334137 100644
@@ -515,6 +515,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
 	imx7d-nitrogen7.dtb \
 	imx7d-pico.dtb \
 	imx7d-sbc-imx7.dtb \
+	imx7d-sbc-iot-imx7.dtb \
 	imx7d-sdb.dtb \
 	imx7d-sdb-sht11.dtb \
 	imx7s-colibri-eval-v3.dtb \
Signature · 1 line
2.9.3
reviewer
#5 lore raw

Re: [PATCH 2/8] ARM: dts: imx7: build imx7d-sbc-iot-imx7 dtb

Quoted 14 lines · On Thu, Nov 30, 2017 at 6:14 PM, <[email protected]> wrote:

From: Tyler Baker <[email protected]>

Build the imx7d-sbc-iot-imx7 device tree blob.

Signed-off-by Tyler Baker <[email protected]>
---
 arch/arm/boot/dts/Makefile | 1 +
 1 file changed, 1 insertion(+)
arch/arm/boot/dts/Makefile +0 -0
index d0381e9..0334137 100644

arch/arm/boot/dts/Makefile dtb-$(CONFIG_SOC_IMX7D) += \ · line 518

Quoted 4 lines
arch/arm/boot/dts/Makefile +1 -0
@@ -515,6 +515,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
        imx7d-nitrogen7.dtb \
        imx7d-pico.dtb \
        imx7d-sbc-imx7.dtb \
+       imx7d-sbc-iot-imx7.dtb \

This could be part of the previous patch that introduces the dts.

author
#6 lore raw

Re: [PATCH 2/8] ARM: dts: imx7: build imx7d-sbc-iot-imx7 dtb

Quoted 10 lines · Fabio Estevam
Quoted 9 lines · On Thu, Nov 30, 2017 at 6:14 PM, <[email protected]> wrote:

From: Tyler Baker <[email protected]>

Build the imx7d-sbc-iot-imx7 device tree blob.

Signed-off-by Tyler Baker <[email protected]>
---
 arch/arm/boot/dts/Makefile | 1 +
 1 file changed, 1 insertion(+)
Quoted 11 lines

arch/arm/boot/dts/Makefile dtb-$(CONFIG_SOC_IMX7D) += \ · line 518

Quoted 9 lines
arch/arm/boot/dts/Makefile +1 -0
index d0381e9..0334137 100644
@@ -515,6 +515,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
        imx7d-nitrogen7.dtb \
        imx7d-pico.dtb \
        imx7d-sbc-imx7.dtb \
+       imx7d-sbc-iot-imx7.dtb \

This could be part of the previous patch that introduces the dts.

Ok will do.

author
#7 lore raw

PATCH 3/8 ARM: dts: imx7d-cl-som: add nodes for usbh, and usbotg2

In reply to [email protected]

From: Tyler Baker <[email protected]>

Add device tree nodes for the USB hub, and USB OTG. i2c2 on this platform supports low state retention power state so lets use it.

Signed-off-by Tyler Baker <[email protected]>
---
 arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 36 +++++++++++++++++++++++++--------
 1 file changed, 28 insertions(+), 8 deletions(-)
arch/arm/boot/dts/imx7d-cl-som-imx7.dts +28 -8
index ae45af1..a9f690b 100644
@@ -30,6 +30,16 @@
 		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 	};
+
+	reg_usbh_nreset: regulator at 4 {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_host_nreset";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pca9555 6 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+	};
 };
 
 &cpu0 {

@@ -199,6 +209,16 @@
 	status = "okay";
 };
 
+&usbotg2 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbh {
+	vbus-supply = <&reg_usbh_nreset>;
+	status = "okay";
+};
+
 &usdhc3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc3>;

@@ -247,13 +267,6 @@
 		>;
 	};
 
-	pinctrl_i2c2: i2c2grp {
-		fsl,pins = <
-			MX7D_PAD_I2C2_SDA__I2C2_SDA		0x4000007f
-			MX7D_PAD_I2C2_SCL__I2C2_SCL		0x4000007f
-		>;
-	};
-
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
 			MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX	0x79

@@ -284,4 +297,11 @@
 			MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5	0x14 /* OTG PWREN */
 		>;
 	};
-};
\ No newline at end of file
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA		0x4000000f
+			MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL		0x4000000f
+		>;
+	};
+};
Signature · 1 line
2.9.3
reviewer
#8 lore raw

Re: [PATCH 3/8] ARM: dts: imx7d-cl-som: add nodes for usbh, and usbotg2

Quoted 15 lines · On Thu, Nov 30, 2017 at 6:14 PM, <[email protected]> wrote:

From: Tyler Baker <[email protected]>

Add device tree nodes for the USB hub, and USB OTG. i2c2 on this platform supports low state retention power state so lets use it.

Signed-off-by Tyler Baker <[email protected]>
---
 arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 36 +++++++++++++++++++++++++--------
 1 file changed, 28 insertions(+), 8 deletions(-)
arch/arm/boot/dts/imx7d-cl-som-imx7.dts +0 -0
index ae45af1..a9f690b 100644

arch/arm/boot/dts/imx7d-cl-som-imx7.dts line 34

Quoted 5 lines
arch/arm/boot/dts/imx7d-cl-som-imx7.dts +2 -0
@@ -30,6 +30,16 @@
                gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
                enable-active-high;
        };
+
+       reg_usbh_nreset: regulator at 4 {

You should not use @4. Please make sure that regulators are not used inside simple-bus.

arch/arm/boot/dts/imx7d-cl-som-imx7.dts line 287

Quoted 10 lines
arch/arm/boot/dts/imx7d-cl-som-imx7.dts +0 -2
-
        pinctrl_uart1: uart1grp {
                fsl,pins = <
                        MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79

@@ -284,4 +297,11 @@
                        MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5     0x14 /* OTG PWREN */
                >;
        };
-};
\ No newline at end of file

This text here looks strange :-)

Quoted 16 lines
arch/arm/boot/dts/imx7d-cl-som-imx7.dts +8 -1
+
+       pinctrl_i2c2: i2c2grp {
+               fsl,pins = <
+                       MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA              0x4000000f
+                       MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL              0x4000000f
+               >;
+       };
+};
--

2.9.3

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linux-arm-kernel at lists.infradead.org
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author
#9 lore raw

Re: [PATCH 3/8] ARM: dts: imx7d-cl-som: add nodes for usbh, and usbotg2

Quoted 11 lines · Fabio Estevam
Quoted 10 lines · On Thu, Nov 30, 2017 at 6:14 PM, <[email protected]> wrote:

From: Tyler Baker <[email protected]>

Add device tree nodes for the USB hub, and USB OTG. i2c2 on this platform supports low state retention power state so lets use it.

Signed-off-by Tyler Baker <[email protected]>
---
 arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 36 +++++++++++++++++++++++++--------
 1 file changed, 28 insertions(+), 8 deletions(-)
Quoted 13 lines

arch/arm/boot/dts/imx7d-cl-som-imx7.dts line 34

Quoted 10 lines
arch/arm/boot/dts/imx7d-cl-som-imx7.dts +2 -0
index ae45af1..a9f690b 100644
@@ -30,6 +30,16 @@
                gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
                enable-active-high;
        };
+
+       reg_usbh_nreset: regulator at 4 {

You should not use @4. Please make sure that regulators are not used inside simple-bus.

Good catch, will fix.

Quoted 4 lines
Quoted 4 lines
arch/arm/boot/dts/imx7d-cl-som-imx7.dts +0 -1
-
        pinctrl_uart1: uart1grp {
                fsl,pins = <
                        MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
Quoted 8 lines

arch/arm/boot/dts/imx7d-cl-som-imx7.dts line 287

Quoted 6 lines
arch/arm/boot/dts/imx7d-cl-som-imx7.dts +0 -1
@@ -284,4 +297,11 @@
                        MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5     0x14 /* OTG PWREN */
                >;
        };
-};
\ No newline at end of file

This text here looks strange :-)

Indeed, I'll scrub it.

author
#10 lore raw

PATCH 4/8 ARM: dts: imx7s: add dma support

In reply to [email protected]

From: Tyler Baker <[email protected]>

Enable dma on all SPI and UART interfaces.

Signed-off-by Tyler Baker <[email protected]>
---
 arch/arm/boot/dts/imx7s.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)
arch/arm/boot/dts/imx7s.dtsi +6 -0
index 82ad26e..7b85659 100644
@@ -700,6 +700,8 @@
 				clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
 					<&clks IMX7D_ECSPI1_ROOT_CLK>;
 				clock-names = "ipg", "per";
+				dmas = <&sdma 0 7 1>, <&sdma 1 7 2>;
+				dma-names = "rx", "tx";
 				status = "disabled";
 			};
 

@@ -712,6 +714,8 @@
 				clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
 					<&clks IMX7D_ECSPI2_ROOT_CLK>;
 				clock-names = "ipg", "per";
+				dmas = <&sdma 2 7 1>, <&sdma 3 7 2>;
+				dma-names = "rx", "tx";
 				status = "disabled";
 			};
 

@@ -724,6 +728,8 @@
 				clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
 					<&clks IMX7D_ECSPI3_ROOT_CLK>;
 				clock-names = "ipg", "per";
+				dmas = <&sdma 4 7 1>, <&sdma 5 7 2>;
+				dma-names = "rx", "tx";
 				status = "disabled";
 			};
Signature · 1 line
2.9.3
reviewer
#11 lore raw

Re: [PATCH 4/8] ARM: dts: imx7s: add dma support

Quoted 3 lines · On Thu, Nov 30, 2017 at 6:14 PM, <[email protected]> wrote:

From: Tyler Baker <[email protected]>

Enable dma on all SPI and UART interfaces.

You only touched SPI ports, not the UART.

author
#12 lore raw

Re: [PATCH 4/8] ARM: dts: imx7s: add dma support

Quoted 6 lines · Fabio Estevam
Quoted 3 lines · On Thu, Nov 30, 2017 at 6:14 PM, <[email protected]> wrote:

From: Tyler Baker <[email protected]>

Enable dma on all SPI and UART interfaces.

You only touched SPI ports, not the UART.

I'll update the commit message, thanks.

author
#13 lore raw

PATCH 5/8 ARM: dts: imx7s: add node and supplies for vdd1p2

In reply to [email protected]

From: Tyler Baker <[email protected]>

Add the regulator nodes and supplies for vdd1p2. This regulator is used to power the GPC and USB HSIC PHY.

Signed-off-by Tyler Baker <[email protected]>
---
 arch/arm/boot/dts/imx7s.dtsi | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)
arch/arm/boot/dts/imx7s.dtsi +16 -1
index 7b85659..151ab34 100644
@@ -522,6 +522,20 @@
 					anatop-max-voltage = <1200000>;
 					anatop-enable-bit = <0>;
 				};
+
+				reg_1p2: regulator-vdd1p2 at 220 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vdd1p2";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1300000>;
+					anatop-reg-offset = <0x220>;
+					anatop-vol-bit-shift = <8>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <8>;
+					anatop-min-voltage = <1100000>;
+					anatop-max-voltage = <1300000>;
+					anatop-enable-bit = <0>;
+				};
 			};
 
 			snvs: snvs at 30370000 {

@@ -578,7 +592,7 @@
 				#interrupt-cells = <3>;
 				interrupt-parent = <&intc>;
 				#power-domain-cells = <1>;
-
+				vcc-supply = <&reg_1p2>;
 				pgc {
 					#address-cells = <1>;
 					#size-cells = <0>;

@@ -961,6 +975,7 @@
 				compatible = "usb-nop-xceiv";
 				clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
 				clock-names = "main_clk";
+				vcc-supply = <&reg_1p2>;
 			};
 
 			usdhc1: usdhc at 30b40000 {
Signature · 1 line
2.9.3
author
#14 lore raw

PATCH 6/8 ARM: dts: imx7d-sbc-iot: enable PCIe peripheral

In reply to [email protected]

From: Tyler Baker <[email protected]>

Add a PCIe device tree node to enable PCIe support.

Signed-off-by Tyler Baker <[email protected]>
---
 arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts +14 -0
index 50dfdd3..7b21366 100644
@@ -127,6 +127,12 @@
 		>;
 	};
 
+	pinctrl_pcie: pciegrp {
+		fsl,pins = <
+			MX7D_PAD_EPDC_BDR1__GPIO2_IO29		0x34 /* PCIe RST */
+		>;
+	};
+
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
 			MX7D_PAD_LCD_ENABLE__UART2_DCE_TX	0x79 /* P7-12 */

@@ -201,6 +207,14 @@
 	};
 };
 
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>;
+	phy-ref-clk = <1>;
+	status = "okay";
+};
+
 &uart2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart2>;
Signature · 1 line
2.9.3
author
#15 lore raw

PATCH 7/8 ARM: dts: imx7s: add usb hsic phy domain

In reply to [email protected]

From: Tyler Baker <[email protected]>

The GPCv2 driver should control the MIPI, PCIe,
and USB HSIC PHY regulators. Add the USB HSIC
power domain to the GPC node.

Signed-off-by Tyler Baker <[email protected]>
---
 arch/arm/boot/dts/imx7s.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)
arch/arm/boot/dts/imx7s.dtsi +6 -0
index 151ab34..9626a3e 100644
@@ -602,6 +602,12 @@
 						reg = <IMX7_POWER_DOMAIN_PCIE_PHY>;
 						power-supply = <&reg_1p0d>;
 					};
+					pgc_usb_hsic_phy: pgc-usb-hsic-phy-domain {
+						#power-domain-cells = <0>;
+
+						reg = <IMX7_POWER_DOMAIN_USB_HSIC_PHY>;
+						power-supply = <&reg_1p2>;
+					};
 				};
 			};
 		};
Signature · 1 line
2.9.3
author
#16 lore raw

PATCH 8/8 PCIe: imx6: imx7d: add support for phy refclk source

In reply to [email protected]

From: Tyler Baker <[email protected]>

In the i.MX7D the PCIe PHY can use either externel oscillator or internal PLL as a reference clock source.
Add support for the PHY Reference Clock source including device tree property phy-ref-clk.
External oscillator is used as a default reference clock source.

Signed-off-by Tyler Baker <[email protected]>
Signed-off-by Ilya Ledvich <[email protected]>
---
 drivers/pci/dwc/pci-imx6.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
drivers/pci/dwc/pci-imx6.c +7 -1
index b734835..e935db4 100644
@@ -45,6 +45,7 @@ enum imx6_pcie_variants {
 struct imx6_pcie {
 	struct dw_pcie		*pci;
 	int			reset_gpio;
+	u32			phy_refclk;
 	bool			gpio_active_high;
 	struct clk		*pcie_bus;
 	struct clk		*pcie_phy;

@@ -474,7 +475,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
 	switch (imx6_pcie->variant) {
 	case IMX7D:
 		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
-				   IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
+				   BIT(5), imx6_pcie->phy_refclk ? BIT(5) : 0);
 		break;
 	case IMX6SX:
 		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,

@@ -733,6 +734,11 @@ static int imx6_pcie_probe(struct platform_device *pdev)
 	if (IS_ERR(pci->dbi_base))
 		return PTR_ERR(pci->dbi_base);
 
+	/* Fetch PHY Reference Clock */
+	if (of_property_read_u32(node, "phy-ref-clk", &imx6_pcie->phy_refclk))
+		imx6_pcie->phy_refclk = 0;
+	pr_info("%s: phy_refclk = %d\n", __func__, imx6_pcie->phy_refclk);
+
 	/* Fetch GPIOs */
 	imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
 	imx6_pcie->gpio_active_high = of_property_read_bool(node,
Signature · 1 line
2.9.3
reviewer
#17 lore raw

Re: [PATCH 8/8] PCIe: imx6: imx7d: add support for phy refclk source

Quoted 10 lines · On Thu, Nov 30, 2017 at 6:14 PM, <[email protected]> wrote:

From: Tyler Baker <[email protected]>

In the i.MX7D the PCIe PHY can use either externel oscillator or internal PLL as a reference clock source.
Add support for the PHY Reference Clock source including device tree property phy-ref-clk.
External oscillator is used as a default reference clock source.

Signed-off-by Tyler Baker <[email protected]>
Signed-off-by Ilya Ledvich <[email protected]>

Please submit this one to the PCI list and PCI maintainers.

As you are adding a new property you should update Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt.

drivers/pci/dwc/pci-imx6.c enum imx6_pcie_variants { · line 48

Quoted 13 lines
---
 drivers/pci/dwc/pci-imx6.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
drivers/pci/dwc/pci-imx6.c +1 -0
index b734835..e935db4 100644
@@ -45,6 +45,7 @@ enum imx6_pcie_variants {
 struct imx6_pcie {
        struct dw_pcie          *pci;
        int                     reset_gpio;
+       u32                     phy_refclk;

Could this be bool instead?

Quoted 13 lines
drivers/pci/dwc/pci-imx6.c +1 -1
        bool                    gpio_active_high;
        struct clk              *pcie_bus;
        struct clk              *pcie_phy;

@@ -474,7 +475,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
        switch (imx6_pcie->variant) {
        case IMX7D:
                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
-                                  IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
+                                  BIT(5), imx6_pcie->phy_refclk ? BIT(5) : 0);
                break;
        case IMX6SX:
                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,

drivers/pci/dwc/pci-imx6.c static int imx6_pcie_probe(struct platform_device *pdev) · line 738

Quoted 5 lines
drivers/pci/dwc/pci-imx6.c +2 -0
@@ -733,6 +734,11 @@ static int imx6_pcie_probe(struct platform_device *pdev)
        if (IS_ERR(pci->dbi_base))
                return PTR_ERR(pci->dbi_base);
 
+       /* Fetch PHY Reference Clock */
+       if (of_property_read_u32(node, "phy-ref-clk", &imx6_pcie->phy_refclk))

You could use of_property_read_bool instead.

author
#18 lore raw

Re: [PATCH 8/8] PCIe: imx6: imx7d: add support for phy refclk source

Quoted 9 lines · Fabio Estevam
Quoted 8 lines · On Thu, Nov 30, 2017 at 6:14 PM, <[email protected]> wrote:

From: Tyler Baker <[email protected]>

In the i.MX7D the PCIe PHY can use either externel oscillator or internal PLL as a reference clock source.
Add support for the PHY Reference Clock source including device tree property phy-ref-clk.
External oscillator is used as a default reference clock source.

Quoted 4 lines
Quoted 2 lines
Signed-off-by Tyler Baker <[email protected]>
Signed-off-by Ilya Ledvich <[email protected]>

Please submit this one to the PCI list and PCI maintainers.

Ack. Will do.

Quoted 3 lines

As you are adding a new property you should update Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt.

I'll add this when I resubmit to the PCI list.

Quoted 33 lines
Quoted 10 lines
---
 drivers/pci/dwc/pci-imx6.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
drivers/pci/dwc/pci-imx6.c +0 -0
index b734835..e935db4 100644

drivers/pci/dwc/pci-imx6.c enum imx6_pcie_variants { · line 48

Quoted 4 lines
drivers/pci/dwc/pci-imx6.c +1 -0
@@ -45,6 +45,7 @@ enum imx6_pcie_variants {
 struct imx6_pcie {
        struct dw_pcie          *pci;
        int                     reset_gpio;
+       u32                     phy_refclk;

Could this be bool instead?

Quoted 16 lines
drivers/pci/dwc/pci-imx6.c +1 -1
        bool                    gpio_active_high;
        struct clk              *pcie_bus;
        struct clk              *pcie_phy;

@@ -474,7 +475,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
        switch (imx6_pcie->variant) {
        case IMX7D:
                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
-                                  IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
+                                  BIT(5), imx6_pcie->phy_refclk ? BIT(5) : 0);
                break;
        case IMX6SX:
                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,

@@ -733,6 +734,11 @@ static int imx6_pcie_probe(struct platform_device *pdev)
        if (IS_ERR(pci->dbi_base))
                return PTR_ERR(pci->dbi_base);
Quoted 4 lines

drivers/pci/dwc/pci-imx6.c static int imx6_pcie_probe(struct platform_device *pdev) · line 738

Quoted 2 lines
drivers/pci/dwc/pci-imx6.c +2 -0
+       /* Fetch PHY Reference Clock */
+       if (of_property_read_u32(node, "phy-ref-clk", &imx6_pcie->phy_refclk))

You could use of_property_read_bool instead.

Thanks for the review, I'll switch to to use a bool instead.