ARM: dts: aspeed: peci-hwmon: Add Aspeed PECI hwmon
Subsystems (2)
PATCH 5/6 ARM: dts: aspeed: peci-hwmon: Add Aspeed PECI hwmon
This commit adds Aspeed PECI hwmon node into aspeed-g4 and aspeed-g5.
Signed-off-by Jae Hyun Yoo <[email protected]>
--- arch/arm/boot/dts/aspeed-g4.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/aspeed-g5.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 128 insertions(+)
arch/arm/boot/dts/aspeed-g4.dtsi +64 -0
@@ -250,6 +250,70 @@ clk-div = <0>; cmd-timeout-ms = <1000>; status = "disabled"; + + peci_hwmon0: peci-hwmon-cpu0 { + compatible = "aspeed,ast2400-peci-hwmon"; + cpu-id = <0>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon1: peci-hwmon-cpu1 { + compatible = "aspeed,ast2400-peci-hwmon"; + cpu-id = <1>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon2: peci-hwmon-cpu2 { + compatible = "aspeed,ast2400-peci-hwmon"; + cpu-id = <2>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon3: peci-hwmon-cpu3 { + compatible = "aspeed,ast2400-peci-hwmon"; + cpu-id = <3>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon4: peci-hwmon-cpu4 { + compatible = "aspeed,ast2400-peci-hwmon"; + cpu-id = <4>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon5: peci-hwmon-cpu5 { + compatible = "aspeed,ast2400-peci-hwmon"; + cpu-id = <5>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon6: peci-hwmon-cpu6 { + compatible = "aspeed,ast2400-peci-hwmon"; + cpu-id = <6>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon7: peci-hwmon-cpu7 { + compatible = "aspeed,ast2400-peci-hwmon"; + cpu-id = <7>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; }; timer: timer@1e782000 {
arch/arm/boot/dts/aspeed-g5.dtsi +64 -0
70 lines not on this page · raw message
Signature · 1 line
2.15.1
Quoted 21 lines · Jae Hyun Yoo
This commit adds Aspeed PECI hwmon node into aspeed-g4 and aspeed-g5.
Signed-off-by Jae Hyun Yoo <[email protected]>--- arch/arm/boot/dts/aspeed-g4.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/aspeed-g5.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 128 insertions(+)arch/arm/boot/dts/aspeed-g4.dtsi +1
-0@@ -250,6 +250,70 @@ clk-div = <0>; cmd-timeout-ms = <1000>; status = "disabled"; +
arch/arm/boot/dts/aspeed-g4.dtsi line 263
Quoted 10 lines
arch/arm/boot/dts/aspeed-g4.dtsi +9
-0+ peci_hwmon0: peci-hwmon-cpu0 { + compatible = "aspeed,ast2400-peci-hwmon"; + cpu-id = <0>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon1: peci-hwmon-cpu1 {
I feel like this is all better left to the platform dts rather than describing then disabling host topology in the SoC dtsi. This applies to the g5 dtsi as well.
Cheers,
Andrew
Quoted 151 lines
arch/arm/boot/dts/aspeed-g4.dtsi +17
-0+ compatible = "aspeed,ast2400-peci-hwmon"; + cpu-id = <1>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon2: peci-hwmon-cpu2 { + compatible = "aspeed,ast2400-peci-hwmon"; + cpu-id = <2>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon3: peci-hwmon-cpu3 { + compatible ="aspeed,ast2400-peci-hwmon";
arch/arm/boot/dts/aspeed-g4.dtsi +8
-0+ cpu-id = <3>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon4: peci-hwmon-cpu4 { + compatible ="aspeed,ast2400-peci-hwmon";
arch/arm/boot/dts/aspeed-g4.dtsi +8
-0+ cpu-id = <4>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon5: peci-hwmon-cpu5 { + compatible ="aspeed,ast2400-peci-hwmon";
arch/arm/boot/dts/aspeed-g4.dtsi +8
-0+ cpu-id = <5>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon6: peci-hwmon-cpu6 { + compatible ="aspeed,ast2400-peci-hwmon";
arch/arm/boot/dts/aspeed-g4.dtsi +8
-0+ cpu-id = <6>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon7: peci-hwmon-cpu7 { + compatible ="aspeed,ast2400-peci-hwmon";
arch/arm/boot/dts/aspeed-g4.dtsi +5
-0+ cpu-id = <7>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; }; timer: timer@1e782000 {arch/arm/boot/dts/aspeed-g5.dtsi +27
-0@@ -301,6 +301,70 @@ clk-div = <0>; cmd-timeout-ms = <1000>; status = "disabled"; + + peci_hwmon0: peci-hwmon-cpu0 { + compatible = "aspeed,ast2500-peci-hwmon"; + cpu-id = <0>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon1: peci-hwmon-cpu1 { + compatible = "aspeed,ast2500-peci-hwmon"; + cpu-id = <1>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon2: peci-hwmon-cpu2 { + compatible = "aspeed,ast2500-peci-hwmon"; + cpu-id = <2>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon3: peci-hwmon-cpu3 { + compatible ="aspeed,ast2500-peci-hwmon";
arch/arm/boot/dts/aspeed-g5.dtsi +8
-0+ cpu-id = <3>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon4: peci-hwmon-cpu4 { + compatible ="aspeed,ast2500-peci-hwmon";
arch/arm/boot/dts/aspeed-g5.dtsi +8
-0+ cpu-id = <4>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon5: peci-hwmon-cpu5 { + compatible ="aspeed,ast2500-peci-hwmon";
arch/arm/boot/dts/aspeed-g5.dtsi +8
-0+ cpu-id = <5>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon6: peci-hwmon-cpu6 { + compatible ="aspeed,ast2500-peci-hwmon";
arch/arm/boot/dts/aspeed-g5.dtsi +8
-0+ cpu-id = <6>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon7: peci-hwmon-cpu7 { + compatible ="aspeed,ast2500-peci-hwmon";
arch/arm/boot/dts/aspeed-g5.dtsi +5
-0+ cpu-id = <7>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; }; timer: timer@1e782000 {Signature · 1 line
2.15.1
Quoted 39 lines · Andrew Jeffery
Quoted 21 lines · Jae Hyun Yoo
This commit adds Aspeed PECI hwmon node into aspeed-g4 and aspeed-g5.
Signed-off-by Jae Hyun Yoo <[email protected]>--- arch/arm/boot/dts/aspeed-g4.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/aspeed-g5.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 128 insertions(+)arch/arm/boot/dts/aspeed-g4.dtsi +1
-0@@ -250,6 +250,70 @@ clk-div = <0>; cmd-timeout-ms = <1000>; status = "disabled"; +arch/arm/boot/dts/aspeed-g4.dtsi line 263
Quoted 10 lines
arch/arm/boot/dts/aspeed-g4.dtsi +9
-0+ peci_hwmon0: peci-hwmon-cpu0 { + compatible = "aspeed,ast2400-peci-hwmon"; + cpu-id = <0>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon1: peci-hwmon-cpu1 {I feel like this is all better left to the platform dts rather than describing then disabling host topology in the SoC dtsi. This applies to the g5 dtsi as well.
Quoted 4 lines
Cheers,
Andrew
Agreed. It is already described in a documentation as an example. I'll remove these default disabled settings from g4 and g5 so that each platform can selectively enable these.
Thanks,
Jae
Quoted 151 lines
Quoted 151 lines
arch/arm/boot/dts/aspeed-g4.dtsi +17
-0+ compatible = "aspeed,ast2400-peci-hwmon"; + cpu-id = <1>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon2: peci-hwmon-cpu2 { + compatible = "aspeed,ast2400-peci-hwmon"; + cpu-id = <2>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon3: peci-hwmon-cpu3 { + compatible ="aspeed,ast2400-peci-hwmon";
arch/arm/boot/dts/aspeed-g4.dtsi +8
-0+ cpu-id = <3>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon4: peci-hwmon-cpu4 { + compatible ="aspeed,ast2400-peci-hwmon";
arch/arm/boot/dts/aspeed-g4.dtsi +8
-0+ cpu-id = <4>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon5: peci-hwmon-cpu5 { + compatible ="aspeed,ast2400-peci-hwmon";
arch/arm/boot/dts/aspeed-g4.dtsi +8
-0+ cpu-id = <5>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon6: peci-hwmon-cpu6 { + compatible ="aspeed,ast2400-peci-hwmon";
arch/arm/boot/dts/aspeed-g4.dtsi +8
-0+ cpu-id = <6>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon7: peci-hwmon-cpu7 { + compatible ="aspeed,ast2400-peci-hwmon";
arch/arm/boot/dts/aspeed-g4.dtsi +5
-0+ cpu-id = <7>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; }; timer: timer@1e782000 {arch/arm/boot/dts/aspeed-g5.dtsi +27
-0@@ -301,6 +301,70 @@ clk-div = <0>; cmd-timeout-ms = <1000>; status = "disabled"; + + peci_hwmon0: peci-hwmon-cpu0 { + compatible = "aspeed,ast2500-peci-hwmon"; + cpu-id = <0>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon1: peci-hwmon-cpu1 { + compatible = "aspeed,ast2500-peci-hwmon"; + cpu-id = <1>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon2: peci-hwmon-cpu2 { + compatible = "aspeed,ast2500-peci-hwmon"; + cpu-id = <2>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon3: peci-hwmon-cpu3 { + compatible ="aspeed,ast2500-peci-hwmon";
arch/arm/boot/dts/aspeed-g5.dtsi +8
-0+ cpu-id = <3>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon4: peci-hwmon-cpu4 { + compatible ="aspeed,ast2500-peci-hwmon";
arch/arm/boot/dts/aspeed-g5.dtsi +8
-0+ cpu-id = <4>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon5: peci-hwmon-cpu5 { + compatible ="aspeed,ast2500-peci-hwmon";
arch/arm/boot/dts/aspeed-g5.dtsi +8
-0+ cpu-id = <5>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon6: peci-hwmon-cpu6 { + compatible ="aspeed,ast2500-peci-hwmon";
arch/arm/boot/dts/aspeed-g5.dtsi +8
-0+ cpu-id = <6>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; + + peci_hwmon7: peci-hwmon-cpu7 { + compatible ="aspeed,ast2500-peci-hwmon";
arch/arm/boot/dts/aspeed-g5.dtsi +5
-0+ cpu-id = <7>; + show-core = <1>; + dimm-nums = <16>; + status = "disabled"; + }; }; timer: timer@1e782000 {Signature · 1 line
2.15.1