lib: copy intel_aub.h from libdrm
PATCH 1/4 lib: copy intel_aub.h from libdrm
No functionality related to aub is provided by libdrm aside from intel_aub.h which somewhat defines the file format. Move the header into this project to ease aub-related development.
---
lib/Makefile.am | 1 -
lib/{stubs/drm => }/intel_aub.h | 0
lib/rendercopy_gen8.c | 2 +-
lib/rendercopy_gen9.c | 2 +-
lib/stubs/drm/README | 6 +++---
5 files changed, 5 insertions(+), 6 deletions(-)
rename lib/{stubs/drm => }/intel_aub.h (100%)lib/Makefile.am +0 -1
@@ -23,7 +23,6 @@ endif if !HAVE_LIBDRM_INTEL libintel_tools_la_SOURCES += \ - stubs/drm/intel_aub.h \ stubs/drm/intel_bufmgr.c \ stubs/drm/intel_bufmgr.h endif
lib/intel_aub.h renamed from lib/stubs/drm/intel_aub.h +0 -0
lib/rendercopy_gen8.c +1 -1
@@ -22,7 +22,7 @@#include "intel_reg.h" #include "igt_aux.h" -#include <intel_aub.h> +#include "intel_aub.h" #define VERTEX_SIZE (3*4)
lib/rendercopy_gen9.c +1 -1
@@ -23,7 +23,7 @@#include "intel_reg.h" #include "igt_aux.h" -#include <intel_aub.h> +#include "intel_aub.h" #define VERTEX_SIZE (3*4)
lib/stubs/drm/README +3 -3
@@ -1,4 +1,4 @@ -intel_bufmgr.h and intel_aub.h are a local copy of the files provided by libdrm. +intel_bufmgr.h is a local copy of the file provided by libdrm (intel/intel_bufmgr.h). -Before releasing i-g-t a current copy of the files should be copied into this -directory of i-g-t. +Before releasing i-g-t a current copy of intel_bufmgr.h should be copied into +this directory of i-g-t.
Signature · 6 lines
2.14.3 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 2/4 tools/intel_aubdump: Set addr_bits before write_header
write_header() uses addr_bits, so do the initialization earlier. Also set the gen to a non-zero value in case of unknown device, for use by a later patch.
--- tools/aubdump.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-)
tools/aubdump.c +9 -5
@@ -417,6 +417,15 @@ dump_execbuffer2(int fd, struct drm_i915_gem_execbuffer2 *execbuffer2) }if (gen ==0 ) { gen =intel_gen (device); + +/* If we don't know the device gen, then it probably is a +* newer device. Set gen to some arbitrarily high number. +*/ +if (gen ==0 ) + gen =9999 ; + + addr_bits = gen >=8 ?48 :32 ; +write_header ();if (verbose)
@@ -425,11 +434,6 @@ dump_execbuffer2(int fd, struct drm_i915_gem_execbuffer2 *execbuffer2) filename, device, gen); } -/* If we don't know the device gen, then it probably is a -* newer device which uses 48-bit addresses. -*/ - addr_bits = (gen >=8 || gen ==0 ) ?48 :32 ; -if (verbose)printf ("Dumping execbuffer2:\n" );
Signature · 6 lines
2.14.3 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 3/4 lib/intel_aub: Add new MEM_TRACE commands
In reply to Scott D PhillipsThe memtrace aub commands are similar to the existing ones, but different. Notably memtrace has commands for register write and poll.
--- lib/intel_aub.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)
lib/intel_aub.h +26 -0
@@ -49,6 +49,12 @@#define CMD_AUB (7 << 29)#define CMD_AUB_HEADER (CMD_AUB | (1 << 23) | (0x05 << 16)) + +#define CMD_MEM_TRACE_REGISTER_POLL (CMD_AUB | (0x2e << 23) | (0x02 << 16)) +#define CMD_MEM_TRACE_REGISTER_WRITE (CMD_AUB | (0x2e << 23) | (0x03 << 16)) +#define CMD_MEM_TRACE_MEMORY_WRITE (CMD_AUB | (0x2e << 23) | (0x06 << 16)) +#define CMD_MEM_TRACE_VERSION (CMD_AUB | (0x2e << 23) | (0x0e << 16)) +/* DW1 */ # define AUB_HEADER_MAJOR_SHIFT 24# define AUB_HEADER_MINOR_SHIFT 16
@@ -92,8 +98,28 @@#define AUB_TRACE_MEMTYPE_PCI (3 << 16)#define AUB_TRACE_MEMTYPE_GTT_ENTRY (4 << 16) +#define AUB_MEM_TRACE_VERSION_FILE_VERSION 1 +/* DW2 */ +#define AUB_MEM_TRACE_VERSION_DEVICE_MASK 0x0000ff00 +#define AUB_MEM_TRACE_VERSION_DEVICE_CNL (15 << 8) + +#define AUB_MEM_TRACE_VERSION_METHOD_MASK 0x000c0000 +#define AUB_MEM_TRACE_VERSION_METHOD_PHY (1 << 18) + +#define AUB_MEM_TRACE_REGISTER_SIZE_MASK 0x000f0000 +#define AUB_MEM_TRACE_REGISTER_SIZE_DWORD (2 << 16) + +#define AUB_MEM_TRACE_REGISTER_SPACE_MASK 0xf0000000 +#define AUB_MEM_TRACE_REGISTER_SPACE_MMIO (0 << 28) + +/* DW3 */ + +#define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_MASK 0xf0000000 +#define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_LOCAL (1 << 28) +#define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT_ENTRY (4 << 28) +/** * aub_state_struct_type enum values are encoded with the top 16 bits * representing the type to be delivered to the .aub file, and the bottom 16
Signature · 6 lines
2.14.3 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH i-g-t 3/4] lib/intel_aub: Add new MEM_TRACE commands
Despite trying, I wasn't able to confirm these values. Nevertheless, I was able to test your series, so:
Quoted 58 lines · Scott D Phillips
The memtrace aub commands are similar to the existing ones, but different. Notably memtrace has commands for register write and poll.
Signed-off-by Scott D Phillips <[email protected]>--- lib/intel_aub.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)lib/intel_aub.h +26
-0@@ -49,6 +49,12 @@#define CMD_AUB (7 << 29)#define CMD_AUB_HEADER (CMD_AUB | (1 << 23) | (0x05 << 16)) + +#define CMD_MEM_TRACE_REGISTER_POLL (CMD_AUB | (0x2e << 23) | (0x02 << 16)) +#define CMD_MEM_TRACE_REGISTER_WRITE (CMD_AUB | (0x2e << 23) | (0x03 << 16)) +#define CMD_MEM_TRACE_MEMORY_WRITE (CMD_AUB | (0x2e << 23) | (0x06 << 16)) +#define CMD_MEM_TRACE_VERSION (CMD_AUB | (0x2e << 23) | (0x0e << 16)) +/* DW1 */ # define AUB_HEADER_MAJOR_SHIFT 24# define AUB_HEADER_MINOR_SHIFT 16@@ -92,8 +98,28 @@#define AUB_TRACE_MEMTYPE_PCI (3 << 16)#define AUB_TRACE_MEMTYPE_GTT_ENTRY (4 << 16) +#define AUB_MEM_TRACE_VERSION_FILE_VERSION 1 +/* DW2 */ +#define AUB_MEM_TRACE_VERSION_DEVICE_MASK 0x0000ff00 +#define AUB_MEM_TRACE_VERSION_DEVICE_CNL (15 << 8) + +#define AUB_MEM_TRACE_VERSION_METHOD_MASK 0x000c0000 +#define AUB_MEM_TRACE_VERSION_METHOD_PHY (1 << 18) + +#define AUB_MEM_TRACE_REGISTER_SIZE_MASK 0x000f0000 +#define AUB_MEM_TRACE_REGISTER_SIZE_DWORD (2 << 16) + +#define AUB_MEM_TRACE_REGISTER_SPACE_MASK 0xf0000000 +#define AUB_MEM_TRACE_REGISTER_SPACE_MMIO (0 << 28) + +/* DW3 */ + +#define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_MASK 0xf0000000 +#define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_LOCAL (1 << 28) +#define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT_ENTRY (4 << 28) +/** * aub_state_struct_type enum values are encoded with the top 16 bits * representing the type to be delivered to the .aub file, and the bottom 16 Signature · 1 line
2.14.3
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v2 4/4 tools/intel_aubdump: Add ability to simulate execlist submission
In reply to Scott D PhillipsNewer devices do not have the legacy ring buffer submission model, so aub files generated using that model cannot be handled by some internal tools. The execlist submission modeled by this change is pretty simplistic, using GGTT only and synchronizing after every batch.
v2:
- Move addr_bits init in separate patch (Jordan)
- Don't change GTT entries in gen < 10
--- tools/aubdump.c | 405 ++++++++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 382 insertions(+), 23 deletions(-)
tools/aubdump.c +382 -23
@@ -46,6 +46,177 @@#define ARRAY_SIZE (x) (sizeof(x)/sizeof((x)[0]))#endif +#ifndef ALIGN +#define ALIGN (x, y) (((x) + (y)-1) & ~((y)-1)) +#endif + +#define min (a, b) ({ \ + typeof(a) _a = (a); \ + typeof(b) _b = (b); \ + _a < _b ? _a : _b; \ +}) + +#define HWS_PGA_RCSUNIT 0x02080 +#define HWS_PGA_VCSUNIT0 0x12080 +#define HWS_PGA_BCSUNIT 0x22080 + +#define GFX_MODE_RCSUNIT 0x0229c +#define GFX_MODE_VCSUNIT0 0x1229c +#define GFX_MODE_BCSUNIT 0x2229c + +#define EXECLIST_SUBMITPORT_RCSUNIT 0x02230 +#define EXECLIST_SUBMITPORT_VCSUNIT0 0x12230 +#define EXECLIST_SUBMITPORT_BCSUNIT 0x22230 + +#define EXECLIST_STATUS_RCSUNIT 0x02234 +#define EXECLIST_STATUS_VCSUNIT0 0x12234 +#define EXECLIST_STATUS_BCSUNIT 0x22234 + +#define MEMORY_MAP_SIZE (64 /* MiB */ * 1024 * 1024) + +#define PTE_SIZE 4 +#define GEN8_PTE_SIZE 8 + +#define NUM_PT_ENTRIES (ALIGN(MEMORY_MAP_SIZE, 4096) / 4096) +#define PT_SIZE ALIGN(NUM_PT_ENTRIES * GEN8_PTE_SIZE, 4096) + +#define RING_SIZE (1 * 4096) +#define PPHWSP_SIZE (1 * 4096) +#define GEN10_LR_CONTEXT_RENDER_SIZE (19 * 4096) +#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * 4096) + +#define STATIC_GGTT_MAP_START 0 + +#define RENDER_RING_ADDR STATIC_GGTT_MAP_START +#define RENDER_CONTEXT_ADDR (RENDER_RING_ADDR + RING_SIZE) + +#define BLITTER_RING_ADDR (RENDER_CONTEXT_ADDR + PPHWSP_SIZE + GEN10_LR_CONTEXT_RENDER_SIZE) +#define BLITTER_CONTEXT_ADDR (BLITTER_RING_ADDR + RING_SIZE) + +#define VIDEO_RING_ADDR (BLITTER_CONTEXT_ADDR + PPHWSP_SIZE + GEN8_LR_CONTEXT_OTHER_SIZE) +#define VIDEO_CONTEXT_ADDR (VIDEO_RING_ADDR + RING_SIZE) + +#define STATIC_GGTT_MAP_END (VIDEO_CONTEXT_ADDR + PPHWSP_SIZE + GEN8_LR_CONTEXT_OTHER_SIZE) +#define STATIC_GGTT_MAP_SIZE (STATIC_GGTT_MAP_END - STATIC_GGTT_MAP_START) + +#define CONTEXT_FLAGS (0x229)/* Normal Priority | L3-LLC Coherency | +Legacy Context with no 64 bit VA support | Valid */ + +#define RENDER_CONTEXT_DESCRIPTOR ((uint64_t)1 << 32 | RENDER_CONTEXT_ADDR | CONTEXT_FLAGS) +#define BLITTER_CONTEXT_DESCRIPTOR ((uint64_t)2 << 32 | BLITTER_CONTEXT_ADDR | CONTEXT_FLAGS) +#define VIDEO_CONTEXT_DESCRIPTOR ((uint64_t)3 << 32 | VIDEO_CONTEXT_ADDR | CONTEXT_FLAGS) + +static const uint32_t render_context_init[GEN10_LR_CONTEXT_RENDER_SIZE / +sizeof (uint32_t )] = { +0 /* MI_NOOP */ , +0x1100101B /* MI_LOAD_REGISTER_IMM */ , +0x2244 /* CONTEXT_CONTROL */ ,0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */ , +0x2034 /* RING_HEAD */ ,0 , +0x2030 /* RING_TAIL */ ,0 , +0x2038 /* RING_BUFFER_START */ ,RENDER_RING_ADDR , +0x203C /* RING_BUFFER_CONTROL */ , (RING_SIZE -4096 ) |1 /* Buffer Length | Ring Buffer Enable */ , +0x2168 /* BB_HEAD_U */ ,0 , +0x2140 /* BB_HEAD_L */ ,0 , +0x2110 /* BB_STATE */ ,0 , +0x211C /* SECOND_BB_HEAD_U */ ,0 , +0x2114 /* SECOND_BB_HEAD_L */ ,0 , +0x2118 /* SECOND_BB_STATE */ ,0 , +0x21C0 /* BB_PER_CTX_PTR */ ,0 , +0x21C4 /* RCS_INDIRECT_CTX */ ,0 , +0x21C8 /* RCS_INDIRECT_CTX_OFFSET */ ,0 , +/* MI_NOOP */ +0 ,0 , + +0 /* MI_NOOP */ , +0x11001011 /* MI_LOAD_REGISTER_IMM */ , +0x23A8 /* CTX_TIMESTAMP */ ,0 , +0x228C /* PDP3_UDW */ ,0 , +0x2288 /* PDP3_LDW */ ,0 , +0x2284 /* PDP2_UDW */ ,0 , +0x2280 /* PDP2_LDW */ ,0 , +0x227C /* PDP1_UDW */ ,0 , +0x2278 /* PDP1_LDW */ ,0 , +0x2274 /* PDP0_UDW */ ,0 , +0x2270 /* PDP0_LDW */ ,0 , +/* MI_NOOP */ +0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , + +0 /* MI_NOOP */ , +0x11000001 /* MI_LOAD_REGISTER_IMM */ , +0x20C8 /* R_PWR_CLK_STATE */ ,0x7FFFFFFF , +0x05000001 /* MI_BATCH_BUFFER_END */ +}; + +static const uint32_t blitter_context_init[GEN8_LR_CONTEXT_OTHER_SIZE / +sizeof (uint32_t )] = { +0 /* MI_NOOP */ , +0x11001015 /* MI_LOAD_REGISTER_IMM */ , +0x22244 /* CONTEXT_CONTROL */ ,0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */ , +0x22034 /* RING_HEAD */ ,0 , +0x22030 /* RING_TAIL */ ,0 , +0x22038 /* RING_BUFFER_START */ ,BLITTER_RING_ADDR , +0x2203C /* RING_BUFFER_CONTROL */ , (RING_SIZE -4096 ) |1 /* Buffer Length | Ring Buffer Enable */ , +0x22168 /* BB_HEAD_U */ ,0 , +0x22140 /* BB_HEAD_L */ ,0 , +0x22110 /* BB_STATE */ ,0 , +0x2211C /* SECOND_BB_HEAD_U */ ,0 , +0x22114 /* SECOND_BB_HEAD_L */ ,0 , +0x22118 /* SECOND_BB_STATE */ ,0 , +/* MI_NOOP */ +0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , + +0 /* MI_NOOP */ , +0x11001011 , +0x223A8 /* CTX_TIMESTAMP */ ,0 , +0x2228C /* PDP3_UDW */ ,0 , +0x22288 /* PDP3_LDW */ ,0 , +0x22284 /* PDP2_UDW */ ,0 , +0x22280 /* PDP2_LDW */ ,0 , +0x2227C /* PDP1_UDW */ ,0 , +0x22278 /* PDP1_LDW */ ,0 , +0x22274 /* PDP0_UDW */ ,0 , +0x22270 /* PDP0_LDW */ ,0 , +/* MI_NOOP */ +0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , + +0x05000001 /* MI_BATCH_BUFFER_END */ +}; + +static const uint32_t video_context_init[GEN8_LR_CONTEXT_OTHER_SIZE / +sizeof (uint32_t )] = { +0 /* MI_NOOP */ , +0x11001015 /* MI_LOAD_REGISTER_IMM */ , +0x1C244 /* CONTEXT_CONTROL */ ,0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */ , +0x1C034 /* RING_HEAD */ ,0 , +0x1C030 /* RING_TAIL */ ,0 , +0x1C038 /* RING_BUFFER_START */ ,VIDEO_RING_ADDR , +0x1C03C /* RING_BUFFER_CONTROL */ , (RING_SIZE -4096 ) |1 /* Buffer Length | Ring Buffer Enable */ , +0x1C168 /* BB_HEAD_U */ ,0 , +0x1C140 /* BB_HEAD_L */ ,0 , +0x1C110 /* BB_STATE */ ,0 , +0x1C11C /* SECOND_BB_HEAD_U */ ,0 , +0x1C114 /* SECOND_BB_HEAD_L */ ,0 , +0x1C118 /* SECOND_BB_STATE */ ,0 , +/* MI_NOOP */ +0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , + +0 /* MI_NOOP */ , +0x11001011 , +0x1C3A8 /* CTX_TIMESTAMP */ ,0 , +0x1C28C /* PDP3_UDW */ ,0 , +0x1C288 /* PDP3_LDW */ ,0 , +0x1C284 /* PDP2_UDW */ ,0 , +0x1C280 /* PDP2_LDW */ ,0 , +0x1C27C /* PDP1_UDW */ ,0 , +0x1C278 /* PDP1_LDW */ ,0 , +0x1C274 /* PDP0_UDW */ ,0 , +0x1C270 /* PDP0_LDW */ ,0 , +/* MI_NOOP */ +0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , + +0x05000001 /* MI_BATCH_BUFFER_END */ +}; +static int close_init_helper (int fd);static int ioctl_init_helper (int fd,unsigned long request, ...);
@@ -171,21 +342,131 @@ data_out(const void *data, size_t size) }static uint32_t -gtt_entry_size (void ) +gtt_size (void ) { -return addr_bits >32 ?8 :4 ; +return NUM_PT_ENTRIES * (addr_bits >32 ?GEN8_PTE_SIZE :PTE_SIZE ); } -static uint32_t -gtt_size (void ) +static void +mem_trace_memory_write_header_out (uint64_t addr,uint32_t len, +uint32_t addr_space) { -/* Enough for 64MB assuming 4kB pages. */ -const unsigned entries =0x4000 ; -return entries *gtt_entry_size (); +uint32_t dwords =ALIGN (len,sizeof (uint32_t )) /sizeof (uint32_t ); + +dword_out (CMD_MEM_TRACE_MEMORY_WRITE | (5 + dwords -1 )); +dword_out (addr &0xFFFFFFFF );/* addr lo */ +dword_out (addr >>32 );/* addr hi */ +dword_out (addr_space);/* gtt */ +dword_out (len); }static void -write_header (void ) +register_write_out (uint32_t addr,uint32_t value) +{ +uint32_t dwords =1 ; + +dword_out (CMD_MEM_TRACE_REGISTER_WRITE | (5 + dwords -1 )); +dword_out (addr); +dword_out (AUB_MEM_TRACE_REGISTER_SIZE_DWORD | +AUB_MEM_TRACE_REGISTER_SPACE_MMIO ); +dword_out (0xFFFFFFFF );/* mask lo */ +dword_out (0x00000000 );/* mask hi */ +dword_out (value); +} + +static void +gen10_write_header (void ) +{ +char app_name[8 *4 ]; +int app_name_len, dwords; +uint32_t entry =0x3 ;/* read/write | present */ + + app_name_len = +snprintf (app_name,sizeof (app_name),"PCI-ID=0x%X %s" , device, + program_invocation_short_name); + app_name_len =ALIGN (app_name_len,sizeof (uint32_t )); + + dwords =5 + app_name_len /sizeof (uint32_t ); +dword_out (CMD_MEM_TRACE_VERSION | (dwords -1 )); +dword_out (AUB_MEM_TRACE_VERSION_FILE_VERSION ); +dword_out (AUB_MEM_TRACE_VERSION_DEVICE_CNL | +AUB_MEM_TRACE_VERSION_METHOD_PHY ); +dword_out (0 );/* version */ +dword_out (0 );/* version */ +data_out (app_name, app_name_len); + +/* GGTT PT */ +for (uint32_t page =0 ; page <ALIGN (PT_SIZE ,4096 ) /4096 ; page++) { +uint32_t to_write =min (PT_SIZE - page *4096 ,4096 ); +mem_trace_memory_write_header_out (page <<12 , to_write, +AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT_ENTRY ); +for (uint32_t i =0 ; i < to_write /GEN8_PTE_SIZE ; i++) { +dword_out (entry +0x1000 * i +0x200000 * page); +dword_out (0 ); + } + } + +/* RENDER_RING */ +mem_trace_memory_write_header_out (RENDER_RING_ADDR ,RING_SIZE , +AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_LOCAL ); +for (uint32_t i =0 ; i <RING_SIZE ; i +=sizeof (uint32_t )) +dword_out (0 ); + +/* RENDER_PPHWSP */ +mem_trace_memory_write_header_out (RENDER_CONTEXT_ADDR , +PPHWSP_SIZE + +sizeof (render_context_init), +AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_LOCAL ); +for (uint32_t i =0 ; i <PPHWSP_SIZE ; i +=sizeof (uint32_t )) +dword_out (0 ); + +/* RENDER_CONTEXT */ +data_out (render_context_init,sizeof (render_context_init)); + +/* BLITTER_RING */ +mem_trace_memory_write_header_out (BLITTER_RING_ADDR ,RING_SIZE , +AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_LOCAL ); +for (uint32_t i =0 ; i <RING_SIZE ; i +=sizeof (uint32_t )) +dword_out (0 ); + +/* BLITTER_PPHWSP */ +mem_trace_memory_write_header_out (BLITTER_CONTEXT_ADDR , +PPHWSP_SIZE + +sizeof (blitter_context_init), +AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_LOCAL ); +for (uint32_t i =0 ; i <PPHWSP_SIZE ; i +=sizeof (uint32_t )) +dword_out (0 ); + +/* BLITTER_CONTEXT */ +data_out (blitter_context_init,sizeof (blitter_context_init)); + +/* VIDEO_RING */ +mem_trace_memory_write_header_out (VIDEO_RING_ADDR ,RING_SIZE , +AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_LOCAL ); +for (uint32_t i =0 ; i <RING_SIZE ; i +=sizeof (uint32_t )) +dword_out (0 ); + +/* VIDEO_PPHWSP */ +mem_trace_memory_write_header_out (VIDEO_CONTEXT_ADDR , +PPHWSP_SIZE + +sizeof (video_context_init), +AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_LOCAL ); +for (uint32_t i =0 ; i <PPHWSP_SIZE ; i +=sizeof (uint32_t )) +dword_out (0 ); + +/* VIDEO_CONTEXT */ +data_out (video_context_init,sizeof (video_context_init)); + +register_write_out (HWS_PGA_RCSUNIT ,RENDER_CONTEXT_ADDR ); +register_write_out (HWS_PGA_VCSUNIT0 ,VIDEO_CONTEXT_ADDR ); +register_write_out (HWS_PGA_BCSUNIT ,BLITTER_CONTEXT_ADDR ); + +register_write_out (GFX_MODE_RCSUNIT ,0x80008000 /* execlist enable */ ); +register_write_out (GFX_MODE_VCSUNIT0 ,0x80008000 /* execlist enable */ ); +register_write_out (GFX_MODE_BCSUNIT ,0x80008000 /* execlist enable */ ); +} + +static void write_header (void ) {char app_name[8 *4 ];char comment[16 ];
@@ -220,7 +501,7 @@ write_header(void)dword_out (gtt_size ());/* size */ if (addr_bits >32 )dword_out (0 ); -for (uint32_t i =0 ; i *gtt_entry_size () <gtt_size (); i++) { +for (uint32_t i =0 ; i <NUM_PT_ENTRIES ; i++) {dword_out (entry +0x1000 * i);if (addr_bits >32 )dword_out (0 );
@@ -245,15 +526,21 @@ aub_write_trace_block(uint32_t type, void *virtual, uint32_t size, uint64_t gtt_if (block_size >8 *4096 ) block_size =8 *4096 ; -dword_out (CMD_AUB_TRACE_HEADER_BLOCK | - ((addr_bits >32 ?6 :5 ) -2 )); -dword_out (AUB_TRACE_MEMTYPE_GTT | - type |AUB_TRACE_OP_DATA_WRITE ); -dword_out (subtype); -dword_out (gtt_offset + offset); -dword_out (align_u32 (block_size,4 )); -if (addr_bits >32 ) -dword_out ((gtt_offset + offset) >>32 ); +if (gen >=10 ) { +mem_trace_memory_write_header_out (gtt_offset + offset, + block_size, +AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_LOCAL ); + }else { +dword_out (CMD_AUB_TRACE_HEADER_BLOCK | + ((addr_bits >32 ?6 :5 ) -2 )); +dword_out (AUB_TRACE_MEMTYPE_GTT | + type |AUB_TRACE_OP_DATA_WRITE ); +dword_out (subtype); +dword_out (gtt_offset + offset); +dword_out (align_u32 (block_size,4 )); +if (addr_bits >32 ) +dword_out ((gtt_offset + offset) >>32 ); + }if (virtual)data_out (((char *)GET_PTR (virtual)) + offset, block_size);
@@ -291,6 +578,64 @@ write_reloc(void *p, uint64_t v) } } +static void +aub_dump_execlist (uint64_t batch_offset,int ring_flag) +{ +uint32_t ring_addr; +uint64_t descriptor; +uint32_t elsp_reg; +uint32_t status_reg; + +switch (ring_flag) { +case I915_EXEC_DEFAULT : +case I915_EXEC_RENDER : + ring_addr =RENDER_RING_ADDR ; + descriptor =RENDER_CONTEXT_DESCRIPTOR ; + elsp_reg =EXECLIST_SUBMITPORT_RCSUNIT ; + status_reg =EXECLIST_STATUS_RCSUNIT ; +break ; +case I915_EXEC_BSD : + ring_addr =VIDEO_RING_ADDR ; + descriptor =VIDEO_CONTEXT_DESCRIPTOR ; + elsp_reg =EXECLIST_SUBMITPORT_VCSUNIT0 ; + status_reg =EXECLIST_STATUS_VCSUNIT0 ; +break ; +case I915_EXEC_BLT : + ring_addr =BLITTER_RING_ADDR ; + descriptor =BLITTER_CONTEXT_DESCRIPTOR ; + elsp_reg =EXECLIST_SUBMITPORT_BCSUNIT ; + status_reg =EXECLIST_STATUS_BCSUNIT ; +break ; + } + +mem_trace_memory_write_header_out (ring_addr,16 , +AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_LOCAL ); +dword_out (AUB_MI_BATCH_BUFFER_START | (3 -2 )); +dword_out (batch_offset &0xFFFFFFFF ); +dword_out (batch_offset >>32 ); +dword_out (0 /* MI_NOOP */ ); + +mem_trace_memory_write_header_out (ring_addr +8192 +20 ,4 , +AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_LOCAL ); +dword_out (0 );/* RING_BUFFER_HEAD */ +mem_trace_memory_write_header_out (ring_addr +8192 +28 ,4 , +AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_LOCAL ); +dword_out (16 );/* RING_BUFFER_TAIL */ + +register_write_out (elsp_reg,0 ); +register_write_out (elsp_reg,8 ); +register_write_out (elsp_reg, descriptor >>32 ); +register_write_out (elsp_reg, descriptor &0xFFFFFFFF ); + +dword_out (CMD_MEM_TRACE_REGISTER_POLL | (5 +1 -1 )); +dword_out (status_reg); +dword_out (AUB_MEM_TRACE_REGISTER_SIZE_DWORD | +AUB_MEM_TRACE_REGISTER_SPACE_MMIO ); +dword_out (0x00000010 );/* mask lo */ +dword_out (0x00000000 );/* mask hi */ +dword_out (0x00000000 ); +} +static void aub_dump_ringbuffer (uint64_t batch_offset,uint64_t offset,int ring_flag) {
@@ -404,7 +749,7 @@ dump_execbuffer2(int fd, struct drm_i915_gem_execbuffer2 *execbuffer2)struct drm_i915_gem_exec_object2 *exec_objects = (struct drm_i915_gem_exec_object2 *) (uintptr_t ) execbuffer2->buffers_ptr;uint32_t ring_flag = execbuffer2->flags &I915_EXEC_RING_MASK ; -uint32_t offset =gtt_size (); +uint32_t offset;struct drm_i915_gem_exec_object2 *obj;struct bo *bo, *batch_bo;int batch_index;
@@ -426,7 +771,10 @@ dump_execbuffer2(int fd, struct drm_i915_gem_execbuffer2 *execbuffer2) addr_bits = gen >=8 ?48 :32 ; -write_header (); +if (gen >=10 ) +gen10_write_header (); +else +write_header ();if (verbose) printf("[intel_aubdump: running, "
@@ -434,6 +782,11 @@ dump_execbuffer2(int fd, struct drm_i915_gem_execbuffer2 *execbuffer2) filename, device, gen); } +if (gen >=10 ) + offset =STATIC_GGTT_MAP_END ; +else + offset =gtt_size (); +if (verbose)printf ("Dumping execbuffer2:\n" );
@@ -488,9 +841,15 @@ dump_execbuffer2(int fd, struct drm_i915_gem_execbuffer2 *execbuffer2)free (data); } -/* Dump ring buffer */ -aub_dump_ringbuffer (batch_bo->offset + execbuffer2->batch_start_offset, - offset, ring_flag); +if (gen >=10 ) { +aub_dump_execlist (batch_bo->offset + + execbuffer2->batch_start_offset, ring_flag); + }else { +/* Dump ring buffer */ +aub_dump_ringbuffer (batch_bo->offset + + execbuffer2->batch_start_offset, offset, + ring_flag); + }for (int i =0 ; i <ARRAY_SIZE (files); i++) {if (files[i] !=NULL )
Signature · 6 lines
2.14.3 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Patchwork
CI✓ Fi.CI.BAT: success for series starting with [1/4] lib: copy intel_aub.h from libdrm
In reply to Scott D Phillips== Series Details ==
== Series Details ==
Series: series starting with [1/4] lib: copy intel_aub.h from libdrm
URL : https://patchwork.freedesktop.org/series/34999/
State : success
== Summary ==
IGT patchset tested on top of latest successful build 1db12466cb5ad8483cd469753d2e312a62d717b7 meson: build a full dependency for lib_igt_perf
with latest DRM-Tip kernel build CI_DRM_346895f37eb3ebfd drm-tip: 2017y-12m-06d-21h-01m-04s UTC integration manifest
No testlist changes.
Test debugfs_test:
Subgroup read_all_entries:
dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989
Test gem_exec_reloc:
Subgroup basic-write-gtt-active:
pass -> FAIL (fi-gdg-551) fdo#102582
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail -> PASS (fi-gdg-551) fdo#102575fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:438s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:387s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:521s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:283s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:504s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:513s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:495s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:477s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:268s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:537s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:374s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:259s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:476s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:453s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:525s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:477s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:533s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:596s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:451s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:548s fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:566s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:519s fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:501s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:547s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:419s Blacklisted hosts: fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:640s fi-glk-dsi total:216 pass:180 dwarn:0 dfail:1 fail:0 skip:34
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_607/
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Patchwork
CI✗ Fi.CI.IGT: warning for series starting with [1/4] lib: copy intel_aub.h from libdrm
In reply to Scott D Phillips== Series Details ==
== Series Details ==
Series: series starting with [1/4] lib: copy intel_aub.h from libdrm
URL : https://patchwork.freedesktop.org/series/34999/
State : warning
== Summary ==
Test pm_rc6_residency:
Subgroup rc6-accuracy:
pass -> SKIP (shard-snb)
Test gem_softpin:
Subgroup noreloc-s3:
pass -> SKIP (shard-snb) fdo#102365
Test kms_cursor_crc:
Subgroup cursor-256x256-suspend:
pass -> INCOMPLETE (shard-hsw) fdo#103375
Test gem_tiled_swapping:
Subgroup non-threaded:
pass -> INCOMPLETE (shard-snb) fdo#104009 +1fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#104009 https://bugs.freedesktop.org/show_bug.cgi?id=104009
shard-hsw total:2579 pass:1466 dwarn:1 dfail:0 fail:10 skip:1100 time:8861s shard-snb total:2607 pass:1259 dwarn:1 dfail:0 fail:13 skip:1333 time:7722s Blacklisted hosts: shard-apl total:2679 pass:1679 dwarn:2 dfail:0 fail:21 skip:977 time:13622s shard-kbl total:2679 pass:1784 dwarn:9 dfail:0 fail:26 skip:860 time:10930s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_607/shards.html
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoted 71 lines · Scott D Phillips
No functionality related to aub is provided by libdrm aside from
intel_aub.hwhich somewhat defines the file format. Move the header into this project to ease aub-related development.Signed-off-by Scott D Phillips <[email protected]>--- lib/Makefile.am | 1 - lib/{stubs/drm => }/intel_aub.h | 0 lib/rendercopy_gen8.c | 2 +- lib/rendercopy_gen9.c | 2 +- lib/stubs/drm/README | 6 +++--- 5 files changed, 5 insertions(+), 6 deletions(-) rename lib/{stubs/drm => }/intel_aub.h (100%)lib/Makefile.am +0
-1@@ -23,7 +23,6 @@ endif if !HAVE_LIBDRM_INTEL libintel_tools_la_SOURCES += \ - stubs/drm/intel_aub.h \ stubs/drm/intel_bufmgr.c \ stubs/drm/intel_bufmgr.h endiflib/intel_aub.h renamed from lib/stubs/drm/intel_aub.h +0
-0lib/rendercopy_gen8.c +1
-1@@ -22,7 +22,7 @@#include "intel_reg.h" #include "igt_aux.h" -#include <intel_aub.h> +#include "intel_aub.h" #define VERTEX_SIZE (3*4)lib/rendercopy_gen9.c +1
-1@@ -23,7 +23,7 @@#include "intel_reg.h" #include "igt_aux.h" -#include <intel_aub.h> +#include "intel_aub.h" #define VERTEX_SIZE (3*4)lib/stubs/drm/README +3
-3@@ -1,4 +1,4 @@ -intel_bufmgr.h and intel_aub.h are a local copy of the files provided by libdrm. +intel_bufmgr.h is a local copy of the file provided by libdrm (intel/intel_bufmgr.h). -Before releasing i-g-t a current copy of the files should be copied into this -directory of i-g-t. +Before releasing i-g-t a current copy of intel_bufmgr.h should be copied into +this directory of i-g-t.Signature · 1 line
2.14.3
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Series:
Quoted 71 lines · Scott D Phillips
No functionality related to aub is provided by libdrm aside from
intel_aub.hwhich somewhat defines the file format. Move the header into this project to ease aub-related development.Signed-off-by Scott D Phillips <[email protected]>--- lib/Makefile.am | 1 - lib/{stubs/drm => }/intel_aub.h | 0 lib/rendercopy_gen8.c | 2 +- lib/rendercopy_gen9.c | 2 +- lib/stubs/drm/README | 6 +++--- 5 files changed, 5 insertions(+), 6 deletions(-) rename lib/{stubs/drm => }/intel_aub.h (100%)lib/Makefile.am +0
-1@@ -23,7 +23,6 @@ endif if !HAVE_LIBDRM_INTEL libintel_tools_la_SOURCES += \ - stubs/drm/intel_aub.h \ stubs/drm/intel_bufmgr.c \ stubs/drm/intel_bufmgr.h endiflib/intel_aub.h renamed from lib/stubs/drm/intel_aub.h +0
-0lib/rendercopy_gen8.c +1
-1@@ -22,7 +22,7 @@#include "intel_reg.h" #include "igt_aux.h" -#include <intel_aub.h> +#include "intel_aub.h" #define VERTEX_SIZE (3*4)lib/rendercopy_gen9.c +1
-1@@ -23,7 +23,7 @@#include "intel_reg.h" #include "igt_aux.h" -#include <intel_aub.h> +#include "intel_aub.h" #define VERTEX_SIZE (3*4)lib/stubs/drm/README +3
-3@@ -1,4 +1,4 @@ -intel_bufmgr.h and intel_aub.h are a local copy of the files provided by libdrm. +intel_bufmgr.h is a local copy of the file provided by libdrm (intel/intel_bufmgr.h). -Before releasing i-g-t a current copy of the files should be copied into this -directory of i-g-t. +Before releasing i-g-t a current copy of intel_bufmgr.h should be copied into +this directory of i-g-t.Signature · 1 line
2.14.3
_______________________________________________
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[email protected]
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