s390x/tcg: facilitites and instructions

PATCH In review David Hildenbrand 2 participants 25 messages Dec 7, 2017 – Dec 8, 2017

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David Hildenbrand

author

2017-12-07 16:54 UTC #0 lore raw

v2 cover s390x/tcg: facilitites and instructions

Wire up some io instructions and implement new facilitites. Make sure to take care of MTTCG when it comes to atomic operations.

As we are now able to install/boot a Fedora 26/27 as well as an upstream kernel compiled for z12, let's bump up the QEMU cpu model to a very stripped down version of a z12 (with missing base features). Take care of backwards compatibility (as we defined the QEMU model as migration-safe).

Try it yourself: https://github.com/davidhildenbrand/qemu.git s390x-queue

This branch is based on https://github.com/cohuck/qemu.git s390x-next and contains other patches sent previously, especially
- s390x/tcg: CCW hotplug support
- cpus: make pause_all_cpus() play with SMP on single threaded TCG
- cpu-exec: fix missed CPU kick during interrupt injection

$ baseurl=https://ftp-stud.hs-esslingen.de/pub/fedora-secondary/releases/27/Server/s390x/os/
$ wget ${baseurl}/images/kernel.img
$ wget ${baseurl}/images/initrd.img
$ qemu-img create -f qcow2 guest-tcg.qcow2 8G
$ qemu-system-s390x \
    -nographic -machine s390-ccw-virtio -m 2048 \
    --accel tcg,thread=multi -smp 4,maxcpus=4 \
    -hda guest-tcg.qcow2 \
    -kernel kernel.img \
    -initrd initrd.img \
    --append "TERM=linux inst.repo=${baseurl}/ ip=dhcp inst.geoloc=0"

I was also able to install and boot Ubuntu 17.10. Enabling channel measurements now also works.

v1 -> v2:
- rephrased/fixed some patch descriptions

David Hildenbrand (10):
s390x/tcg: ASI/ASGI are atomic with interlocked-acccess facility 1 s390x/tcg: ALSI/ALSGI are atomic with interlocked-acccess facility 1 s390x/tcg: implement Interlocked-Access Facility 2 s390x/tcg: wire up SET ADDRESS LIMIT
s390x/tcg: wire up SET CHANNEL MONITOR
s390x/tcg: Implement STORE CHANNEL PATH STATUS
s390x/tcg: Implement SIGNAL ADAPTER instruction s390x/tcg: implement extract-CPU-time facility
s390x/tcg: we already implement the Set-Program-Parameter facility
s390x: change the QEMU cpu model to a stripped down z12

 hw/s390x/s390-virtio-ccw.c  |   8 ++++
 target/s390x/cpu.h          |   3 ++
 target/s390x/cpu_models.c   |  97 +++++++++++++++++----------------------
 target/s390x/cpu_models.h   |   1 +
 target/s390x/gen-features.c |  87 +++++++++++++++++++++++++++++++++++
 target/s390x/helper.h       |   2 +
 target/s390x/insn-data.def  |  26 +++++++----
 target/s390x/misc_helper.c  |  18 ++++++++
 target/s390x/translate.c    | 109 ++++++++++++++++++++++++++++++++++++++++++++
 9 files changed, 285 insertions(+), 66 deletions(-)

Signature · 1 line

2.14.3

David Hildenbrand

author

2017-12-07 16:54 UTC #1 lore raw

PATCH v2 1/10 s390x/tcg: ASI/ASGI are atomic with interlocked-acccess facility 1

The semantics of these operations changed. Let's implement them just like LOAD AND ADD, so they are atomic.

This fixes random crashes when booting a Linux kernel compiled for z196+ with SMP + MTTCG.

Signed-off-by David Hildenbrand <[email protected]>

---
 target/s390x/insn-data.def |  4 ++--
 target/s390x/translate.c   | 11 +++++++++++
 2 files changed, 13 insertions(+), 2 deletions(-)

target/s390x/insn-data.def +2 -2

index 43ab1963c8..57f2e5133f 100644
@@ -39,10 +39,10 @@
     C(0xb9d8, AHHLR,   RRF_a, HW,  r2_sr32, r3, new, r1_32h, add, adds32)
 /* ADD IMMEDIATE */
     C(0xc209, AFI,     RIL_a, EI,  r1, i2, new, r1_32, add, adds32)
-    C(0xeb6a, ASI,     SIY,   GIE, m1_32s, i2, new, m1_32, add, adds32)
+    D(0xeb6a, ASI,     SIY,   GIE, la1, i2, new, 0, asi, adds32, MO_TESL)
     C(0xecd8, AHIK,    RIE_d, DO,  r3, i2, new, r1_32, add, adds32)
     C(0xc208, AGFI,    RIL_a, EI,  r1, i2, r1, 0, add, adds64)
-    C(0xeb7a, AGSI,    SIY,   GIE, m1_64, i2, new, m1_64, add, adds64)
+    D(0xeb7a, AGSI,    SIY,   GIE, la1, i2, new, 0, asi, adds64, MO_TEQ)
     C(0xecd9, AGHIK,   RIE_d, DO,  r3, i2, r1, 0, add, adds64)
 /* ADD IMMEDIATE HIGH */
     C(0xcc08, AIH,     RIL_a, HW,  r1_sr32, i2, new, r1_32h, add, adds32)

target/s390x/translate.c +11 -0

index 5e051fdd03..79d2ee650c 100644
@@ -1364,6 +1364,17 @@ static ExitStatus op_addc(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
+static ExitStatus op_asi(DisasContext *s, DisasOps *o)
+{
+    o->in1 = tcg_temp_new_i64();
+    /* Perform the atomic addition in memory. */
+    tcg_gen_atomic_fetch_add_i64(o->in1, o->addr1, o->in2, get_mem_index(s),
+                                 s->insn->data);
+    /* However, we need to recompute the addition for setting CC.  */
+    tcg_gen_add_i64(o->out, o->in1, o->in2);
+    return NO_EXIT;
+}
+
 static ExitStatus op_aeb(DisasContext *s, DisasOps *o)
 {
     gen_helper_aeb(o->out, cpu_env, o->in1, o->in2);

Signature · 1 line

2.14.3

Richard Henderson

2017-12-07 23:41 UTC #2 lore raw

Re: [Qemu-devel] [PATCH v2 for-2.12 01/10] s390x/tcg: ASI/ASGI are atomic with interlocked-acccess facility 1

target/s390x/translate.c static ExitStatus op_addc(DisasContext *s, DisasOps *o) · line 1376

Quoted 10 lines · David Hildenbrand

target/s390x/translate.c +10 -0

+static ExitStatus op_asi(DisasContext *s, DisasOps *o)
+{
+    o->in1 = tcg_temp_new_i64();
+    /* Perform the atomic addition in memory. */
+    tcg_gen_atomic_fetch_add_i64(o->in1, o->addr1, o->in2, get_mem_index(s),
+                                 s->insn->data);
+    /* However, we need to recompute the addition for setting CC.  */
+    tcg_gen_add_i64(o->out, o->in1, o->in2);
+    return NO_EXIT;
+}

Is it worth conditionalizing the atomic operation on having interlocked-access-facility-1 enabled?

David Hildenbrand

author

2017-12-08 12:51 UTC #3 lore raw

Re: [Qemu-devel] [PATCH v2 for-2.12 01/10] s390x/tcg: ASI/ASGI are atomic with interlocked-acccess facility 1

Quoted 15 lines · Richard Henderson

target/s390x/translate.c static ExitStatus op_addc(DisasContext *s, DisasOps *o) · line 1376
Quoted 10 lines · David Hildenbrand
target/s390x/translate.c +10 -0
+static ExitStatus op_asi(DisasContext *s, DisasOps *o)
+{
+    o->in1 = tcg_temp_new_i64();
+    /* Perform the atomic addition in memory. */
+    tcg_gen_atomic_fetch_add_i64(o->in1, o->addr1, o->in2, get_mem_index(s),
+                                 s->insn->data);
+    /* However, we need to recompute the addition for setting CC.  */
+    tcg_gen_add_i64(o->out, o->in1, o->in2);
+    return NO_EXIT;
+}
Is it worth conditionalizing the atomic operation on having interlocked-access-facility-1 enabled?

Should be easily doable with a few LOC. Will give it a shot.

Quoted 3 lines

r~

Signature · 3 lines

Thanks,

David / dhildenb

David Hildenbrand

author

2017-12-07 16:54 UTC #4 lore raw

PATCH v2 2/10 s390x/tcg: ALSI/ALSGI are atomic with interlocked-acccess facility 1

In reply to David Hildenbrand

We can simply reuse our ASI implementation. Only the way CC is calculated differs.

Signed-off-by David Hildenbrand <[email protected]>

---
 target/s390x/insn-data.def | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

target/s390x/insn-data.def +2 -2

index 57f2e5133f..166ee7c80b 100644
@@ -70,9 +70,9 @@
     C(0xc20b, ALFI,    RIL_a, EI,  r1, i2_32u, new, r1_32, add, addu32)
     C(0xc20a, ALGFI,   RIL_a, EI,  r1, i2_32u, r1, 0, add, addu64)
 /* ADD LOGICAL WITH SIGNED IMMEDIATE */
-    C(0xeb6e, ALSI,    SIY,   GIE, m1_32u, i2, new, m1_32, add, addu32)
+    D(0xeb6e, ALSI,    SIY,   GIE, la1, i2, new, 0, asi, addu32, MO_TEUL)
     C(0xecda, ALHSIK,  RIE_d, DO,  r3, i2, new, r1_32, add, addu32)
-    C(0xeb7e, ALGSI,   SIY,   GIE, m1_64, i2, new, m1_64, add, addu64)
+    D(0xeb7e, ALGSI,   SIY,   GIE, la1, i2, new, 0, asi, addu64, MO_TEQ)
     C(0xecdb, ALGHSIK, RIE_d, DO,  r3, i2, r1, 0, add, addu64)
 /* ADD LOGICAL WITH SIGNED IMMEDIATE HIGH */
     C(0xcc0a, ALSIH,   RIL_a, HW,  r1_sr32, i2, new, r1_32h, add, addu32)

Signature · 1 line

2.14.3

Richard Henderson

2017-12-07 23:43 UTC #5 lore raw

Re: [Qemu-devel] [PATCH v2 for-2.12 02/10] s390x/tcg: ALSI/ALSGI are atomic with interlocked-acccess facility 1

Quoted 7 lines · David Hildenbrand

We can simply reuse our ASI implementation. Only the way CC is calculated differs.
Signed-off-by David Hildenbrand <[email protected]>
---
 target/s390x/insn-data.def | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Squash with previous?

David Hildenbrand

author

2017-12-08 12:52 UTC #6 lore raw

Re: [Qemu-devel] [PATCH v2 for-2.12 02/10] s390x/tcg: ALSI/ALSGI are atomic with interlocked-acccess facility 1

Quoted 10 lines · Richard Henderson

Quoted 7 lines · David Hildenbrand
We can simply reuse our ASI implementation. Only the way CC is calculated differs.
Signed-off-by David Hildenbrand <[email protected]>
---
 target/s390x/insn-data.def | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
Squash with previous?

Yes, can do that!

Quoted 4 lines

r~

Signature · 3 lines

Thanks,

David / dhildenb

David Hildenbrand

author

2017-12-07 16:54 UTC #7 lore raw

PATCH v2 3/10 s390x/tcg: implement Interlocked-Access Facility 2

In reply to David Hildenbrand

With this facility, OI/OIY, NI/NIY and XI/XIY are atomic. All operate on one byte (MO_UB).

Signed-off-by David Hildenbrand <[email protected]>

---
 target/s390x/cpu_models.c  |  1 +
 target/s390x/insn-data.def | 12 ++++++------
 target/s390x/translate.c   | 33 +++++++++++++++++++++++++++++++++
 3 files changed, 40 insertions(+), 6 deletions(-)

target/s390x/cpu_models.c +1 -0

index c4c37b3b15..94d24e423d 100644
@@ -842,6 +842,7 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
         S390_FEAT_STFLE_45,
         S390_FEAT_STFLE_49,
         S390_FEAT_LOCAL_TLB_CLEARING,
+        S390_FEAT_INTERLOCKED_ACCESS_2,
         S390_FEAT_STFLE_53,
         S390_FEAT_MSA_EXT_5,
         S390_FEAT_MSA_EXT_3,

target/s390x/insn-data.def +6 -6

index 166ee7c80b..4e6dd6e348 100644
@@ -99,8 +99,8 @@
     D(0xa505, NIHL,    RI_a,  Z,   r1_o, i2_16u, r1, 0, andi, 0, 0x1020)
     D(0xa506, NILH,    RI_a,  Z,   r1_o, i2_16u, r1, 0, andi, 0, 0x1010)
     D(0xa507, NILL,    RI_a,  Z,   r1_o, i2_16u, r1, 0, andi, 0, 0x1000)
-    C(0x9400, NI,      SI,    Z,   m1_8u, i2_8u, new, m1_8, and, nz64)
-    C(0xeb54, NIY,     SIY,   LD,  m1_8u, i2_8u, new, m1_8, and, nz64)
+    C(0x9400, NI,      SI,    Z,   la1, i2_8u, new, 0, ni, nz64)
+    C(0xeb54, NIY,     SIY,   LD,  la1, i2_8u, new, 0, ni, nz64)
 
 /* BRANCH AND SAVE */
     C(0x0d00, BASR,    RR_a,  Z,   0, r2_nz, r1, 0, bas, 0)

@@ -357,8 +357,8 @@
 /* EXCLUSIVE OR IMMEDIATE */
     D(0xc006, XIHF,    RIL_a, EI,  r1_o, i2_32u, r1, 0, xori, 0, 0x2020)
     D(0xc007, XILF,    RIL_a, EI,  r1_o, i2_32u, r1, 0, xori, 0, 0x2000)
-    C(0x9700, XI,      SI,    Z,   m1_8u, i2_8u, new, m1_8, xor, nz64)
-    C(0xeb57, XIY,     SIY,   LD,  m1_8u, i2_8u, new, m1_8, xor, nz64)
+    C(0x9700, XI,      SI,    Z,   la1, i2_8u, new, 0, xi, nz64)
+    C(0xeb57, XIY,     SIY,   LD,  la1, i2_8u, new, 0, xi, nz64)
 
 /* EXECUTE */
     C(0x4400, EX,      RX_a,  Z,   0, a2, 0, 0, ex, 0)

@@ -698,8 +698,8 @@
     D(0xa509, OIHL,    RI_a,  Z,   r1_o, i2_16u, r1, 0, ori, 0, 0x1020)
     D(0xa50a, OILH,    RI_a,  Z,   r1_o, i2_16u, r1, 0, ori, 0, 0x1010)
     D(0xa50b, OILL,    RI_a,  Z,   r1_o, i2_16u, r1, 0, ori, 0, 0x1000)
-    C(0x9600, OI,      SI,    Z,   m1_8u, i2_8u, new, m1_8, or, nz64)
-    C(0xeb56, OIY,     SIY,   LD,  m1_8u, i2_8u, new, m1_8, or, nz64)
+    C(0x9600, OI,      SI,    Z,   la1, i2_8u, new, 0, oi, nz64)
+    C(0xeb56, OIY,     SIY,   LD,  la1, i2_8u, new, 0, oi, nz64)
 
 /* PACK */
     /* Really format SS_b, but we pack both lengths into one argument

target/s390x/translate.c +33 -0

index 79d2ee650c..edfe51b5c3 100644
@@ -1417,6 +1417,17 @@ static ExitStatus op_andi(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
+static ExitStatus op_ni(DisasContext *s, DisasOps *o)
+{
+    o->in1 = tcg_temp_new_i64();
+    /* Perform the atomic operation in memory. */
+    tcg_gen_atomic_fetch_and_i64(o->in1, o->addr1, o->in2, get_mem_index(s),
+                                 MO_UB);
+    /* We need to recompute the operation for setting CC.  */
+    tcg_gen_and_i64(o->out, o->in1, o->in2);
+    return NO_EXIT;
+}
+
 static ExitStatus op_bas(DisasContext *s, DisasOps *o)
 {
     tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));

@@ -3368,6 +3379,17 @@ static ExitStatus op_ori(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
+static ExitStatus op_oi(DisasContext *s, DisasOps *o)
+{
+    o->in1 = tcg_temp_new_i64();
+    /* Perform the atomic operation in memory. */
+    tcg_gen_atomic_fetch_or_i64(o->in1, o->addr1, o->in2, get_mem_index(s),
+                                MO_UB);
+    /* We need to recompute the operation for setting CC.  */
+    tcg_gen_or_i64(o->out, o->in1, o->in2);
+    return NO_EXIT;
+}
+
 static ExitStatus op_pack(DisasContext *s, DisasOps *o)
 {
     TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));

@@ -4633,6 +4655,17 @@ static ExitStatus op_xori(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
+static ExitStatus op_xi(DisasContext *s, DisasOps *o)
+{
+    o->in1 = tcg_temp_new_i64();
+    /* Perform the atomic operation in memory. */
+    tcg_gen_atomic_fetch_xor_i64(o->in1, o->addr1, o->in2, get_mem_index(s),
+                                 MO_UB);
+    /* We need to recompute the operation for setting CC.  */
+    tcg_gen_xor_i64(o->out, o->in1, o->in2);
+    return NO_EXIT;
+}
+
 static ExitStatus op_zero(DisasContext *s, DisasOps *o)
 {
     o->out = tcg_const_i64(0);

Signature · 1 line

2.14.3

Richard Henderson

2017-12-07 23:44 UTC #8 lore raw

Re: [Qemu-devel] [PATCH v2 for-2.12 03/10] s390x/tcg: implement Interlocked-Access Facility 2

target/s390x/translate.c static ExitStatus op_andi(DisasContext *s, DisasOps *o) · line 1429

Quoted 10 lines · David Hildenbrand

target/s390x/translate.c +10 -0

+static ExitStatus op_ni(DisasContext *s, DisasOps *o)
+{
+    o->in1 = tcg_temp_new_i64();
+    /* Perform the atomic operation in memory. */
+    tcg_gen_atomic_fetch_and_i64(o->in1, o->addr1, o->in2, get_mem_index(s),
+                                 MO_UB);
+    /* We need to recompute the operation for setting CC.  */
+    tcg_gen_and_i64(o->out, o->in1, o->in2);
+    return NO_EXIT;
+}

Similarly, check interlocked-access-facility-2?

David Hildenbrand

author

2017-12-07 16:54 UTC #9 lore raw

PATCH v2 4/10 s390x/tcg: wire up SET ADDRESS LIMIT

In reply to David Hildenbrand

Let's handle it just like KVM:
Depending on the model, this instruction may not be provided. When this instruction is not provided, it is checked for operand exception and privileged-opera- tion exception, and then is suppressed.

Signed-off-by David Hildenbrand <[email protected]>

---
 target/s390x/helper.h      | 1 +
 target/s390x/insn-data.def | 1 +
 target/s390x/misc_helper.c | 9 +++++++++
 target/s390x/translate.c   | 7 +++++++
 4 files changed, 18 insertions(+)

target/s390x/helper.h +1 -0

index 2ce57edc14..95ad44bc39 100644
@@ -165,6 +165,7 @@ DEF_HELPER_2(hsch, void, env, i64)
 DEF_HELPER_3(msch, void, env, i64, i64)
 DEF_HELPER_2(rchp, void, env, i64)
 DEF_HELPER_2(rsch, void, env, i64)
+DEF_HELPER_2(sal, void, env, i64)
 DEF_HELPER_3(ssch, void, env, i64, i64)
 DEF_HELPER_2(stcrw, void, env, i64)
 DEF_HELPER_3(stsch, void, env, i64, i64)

target/s390x/insn-data.def +1 -0

index 4e6dd6e348..8793350963 100644
@@ -1054,6 +1054,7 @@
     C(0xb232, MSCH,    S,     Z,   0, insn, 0, 0, msch, 0)
     C(0xb23b, RCHP,    S,     Z,   0, 0, 0, 0, rchp, 0)
     C(0xb238, RSCH,    S,     Z,   0, 0, 0, 0, rsch, 0)
+    C(0xb237, SAL,     S,     Z,   0, 0, 0, 0, sal, 0)
     C(0xb233, SSCH,    S,     Z,   0, insn, 0, 0, ssch, 0)
     C(0xb239, STCRW,   S,     Z,   0, insn, 0, 0, stcrw, 0)
     C(0xb234, STSCH,   S,     Z,   0, insn, 0, 0, stsch, 0)

target/s390x/misc_helper.c +9 -0

index 3541e47114..64bf37049e 100644
@@ -377,6 +377,15 @@ void HELPER(rsch)(CPUS390XState *env, uint64_t r1)
     qemu_mutex_unlock_iothread();
 }
 
+void HELPER(sal)(CPUS390XState *env, uint64_t r1)
+{
+    S390CPU *cpu = s390_env_get_cpu(env);
+
+    qemu_mutex_lock_iothread();
+    ioinst_handle_sal(cpu, r1, GETPC());
+    qemu_mutex_unlock_iothread();
+}
+
 void HELPER(ssch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
 {
     S390CPU *cpu = s390_env_get_cpu(env);

target/s390x/translate.c +7 -0

index edfe51b5c3..a6346ac139 100644
@@ -4088,6 +4088,13 @@ static ExitStatus op_rsch(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
+static ExitStatus op_sal(DisasContext *s, DisasOps *o)
+{
+    check_privileged(s);
+    gen_helper_sal(cpu_env, regs[1]);
+    return NO_EXIT;
+}
+
 static ExitStatus op_ssch(DisasContext *s, DisasOps *o)
 {
     check_privileged(s);

Signature · 1 line

2.14.3

Richard Henderson

Reviewed-by on v2 4/10

2017-12-07 23:46 UTC #10 lore raw

Re: [Qemu-devel] [PATCH v2 for-2.12 04/10] s390x/tcg: wire up SET ADDRESS LIMIT

Quoted 6 lines · David Hildenbrand

Let's handle it just like KVM:
Depending on the model, this instruction may not be provided. When this instruction is not provided, it is checked for operand exception and privileged-opera- tion exception, and then is suppressed.

Quoted 7 lines

Signed-off-by David Hildenbrand <[email protected]>

---
 target/s390x/helper.h      | 1 +
 target/s390x/insn-data.def | 1 +
 target/s390x/misc_helper.c | 9 +++++++++
 target/s390x/translate.c   | 7 +++++++
 4 files changed, 18 insertions(+)

Reviewed-by Richard Henderson <[email protected]>

David Hildenbrand

author

2017-12-07 16:54 UTC #11 lore raw

PATCH v2 5/10 s390x/tcg: wire up SET CHANNEL MONITOR

In reply to David Hildenbrand

Let's just wire it up like KVM.

Signed-off-by David Hildenbrand <[email protected]>

---
 target/s390x/helper.h      | 1 +
 target/s390x/insn-data.def | 1 +
 target/s390x/misc_helper.c | 9 +++++++++
 target/s390x/translate.c   | 7 +++++++
 4 files changed, 18 insertions(+)

target/s390x/helper.h +1 -0

index 95ad44bc39..e5282b939c 100644
@@ -166,6 +166,7 @@ DEF_HELPER_3(msch, void, env, i64, i64)
 DEF_HELPER_2(rchp, void, env, i64)
 DEF_HELPER_2(rsch, void, env, i64)
 DEF_HELPER_2(sal, void, env, i64)
+DEF_HELPER_4(schm, void, env, i64, i64, i64)
 DEF_HELPER_3(ssch, void, env, i64, i64)
 DEF_HELPER_2(stcrw, void, env, i64)
 DEF_HELPER_3(stsch, void, env, i64, i64)

target/s390x/insn-data.def +1 -0

index 8793350963..e21d226092 100644
@@ -1055,6 +1055,7 @@
     C(0xb23b, RCHP,    S,     Z,   0, 0, 0, 0, rchp, 0)
     C(0xb238, RSCH,    S,     Z,   0, 0, 0, 0, rsch, 0)
     C(0xb237, SAL,     S,     Z,   0, 0, 0, 0, sal, 0)
+    C(0xb23c, SCHM,    S,     Z,   0, insn, 0, 0, schm, 0)
     C(0xb233, SSCH,    S,     Z,   0, insn, 0, 0, ssch, 0)
     C(0xb239, STCRW,   S,     Z,   0, insn, 0, 0, stcrw, 0)
     C(0xb234, STSCH,   S,     Z,   0, insn, 0, 0, stsch, 0)

target/s390x/misc_helper.c +9 -0

index 64bf37049e..aeed2ba6a2 100644
@@ -386,6 +386,15 @@ void HELPER(sal)(CPUS390XState *env, uint64_t r1)
     qemu_mutex_unlock_iothread();
 }
 
+void HELPER(schm)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint64_t inst)
+{
+    S390CPU *cpu = s390_env_get_cpu(env);
+
+    qemu_mutex_lock_iothread();
+    ioinst_handle_schm(cpu, r1, r2, inst >> 16, GETPC());
+    qemu_mutex_unlock_iothread();
+}
+
 void HELPER(ssch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
 {
     S390CPU *cpu = s390_env_get_cpu(env);

target/s390x/translate.c +7 -0

index a6346ac139..bd3fc6448e 100644
@@ -4095,6 +4095,13 @@ static ExitStatus op_sal(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
+static ExitStatus op_schm(DisasContext *s, DisasOps *o)
+{
+    check_privileged(s);
+    gen_helper_schm(cpu_env, regs[1], regs[2], o->in2);
+    return NO_EXIT;
+}
+
 static ExitStatus op_ssch(DisasContext *s, DisasOps *o)
 {
     check_privileged(s);

Signature · 1 line

2.14.3

Richard Henderson

Reviewed-by on v2 5/10

2017-12-07 23:47 UTC #12 lore raw

Re: [Qemu-devel] [PATCH v2 for-2.12 05/10] s390x/tcg: wire up SET CHANNEL MONITOR

Quoted 9 lines · David Hildenbrand

Let's just wire it up like KVM.
Signed-off-by David Hildenbrand <[email protected]>
---
 target/s390x/helper.h      | 1 +
 target/s390x/insn-data.def | 1 +
 target/s390x/misc_helper.c | 9 +++++++++
 target/s390x/translate.c   | 7 +++++++
 4 files changed, 18 insertions(+)

Reviewed-by Richard Henderson <[email protected]>

David Hildenbrand

author

2017-12-07 16:54 UTC #13 lore raw

PATCH v2 6/10 s390x/tcg: Implement STORE CHANNEL PATH STATUS

In reply to David Hildenbrand

Just like KVM does, we should suppress this instruction:
When this instruction is not provided, it is checked for privileged operation exception and the instruction is suppressed by the machine

Signed-off-by David Hildenbrand <[email protected]>

---
 target/s390x/insn-data.def | 1 +
 target/s390x/translate.c   | 7 +++++++
 2 files changed, 8 insertions(+)

target/s390x/insn-data.def +1 -0

index e21d226092..c7353e7f11 100644
@@ -1056,6 +1056,7 @@
     C(0xb238, RSCH,    S,     Z,   0, 0, 0, 0, rsch, 0)
     C(0xb237, SAL,     S,     Z,   0, 0, 0, 0, sal, 0)
     C(0xb23c, SCHM,    S,     Z,   0, insn, 0, 0, schm, 0)
+    C(0xb23a, STCPS,   S,     Z,   0, 0, 0, 0, stcps, 0)
     C(0xb233, SSCH,    S,     Z,   0, insn, 0, 0, ssch, 0)
     C(0xb239, STCRW,   S,     Z,   0, insn, 0, 0, stcrw, 0)
     C(0xb234, STSCH,   S,     Z,   0, insn, 0, 0, stsch, 0)

target/s390x/translate.c +7 -0

index bd3fc6448e..5c2432678c 100644
@@ -4102,6 +4102,13 @@ static ExitStatus op_schm(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
+static ExitStatus op_stcps(DisasContext *s, DisasOps *o)
+{
+    check_privileged(s);
+    /* The instruction is suppressed if not provided. */
+    return NO_EXIT;
+}
+
 static ExitStatus op_ssch(DisasContext *s, DisasOps *o)
 {
     check_privileged(s);

Signature · 1 line

2.14.3

Richard Henderson

Reviewed-by on v2 6/10

2017-12-07 23:48 UTC #14 lore raw

Re: [Qemu-devel] [PATCH v2 for-2.12 06/10] s390x/tcg: Implement STORE CHANNEL PATH STATUS

Quoted 10 lines · David Hildenbrand

Just like KVM does, we should suppress this instruction:
When this instruction is not provided, it is checked for privileged operation exception and the instruction is suppressed by the machine
Signed-off-by David Hildenbrand <[email protected]>
---
 target/s390x/insn-data.def | 1 +
 target/s390x/translate.c   | 7 +++++++
 2 files changed, 8 insertions(+)

Reviewed-by Richard Henderson <[email protected]>

David Hildenbrand

author

2017-12-07 16:54 UTC #15 lore raw

PATCH v2 7/10 s390x/tcg: Implement SIGNAL ADAPTER instruction

In reply to David Hildenbrand

KVM suppresses SIGA, setting cc=3. Let's do the same for TCG, so we're at least equal.

Signed-off-by David Hildenbrand <[email protected]>

---
 target/s390x/insn-data.def | 1 +
 target/s390x/translate.c   | 8 ++++++++
 2 files changed, 9 insertions(+)

target/s390x/insn-data.def +1 -0

index c7353e7f11..f7b66b0091 100644
@@ -1056,6 +1056,7 @@
     C(0xb238, RSCH,    S,     Z,   0, 0, 0, 0, rsch, 0)
     C(0xb237, SAL,     S,     Z,   0, 0, 0, 0, sal, 0)
     C(0xb23c, SCHM,    S,     Z,   0, insn, 0, 0, schm, 0)
+    C(0xb274, SIGA,    S,     Z,   0, 0, 0, 0, siga, 0)
     C(0xb23a, STCPS,   S,     Z,   0, 0, 0, 0, stcps, 0)
     C(0xb233, SSCH,    S,     Z,   0, insn, 0, 0, ssch, 0)
     C(0xb239, STCRW,   S,     Z,   0, insn, 0, 0, stcrw, 0)

target/s390x/translate.c +8 -0

index 5c2432678c..1e4079464a 100644
@@ -4102,6 +4102,14 @@ static ExitStatus op_schm(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
+static ExitStatus op_siga(DisasContext *s, DisasOps *o)
+{
+    check_privileged(s);
+    /* From KVM code: Not provided, set CC = 3 for subchannel not operational */
+    gen_op_movi_cc(s, 3);
+    return NO_EXIT;
+}
+
 static ExitStatus op_stcps(DisasContext *s, DisasOps *o)
 {
     check_privileged(s);

Signature · 1 line

2.14.3

Richard Henderson

Reviewed-by on v2 7/10

2017-12-07 23:49 UTC #16 lore raw

Re: [Qemu-devel] [PATCH v2 for-2.12 07/10] s390x/tcg: Implement SIGNAL ADAPTER instruction

Quoted 8 lines · David Hildenbrand

KVM suppresses SIGA, setting cc=3. Let's do the same for TCG, so we're at least equal.
Signed-off-by David Hildenbrand <[email protected]>
---
 target/s390x/insn-data.def | 1 +
 target/s390x/translate.c   | 8 ++++++++
 2 files changed, 9 insertions(+)

Reviewed-by Richard Henderson <[email protected]>

David Hildenbrand

author

2017-12-07 16:54 UTC #17 lore raw

PATCH v2 8/10 s390x/tcg: implement extract-CPU-time facility

In reply to David Hildenbrand

It only provides the EXTRACT CPU TIME instruction. We can reuse the stpt helper, which calculates the CPU timer value.

As the instruction is not privileged, but we don't have a CPU timer value in case of linux user, we simply fake the CPU timer to be 0.

Signed-off-by David Hildenbrand <[email protected]>

---
 target/s390x/cpu_models.c  |  1 +
 target/s390x/insn-data.def |  2 ++
 target/s390x/translate.c   | 36 ++++++++++++++++++++++++++++++++++++
 3 files changed, 39 insertions(+)

target/s390x/cpu_models.c +1 -0

index 94d24e423d..0be037eac1 100644
@@ -834,6 +834,7 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
         S390_FEAT_STORE_CLOCK_FAST,
         S390_FEAT_MOVE_WITH_OPTIONAL_SPEC,
         S390_FEAT_ETF3_ENH,
+        S390_FEAT_EXTRACT_CPU_TIME,
         S390_FEAT_COMPARE_AND_SWAP_AND_STORE,
         S390_FEAT_COMPARE_AND_SWAP_AND_STORE_2,
         S390_FEAT_GENERAL_INSTRUCTIONS_EXT,

target/s390x/insn-data.def +2 -0

index f7b66b0091..5e33bd27ff 100644
@@ -369,6 +369,8 @@
     C(0xb24f, EAR,     RRE,   Z,   0, 0, new, r1_32, ear, 0)
 /* EXTRACT CPU ATTRIBUTE */
     C(0xeb4c, ECAG,    RSY_a, GIE, 0, a2, r1, 0, ecag, 0)
+/* EXTRACT CPU TIME */
+    C(0xc801, ECTG,    SSF,   ECT, 0, 0, 0, 0, ectg, 0)
 /* EXTRACT FPC */
     C(0xb38c, EFPC,    RRE,   Z,   0, 0, new, r1_32, efpc, 0)
 /* EXTRACT PSW */

target/s390x/translate.c +36 -0

index 1e4079464a..e0f55fc8e9 100644
@@ -3887,6 +3887,41 @@ static ExitStatus op_spm(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
+static ExitStatus op_ectg(DisasContext *s, DisasOps *o)
+{
+    int b1 = get_field(s->fields, b1);
+    int d1 = get_field(s->fields, d1);
+    int b2 = get_field(s->fields, b2);
+    int d2 = get_field(s->fields, d2);
+    int r3 = get_field(s->fields, r3);
+    TCGv_i64 tmp = tcg_temp_new_i64();
+
+    /* fetch all operands first */
+    o->in1 = tcg_temp_new_i64();
+    tcg_gen_addi_i64(o->in1, regs[b1], d1);
+    o->in2 = tcg_temp_new_i64();
+    tcg_gen_addi_i64(o->in2, regs[b2], d2);
+    o->addr1 = get_address(s, 0, r3, 0);
+
+    /* load the third operand into r3 before modifying anything */
+    tcg_gen_qemu_ld64(regs[r3], o->addr1, get_mem_index(s));
+
+#ifndef CONFIG_USER_ONLY
+    /* subtract CPU timer from first operand and store in GR0 */
+    gen_helper_stpt(tmp, cpu_env);
+    tcg_gen_sub_i64(regs[0], o->in1, tmp);
+#else
+    /* we don't have a CPU timer, fake value 0 */
+    tcg_gen_mov_i64(regs[0], o->in1);
+#endif
+
+    /* store second operand in GR1 */
+    tcg_gen_mov_i64(regs[1], o->in2);
+
+    tcg_temp_free_i64(tmp);
+    return NO_EXIT;
+}
+
 #ifndef CONFIG_USER_ONLY
 static ExitStatus op_spka(DisasContext *s, DisasOps *o)
 {

@@ -5639,6 +5674,7 @@ enum DisasInsnEnum {
 #define FAC_MSA3        S390_FEAT_MSA_EXT_3 /* msa-extension-3 facility */
 #define FAC_MSA4        S390_FEAT_MSA_EXT_4 /* msa-extension-4 facility */
 #define FAC_MSA5        S390_FEAT_MSA_EXT_5 /* msa-extension-5 facility */
+#define FAC_ECT         S390_FEAT_EXTRACT_CPU_TIME
 
 static const DisasInsn insn_info[] = {
 #include "insn-data.def"

Signature · 1 line

2.14.3

Richard Henderson

2017-12-07 23:54 UTC #18 lore raw

Re: [Qemu-devel] [PATCH v2 for-2.12 08/10] s390x/tcg: implement extract-CPU-time facility

Quoted 63 lines · David Hildenbrand

It only provides the EXTRACT CPU TIME instruction. We can reuse the stpt helper, which calculates the CPU timer value.

As the instruction is not privileged, but we don't have a CPU timer value in case of linux user, we simply fake the CPU timer to be 0.

Signed-off-by David Hildenbrand <[email protected]>

---
 target/s390x/cpu_models.c  |  1 +
 target/s390x/insn-data.def |  2 ++
 target/s390x/translate.c   | 36 ++++++++++++++++++++++++++++++++++++
 3 files changed, 39 insertions(+)

target/s390x/cpu_models.c +1 -0

index 94d24e423d..0be037eac1 100644
@@ -834,6 +834,7 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
         S390_FEAT_STORE_CLOCK_FAST,
         S390_FEAT_MOVE_WITH_OPTIONAL_SPEC,
         S390_FEAT_ETF3_ENH,
+        S390_FEAT_EXTRACT_CPU_TIME,
         S390_FEAT_COMPARE_AND_SWAP_AND_STORE,
         S390_FEAT_COMPARE_AND_SWAP_AND_STORE_2,
         S390_FEAT_GENERAL_INSTRUCTIONS_EXT,

target/s390x/insn-data.def +2 -0

index f7b66b0091..5e33bd27ff 100644
@@ -369,6 +369,8 @@
     C(0xb24f, EAR,     RRE,   Z,   0, 0, new, r1_32, ear, 0)
 /* EXTRACT CPU ATTRIBUTE */
     C(0xeb4c, ECAG,    RSY_a, GIE, 0, a2, r1, 0, ecag, 0)
+/* EXTRACT CPU TIME */
+    C(0xc801, ECTG,    SSF,   ECT, 0, 0, 0, 0, ectg, 0)
 /* EXTRACT FPC */
     C(0xb38c, EFPC,    RRE,   Z,   0, 0, new, r1_32, efpc, 0)
 /* EXTRACT PSW */

target/s390x/translate.c +17 -0

index 1e4079464a..e0f55fc8e9 100644
@@ -3887,6 +3887,41 @@ static ExitStatus op_spm(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
+static ExitStatus op_ectg(DisasContext *s, DisasOps *o)
+{
+    int b1 = get_field(s->fields, b1);
+    int d1 = get_field(s->fields, d1);
+    int b2 = get_field(s->fields, b2);
+    int d2 = get_field(s->fields, d2);
+    int r3 = get_field(s->fields, r3);
+    TCGv_i64 tmp = tcg_temp_new_i64();
+
+    /* fetch all operands first */
+    o->in1 = tcg_temp_new_i64();
+    tcg_gen_addi_i64(o->in1, regs[b1], d1);
+    o->in2 = tcg_temp_new_i64();
+    tcg_gen_addi_i64(o->in2, regs[b2], d2);
+    o->addr1 = get_address(s, 0, r3, 0);
+
+    /* load the third operand into r3 before modifying anything */

target/s390x/translate.c static ExitStatus op_spm(DisasContext *s, DisasOps *o) · line 3916

Quoted 10 lines

target/s390x/translate.c +10 -0

+    tcg_gen_qemu_ld64(regs[r3], o->addr1, get_mem_index(s));
+
+#ifndef CONFIG_USER_ONLY
+    /* subtract CPU timer from first operand and store in GR0 */
+    gen_helper_stpt(tmp, cpu_env);
+    tcg_gen_sub_i64(regs[0], o->in1, tmp);
+#else
+    /* we don't have a CPU timer, fake value 0 */
+    tcg_gen_mov_i64(regs[0], o->in1);
+#endif

It's easy enough to pass along cpu_get_host_ticks() for user-only. Possibly not quite right, but better than nothing.

David Hildenbrand

author

2017-12-08 15:03 UTC #19 lore raw

Re: [Qemu-devel] [PATCH v2 for-2.12 08/10] s390x/tcg: implement extract-CPU-time facility

Quoted 79 lines · Richard Henderson

Quoted 63 lines · David Hildenbrand

It only provides the EXTRACT CPU TIME instruction. We can reuse the stpt helper, which calculates the CPU timer value.

As the instruction is not privileged, but we don't have a CPU timer value in case of linux user, we simply fake the CPU timer to be 0.

Signed-off-by David Hildenbrand <[email protected]>

---
 target/s390x/cpu_models.c  |  1 +
 target/s390x/insn-data.def |  2 ++
 target/s390x/translate.c   | 36 ++++++++++++++++++++++++++++++++++++
 3 files changed, 39 insertions(+)

target/s390x/cpu_models.c +1 -0

index 94d24e423d..0be037eac1 100644
@@ -834,6 +834,7 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
         S390_FEAT_STORE_CLOCK_FAST,
         S390_FEAT_MOVE_WITH_OPTIONAL_SPEC,
         S390_FEAT_ETF3_ENH,
+        S390_FEAT_EXTRACT_CPU_TIME,
         S390_FEAT_COMPARE_AND_SWAP_AND_STORE,
         S390_FEAT_COMPARE_AND_SWAP_AND_STORE_2,
         S390_FEAT_GENERAL_INSTRUCTIONS_EXT,

target/s390x/insn-data.def +2 -0

index f7b66b0091..5e33bd27ff 100644
@@ -369,6 +369,8 @@
     C(0xb24f, EAR,     RRE,   Z,   0, 0, new, r1_32, ear, 0)
 /* EXTRACT CPU ATTRIBUTE */
     C(0xeb4c, ECAG,    RSY_a, GIE, 0, a2, r1, 0, ecag, 0)
+/* EXTRACT CPU TIME */
+    C(0xc801, ECTG,    SSF,   ECT, 0, 0, 0, 0, ectg, 0)
 /* EXTRACT FPC */
     C(0xb38c, EFPC,    RRE,   Z,   0, 0, new, r1_32, efpc, 0)
 /* EXTRACT PSW */

target/s390x/translate.c +17 -0

index 1e4079464a..e0f55fc8e9 100644
@@ -3887,6 +3887,41 @@ static ExitStatus op_spm(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
+static ExitStatus op_ectg(DisasContext *s, DisasOps *o)
+{
+    int b1 = get_field(s->fields, b1);
+    int d1 = get_field(s->fields, d1);
+    int b2 = get_field(s->fields, b2);
+    int d2 = get_field(s->fields, d2);
+    int r3 = get_field(s->fields, r3);
+    TCGv_i64 tmp = tcg_temp_new_i64();
+
+    /* fetch all operands first */
+    o->in1 = tcg_temp_new_i64();
+    tcg_gen_addi_i64(o->in1, regs[b1], d1);
+    o->in2 = tcg_temp_new_i64();
+    tcg_gen_addi_i64(o->in2, regs[b2], d2);
+    o->addr1 = get_address(s, 0, r3, 0);
+
+    /* load the third operand into r3 before modifying anything */

target/s390x/translate.c static ExitStatus op_spm(DisasContext *s, DisasOps *o) · line 3916

Quoted 10 lines

target/s390x/translate.c +10 -0

+    tcg_gen_qemu_ld64(regs[r3], o->addr1, get_mem_index(s));
+
+#ifndef CONFIG_USER_ONLY
+    /* subtract CPU timer from first operand and store in GR0 */
+    gen_helper_stpt(tmp, cpu_env);
+    tcg_gen_sub_i64(regs[0], o->in1, tmp);
+#else
+    /* we don't have a CPU timer, fake value 0 */
+    tcg_gen_mov_i64(regs[0], o->in1);
+#endif

It's easy enough to pass along cpu_get_host_ticks() for user-only. Possibly not quite right, but better than nothing.

Quoted 2 lines

r~

What about this:

+/* Store CPU Timer (also used for EXTRACT CPU TIME) */ +uint64_t HELPER(stpt)(CPUS390XState *env)
+{
+#if defined(CONFIG_USER_ONLY)
+ /*

+     * Fake a descending CPU timer. We could get negative values here,
+     * but we don't care as it is up to the OS when to process that
+     * interrupt and reset to > 0.
+     */

+ return UINT64_MAX - (uint64_t)cpu_get_host_ticks();
+#else
+ return time2tod(env->cputm - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
+#endif
+}
+

Signature · 3 lines

Thanks,

David / dhildenb

Richard Henderson

2017-12-08 15:12 UTC #20 lore raw

Re: [Qemu-devel] [PATCH v2 for-2.12 08/10] s390x/tcg: implement extract-CPU-time facility

Quoted 6 lines · David Hildenbrand

(quoted diff) +5 -0

+/* Store CPU Timer (also used for EXTRACT CPU TIME) */
+uint64_t HELPER(stpt)(CPUS390XState *env)
+{
+#if defined(CONFIG_USER_ONLY)
+    /*

Review

Quoted 10 lines

(quoted diff) +10 -0

+     * Fake a descending CPU timer. We could get negative values here,
+     * but we don't care as it is up to the OS when to process that
+     * interrupt and reset to > 0.
+     */
+    return UINT64_MAX - (uint64_t)cpu_get_host_ticks();
+#else
+    return time2tod(env->cputm - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
+#endif
+}
+

Looks good to me.

David Hildenbrand

author

2017-12-07 16:55 UTC #21 lore raw

PATCH v2 9/10 s390x/tcg: we already implement the Set-Program-Parameter facility

In reply to David Hildenbrand

The Set-Program-Parameter facility (also known as Load-Program-Parameter facility) provides the LPP instruction used to load the program parameter. We already implement that instruction in TCG, so add it to our list.

Note: Not documented in the PoP but in "The Load-Program-Parameter and CPU-Measurement Facilities) - SA23-2260-05 document.

While at it, make the whole list ordered (according to cpu_features_def.h).

Signed-off-by David Hildenbrand <[email protected]>

---
 target/s390x/cpu_models.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

target/s390x/cpu_models.c +3 -2

index 0be037eac1..edac7fdecf 100644
@@ -824,12 +824,12 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
         S390_FEAT_IDTE_SEGMENT,
         S390_FEAT_STFLE,
         S390_FEAT_SENSE_RUNNING_STATUS,
-        S390_FEAT_EXTENDED_IMMEDIATE,
         S390_FEAT_EXTENDED_TRANSLATION_2,
         S390_FEAT_MSA,
-        S390_FEAT_EXTENDED_TRANSLATION_3,
         S390_FEAT_LONG_DISPLACEMENT,
         S390_FEAT_LONG_DISPLACEMENT_FAST,
+        S390_FEAT_EXTENDED_IMMEDIATE,
+        S390_FEAT_EXTENDED_TRANSLATION_3,
         S390_FEAT_ETF2_ENH,
         S390_FEAT_STORE_CLOCK_FAST,
         S390_FEAT_MOVE_WITH_OPTIONAL_SPEC,

@@ -839,6 +839,7 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
         S390_FEAT_COMPARE_AND_SWAP_AND_STORE_2,
         S390_FEAT_GENERAL_INSTRUCTIONS_EXT,
         S390_FEAT_EXECUTE_EXT,
+        S390_FEAT_SET_PROGRAM_PARAMETERS,
         S390_FEAT_FLOATING_POINT_SUPPPORT_ENH,
         S390_FEAT_STFLE_45,
         S390_FEAT_STFLE_49,

Signature · 1 line

2.14.3

Richard Henderson

Reviewed-by on v2 9/10

2017-12-07 23:55 UTC #22 lore raw

Re: [Qemu-devel] [PATCH v2 for-2.12 09/10] s390x/tcg: we already implement the Set-Program-Parameter facility

Quoted 8 lines · David Hildenbrand

The Set-Program-Parameter facility (also known as Load-Program-Parameter facility) provides the LPP instruction used to load the program parameter. We already implement that instruction in TCG, so add it to our list.
Note: Not documented in the PoP but in "The Load-Program-Parameter and CPU-Measurement Facilities) - SA23-2260-05 document.

Quoted 6 lines

While at it, make the whole list ordered (according to cpu_features_def.h).
Signed-off-by David Hildenbrand <[email protected]>
---
 target/s390x/cpu_models.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

Reviewed-by Richard Henderson <[email protected]>

David Hildenbrand

author

2017-12-07 16:55 UTC #23 lore raw

PATCH v2 10/10 s390x: change the QEMU cpu model to a stripped down z12

In reply to David Hildenbrand

We are good enough to boot upstream Linux kernels / Fedora 26/27. That should be sufficient for now.

As the QEMU CPU model is migration safe, let's add compatibility code. Generate the feature list to reduce the chance of messing things up in the future.

Signed-off-by David Hildenbrand <[email protected]>

---
 hw/s390x/s390-virtio-ccw.c  |   8 ++++
 target/s390x/cpu.h          |   3 ++
 target/s390x/cpu_models.c   | 100 ++++++++++++++++++--------------------------
 target/s390x/cpu_models.h   |   1 +
 target/s390x/gen-features.c |  87 ++++++++++++++++++++++++++++++++++++++
 5 files changed, 140 insertions(+), 59 deletions(-)

hw/s390x/s390-virtio-ccw.c +8 -0

index a23b8aec9f..dbcfee5b1a 100644
@@ -721,6 +721,10 @@ bool css_migration_enabled(void)
 
 static void ccw_machine_2_12_instance_options(MachineState *machine)
 {
+    const S390FeatBitmap qemu_cpu_feat = { S390_FEAT_LIST_QEMU_V2_12 };
+
+    /* with 2.12 we emulated a stripped down zEC12 (GA 2) */
+    s390_set_qemu_cpu_model(0x2827, 12, 2, qemu_cpu_feat);
 }
 
 static void ccw_machine_2_12_class_options(MachineClass *mc)

@@ -730,7 +734,11 @@ DEFINE_CCW_MACHINE(2_12, "2.12", true);
 
 static void ccw_machine_2_11_instance_options(MachineState *machine)
 {
+    const S390FeatBitmap qemu_cpu_feat = { S390_FEAT_LIST_QEMU_V2_11 };
     ccw_machine_2_12_instance_options(machine);
+
+    /* before 2.12 we emulated the very first z900 */
+    s390_set_qemu_cpu_model(0x2064, 7, 1, qemu_cpu_feat);
 }
 
 static void ccw_machine_2_11_class_options(MachineClass *mc)

target/s390x/cpu.h +3 -0

index f29f4ccd8b..511b39cd17 100644
@@ -721,6 +721,9 @@ static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
 /* cpu_models.c */
 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 #define cpu_list s390_cpu_list
+void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
+                             const S390FeatBitmap features);
+
 
 /* helper.c */
 #define cpu_init(cpu_model) cpu_generic_init(TYPE_S390_CPU, cpu_model)

target/s390x/cpu_models.c +41 ~~-59~~

135 lines not on this page · raw message

target/s390x/cpu_models.h +1 -0

index 4c6dee1871..11cf5386fb 100644
@@ -14,6 +14,7 @@
 #define TARGET_S390X_CPU_MODELS_H
 
 #include "cpu_features.h"
+#include "gen-features.h"
 #include "qom/cpu.h"
 
 /* static CPU definition */

target/s390x/gen-features.c +87 -0

111 lines not on this page · raw message

Signature · 1 line

2.14.3

Richard Henderson

2017-12-07 23:58 UTC #24 lore raw

Re: [Qemu-devel] [PATCH v2 for-2.12 10/10] s390x: change the QEMU cpu model to a stripped down z12

Quoted 1 line · David Hildenbrand

+ const S390FeatBitmap qemu_cpu_feat = { S390_FEAT_LIST_QEMU_V2_12 };

static const?