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x86/MCE/AMD: Define a function to get SMCA bank type

PATCH New Borislav Petkov 1 participant 3 messages Dec 18, 2017 x86

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Borislav Petkov

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#0 lore raw

PATCH 1/3 x86/MCE/AMD: Define a function to get SMCA bank type

From: Yazen Ghannam <[email protected]>

Scalable MCA systems have various types of banks. The bank's type can determine how we handle errors from it. For example, if a bank represents a UMC (Unified Memory Controller) then we will need to convert its address from a normalized address to a system physical address before handling the error.

Signed-off-by Yazen Ghannam <[email protected]>
Cc Tony Luck <[email protected]>
Cc linux-edac <[email protected]>
Cc x86-ml <[email protected]>
Link http://lkml.kernel.org/r/[email protected] open here
[ Verify m->bank is within range and use bank pointer. ]
Signed-off-by Borislav Petkov <[email protected]>
---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
arch/x86/kernel/cpu/mcheck/mce_amd.c +14 -0
index a38ab1fa53a2..661c4738be27 100644
@@ -110,6 +110,20 @@ const char *smca_get_long_name(enum smca_bank_types t)
 }
 EXPORT_SYMBOL_GPL(smca_get_long_name);
 
+static enum smca_bank_types smca_get_bank_type(struct mce *m)
+{
+	struct smca_bank *b;
+
+	if (m->bank >= N_SMCA_BANK_TYPES)
+		return N_SMCA_BANK_TYPES;
+
+	b = &smca_banks[m->bank];
+	if (!b->hwid)
+		return N_SMCA_BANK_TYPES;
+
+	return b->hwid->bank_type;
+}
+
 static struct smca_hwid smca_hwid_mcatypes[] = {
 	/* { bank_type, hwid_mcatype, xec_bitmap } */
Signature · 1 line
2.13.0
author maintainer
#1 lore raw

PATCH 2/3 x86/MCE: Report only DRAM ECC as memory errors on AMD systems

From: Yazen Ghannam <[email protected]>

The MCA_STATUS[ErrorCodeExt] field is very bank type specific. We currently check if the ErrorCodeExt value is 0x0 or 0x8 in mce_is_memory_error(), but we don't check the bank number. This means that we could flag non-memory errors as memory errors.

We know that we want to flag DRAM ECC errors as memory errors, so let's do those cases first. We can add more cases later when needed.

Define a wrapper function in mce_amd.c so we can use SMCA enums.

Signed-off-by Yazen Ghannam <[email protected]>
Cc Tony Luck <[email protected]>
Cc linux-edac <[email protected]>
Cc x86-ml <[email protected]>
Link http://lkml.kernel.org/r/[email protected] open here
[ Remove brackets around return statements. ]
Signed-off-by Borislav Petkov <[email protected]>
---
 arch/x86/include/asm/mce.h           |  2 ++
 arch/x86/kernel/cpu/mcheck/mce.c     |  4 +---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 11 +++++++++++
 3 files changed, 14 insertions(+), 3 deletions(-)
arch/x86/include/asm/mce.h +2 -0
index b1e8d8db921f..96ea4b5ba658 100644
@@ -376,6 +376,7 @@ struct smca_bank {
 extern struct smca_bank smca_banks[MAX_NR_BANKS];
 
 extern const char *smca_get_long_name(enum smca_bank_types t);
+extern bool amd_mce_is_memory_error(struct mce *m);
 
 extern int mce_threshold_create_device(unsigned int cpu);
 extern int mce_threshold_remove_device(unsigned int cpu);

@@ -384,6 +385,7 @@ extern int mce_threshold_remove_device(unsigned int cpu);
 
 static inline int mce_threshold_create_device(unsigned int cpu) { return 0; };
 static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; };
+static inline bool amd_mce_is_memory_error(struct mce *m) { return false; };
 
 #endif
arch/x86/kernel/cpu/mcheck/mce.c +1 -3
index b1d616d08eee..321c7a80be66 100644
@@ -503,10 +503,8 @@ static int mce_usable_address(struct mce *m)
 bool mce_is_memory_error(struct mce *m)
 {
 	if (m->cpuvendor == X86_VENDOR_AMD) {
-		/* ErrCodeExt[20:16] */
-		u8 xec = (m->status >> 16) & 0x1f;
+		return amd_mce_is_memory_error(m);
 
-		return (xec == 0x0 || xec == 0x8);
 	} else if (m->cpuvendor == X86_VENDOR_INTEL) {
 		/*
 		 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
arch/x86/kernel/cpu/mcheck/mce_amd.c +11 -0
index 661c4738be27..0f32ad242324 100644
@@ -754,6 +754,17 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
 }
 EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr);
 
+bool amd_mce_is_memory_error(struct mce *m)
+{
+	/* ErrCodeExt[20:16] */
+	u8 xec = (m->status >> 16) & 0x1f;
+
+	if (mce_flags.smca)
+		return smca_get_bank_type(m) == SMCA_UMC && xec == 0x0;
+
+	return m->bank == 4 && xec == 0x8;
+}
+
 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
 {
 	struct mce m;
Signature · 1 line
2.13.0
author maintainer
#2 lore raw

PATCH 3/3 x86/MCE: Make correctable error detection look at the Deferred bit

In reply to Borislav Petkov

From: Yazen Ghannam <[email protected]>

AMD systems may log Deferred errors. These are errors that are uncorrected but which do not need immediate action. The MCA_STATUS[UC] bit may not be set for Deferred errors.

Flag the error as not correctable when MCA_STATUS[Deferred] is set and do not feed it into the Correctable Errors Collector.

Signed-off-by Yazen Ghannam <[email protected]>
Cc [email protected] # 4.13.x
Cc Tony Luck <[email protected]>
Cc linux-edac <[email protected]>
Cc x86-ml <[email protected]>
Link http://lkml.kernel.org/r/[email protected] open here
[ Massage commit message. ]
Signed-off-by Borislav Petkov <[email protected]>
---
 arch/x86/kernel/cpu/mcheck/mce.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)
arch/x86/kernel/cpu/mcheck/mce.c +12 -1
index 321c7a80be66..1b2c11473376 100644
@@ -528,6 +528,17 @@ bool mce_is_memory_error(struct mce *m)
 }
 EXPORT_SYMBOL_GPL(mce_is_memory_error);
 
+static bool mce_is_correctable(struct mce *m)
+{
+	if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
+		return false;
+
+	if (m->status & MCI_STATUS_UC)
+		return false;
+
+	return true;
+}
+
 static bool cec_add_mce(struct mce *m)
 {
 	if (!m)

@@ -535,7 +546,7 @@ static bool cec_add_mce(struct mce *m)
 
 	/* We eat only correctable DRAM errors with usable addresses. */
 	if (mce_is_memory_error(m) &&
-	    !(m->status & MCI_STATUS_UC) &&
+	    mce_is_correctable(m)  &&
 	    mce_usable_address(m))
 		if (!cec_add_elem(m->addr >> PAGE_SHIFT))
 			return true;
Signature · 1 line
2.13.0