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arm: am57xx: Add support for am574-idk

PATCH Superseded Lokesh Vutla 3 participants 28 messages Dec 18, 2017 – Jan 10, 2018

Subsystems (5)
Arm (32-bit) Arm sub-architectures OMAP2+ support dmaengine +1 more subsystems

v1 of 2 Superseded Latest is v2 →

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Lokesh Vutla

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#0 lore raw

cover arm: am57xx: Add support for am574-idk

am574x-idk board is similar to am572x-idk with am574x SoC. This series adds support for this board.

Logs: http://pastebin.ubuntu.com/26207045/

Lokesh Vutla (12):
arm: emif-common: Add ecc specific emif registers
arm: emif-common: Add suppport for enabling ECC
arm: keystone: Move cmd_ddr3 to a common place
arm: ti: Generalize cmd_ddr3 command
arm: dra762: Add support for device package identification
board: ti: am574x-idk: Add epprom support
board: ti: am574x-idk: Add hw data support
board: ti: am574x-idk: Add ddr data support
board: ti: am574x-idk: Update pinmux using latest PMT
board: ti: am57xx: Enable CMD_DDR3
ARM: dts: am574x-idk: Add initial support
env: ti: Select dtb name for dra76x and am574

Tero Kristo (1):
drivers: dma: ti-edma3: add support for memory fill

 arch/arm/dts/Makefile                              |   1 +
 arch/arm/dts/am572x-idk-common.dtsi                | 100 +++++++
 arch/arm/dts/am572x-idk.dts                        |  93 +------
 arch/arm/dts/am574x-idk.dts                        |  22 ++
 arch/arm/dts/am57xx-commercial-grade.dtsi          |   1 +
 arch/arm/dts/am57xx-industrial-grade.dtsi          |   1 +
 arch/arm/include/asm/arch-omap5/omap.h             |   3 +
 arch/arm/include/asm/arch-omap5/sys_proto.h        |   1 +
 arch/arm/include/asm/emif.h                        |  50 +++-
 arch/arm/include/asm/omap_common.h                 |  15 ++
 arch/arm/include/asm/ti-common/ti-edma3.h          |   2 +
 arch/arm/mach-keystone/Kconfig                     |   4 +
 arch/arm/mach-keystone/Makefile                    |   1 -
 arch/arm/mach-keystone/include/mach/hardware.h     |   1 +
 arch/arm/mach-omap2/emif-common.c                  |  95 ++++++-
 arch/arm/mach-omap2/hwinit-common.c                |  33 ++-
 arch/arm/mach-omap2/omap5/Kconfig                  |   1 +
 arch/arm/mach-omap2/omap5/hw_data.c                |   4 +
 arch/arm/mach-omap2/omap5/hwinit.c                 |  21 ++
 arch/arm/mach-omap2/omap5/sdram.c                  |   4 +
 board/ti/am57xx/board.c                            |  64 ++++-
 board/ti/am57xx/mux_data.h                         | 299 +++++++++++++++++++++
 board/ti/common/Kconfig                            |   7 +
 board/ti/common/Makefile                           |   3 +
 .../mach-keystone => board/ti/common}/cmd_ddr3.c   | 179 +++++++++---
 board/ti/dra7xx/evm.c                              |  17 +-
 configs/am57xx_evm_defconfig                       |   2 +-
 configs/am57xx_hs_evm_defconfig                    |   2 +-
 drivers/dma/ti-edma3.c                             |  55 +++-
 include/environment/ti/boot.h                      |   4 +-
 30 files changed, 927 insertions(+), 158 deletions(-)
 create mode 100644 arch/arm/dts/am572x-idk-common.dtsi
 create mode 100644 arch/arm/dts/am574x-idk.dts
 rename {arch/arm/mach-keystone => board/ti/common}/cmd_ddr3.c (54%)
Signature · 1 line
2.15.1
author
#1 lore raw

PATCH 1/13 drivers: dma: ti-edma3: add support for memory fill

From: Tero Kristo <[email protected]>

Add support for simple memory fill operation. With large data sizes it is much faster to use EDMA for memory fill rather than CPU.

Signed-off-by Tero Kristo <[email protected]>
Signed-off-by Lokesh Vutla <[email protected]>
---
 arch/arm/include/asm/ti-common/ti-edma3.h |  2 ++
 drivers/dma/ti-edma3.c                    | 55 +++++++++++++++++++++++++++----
 2 files changed, 50 insertions(+), 7 deletions(-)
arch/arm/include/asm/ti-common/ti-edma3.h +2 -0
index 6a7a321c1b..3f41d34a7a 100644
@@ -119,5 +119,7 @@ void edma3_set_transfer_params(u32 base, int slot, int acnt,
 			       enum edma3_sync_dimension sync_mode);
 void edma3_transfer(unsigned long edma3_base_addr, unsigned int
 		edma_slot_num, void *dst, void *src, size_t len);
+void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
+		void *dst, u8 val, size_t len);
 
 #endif
drivers/dma/ti-edma3.c +48 -7

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Signature · 1 line
2.15.1
author
#2 lore raw

PATCH 2/13 arm: emif-common: Add ecc specific emif registers

In reply to Lokesh Vutla

This is a slight difference in emif_ddr_phy_status register offsets for DRA7xx/keystone EMIF and older versions. And ecc registers are available only in DRA7xx EMIF. Add support for this difference and ecc registers.

Signed-off-by Lokesh Vutla <[email protected]>
---
 arch/arm/include/asm/emif.h       | 17 ++++++++++++++++-
 arch/arm/mach-omap2/emif-common.c |  6 +++---
 2 files changed, 19 insertions(+), 4 deletions(-)
arch/arm/include/asm/emif.h +16 -1
index 9a46340deb..a661ba9032 100644
@@ -664,12 +664,27 @@ struct emif_reg_struct {
 	u32 emif_prio_class_serv_map;
 	u32 emif_connect_id_serv_1_map;
 	u32 emif_connect_id_serv_2_map;
-	u32 padding8[5];
+	u32 padding8;
+	u32 emif_ecc_ctrl_reg;
+	u32 emif_ecc_address_range_1;
+	u32 emif_ecc_address_range_2;
+	u32 padding8_1;
 	u32 emif_rd_wr_exec_thresh;
 	u32 emif_cos_config;
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_ARCH_KEYSTONE)
+	u32 padding9[2];
+	u32 emif_1b_ecc_err_cnt;
+	u32 emif_1b_ecc_err_thrush;
+	u32 emif_1b_ecc_err_dist_1;
+	u32 emif_1b_ecc_err_addr_log;
+	u32 emif_2b_ecc_err_addr_log;
+	u32 emif_ddr_phy_status[28];
+	u32 padding10[19];
+#else
 	u32 padding9[6];
 	u32 emif_ddr_phy_status[28];
 	u32 padding10[20];
+#endif
 	u32 emif_ddr_ext_phy_ctrl_1;
 	u32 emif_ddr_ext_phy_ctrl_1_shdw;
 	u32 emif_ddr_ext_phy_ctrl_2;
arch/arm/mach-omap2/emif-common.c +3 -3
index def7fe0f0a..2b03dbecf4 100644
@@ -255,7 +255,7 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
 	u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
 	u32 reg, i, phy;
 
-	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];
+	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[6];
 	phy = readl(&emif->emif_ddr_phy_ctrl_1);
 
 	/* Update PHY_REG_RDDQS_RATIO */

@@ -269,7 +269,7 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
 
 	/* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
 	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
-	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12];
+	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[11];
 	if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK))
 		for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
 			reg = readl(emif_phy_status++);

@@ -279,7 +279,7 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
 
 	/* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
 	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
-	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17];
+	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[16];
 	if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK))
 		for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
 			reg = readl(emif_phy_status++);
Signature · 1 line
2.15.1
author
#3 lore raw

PATCH 3/13 arm: emif-common: Add suppport for enabling ECC

In reply to Lokesh Vutla

For data integrity, the EMIF1 supports ECC on the data written or read from the SDRAM. Add support for enabling ECC support in EMIF1.

Signed-off-by Lokesh Vutla <[email protected]>
Signed-off-by Krunal Bhargav <[email protected]>
---
 arch/arm/include/asm/emif.h       | 31 ++++++++++++++
 arch/arm/mach-omap2/emif-common.c | 89 ++++++++++++++++++++++++++++++++++++++-
 2 files changed, 119 insertions(+), 1 deletion(-)
arch/arm/include/asm/emif.h +31 -0
index a661ba9032..6a2ccd2350 100644
@@ -604,6 +604,34 @@
 
 #define EMIF_EXT_PHY_CTRL_TIMING_REG	0x5
 
+/* EMIF ECC CTRL reg */
+#define EMIF_ECC_CTRL_REG_ECC_EN_SHIFT			31
+#define EMIF_ECC_CTRL_REG_ECC_EN_MASK			(1 << 31)
+#define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_SHIFT	30
+#define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK	(1 << 31)
+#define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_SHIFT		29
+#define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK		(1 << 29)
+#define EMIF_ECC_REG_RMW_EN_SHIFT			28
+#define EMIF_ECC_REG_RMW_EN_MASK			(1 << 28)
+#define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_SHIFT		1
+#define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK		(1 << 1)
+#define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_SHIFT		0
+#define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK		(1 << 0)
+
+/* EMIF ECC ADDRESS RANGE */
+#define EMIF_ECC_REG_ECC_END_ADDR_SHIFT			16
+#define EMIF_ECC_REG_ECC_END_ADDR_MASK			(0xffff << 16)
+#define EMIF_ECC_REG_ECC_START_ADDR_SHIFT		0
+#define EMIF_ECC_REG_ECC_START_ADDR_MASK		(0xffff << 0)
+
+/* EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS */
+#define EMIF_INT_ONEBIT_ECC_ERR_SYS_SHIFT		5
+#define EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK		(1 << 5)
+#define EMIF_INT_TWOBIT_ECC_ERR_SYS_SHIFT		4
+#define EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK		(1 << 4)
+#define EMIF_INT_WR_ECC_ERR_SYS_SHIFT			3
+#define EMIF_INT_WR_ECC_ERR_SYS_MASK			(1 << 3)
+
 /* Reg mapping structure */
 struct emif_reg_struct {
 	u32 emif_mod_id_rev;

@@ -1205,6 +1233,9 @@ struct emif_regs {
 	u32 emif_connect_id_serv_1_map;
 	u32 emif_connect_id_serv_2_map;
 	u32 emif_cos_config;
+	u32 emif_ecc_ctrl_reg;
+	u32 emif_ecc_address_range_1;
+	u32 emif_ecc_address_range_2;
 };
 
 struct lpddr2_mr_regs {
arch/arm/mach-omap2/emif-common.c +88 -1

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Signature · 1 line
2.15.1
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#4 lore raw

PATCH 4/13 arm: keystone: Move cmd_ddr3 to a common place

In reply to Lokesh Vutla

Move cmd_ddr3 to board/ti/common/ in order to make it build for non-keystone TI platforms.

Signed-off-by Lokesh Vutla <[email protected]>
---
 arch/arm/mach-keystone/Kconfig                         | 4 ++++
 arch/arm/mach-keystone/Makefile                        | 1 -
 board/ti/common/Kconfig                                | 7 +++++++
 board/ti/common/Makefile                               | 3 +++
 {arch/arm/mach-keystone => board/ti/common}/cmd_ddr3.c | 5 ++---
 5 files changed, 16 insertions(+), 4 deletions(-)
 rename {arch/arm/mach-keystone => board/ti/common}/cmd_ddr3.c (98%)
arch/arm/mach-keystone/Kconfig +4 -0
index cababdba52..d24596eccb 100644
@@ -7,16 +7,19 @@ choice
 config TARGET_K2HK_EVM
 	bool "TI Keystone 2 Kepler/Hawking EVM"
 	select SPL_BOARD_INIT if SPL
+	select CMD_DDR3
 	imply DM_I2C
 
 config TARGET_K2E_EVM
 	bool "TI Keystone 2 Edison EVM"
 	select SPL_BOARD_INIT if SPL
+	select CMD_DDR3
 	imply DM_I2C
 
 config TARGET_K2L_EVM
 	bool "TI Keystone 2 Lamar EVM"
 	select SPL_BOARD_INIT if SPL
+	select CMD_DDR3
 	imply DM_I2C
 
 config TARGET_K2G_EVM

@@ -24,6 +27,7 @@ config TARGET_K2G_EVM
         select BOARD_LATE_INIT
 	select SPL_BOARD_INIT if SPL
         select TI_I2C_BOARD_DETECT
+	select CMD_DDR3
 	imply DM_I2C
 
 endchoice
arch/arm/mach-keystone/Makefile +0 -1
index 8253a3bcc1..3e076e12ec 100644
@@ -13,7 +13,6 @@ ifndef CONFIG_SPL_BUILD
 obj-y	+= cmd_clock.o
 obj-y	+= cmd_mon.o
 obj-y	+= cmd_poweroff.o
-obj-y	+= cmd_ddr3.o
 endif
 obj-y	+= msmc.o
 obj-y	+= ddr3.o
board/ti/common/Kconfig +7 -0
index c21eb8c2d2..d7c05e2451 100644
@@ -42,3 +42,10 @@ config TI_COMMON_CMD_OPTIONS
 	imply CMD_SPI
 	imply CMD_TIME
 	imply CMD_USB if USB
+
+config CMD_DDR3
+	bool "command for verifying DDR features"
+	help
+	   Support for testing ddr3 on TI platforms. This command
+	   supports memory verification, memory comapre and ecc
+	   verification if supported.
board/ti/common/Makefile +3 -0
index 7170eac81e..66025040bc 100644
@@ -4,3 +4,6 @@
 #
 
 obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o
+ifndef CONFIG_SPL_BUILD
+obj-${CONFIG_CMD_DDR3} += cmd_ddr3.o
+endif
board/ti/common/cmd_ddr3.c renamed from arch/arm/mach-keystone/cmd_ddr3.c +2 -3
similarity index 98%
rename from arch/arm/mach-keystone/cmd_ddr3.c
rename to board/ti/common/cmd_ddr3.c
index d3eab0711c..b6435a43f4 100644
@@ -1,8 +1,7 @@
 /*
- * Keystone2: DDR3 test commands
+ * EMIF: DDR3 test commands
  *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
+ * Copyright (C) 2012-2017 Texas Instruments Incorporated, <www.ti.com>
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
Signature · 1 line
2.15.1
#5 lore raw

PATCH 4/13 arm: keystone: Move cmd_ddr3 to a common place

Quoted 4 lines · Lokesh Vutla

Move cmd_ddr3 to board/ti/common/ in order to make it build for non-keystone TI platforms.

Signed-off-by Lokesh Vutla <[email protected]>

[snip]

board/ti/common/Makefile line 9

Quoted 11 lines
board/ti/common/Makefile +3 -0
index 7170eac81e..66025040bc 100644
@@ -4,3 +4,6 @@
 #
 
 obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o
+ifndef CONFIG_SPL_BUILD
+obj-${CONFIG_CMD_DDR3} += cmd_ddr3.o
+endif

We shouldn't need games like that now to have all strings be discarded, now that we're mandating gcc-6 or later. Thanks!

Signature · 8 lines
Tom
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author
#6 lore raw

PATCH 4/13 arm: keystone: Move cmd_ddr3 to a common place

Quoted 14 lines · Tom Rini
Quoted 4 lines · Lokesh Vutla

Move cmd_ddr3 to board/ti/common/ in order to make it build for non-keystone TI platforms.

Signed-off-by Lokesh Vutla <[email protected]>

[snip]

Quoted 7 lines
board/ti/common/Makefile +0 -0
index 7170eac81e..66025040bc 100644
@@ -4,3 +4,6 @@
 #
Quoted 8 lines

board/ti/common/Makefile line 9

Quoted 4 lines
board/ti/common/Makefile +3 -0
 obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o
+ifndef CONFIG_SPL_BUILD
+obj-${CONFIG_CMD_DDR3} += cmd_ddr3.o
+endif

We shouldn't need games like that now to have all strings be discarded, now that we're mandating gcc-6 or later. Thanks!

whithout guarding with !SPL_BUILD, following build erroris seen if SPL_ENV is not enabled:

#
env/built-in.o:(.data.env_htab+0xc): undefined reference to `env_flags_validate'
lib/built-in.o: In function `hsearch_r':
/home/lokesh/working/mainline/u-boot/lib/hashtable.c:380: undefined reference to env_callback_init' /home/lokesh/working/mainline/u-boot/lib/hashtable.c:382: undefined reference to env_flags_init'
scripts/Makefile.spl:343: recipe for target 'spl/u-boot-spl' failed make[1]: *** [spl/u-boot-spl] Error 1
Makefile:1400: recipe for target 'spl/u-boot-spl' failed
make: *** [spl/u-boot-spl] Error 2

gcc-6 is being used. Am I missing something?

Thanks and regards,
Lokesh

#7 lore raw

PATCH 4/13 arm: keystone: Move cmd_ddr3 to a common place

Quoted 42 lines · Lokesh Vutla
Quoted 14 lines · Tom Rini
Quoted 4 lines · Lokesh Vutla

Move cmd_ddr3 to board/ti/common/ in order to make it build for non-keystone TI platforms.

Signed-off-by Lokesh Vutla <[email protected]>

[snip]

Quoted 7 lines
board/ti/common/Makefile +0 -0
index 7170eac81e..66025040bc 100644
@@ -4,3 +4,6 @@
 #
Quoted 7 lines

board/ti/common/Makefile line 9

Quoted 4 lines
board/ti/common/Makefile +3 -0
 obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o
+ifndef CONFIG_SPL_BUILD
+obj-${CONFIG_CMD_DDR3} += cmd_ddr3.o
+endif

We shouldn't need games like that now to have all strings be discarded, now that we're mandating gcc-6 or later. Thanks!

whithout guarding with !SPL_BUILD, following build erroris seen if SPL_ENV is not enabled:

#
env/built-in.o:(.data.env_htab+0xc): undefined reference to `env_flags_validate'
lib/built-in.o: In function `hsearch_r':
/home/lokesh/working/mainline/u-boot/lib/hashtable.c:380: undefined reference to env_callback_init' /home/lokesh/working/mainline/u-boot/lib/hashtable.c:382: undefined reference to env_flags_init'
scripts/Makefile.spl:343: recipe for target 'spl/u-boot-spl' failed make[1]: *** [spl/u-boot-spl] Error 1
Makefile:1400: recipe for target 'spl/u-boot-spl' failed
make: *** [spl/u-boot-spl] Error 2

Quoted 1 line

gcc-6 is being used. Am I missing something?

Hmmm, I would have expected it to be gc'd away. But I guess we're forcing commands to be linked in for some reason, I'll dig more just so I know again but disregard my comment about removing the guard, thanks!

Signature · 8 lines
Tom
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#8 lore raw

PATCH 4/13 arm: keystone: Move cmd_ddr3 to a common place

In reply to Lokesh Vutla
Quoted 17 lines · Lokesh Vutla
Quoted 14 lines · Tom Rini
Quoted 4 lines · Lokesh Vutla

Move cmd_ddr3 to board/ti/common/ in order to make it build for non-keystone TI platforms.

Signed-off-by Lokesh Vutla <[email protected]>

[snip]

Quoted 7 lines
board/ti/common/Makefile +0 -0
index 7170eac81e..66025040bc 100644
@@ -4,3 +4,6 @@
 #
Quoted 4 lines
Quoted 4 lines

board/ti/common/Makefile line 9

Quoted 4 lines
board/ti/common/Makefile +3 -0
 obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o
+ifndef CONFIG_SPL_BUILD
+obj-${CONFIG_CMD_DDR3} += cmd_ddr3.o
+endif

While I'm looking at this again, we should probably mirror cmd/mvebu here and move this to cmd/ti/ instead of board/ti/common/, thanks!

Signature · 8 lines
Tom
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author
#9 lore raw

PATCH 5/13 arm: ti: Generalize cmd_ddr3 command

In reply to Lokesh Vutla

Keystone and DRA7 based TI platforms uses same EMIF memory controller. cmd_ddr3 command is customized for keystone platforms, make it generic so that it can be re used for DRA7 platforms.

Signed-off-by Lokesh Vutla <[email protected]>
---
 arch/arm/include/asm/emif.h                    |   2 +
 arch/arm/mach-keystone/include/mach/hardware.h |   1 +
 board/ti/common/cmd_ddr3.c                     | 174 ++++++++++++++++++++-----
 3 files changed, 141 insertions(+), 36 deletions(-)
arch/arm/include/asm/emif.h +2 -0
index 6a2ccd2350..b9fa3bb827 100644
@@ -17,7 +17,9 @@
 #include <asm/io.h>
 
 /* Base address */
+#ifndef EMIF1_BASE
 #define EMIF1_BASE				0x4c000000
+#endif
 #define EMIF2_BASE				0x4d000000
 
 #define EMIF_4D					0x4
arch/arm/mach-keystone/include/mach/hardware.h +1 -0
index 1969a10ab3..6629406870 100644
@@ -78,6 +78,7 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_DDR3A_EMIF_CTRL_BASE	0x21010000
 #define KS2_DDR3A_EMIF_DATA_BASE	0x80000000
 #define KS2_DDR3A_DDRPHYC		0x02329000
+#define EMIF1_BASE			KS2_DDR3A_EMIF_CTRL_BASE
 
 #define KS2_DDR3_MIDR_OFFSET            0x00
 #define KS2_DDR3_STATUS_OFFSET          0x04
board/ti/common/cmd_ddr3.c +138 -36

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author
#10 lore raw

PATCH 6/13 arm: dra762: Add support for device package identification

In reply to Lokesh Vutla

DRA762 comes in two packages:
- ABZ: Pin compatible package with DRA742 with DDR at 1333MHz
- ACD: High performance(OPP_PLUS) package with new IPs

Both the above packages uses the same IDCODE hence needs to differentiate using package information in DIE_ID_2.
Add support for the same. Also update clock, ddr, emif information.

Signed-off-by Lokesh Vutla <[email protected]>
---
 arch/arm/include/asm/arch-omap5/omap.h      |  3 +++
 arch/arm/include/asm/arch-omap5/sys_proto.h |  1 +
 arch/arm/include/asm/omap_common.h          | 14 ++++++++++++
 arch/arm/mach-omap2/hwinit-common.c         | 33 +++++++++++++++++++++++++++--
 arch/arm/mach-omap2/omap5/hw_data.c         |  4 ++++
 arch/arm/mach-omap2/omap5/hwinit.c          | 21 ++++++++++++++++++
 arch/arm/mach-omap2/omap5/sdram.c           |  4 ++++
 board/ti/dra7xx/evm.c                       | 17 +++++++++++----
 8 files changed, 91 insertions(+), 6 deletions(-)
arch/arm/include/asm/arch-omap5/omap.h +3 -0
index 81feac704a..f8e7f06442 100644
@@ -66,6 +66,9 @@
 #define DRA722_CONTROL_ID_CODE_ES2_0		0x1B9BC02F
 #define DRA722_CONTROL_ID_CODE_ES2_1		0x2B9BC02F
 
+#define DRA762_ABZ_PACKAGE			0x2
+#define DRA762_ACD_PACKAGE			0x3
+
 /* UART */
 #define UART1_BASE		(OMAP54XX_L4_PER_BASE + 0x6a000)
 #define UART2_BASE		(OMAP54XX_L4_PER_BASE + 0x6c000)
arch/arm/include/asm/arch-omap5/sys_proto.h +1 -0
index ab0e7fae9c..a6b3557b50 100644
@@ -62,6 +62,7 @@ u32 omap_sdram_size(void);
 u32 cortex_rev(void);
 void save_omap_boot_params(void);
 void init_omap_revision(void);
+void init_package_revision(void);
 void do_io_settings(void);
 void sri2c_init(void);
 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
arch/arm/include/asm/omap_common.h +14 -0
index 481e9389c4..9624fb81fa 100644
@@ -743,6 +743,18 @@ static inline u8 is_dra76x(void)
 	extern u32 *const omap_si_rev;
 	return (*omap_si_rev & 0xFFF00000) == DRA76X;
 }
+
+static inline u8 is_dra76x_abz(void)
+{
+	extern u32 *const omap_si_rev;
+	return (*omap_si_rev & 0xF) == 2;
+}
+
+static inline u8 is_dra76x_acd(void)
+{
+	extern u32 *const omap_si_rev;
+	return (*omap_si_rev & 0xF) == 3;
+}
 #endif
 
 /*

@@ -778,6 +790,8 @@ static inline u8 is_dra76x(void)
 #define DRA722_ES2_0	0x07220200
 #define DRA722_ES2_1	0x07220210
 
+#define DRA762_ABZ_ES1_0	0x07620102
+#define DRA762_ACD_ES1_0	0x07620103
 /*
  * silicon device type
  * Moving to common from cpu.h, since it is shared by various omap devices
arch/arm/mach-omap2/hwinit-common.c +31 -2
index 56890a0c54..4f491e60f2 100644
@@ -66,7 +66,7 @@ static void omap_rev_string(void)
 	u32 major_rev = (omap_rev & 0x00000F00) >> 8;
 	u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
 
-	const char *sec_s;
+	const char *sec_s, *package = NULL;
 
 	switch (get_device_type()) {
 	case TST_DEVICE:

@@ -85,11 +85,29 @@ static void omap_rev_string(void)
 		sec_s = "?";
 	}
 
+#if defined(CONFIG_DRA7XX)
+	if (is_dra76x()) {
+		switch (omap_rev & 0xF) {
+		case DRA762_ABZ_PACKAGE:
+			package = "ABZ";
+			break;
+		case DRA762_ACD_PACKAGE:
+		default:
+			package = "ACD";
+			break;
+		}
+	}
+#endif
+
 	if (soc_variant)
 		printf("OMAP");
 	else
 		printf("DRA");
-	printf("%x-%s ES%x.%x\n", omap_variant, sec_s, major_rev, minor_rev);
+	printf("%x-%s ES%x.%x", omap_variant, sec_s, major_rev, minor_rev);
+	if (package)
+		printf(" %s package\n", package);
+	else
+		puts("\n");
 }
 
 #ifdef CONFIG_SPL_BUILD

@@ -127,6 +145,16 @@ void s_init(void)
 {
 }
 
+/**
+ * init_package_revision() - Initialize package revision
+ *
+ * Function to get the pacakage information. This is expected to be
+ * overridden in the SoC family file where desired.
+ */
+void __weak init_package_revision(void)
+{
+}
+
 /**
  * early_system_init - Does Early system initialization.
  *

@@ -146,6 +174,7 @@ void early_system_init(void)
 {
 	init_omap_revision();
 	hw_data_init();
+	init_package_revision();
 
 #ifdef CONFIG_SPL_BUILD
 	if (warm_reset())
arch/arm/mach-omap2/omap5/hw_data.c +4 -0
index 3bdb114bb6..bb05e1920b 100644
@@ -746,6 +746,8 @@ void __weak hw_data_init(void)
 	*ctrl = &omap5_ctrl;
 	break;
 
+	case DRA762_ABZ_ES1_0:
+	case DRA762_ACD_ES1_0:
 	case DRA762_ES1_0:
 	*prcm = &dra7xx_prcm;
 	*dplls_data = &dra76x_dplls;

@@ -792,6 +794,8 @@ void get_ioregs(const struct ctrl_ioregs **regs)
 	case DRA752_ES1_1:
 	case DRA752_ES2_0:
 	case DRA762_ES1_0:
+	case DRA762_ACD_ES1_0:
+	case DRA762_ABZ_ES1_0:
 		*regs = &ioregs_dra7xx_es1;
 		break;
 	case DRA722_ES1_0:
arch/arm/mach-omap2/omap5/hwinit.c +21 -0
index 14a35dd284..57f2a8664c 100644
@@ -389,6 +389,27 @@ void init_omap_revision(void)
 	init_cpu_configuration();
 }
 
+void init_package_revision(void)
+{
+	unsigned int die_id[4] = { 0 };
+	u8 package;
+
+	omap_die_id(die_id);
+	package = (die_id[2] >> 16) & 0x3;
+
+	if (is_dra76x()) {
+		switch (package) {
+		case DRA762_ABZ_PACKAGE:
+			*omap_si_rev = DRA762_ABZ_ES1_0;
+			break;
+		case DRA762_ACD_PACKAGE:
+		default:
+			*omap_si_rev = DRA762_ACD_ES1_0;
+			break;
+		}
+	}
+}
+
 void omap_die_id(unsigned int *die_id)
 {
 	die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
arch/arm/mach-omap2/omap5/sdram.c +4 -0
index 8fb962e39d..c0e0e0888c 100644
@@ -481,6 +481,8 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
 		*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
 		break;
 	case DRA762_ES1_0:
+	case DRA762_ABZ_ES1_0:
+	case DRA762_ACD_ES1_0:
 	case DRA722_ES2_0:
 	case DRA722_ES2_1:
 		*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;

@@ -711,6 +713,8 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
 		*iterations = sizeof(omap5_bug_00339_regs)/
 			     sizeof(omap5_bug_00339_regs[0]);
 		break;
+	case DRA762_ABZ_ES1_0:
+	case DRA762_ACD_ES1_0:
 	case DRA762_ES1_0:
 	case DRA752_ES1_0:
 	case DRA752_ES1_1:
board/ti/dra7xx/evm.c +13 -4
index 6bcfa48231..41868822b1 100644
@@ -285,6 +285,8 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 			break;
 		}
 		break;
+	case DRA762_ABZ_ES1_0:
+	case DRA762_ACD_ES1_0:
 	case DRA762_ES1_0:
 		if (emif_nr == 1)
 			*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;

@@ -347,6 +349,8 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 	ram_size = board_ti_get_emif_size();
 
 	switch (omap_revision()) {
+	case DRA762_ABZ_ES1_0:
+	case DRA762_ACD_ES1_0:
 	case DRA762_ES1_0:
 	case DRA752_ES1_0:
 	case DRA752_ES1_1:

@@ -655,8 +659,10 @@ int board_late_init(void)
 			name = "dra71x";
 		else
 			name = "dra72x";
-	} else if (is_dra76x()) {
-		name = "dra76x";
+	} else if (is_dra76x_abz()) {
+		name = "dra76x_abz";
+	} else if (is_dra76x_acd()) {
+		name = "dra76x_acd";
 	} else {
 		name = "dra7xx";
 	}

@@ -793,6 +799,7 @@ void recalibrate_iodelay(void)
 		iodelay = dra742_es1_1_iodelay_cfg_array;
 		niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
 		break;
+	case DRA762_ACD_ES1_0:
 	case DRA762_ES1_0:
 		pads = dra76x_core_padconf_array;
 		npads = ARRAY_SIZE(dra76x_core_padconf_array);

@@ -801,6 +808,7 @@ void recalibrate_iodelay(void)
 		break;
 	default:
 	case DRA752_ES2_0:
+	case DRA762_ABZ_ES1_0:
 		pads = dra74x_core_padconf_array;
 		npads = ARRAY_SIZE(dra74x_core_padconf_array);
 		iodelay = dra742_es2_0_iodelay_cfg_array;

@@ -1125,9 +1133,10 @@ int board_fit_config_name_match(const char *name)
 		} else if (!strcmp(name, "dra72-evm")) {
 			return 0;
 		}
-	} else if (is_dra76x() && !strcmp(name, "dra76-evm")) {
+	} else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
 		return 0;
-	} else if (!is_dra72x() && !is_dra76x() && !strcmp(name, "dra7-evm")) {
+	} else if (!is_dra72x() && !is_dra76x_acd() &&
+		   !strcmp(name, "dra7-evm")) {
 		return 0;
 	}
Signature · 1 line
2.15.1
author
#11 lore raw

PATCH 7/13 board: ti: am574x-idk: Add epprom support

In reply to Lokesh Vutla

am574x-idk is a board based on TI's am574 processor Add eeprom support.

Signed-off-by Lokesh Vutla <[email protected]>
---
 board/ti/am57xx/board.c | 5 +++++
 1 file changed, 5 insertions(+)
board/ti/am57xx/board.c +5 -0
index f79aefd400..082346d2b1 100644
@@ -43,6 +43,7 @@
 #define board_is_am572x_evm_reva3()	\
 				(board_ti_is("AM572PM_") && \
 				 !strncmp("A.30", board_ti_get_rev(), 3))
+#define board_is_am574x_idk()	board_ti_is("AM574IDK")
 #define board_is_am572x_idk()	board_ti_is("AM572IDK")
 #define board_is_am571x_idk()	board_ti_is("AM571IDK")
 

@@ -481,6 +482,8 @@ void do_board_detect(void)
 		bname = "BeagleBoard X15";
 	else if (board_is_am572x_evm())
 		bname = "AM572x EVM";
+	else if (board_is_am574x_idk())
+		bname = "AM574x IDK";
 	else if (board_is_am572x_idk())
 		bname = "AM572x IDK";
 	else if (board_is_am571x_idk())

@@ -513,6 +516,8 @@ static void setup_board_eeprom_env(void)
 			name = "am57xx_evm_reva3";
 		else
 			name = "am57xx_evm";
+	} else if (board_is_am574x_idk()) {
+		name = "am574x_idk";
 	} else if (board_is_am572x_idk()) {
 		name = "am572x_idk";
 	} else if (board_is_am571x_idk()) {
Signature · 1 line
2.15.1
author
#12 lore raw

PATCH 8/13 board: ti: am574x-idk: Add hw data support

In reply to Lokesh Vutla

Update prcm, voltages support for am574x-idk.

Signed-off-by Lokesh Vutla <[email protected]>
---
 arch/arm/include/asm/omap_common.h | 1 +
 board/ti/am57xx/board.c            | 9 ++++++---
 2 files changed, 7 insertions(+), 3 deletions(-)
arch/arm/include/asm/omap_common.h +1 -0
index 9624fb81fa..5710136e88 100644
@@ -597,6 +597,7 @@ extern struct prcm_regs const dra7xx_prcm;
 extern struct dplls const **dplls_data;
 extern struct dplls dra7xx_dplls;
 extern struct dplls dra72x_dplls;
+extern struct dplls dra76x_dplls;
 extern struct vcores_data const **omap_vcores;
 extern const u32 sys_clk_array[8];
 extern struct omap_sys_ctrl_regs const **ctrl;
board/ti/am57xx/board.c +6 -3
index 082346d2b1..2d14ae54fe 100644
@@ -535,7 +535,7 @@ invalid_eeprom:
 
 void vcores_init(void)
 {
-	if (board_is_am572x_idk())
+	if (board_is_am572x_idk() || board_is_am574x_idk())
 		*omap_vcores = &am572x_idk_volts;
 	else if (board_is_am571x_idk())
 		*omap_vcores = &am571x_idk_volts;

@@ -548,6 +548,8 @@ void hw_data_init(void)
 	*prcm = &dra7xx_prcm;
 	if (is_dra72x())
 		*dplls_data = &dra72x_dplls;
+	else if (is_dra76x())
+		*dplls_data = &dra76x_dplls;
 	else
 		*dplls_data = &dra7xx_dplls;
 	*ctrl = &dra7xx_ctrl;

@@ -688,7 +690,7 @@ void recalibrate_iodelay(void)
 	int pconf_sz, iod_sz, delta_iod_sz = 0;
 	int ret;
 
-	if (board_is_am572x_idk()) {
+	if (board_is_am572x_idk() || board_is_am574x_idk()) {
 		pconf = core_padconf_array_essential_am572x_idk;
 		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 		iod = iodelay_cfg_array_am572x_idk;

@@ -995,7 +997,8 @@ int board_eth_init(bd_t *bis)
 	writel(ctrl_val, (*ctrl)->control_core_control_io1);
 
 	/* The phy address for the AM57xx IDK are different than x15 */
-	if (board_is_am572x_idk() || board_is_am571x_idk()) {
+	if (board_is_am572x_idk() || board_is_am571x_idk() ||
+	    board_is_am574x_idk()) {
 		cpsw_data.slave_data[0].phy_addr = 0;
 		cpsw_data.slave_data[1].phy_addr = 1;
 	}
Signature · 1 line
2.15.1
author
#13 lore raw

PATCH 9/13 board: ti: am574x-idk: Add ddr data support

In reply to Lokesh Vutla

AM574x-idk has the following DDR parts attached:
EMIF1: MT41K256M16HA (1GB with ECC)
EMIF2: MT41K256M16HA (1GB without ECC)

Enabling 2GB DDR without interleaving between EMIFs. And enabling ECC on EMIF1.

Signed-off-by Lokesh Vutla <[email protected]>
Signed-off-by Krunal Bhargav <[email protected]>
---
 board/ti/am57xx/board.c | 47 ++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 44 insertions(+), 3 deletions(-)
board/ti/am57xx/board.c +44 -3
index 2d14ae54fe..1377c7b1fe 100644
@@ -89,10 +89,18 @@ static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
 	.is_ma_present  = 0x1
 };
 
+static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
+	.dmm_lisa_map_2 = 0xc0600200,
+	.dmm_lisa_map_3 = 0x80600100,
+	.is_ma_present  = 0x1
+};
+
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 {
 	if (board_is_am571x_idk())
 		*dmm_lisa_regs = &am571x_idk_lisa_regs;
+	else if (board_is_am574x_idk())
+		*dmm_lisa_regs = &am574x_idk_lisa_regs;
 	else
 		*dmm_lisa_regs = &beagle_x15_lisa_regs;
 }

@@ -231,8 +239,8 @@ static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
 	.ref_ctrl			= 0x0000514d,
 	.ref_ctrl_final			= 0x0000144a,
 	.sdram_tim1			= 0xd333887c,
-	.sdram_tim2			= 0x40b37fe3,
-	.sdram_tim3			= 0x409f8ada,
+	.sdram_tim2			= 0x30b37fe3,
+	.sdram_tim3			= 0x409f8ad8,
 	.read_idle_ctrl			= 0x00050000,
 	.zq_config			= 0x5007190b,
 	.temp_alert_config		= 0x00000000,

@@ -249,17 +257,50 @@ static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
 	.emif_rd_wr_exec_thresh		= 0x00000305
 };
 
+static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
+	.sdram_config_init		= 0x61863332,
+	.sdram_config			= 0x61863332,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl			= 0x0000514d,
+	.ref_ctrl_final			= 0x0000144a,
+	.sdram_tim1			= 0xd333887c,
+	.sdram_tim2			= 0x30b37fe3,
+	.sdram_tim3			= 0x409f8ad8,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x5007190b,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init	= 0x0024400f,
+	.emif_ddr_phy_ctlr_1		= 0x0e24400f,
+	.emif_ddr_ext_phy_ctrl_1	= 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4	= 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5	= 0x009e009e,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000305,
+	.emif_ecc_ctrl_reg		= 0xD0000001,
+	.emif_ecc_address_range_1	= 0x3FFF0000,
+	.emif_ecc_address_range_2	= 0x00000000
+};
+
 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 {
 	switch (emif_nr) {
 	case 1:
 		if (board_is_am571x_idk())
 			*regs = &am571x_emif1_ddr3_666mhz_emif_regs;
+		else if (board_is_am574x_idk())
+			*regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
 		else
 			*regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 		break;
 	case 2:
-		*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
+		if (board_is_am574x_idk())
+			*regs = &am571x_emif1_ddr3_666mhz_emif_regs;
+		else
+			*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 		break;
 	}
 }
Signature · 1 line
2.15.1
#14 lore raw

PATCH 9/13 board: ti: am574x-idk: Add ddr data support

Hi Lokesh,

Quoted 71 lines

AM574x-idk has the following DDR parts attached:
EMIF1: MT41K256M16HA (1GB with ECC)
EMIF2: MT41K256M16HA (1GB without ECC)

Enabling 2GB DDR without interleaving between EMIFs. And enabling ECC on EMIF1.

Signed-off-by Lokesh Vutla <[email protected]>
Signed-off-by Krunal Bhargav <[email protected]>
---
 board/ti/am57xx/board.c | 47

++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-)

board/ti/am57xx/board.c +0 -0
index 2d14ae54fe..1377c7b1fe 100644
@@ -89,10 +89,18 @@ static const struct dmm_lisa_map_regs

am571x_idk_lisa_regs = { .is_ma_present = 0x1
};

board/ti/am57xx/board.c +6 -0
+static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
+	.dmm_lisa_map_2 = 0xc0600200,
+	.dmm_lisa_map_3 = 0x80600100,
+	.is_ma_present  = 0x1
+};
+
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs

**dmm_lisa_regs) {

board/ti/am57xx/board.c +2 -0
 	if (board_is_am571x_idk())
 		*dmm_lisa_regs = &am571x_idk_lisa_regs;
+	else if (board_is_am574x_idk())
+		*dmm_lisa_regs = &am574x_idk_lisa_regs;
 	else
 		*dmm_lisa_regs = &beagle_x15_lisa_regs;
 }

@@ -231,8 +239,8 @@ static const struct emif_regs

am571x_emif1_ddr3_666mhz_emif_regs =
{ .ref_ctrl =
0x0000514d, .ref_ctrl_final =
0x0000144a, .sdram_tim1 = 0xd333887c,

board/ti/am57xx/board.c +2 -2
-	.sdram_tim2			= 0x40b37fe3,
-	.sdram_tim3			= 0x409f8ada,
+	.sdram_tim2			= 0x30b37fe3,
+	.sdram_tim3			= 0x409f8ad8,
 	.read_idle_ctrl			= 0x00050000,
 	.zq_config			= 0x5007190b,
 	.temp_alert_config		= 0x00000000,

@@ -249,17 +257,50 @@ static const struct emif_regs

am571x_emif1_ddr3_666mhz_emif_regs =
{ .emif_rd_wr_exec_thresh = 0x00000305 };

+static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {

board/ti/am57xx/board.c +16 -0
+	.sdram_config_init		= 0x61863332,
+	.sdram_config			= 0x61863332,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl			= 0x0000514d,
+	.ref_ctrl_final			= 0x0000144a,
+	.sdram_tim1			= 0xd333887c,
+	.sdram_tim2			= 0x30b37fe3,
+	.sdram_tim3			= 0x409f8ad8,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x5007190b,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init	= 0x0024400f,
+	.emif_ddr_phy_ctlr_1		= 0x0e24400f,
+	.emif_ddr_ext_phy_ctrl_1	= 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00950095,

board/ti/am57xx/board.c static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { · line 286

Quoted 10 lines
board/ti/am57xx/board.c +10 -0
+	.emif_ddr_ext_phy_ctrl_4	= 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5	= 0x009e009e,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000305,
+	.emif_ecc_ctrl_reg		= 0xD0000001,
+	.emif_ecc_address_range_1	= 0x3FFF0000,
+	.emif_ecc_address_range_2	= 0x00000000
+};

I'm wondering if it would be possible to:

Embed this memory setup (even as binary blob) to SPL FIT -> Those values are generated from TI supplied excel sheet (when memory details are provided).

Pros:
----

- Since the same EMIF controller is used, one could only adjust the binary blob, when new memory (faster, slower, from other manufacturer) is used in the product.

- There would be no need to add such code to the board file.

Quoted 18 lines
board/ti/am57xx/board.c +3 -0
+
 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 {
 	switch (emif_nr) {
 	case 1:
 		if (board_is_am571x_idk())
 			*regs = &am571x_emif1_ddr3_666mhz_emif_regs;
+		else if (board_is_am574x_idk())
+			*regs =

&am574x_emif1_ddr3_666mhz_emif_ecc_regs; else
*regs =
&beagle_x15_emif1_ddr3_532mhz_emif_regs; break;

board/ti/am57xx/board.c +4 -1
 	case 2:
-		*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
+		if (board_is_am574x_idk())
+			*regs = &am571x_emif1_ddr3_666mhz_emif_regs;
+		else
+			*regs =
Quoted 3 lines

&beagle_x15_emif2_ddr3_532mhz_emif_regs; break;
}
}

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de -------------- next part --------------
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author
#15 lore raw

PATCH 9/13 board: ti: am574x-idk: Add ddr data support

Hi Lukas,

Quoted 91 lines · Lukasz Majewski

Hi Lokesh,

Quoted 71 lines

AM574x-idk has the following DDR parts attached:
EMIF1: MT41K256M16HA (1GB with ECC)
EMIF2: MT41K256M16HA (1GB without ECC)

Enabling 2GB DDR without interleaving between EMIFs. And enabling ECC on EMIF1.

Signed-off-by Lokesh Vutla <[email protected]>
Signed-off-by Krunal Bhargav <[email protected]>
---
 board/ti/am57xx/board.c | 47

++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-)

board/ti/am57xx/board.c +0 -0
index 2d14ae54fe..1377c7b1fe 100644
@@ -89,10 +89,18 @@ static const struct dmm_lisa_map_regs

am571x_idk_lisa_regs = { .is_ma_present = 0x1
};

board/ti/am57xx/board.c +6 -0
+static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
+	.dmm_lisa_map_2 = 0xc0600200,
+	.dmm_lisa_map_3 = 0x80600100,
+	.is_ma_present  = 0x1
+};
+
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs

**dmm_lisa_regs) {

board/ti/am57xx/board.c +2 -0
 	if (board_is_am571x_idk())
 		*dmm_lisa_regs = &am571x_idk_lisa_regs;
+	else if (board_is_am574x_idk())
+		*dmm_lisa_regs = &am574x_idk_lisa_regs;
 	else
 		*dmm_lisa_regs = &beagle_x15_lisa_regs;
 }

@@ -231,8 +239,8 @@ static const struct emif_regs

am571x_emif1_ddr3_666mhz_emif_regs =
{ .ref_ctrl =
0x0000514d, .ref_ctrl_final =
0x0000144a, .sdram_tim1 = 0xd333887c,

board/ti/am57xx/board.c +2 -2
-	.sdram_tim2			= 0x40b37fe3,
-	.sdram_tim3			= 0x409f8ada,
+	.sdram_tim2			= 0x30b37fe3,
+	.sdram_tim3			= 0x409f8ad8,
 	.read_idle_ctrl			= 0x00050000,
 	.zq_config			= 0x5007190b,
 	.temp_alert_config		= 0x00000000,

@@ -249,17 +257,50 @@ static const struct emif_regs

am571x_emif1_ddr3_666mhz_emif_regs =
{ .emif_rd_wr_exec_thresh = 0x00000305 };

+static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {

board/ti/am57xx/board.c +16 -0
+	.sdram_config_init		= 0x61863332,
+	.sdram_config			= 0x61863332,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl			= 0x0000514d,
+	.ref_ctrl_final			= 0x0000144a,
+	.sdram_tim1			= 0xd333887c,
+	.sdram_tim2			= 0x30b37fe3,
+	.sdram_tim3			= 0x409f8ad8,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x5007190b,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init	= 0x0024400f,
+	.emif_ddr_phy_ctlr_1		= 0x0e24400f,
+	.emif_ddr_ext_phy_ctrl_1	= 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00950095,

board/ti/am57xx/board.c static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { · line 286

Quoted 10 lines
board/ti/am57xx/board.c +10 -0
+	.emif_ddr_ext_phy_ctrl_4	= 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5	= 0x009e009e,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000305,
+	.emif_ecc_ctrl_reg		= 0xD0000001,
+	.emif_ecc_address_range_1	= 0x3FFF0000,
+	.emif_ecc_address_range_2	= 0x00000000
+};

I'm wondering if it would be possible to:

Embed this memory setup (even as binary blob) to SPL FIT -> Those values are generated from TI supplied excel sheet (when memory details are provided).

Quoted 8 lines

Pros:
----

- Since the same EMIF controller is used, one could only adjust the binary blob, when new memory (faster, slower, from other manufacturer) is used in the product.

- There would be no need to add such code to the board file.

yeah, ddr is not the only thing that comes in this bucket, PMIC data as well can be also made in similar way. I mean all the board related information can be moved out. But then the binary size will still remain the same. Also, we will need a new driver to parse these new binary formats.

As of now, the ddr excel sheet outputs the data in the $patch format, so still sticking to this format.

Yeah, i agree that it would be nice if we can come up with the separate binary for all board related info(i guess DT can be re used here).

Thanks and regards,
Lokesh

Quoted 35 lines
Quoted 19 lines
board/ti/am57xx/board.c +3 -0
+
 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 {
 	switch (emif_nr) {
 	case 1:
 		if (board_is_am571x_idk())
 			*regs = &am571x_emif1_ddr3_666mhz_emif_regs;
+		else if (board_is_am574x_idk())
+			*regs =

&am574x_emif1_ddr3_666mhz_emif_ecc_regs; else
*regs =
&beagle_x15_emif1_ddr3_532mhz_emif_regs; break;

board/ti/am57xx/board.c +4 -1
 	case 2:
-		*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
+		if (board_is_am574x_idk())
+			*regs = &am571x_emif1_ddr3_666mhz_emif_regs;
+		else
+			*regs =
Quoted 3 lines

&beagle_x15_emif2_ddr3_532mhz_emif_regs; break;
}
}

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de

#16 lore raw

PATCH 9/13 board: ti: am574x-idk: Add ddr data support

Hi Lokesh,

Quoted 101 lines

Hi Lukas,

Quoted 98 lines · Lukasz Majewski

Hi Lokesh,

Quoted 71 lines

AM574x-idk has the following DDR parts attached:
EMIF1: MT41K256M16HA (1GB with ECC)
EMIF2: MT41K256M16HA (1GB without ECC)

Enabling 2GB DDR without interleaving between EMIFs. And enabling ECC on EMIF1.

Signed-off-by Lokesh Vutla <[email protected]>
Signed-off-by Krunal Bhargav <[email protected]>
---
 board/ti/am57xx/board.c | 47

++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-)

board/ti/am57xx/board.c +0 -0
index 2d14ae54fe..1377c7b1fe 100644
@@ -89,10 +89,18 @@ static const struct dmm_lisa_map_regs

am571x_idk_lisa_regs = { .is_ma_present = 0x1
};

board/ti/am57xx/board.c +6 -0
+static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
+	.dmm_lisa_map_2 = 0xc0600200,
+	.dmm_lisa_map_3 = 0x80600100,
+	.is_ma_present  = 0x1
+};
+
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs

**dmm_lisa_regs) {

board/ti/am57xx/board.c +2 -0
 	if (board_is_am571x_idk())
 		*dmm_lisa_regs = &am571x_idk_lisa_regs;
+	else if (board_is_am574x_idk())
+		*dmm_lisa_regs = &am574x_idk_lisa_regs;
 	else
 		*dmm_lisa_regs = &beagle_x15_lisa_regs;
 }

@@ -231,8 +239,8 @@ static const struct emif_regs

am571x_emif1_ddr3_666mhz_emif_regs =
{ .ref_ctrl =
0x0000514d, .ref_ctrl_final =
0x0000144a, .sdram_tim1 = 0xd333887c,

board/ti/am57xx/board.c +2 -2
-	.sdram_tim2			= 0x40b37fe3,
-	.sdram_tim3			= 0x409f8ada,
+	.sdram_tim2			= 0x30b37fe3,
+	.sdram_tim3			= 0x409f8ad8,
 	.read_idle_ctrl			= 0x00050000,
 	.zq_config			= 0x5007190b,
 	.temp_alert_config		= 0x00000000,

@@ -249,17 +257,50 @@ static const struct emif_regs

am571x_emif1_ddr3_666mhz_emif_regs =
{ .emif_rd_wr_exec_thresh = 0x00000305 };

+static const struct emif_regs
am574x_emif1_ddr3_666mhz_emif_ecc_regs = {

board/ti/am57xx/board.c +16 -0
+	.sdram_config_init		= 0x61863332,
+	.sdram_config			= 0x61863332,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl			= 0x0000514d,
+	.ref_ctrl_final			= 0x0000144a,
+	.sdram_tim1			= 0xd333887c,
+	.sdram_tim2			= 0x30b37fe3,
+	.sdram_tim3			= 0x409f8ad8,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x5007190b,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init	= 0x0024400f,
+	.emif_ddr_phy_ctlr_1		= 0x0e24400f,
+	.emif_ddr_ext_phy_ctrl_1	= 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00950095,

board/ti/am57xx/board.c static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { · line 286

Quoted 10 lines
board/ti/am57xx/board.c +10 -0
+	.emif_ddr_ext_phy_ctrl_4	= 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5	= 0x009e009e,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000305,
+	.emif_ecc_ctrl_reg		= 0xD0000001,
+	.emif_ecc_address_range_1	= 0x3FFF0000,
+	.emif_ecc_address_range_2	= 0x00000000
+};

I'm wondering if it would be possible to:

Embed this memory setup (even as binary blob) to SPL FIT -> Those values are generated from TI supplied excel sheet (when memory details are provided).

Pros:
----

- Since the same EMIF controller is used, one could only adjust the binary blob, when new memory (faster, slower, from other
manufacturer) is used in the product.

Quoted 5 lines
Quoted 1 line

- There would be no need to add such code to the board file.

yeah, ddr is not the only thing that comes in this bucket, PMIC data as well can be also made in similar way. I mean all the board related information can be moved out.

I think that the EMIF controller configuration is a bit special.

As you pointed out - for the whole AM57xx family one EMIF controller type is used.

Quoted 2 lines

But then the binary size will still
remain the same.

The goal here would be to not make the binary smaller, but reducing the maintanence effort.

Example use case - company X has a product. They are using single u-boot (with SPL and dts). The only thing, which they need to change is the data needed for setting up proper memory configuration (DDR2/DDR3, speed - 1500, 1333, ECC enabled/disabled, module size, etc). This all is done in EMIF.

With separate EMIF blob configuration they don't need to rebuild u-boot
- they only change memory configuration binary data.

This data has a separate room in the non-volatile memory (e.g. SPI-NOR flash).

Quoted 2 lines

Also, we will need a new driver to parse these new binary formats.

EMIF configuration data is IIRC 128 B at most. It is even possible to copy 1:1 the binary data to EMIF (as it is now done in the u-boot code).

Hence, the "driver" would boil down to "memcpy".

Quoted 3 lines

As of now, the ddr excel sheet outputs the data in the $patch format, so still sticking to this format.

As stated before, those Ctrl+C and Ctrl+V data are then copied (in for loop) to the EMIF registers.

Why not wrap EMIF binary data to FIT, store on non-volatile memory and on each reset read it and "just" copy this data to EMIF? As fallback we can use the "from excel" structure.

Quoted 4 lines

Yeah, i agree that it would be nice if we can come up with the separate binary for all board related info(i guess DT can be re used here).

Not all board related info - just EMIF.

DT is not an option here - it would require re-flashing u-boot binary.

Quoted 41 lines

Thanks and regards,
Lokesh

Quoted 37 lines
Quoted 21 lines
board/ti/am57xx/board.c +1 -0
+
 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 {
 	switch (emif_nr) {
 	case 1:
 		if (board_is_am571x_idk())
 			*regs =

&am571x_emif1_ddr3_666mhz_emif_regs;

board/ti/am57xx/board.c +2 -0
+		else if (board_is_am574x_idk())
+			*regs =

&am574x_emif1_ddr3_666mhz_emif_ecc_regs; else
*regs =
&beagle_x15_emif1_ddr3_532mhz_emif_regs; break;

board/ti/am57xx/board.c +2 -1
 	case 2:
-		*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
+		if (board_is_am574x_idk())
+			*regs =

&am571x_emif1_ddr3_666mhz_emif_regs;

board/ti/am57xx/board.c +2 -0
+		else
+			*regs =
Quoted 3 lines

&beagle_x15_emif2_ddr3_532mhz_emif_regs; break;
}
}

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang
Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email:
wd at denx.de

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de -------------- next part --------------
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author
#17 lore raw

PATCH 9/13 board: ti: am574x-idk: Add ddr data support

Hi Lukas,

Sorry for the delayed response.

Quoted 132 lines · Lukasz Majewski

Hi Lokesh,

Quoted 101 lines

Hi Lukas,

Quoted 98 lines · Lukasz Majewski

Hi Lokesh,

Quoted 71 lines

AM574x-idk has the following DDR parts attached:
EMIF1: MT41K256M16HA (1GB with ECC)
EMIF2: MT41K256M16HA (1GB without ECC)

Enabling 2GB DDR without interleaving between EMIFs. And enabling ECC on EMIF1.

Signed-off-by Lokesh Vutla <[email protected]>
Signed-off-by Krunal Bhargav <[email protected]>
---
 board/ti/am57xx/board.c | 47

++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-)

board/ti/am57xx/board.c +0 -0
index 2d14ae54fe..1377c7b1fe 100644
@@ -89,10 +89,18 @@ static const struct dmm_lisa_map_regs

am571x_idk_lisa_regs = { .is_ma_present = 0x1
};

board/ti/am57xx/board.c +6 -0
+static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
+	.dmm_lisa_map_2 = 0xc0600200,
+	.dmm_lisa_map_3 = 0x80600100,
+	.is_ma_present  = 0x1
+};
+
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs

**dmm_lisa_regs) {

board/ti/am57xx/board.c +2 -0
 	if (board_is_am571x_idk())
 		*dmm_lisa_regs = &am571x_idk_lisa_regs;
+	else if (board_is_am574x_idk())
+		*dmm_lisa_regs = &am574x_idk_lisa_regs;
 	else
 		*dmm_lisa_regs = &beagle_x15_lisa_regs;
 }

@@ -231,8 +239,8 @@ static const struct emif_regs

am571x_emif1_ddr3_666mhz_emif_regs =
{ .ref_ctrl =
0x0000514d, .ref_ctrl_final =
0x0000144a, .sdram_tim1 = 0xd333887c,

board/ti/am57xx/board.c +2 -2
-	.sdram_tim2			= 0x40b37fe3,
-	.sdram_tim3			= 0x409f8ada,
+	.sdram_tim2			= 0x30b37fe3,
+	.sdram_tim3			= 0x409f8ad8,
 	.read_idle_ctrl			= 0x00050000,
 	.zq_config			= 0x5007190b,
 	.temp_alert_config		= 0x00000000,

@@ -249,17 +257,50 @@ static const struct emif_regs

am571x_emif1_ddr3_666mhz_emif_regs =
{ .emif_rd_wr_exec_thresh = 0x00000305 };

+static const struct emif_regs
am574x_emif1_ddr3_666mhz_emif_ecc_regs = {

board/ti/am57xx/board.c +16 -0
+	.sdram_config_init		= 0x61863332,
+	.sdram_config			= 0x61863332,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl			= 0x0000514d,
+	.ref_ctrl_final			= 0x0000144a,
+	.sdram_tim1			= 0xd333887c,
+	.sdram_tim2			= 0x30b37fe3,
+	.sdram_tim3			= 0x409f8ad8,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x5007190b,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init	= 0x0024400f,
+	.emif_ddr_phy_ctlr_1		= 0x0e24400f,
+	.emif_ddr_ext_phy_ctrl_1	= 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00950095,

board/ti/am57xx/board.c static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { · line 286

Quoted 10 lines
board/ti/am57xx/board.c +10 -0
+	.emif_ddr_ext_phy_ctrl_4	= 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5	= 0x009e009e,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000305,
+	.emif_ecc_ctrl_reg		= 0xD0000001,
+	.emif_ecc_address_range_1	= 0x3FFF0000,
+	.emif_ecc_address_range_2	= 0x00000000
+};

I'm wondering if it would be possible to:

Embed this memory setup (even as binary blob) to SPL FIT -> Those values are generated from TI supplied excel sheet (when memory details are provided).

Pros:
----

- Since the same EMIF controller is used, one could only adjust the binary blob, when new memory (faster, slower, from other
manufacturer) is used in the product.

Quoted 5 lines
Quoted 1 line

- There would be no need to add such code to the board file.

yeah, ddr is not the only thing that comes in this bucket, PMIC data as well can be also made in similar way. I mean all the board related information can be moved out.

I think that the EMIF controller configuration is a bit special.

As you pointed out - for the whole AM57xx family one EMIF controller type is used.

Quoted 2 lines

But then the binary size will still
remain the same.

The goal here would be to not make the binary smaller, but reducing the maintanence effort.

Example use case - company X has a product. They are using single u-boot (with SPL and dts). The only thing, which they need to change is the data needed for setting up proper memory configuration (DDR2/DDR3, speed - 1500, 1333, ECC enabled/disabled, module size, etc). This all is done in EMIF.

With separate EMIF blob configuration they don't need to rebuild u-boot
- they only change memory configuration binary data.

This data has a separate room in the non-volatile memory (e.g. SPI-NOR flash).

Quoted 7 lines
Quoted 2 lines

Also, we will need a new driver to parse these new binary formats.

EMIF configuration data is IIRC 128 B at most. It is even possible to copy 1:1 the binary data to EMIF (as it is now done in the u-boot code).

Hence, the "driver" would boil down to "memcpy".

Agreed. This should be doable. Tom, do you have any comments on this new sequence?

On a side node, I will post a v2 for this series with the existing data. Cleanup can be done for the entire supported boards once the above discussion is concluded.

Thanks and regards,
Lokesh

#18 lore raw

PATCH 9/13 board: ti: am574x-idk: Add ddr data support

Hi Lokesh,

Quoted 3 lines

Hi Lukas,

Sorry for the delayed response.

No problem :-). Happy new year :-)

Quoted 142 lines · Lukasz Majewski
Quoted 140 lines

Hi Lokesh,

Quoted 101 lines

Hi Lukas,

Quoted 98 lines · Lukasz Majewski

Hi Lokesh,

Quoted 71 lines

AM574x-idk has the following DDR parts attached:
EMIF1: MT41K256M16HA (1GB with ECC)
EMIF2: MT41K256M16HA (1GB without ECC)

Enabling 2GB DDR without interleaving between EMIFs. And enabling ECC on EMIF1.

Signed-off-by Lokesh Vutla <[email protected]>
Signed-off-by Krunal Bhargav <[email protected]>
---
 board/ti/am57xx/board.c | 47

++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-)

board/ti/am57xx/board.c +0 -0
index 2d14ae54fe..1377c7b1fe 100644
@@ -89,10 +89,18 @@ static const struct dmm_lisa_map_regs

am571x_idk_lisa_regs = { .is_ma_present = 0x1
};

board/ti/am57xx/board.c +6 -0
+static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
+	.dmm_lisa_map_2 = 0xc0600200,
+	.dmm_lisa_map_3 = 0x80600100,
+	.is_ma_present  = 0x1
+};
+
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs

**dmm_lisa_regs) {

board/ti/am57xx/board.c +2 -0
 	if (board_is_am571x_idk())
 		*dmm_lisa_regs = &am571x_idk_lisa_regs;
+	else if (board_is_am574x_idk())
+		*dmm_lisa_regs = &am574x_idk_lisa_regs;
 	else
 		*dmm_lisa_regs = &beagle_x15_lisa_regs;
 }

@@ -231,8 +239,8 @@ static const struct emif_regs

am571x_emif1_ddr3_666mhz_emif_regs =
{ .ref_ctrl =
0x0000514d, .ref_ctrl_final =
0x0000144a, .sdram_tim1 = 0xd333887c,

board/ti/am57xx/board.c +2 -2
-	.sdram_tim2			= 0x40b37fe3,
-	.sdram_tim3			= 0x409f8ada,
+	.sdram_tim2			= 0x30b37fe3,
+	.sdram_tim3			= 0x409f8ad8,
 	.read_idle_ctrl			= 0x00050000,
 	.zq_config			= 0x5007190b,
 	.temp_alert_config		= 0x00000000,

@@ -249,17 +257,50 @@ static const struct emif_regs

am571x_emif1_ddr3_666mhz_emif_regs =
{ .emif_rd_wr_exec_thresh = 0x00000305 };

+static const struct emif_regs
am574x_emif1_ddr3_666mhz_emif_ecc_regs = {

board/ti/am57xx/board.c +16 -0
+	.sdram_config_init		= 0x61863332,
+	.sdram_config			= 0x61863332,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl			= 0x0000514d,
+	.ref_ctrl_final			= 0x0000144a,
+	.sdram_tim1			= 0xd333887c,
+	.sdram_tim2			= 0x30b37fe3,
+	.sdram_tim3			= 0x409f8ad8,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x5007190b,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init	= 0x0024400f,
+	.emif_ddr_phy_ctlr_1		= 0x0e24400f,
+	.emif_ddr_ext_phy_ctrl_1	= 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00950095,

board/ti/am57xx/board.c static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { · line 286

Quoted 10 lines
board/ti/am57xx/board.c +10 -0
+	.emif_ddr_ext_phy_ctrl_4	= 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5	= 0x009e009e,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000305,
+	.emif_ecc_ctrl_reg		= 0xD0000001,
+	.emif_ecc_address_range_1	= 0x3FFF0000,
+	.emif_ecc_address_range_2	= 0x00000000
+};

I'm wondering if it would be possible to:

Embed this memory setup (even as binary blob) to SPL FIT -> Those values are generated from TI supplied excel sheet (when memory details are provided).

Pros:
----

- Since the same EMIF controller is used, one could only adjust the binary blob, when new memory (faster, slower, from other manufacturer) is used in the product.

Quoted 5 lines
Quoted 1 line

- There would be no need to add such code to the board file.

yeah, ddr is not the only thing that comes in this bucket, PMIC data as well can be also made in similar way. I mean all the board related information can be moved out.

I think that the EMIF controller configuration is a bit special.

As you pointed out - for the whole AM57xx family one EMIF controller type is used.

Quoted 2 lines

But then the binary size will still
remain the same.

The goal here would be to not make the binary smaller, but reducing the maintanence effort.

Example use case - company X has a product. They are using single u-boot (with SPL and dts). The only thing, which they need to change is the data needed for setting up proper memory configuration (DDR2/DDR3, speed - 1500, 1333, ECC enabled/disabled, module size, etc). This all is done in EMIF.

With separate EMIF blob configuration they don't need to rebuild u-boot
- they only change memory configuration binary data.

This data has a separate room in the non-volatile memory (e.g. SPI-NOR flash).

Quoted 2 lines

Also, we will need a new driver to parse these new binary formats.

EMIF configuration data is IIRC 128 B at most. It is even possible to copy 1:1 the binary data to EMIF (as it is now done in the u-boot code).

Quoted 5 lines
Quoted 1 line

Hence, the "driver" would boil down to "memcpy".

Agreed. This should be doable. Tom, do you have any comments on this new sequence?

Ok. Lets wait for Tom's opinion.

Quoted 9 lines

On a side node, I will post a v2 for this series with the existing data. Cleanup can be done for the entire supported boards once the above discussion is concluded.

Thanks and regards,
Lokesh

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de -------------- next part --------------
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#19 lore raw

PATCH 9/13 board: ti: am574x-idk: Add ddr data support

In reply to Lokesh Vutla
Quoted 140 lines · Lokesh Vutla

Hi Lukas,

Sorry for the delayed response.

Quoted 135 lines · Lukasz Majewski

Hi Lokesh,

Quoted 101 lines

Hi Lukas,

Quoted 98 lines · Lukasz Majewski

Hi Lokesh,

Quoted 71 lines

AM574x-idk has the following DDR parts attached:
EMIF1: MT41K256M16HA (1GB with ECC)
EMIF2: MT41K256M16HA (1GB without ECC)

Enabling 2GB DDR without interleaving between EMIFs. And enabling ECC on EMIF1.

Signed-off-by Lokesh Vutla <[email protected]>
Signed-off-by Krunal Bhargav <[email protected]>
---
 board/ti/am57xx/board.c | 47

++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-)

board/ti/am57xx/board.c +0 -0
index 2d14ae54fe..1377c7b1fe 100644
@@ -89,10 +89,18 @@ static const struct dmm_lisa_map_regs

am571x_idk_lisa_regs = { .is_ma_present = 0x1
};

board/ti/am57xx/board.c +6 -0
+static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
+	.dmm_lisa_map_2 = 0xc0600200,
+	.dmm_lisa_map_3 = 0x80600100,
+	.is_ma_present  = 0x1
+};
+
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs

**dmm_lisa_regs) {

board/ti/am57xx/board.c +2 -0
 	if (board_is_am571x_idk())
 		*dmm_lisa_regs = &am571x_idk_lisa_regs;
+	else if (board_is_am574x_idk())
+		*dmm_lisa_regs = &am574x_idk_lisa_regs;
 	else
 		*dmm_lisa_regs = &beagle_x15_lisa_regs;
 }

@@ -231,8 +239,8 @@ static const struct emif_regs

am571x_emif1_ddr3_666mhz_emif_regs =
{ .ref_ctrl =
0x0000514d, .ref_ctrl_final =
0x0000144a, .sdram_tim1 = 0xd333887c,

board/ti/am57xx/board.c +2 -2
-	.sdram_tim2			= 0x40b37fe3,
-	.sdram_tim3			= 0x409f8ada,
+	.sdram_tim2			= 0x30b37fe3,
+	.sdram_tim3			= 0x409f8ad8,
 	.read_idle_ctrl			= 0x00050000,
 	.zq_config			= 0x5007190b,
 	.temp_alert_config		= 0x00000000,

@@ -249,17 +257,50 @@ static const struct emif_regs

am571x_emif1_ddr3_666mhz_emif_regs =
{ .emif_rd_wr_exec_thresh = 0x00000305 };

+static const struct emif_regs
am574x_emif1_ddr3_666mhz_emif_ecc_regs = {

board/ti/am57xx/board.c +16 -0
+	.sdram_config_init		= 0x61863332,
+	.sdram_config			= 0x61863332,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl			= 0x0000514d,
+	.ref_ctrl_final			= 0x0000144a,
+	.sdram_tim1			= 0xd333887c,
+	.sdram_tim2			= 0x30b37fe3,
+	.sdram_tim3			= 0x409f8ad8,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x5007190b,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init	= 0x0024400f,
+	.emif_ddr_phy_ctlr_1		= 0x0e24400f,
+	.emif_ddr_ext_phy_ctrl_1	= 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00950095,

board/ti/am57xx/board.c static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { · line 286

Quoted 10 lines
board/ti/am57xx/board.c +10 -0
+	.emif_ddr_ext_phy_ctrl_4	= 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5	= 0x009e009e,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000305,
+	.emif_ecc_ctrl_reg		= 0xD0000001,
+	.emif_ecc_address_range_1	= 0x3FFF0000,
+	.emif_ecc_address_range_2	= 0x00000000
+};

I'm wondering if it would be possible to:

Embed this memory setup (even as binary blob) to SPL FIT -> Those values are generated from TI supplied excel sheet (when memory details are provided).

Pros:
----

- Since the same EMIF controller is used, one could only adjust the binary blob, when new memory (faster, slower, from other
manufacturer) is used in the product.

Quoted 5 lines
Quoted 1 line

- There would be no need to add such code to the board file.

yeah, ddr is not the only thing that comes in this bucket, PMIC data as well can be also made in similar way. I mean all the board related information can be moved out.

I think that the EMIF controller configuration is a bit special.

As you pointed out - for the whole AM57xx family one EMIF controller type is used.

Quoted 2 lines

But then the binary size will still
remain the same.

The goal here would be to not make the binary smaller, but reducing the maintanence effort.

Example use case - company X has a product. They are using single u-boot (with SPL and dts). The only thing, which they need to change is the data needed for setting up proper memory configuration (DDR2/DDR3, speed - 1500, 1333, ECC enabled/disabled, module size, etc). This all is done in EMIF.

With separate EMIF blob configuration they don't need to rebuild u-boot
- they only change memory configuration binary data.

This data has a separate room in the non-volatile memory (e.g. SPI-NOR flash).

Quoted 2 lines

Also, we will need a new driver to parse these new binary formats.

Quoted 8 lines
Quoted 4 lines

EMIF configuration data is IIRC 128 B at most. It is even possible to copy 1:1 the binary data to EMIF (as it is now done in the u-boot code).

Hence, the "driver" would boil down to "memcpy".

Agreed. This should be doable. Tom, do you have any comments on this new sequence?

Sorry for the delayed response. I'm not sure this is a good idea, at least not without seeing a patch doing it. While a lot of this data is fairly opaque, the structs that say field X is value Y is helpful at times when debugging the odd problem. And there's always the programming sequence issues as well. So, I guess I'd have to see a patch where moving in this direction really does make life easier / cleaner to be convinced it's a good idea. Thanks!

Signature · 8 lines
Tom
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author
#20 lore raw

PATCH 10/13 board: ti: am574x-idk: Update pinmux using latest PMT

In reply to Lokesh Vutla

Update the board pinmux for AM574x-IDK board using latest PMT[1] and the board files named am574x_idk_v1p3b_sr2p0 that were auto generated on 13th October, 2017 by "Ahmad Rashed <[email protected]>".

Signed-off-by Lokesh Vutla <[email protected]>
---
 board/ti/am57xx/board.c    |   7 +-
 board/ti/am57xx/mux_data.h | 299 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 305 insertions(+), 1 deletion(-)
board/ti/am57xx/board.c +6 -1
index 1377c7b1fe..8862ee932c 100644
@@ -731,11 +731,16 @@ void recalibrate_iodelay(void)
 	int pconf_sz, iod_sz, delta_iod_sz = 0;
 	int ret;
 
-	if (board_is_am572x_idk() || board_is_am574x_idk()) {
+	if (board_is_am572x_idk()) {
 		pconf = core_padconf_array_essential_am572x_idk;
 		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 		iod = iodelay_cfg_array_am572x_idk;
 		iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
+	} else if (board_is_am574x_idk()) {
+		pconf = core_padconf_array_essential_am574x_idk;
+		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
+		iod = iodelay_cfg_array_am574x_idk;
+		iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
 	} else if (board_is_am571x_idk()) {
 		pconf = core_padconf_array_essential_am571x_idk;
 		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
board/ti/am57xx/mux_data.h +299 -0

311 lines not on this page · raw message

Signature · 1 line
2.15.1
author
#21 lore raw

PATCH 11/13 board: ti: am57xx: Enable CMD_DDR3

In reply to Lokesh Vutla

Enable CMD_DDR3 on all am57xx based platforms.

Signed-off-by Lokesh Vutla <[email protected]>
---
 arch/arm/mach-omap2/omap5/Kconfig | 1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-omap2/omap5/Kconfig +1 -0
index 8c1730a6be..deb9873cc5 100644
@@ -39,6 +39,7 @@ config TARGET_AM57XX_EVM
 	select BOARD_LATE_INIT
 	select DRA7XX
 	select TI_I2C_BOARD_DETECT
+	select CMD_DDR3
 	imply SCSI
 	imply SPL_THERMAL
 	imply DM_THERMAL
Signature · 1 line
2.15.1
#22 lore raw

PATCH 11/13 board: ti: am57xx: Enable CMD_DDR3

Hi Lokesh,

Quoted 12 lines

Enable CMD_DDR3 on all am57xx based platforms.

Signed-off-by Lokesh Vutla <[email protected]>
---
 arch/arm/mach-omap2/omap5/Kconfig | 1 +
 1 file changed, 1 insertion(+)
(quoted diff) +0 -0

b/arch/arm/mach-omap2/omap5/Kconfig index 8c1730a6be..deb9873cc5 100644 --- a/arch/arm/mach-omap2/omap5/Kconfig
+++ b/arch/arm/mach-omap2/omap5/Kconfig

arch/arm/mach-omap2/omap5/Kconfig config TARGET_AM57XX_EVM · line 42

Quoted 4 lines
arch/arm/mach-omap2/omap5/Kconfig +1 -0
@@ -39,6 +39,7 @@ config TARGET_AM57XX_EVM
 	select BOARD_LATE_INIT
 	select DRA7XX
 	select TI_I2C_BOARD_DETECT
+	select CMD_DDR3

I'm just curious - what is the purpose of this command?

arch/arm/mach-omap2/omap5/Kconfig config TARGET_AM57XX_EVM · line 45

Quoted 3 lines
arch/arm/mach-omap2/omap5/Kconfig +0 -0
 	imply SCSI
 	imply SPL_THERMAL
 	imply DM_THERMAL

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de -------------- next part --------------
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author
#23 lore raw

PATCH 11/13 board: ti: am57xx: Enable CMD_DDR3

Hi Lukas,

Quoted 9 lines · Lukasz Majewski

Hi Lokesh,

Quoted 7 lines

Enable CMD_DDR3 on all am57xx based platforms.

Signed-off-by Lokesh Vutla <[email protected]>
---
 arch/arm/mach-omap2/omap5/Kconfig | 1 +
 1 file changed, 1 insertion(+)
Quoted 11 lines

arch/arm/mach-omap2/omap5/Kconfig config TARGET_AM57XX_EVM · line 42

Quoted 9 lines
(quoted diff) +0 -0

b/arch/arm/mach-omap2/omap5/Kconfig index 8c1730a6be..deb9873cc5 100644 --- a/arch/arm/mach-omap2/omap5/Kconfig
+++ b/arch/arm/mach-omap2/omap5/Kconfig

arch/arm/mach-omap2/omap5/Kconfig +1 -0
@@ -39,6 +39,7 @@ config TARGET_AM57XX_EVM
 	select BOARD_LATE_INIT
 	select DRA7XX
 	select TI_I2C_BOARD_DETECT
+	select CMD_DDR3

I'm just curious - what is the purpose of this command?

This command supports memory testing and ecc testing.

Thanks and regards,
Lokesh

author
#24 lore raw

PATCH 12/13 ARM: dts: am574x-idk: Add initial support

In reply to Lokesh Vutla

Add initial dts support for am574x-idk

Signed-off-by Lokesh Vutla <[email protected]>

---
- DTS patch posted to kernel: https://patchwork.kernel.org/patch/10118295/

 arch/arm/dts/Makefile                     |   1 +
 arch/arm/dts/am572x-idk-common.dtsi       | 100 ++++++++++++++++++++++++++++++
 arch/arm/dts/am572x-idk.dts               |  93 +--------------------------
 arch/arm/dts/am574x-idk.dts               |  22 +++++++
 arch/arm/dts/am57xx-commercial-grade.dtsi |   1 +
 arch/arm/dts/am57xx-industrial-grade.dtsi |   1 +
 configs/am57xx_evm_defconfig              |   2 +-
 configs/am57xx_hs_evm_defconfig           |   2 +-
 8 files changed, 128 insertions(+), 94 deletions(-)
 create mode 100644 arch/arm/dts/am572x-idk-common.dtsi
 create mode 100644 arch/arm/dts/am574x-idk.dts
arch/arm/dts/Makefile +1 -0
index 1c9ac1468b..c0fc414292 100644
@@ -187,6 +187,7 @@ dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb	\
 dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
 	am57xx-beagle-x15-revb1.dtb \
 	am57xx-beagle-x15-revc.dtb \
+	am574x-idk.dtb \
 	am572x-idk.dtb	\
 	am571x-idk.dtb
 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
arch/arm/dts/am572x-idk-common.dtsi new file +100 -0

100 lines not on this page · raw message

arch/arm/dts/am572x-idk.dts +1 -92

108 lines not on this page · raw message

arch/arm/dts/am574x-idk.dts new file +22 -0
new file mode 100644
index 0000000000..41e12a382d
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+
+/dts-v1/;
+
+#include "dra76x.dtsi"
+#include "am572x-idk-common.dtsi"
+
+/ {
+	model = "TI AM5748 IDK";
+	compatible = "ti,am5728-idk", "ti,dra762", "ti,dra7";
+};
+
+&qspi {
+	spi-max-frequency = <96000000>;
+	m25p80 at 0 {
+		spi-max-frequency = <96000000>;
+	};
+};
arch/arm/dts/am57xx-commercial-grade.dtsi +1 -0
index c183654464..3eed6e09c8 100644
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 &cpu_alert0 {
 	temperature = <80000>; /* milliCelsius */
 };
arch/arm/dts/am57xx-industrial-grade.dtsi +1 -0
index 70c8c4ba19..422f953fc8 100644
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 &cpu_alert0 {
 	temperature = <90000>; /* milliCelsius */
 };
configs/am57xx_evm_defconfig +1 -1
index fc96401d3e..e1738e00d0 100644
@@ -35,7 +35,7 @@ CONFIG_CMD_SPL=y
 CONFIG_ISO_PARTITION=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk"
+CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
configs/am57xx_hs_evm_defconfig +1 -1
index 681e2a54c8..25e620c6dc 100644
@@ -38,7 +38,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_ISO_PARTITION=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk"
+CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
Signature · 1 line
2.15.1
#25 lore raw

PATCH 12/13 ARM: dts: am574x-idk: Add initial support

Quoted 5 lines · Lokesh Vutla

Add initial dts support for am574x-idk

Signed-off-by Lokesh Vutla <[email protected]>

---
- DTS patch posted to kernel: https://patchwork.kernel.org/patch/10118295/

Quoted 11 lines
 arch/arm/dts/Makefile                     |   1 +
 arch/arm/dts/am572x-idk-common.dtsi       | 100 ++++++++++++++++++++++++++++++
 arch/arm/dts/am572x-idk.dts               |  93 +--------------------------
 arch/arm/dts/am574x-idk.dts               |  22 +++++++
 arch/arm/dts/am57xx-commercial-grade.dtsi |   1 +
 arch/arm/dts/am57xx-industrial-grade.dtsi |   1 +
 configs/am57xx_evm_defconfig              |   2 +-
 configs/am57xx_hs_evm_defconfig           |   2 +-
 8 files changed, 128 insertions(+), 94 deletions(-)
 create mode 100644 arch/arm/dts/am572x-idk-common.dtsi
 create mode 100644 arch/arm/dts/am574x-idk.dts

What's the status of these DTS/DTSI files wrt the kernel? Thanks!

Signature · 8 lines
Tom
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author
#26 lore raw

PATCH 12/13 ARM: dts: am574x-idk: Add initial support

Quoted 19 lines · Tom Rini
Quoted 5 lines · Lokesh Vutla

Add initial dts support for am574x-idk

Signed-off-by Lokesh Vutla <[email protected]>

---
- DTS patch posted to kernel: https://patchwork.kernel.org/patch/10118295/

Quoted 11 lines
 arch/arm/dts/Makefile                     |   1 +
 arch/arm/dts/am572x-idk-common.dtsi       | 100 ++++++++++++++++++++++++++++++
 arch/arm/dts/am572x-idk.dts               |  93 +--------------------------
 arch/arm/dts/am574x-idk.dts               |  22 +++++++
 arch/arm/dts/am57xx-commercial-grade.dtsi |   1 +
 arch/arm/dts/am57xx-industrial-grade.dtsi |   1 +
 configs/am57xx_evm_defconfig              |   2 +-
 configs/am57xx_hs_evm_defconfig           |   2 +-
 8 files changed, 128 insertions(+), 94 deletions(-)
 create mode 100644 arch/arm/dts/am572x-idk-common.dtsi
 create mode 100644 arch/arm/dts/am574x-idk.dts
Quoted 2 lines

What's the status of these DTS/DTSI files wrt the kernel? Thanks!

DTS patches merged today. Will post a v2 of this series soon.

Thanks and regards,
Lokesh

author
#27 lore raw

PATCH 13/13 env: ti: Select dtb name for dra76x and am574

In reply to Lokesh Vutla

Select dtb name for am574x-idk and dra76x evm with acd package.

Signed-off-by Lokesh Vutla <[email protected]>
---
 include/environment/ti/boot.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
include/environment/ti/boot.h +3 -1
index 799d9840aa..0a2342061c 100644
@@ -67,7 +67,7 @@
 			"setenv fdtfile dra72-evm.dtb; fi;" \
 		"if test $board_name = dra71x; then " \
 			"setenv fdtfile dra71-evm.dtb; fi;" \
-		"if test $board_name = dra76x; then " \
+		"if test $board_name = dra76x_acd; then " \
 			"setenv fdtfile dra76-evm.dtb; fi;" \
 		"if test $board_name = beagle_x15; then " \
 			"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \

@@ -77,6 +77,8 @@
 			"setenv fdtfile am57xx-beagle-x15-revc.dtb; fi;" \
 		"if test $board_name = am572x_idk; then " \
 			"setenv fdtfile am572x-idk.dtb; fi;" \
+		"if test $board_name = am574x_idk; then " \
+			"setenv fdtfile am574x-idk.dtb; fi;" \
 		"if test $board_name = am57xx_evm; then " \
 			"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
 		"if test $board_name = am57xx_evm_reva3; then " \
Signature · 1 line
2.15.1