dma: xilinx: Add driver for Video Framebuffer IP
PATCH 2/2 dma: xilinx: Add driver for Video Framebuffer IP
Quoted 1 line · Michal Simek
Hi Vinod,
Hey Michal,
Quoted 63 lines · Vinod Koul
Quoted 60 lines · Vishal Sagar
Quoted 8 lines
The Video Framebuffer IP is available in two forms: read or write. This driver supports either form of the IP.
Each IP is a single channel DMA and is video format aware. It can read/write video data arranged from/to memory as packed or semi-planar way based on the selected video format.
To get list of supported video formats, clients can call certain APIs exposed by the driver. This driver introduces support for these IPs and integrates with the DMA Engine Framework.The subsytem name is dmaengine!
Quoted 10 lines
Signed-off-by Radhey Shyam Pandey <[email protected]>Signed-off-by John Nichols <[email protected]>Signed-off-by Jeffrey Mouroux <[email protected]>Signed-off-by Michal Simek <[email protected]>Signed-off-by Hyun Kwon <[email protected]>Signed-off-by Vishal Sagar <[email protected]>--- drivers/dma/Kconfig | 14 +- drivers/dma/xilinx/Makefile | 1 + drivers/dma/xilinx/xilinx_frmbuf.c | 1155 ++++++++++++++++++++++++++++++++++++Thats a very large file for review, do consider splitting stuff
Review config MOXART_DMA · line 345
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-1@@ -342,7 +342,7 @@ config MOXART_DMA select DMA_VIRTUAL_CHANNELS help Enable support for the MOXA ART SoC DMA controller. - +why this noise, this patch has some many sign-off's but didnt anyone see this noise?
Review config MOXART_DMA · line 346
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-0+// SPDX-License-Identifier: GPL-2.0Copyright needs to follow this in C99 style
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-0+/* + * DMAEngine driver for Xilinx Framebuffer IP + * + * Copyright (C) 2016 - 2017 Xilinx, Inc. All rights reserved. + * + * Authors: Radhey Shyam Pandey <[email protected]> + * John Nichols <[email protected]> + * Jeffrey Mouroux <[email protected]> + * + * Based on the Freescale DMA driver.Review config MOXART_DMA
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-0+ * + * Description: + * The AXI Framebuffer core is a soft Xilinx IP core that + * provides high-bandwidth direct memory access between memory + * and AXI4-Stream. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version.Quoted 1 line
why do you need this license text? With SPDX tag this is implied..
Quoted 7 lines
We are in touch with Xilinx Legal to clear this if SPDX is enough. We have been discussing this recently here.
https://lkml.org/lkml/2017/12/18/112I will let you know when we have this discussion done. Right now I have recommended to add SPDX header and also license text fragment which was present in driver version added to Xilinx git tree.
Been there done that :) I was adding soundwire subsystem and went thru same hoops and finally had to remov the text, so it would help if you can remove.
Adding Philippe for his comments.