Add efuse driver for Ingenic JZ4780 SoC
Subsystems (4)
v2 cover Add efuse driver for Ingenic JZ4780 SoC
This patchset bring support for read-only access to the JZ4780 efuse as found on MIPS Creator CI20.
To keep the driver as simple as possible, it was not possible to re-use most of the nvmem core functionalities. This driver is not compatible with the original efuse driver as found in the custom linux kernel from upstream (1), in particular it does not expose to the users neither:/sys/devices/platform/*/chip_id nor /sys/devices/platform/*/user_id.
The goal of this driver is to provide access to the MAC address to the dm9000 driver.
(1) https://github.com/ZubairLK/CI20_linux/commit/6efd4ffca7dcfaff0794ab60cd6922ce96c60419
Changes in v2:
Properly handle offset and byte value from the main entry point. Also add a commit message in patch #2.
Mathieu Malaterre (1):
dts: Probe efuse for CI20
PrasannaKumar Muralidharan (1):
nvmem: add driver for JZ4780 efuse
.../ABI/testing/sysfs-driver-jz4780-efuse | 16 ++ .../bindings/nvmem/ingenic,jz4780-efuse.txt | 17 ++ MAINTAINERS | 5 + arch/mips/boot/dts/ingenic/jz4780.dtsi | 40 ++- arch/mips/configs/ci20_defconfig | 2 + drivers/nvmem/Kconfig | 10 + drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 305 +++++++++++++++++++++ 8 files changed, 385 insertions(+), 12 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt create mode 100644 drivers/nvmem/jz4780-efuse.c
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PATCH v2 1/2 nvmem: add driver for JZ4780 efuse
From: PrasannaKumar Muralidharan <[email protected]>
This patch brings support for the JZ4780 efuse. Currently it only expose a read only access to the entire 8K bits efuse memory.
--- .../ABI/testing/sysfs-driver-jz4780-efuse | 16 ++ .../bindings/nvmem/ingenic,jz4780-efuse.txt | 17 ++ MAINTAINERS | 5 + arch/mips/boot/dts/ingenic/jz4780.dtsi | 40 ++- drivers/nvmem/Kconfig | 10 + drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 305 +++++++++++++++++++++ 7 files changed, 383 insertions(+), 12 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt create mode 100644 drivers/nvmem/jz4780-efuse.c
Documentation/ABI/testing/sysfs-driver-jz4780-efuse new file +16 -0
@@ -0,0 +1,16 @@ +What: /sys/devices/*/<our-device>/nvmem +Date: December 2017 +Contact: PrasannaKumar Muralidharan <[email protected]> +Description: read-only access to the efuse on the Ingenic JZ4780 SoC + The SoC has a one time programmable 8K efuse that is + split into segments. The driver supports read only. + The segments are + 0x000 64 bit Random Number + 0x008 128 bit Ingenic Chip ID + 0x018 128 bit Customer ID + 0x028 3520 bit Reserved + 0x1E0 8 bit Protect Segment + 0x1E1 2296 bit HDMI Key + 0x300 2048 bit Security boot key +Users: any user space application which wants to read the Chip + and Customer ID
Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt new file +17 -0
@@ -0,0 +1,17 @@ +Ingenic JZ EFUSE driver bindings + +Required properties: +- "compatible" Must be set to "ingenic,jz4780-efuse" +- "reg" Register location and length +- "clocks" Handle for the ahb clock for the efuse. +- "clock-names" Must be "bus_clk" + +Example: + +efuse: efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100D0 0xFF>; + + clocks = <&cgu JZ4780_CLK_AHB2>; + clock-names = "bus_clk"; +};
MAINTAINERS +5 -0
@@ -6902,6 +6902,11 @@ M: Zubair Lutfullah Kakakhel <[email protected]> S: Maintained F: drivers/dma/dma-jz4780.c +INGENIC JZ4780 EFUSE Driver +M: PrasannaKumar Muralidharan <[email protected]> +S: Maintained +F: drivers/nvmem/jz4780-efuse.c + INGENIC JZ4780 NAND DRIVER M: Harvey Hunt <[email protected]> L: [email protected]
arch/mips/boot/dts/ingenic/jz4780.dtsi +28 -12
@@ -224,21 +224,37 @@ reg = <0x10002000 0x100>; }; - nemc: nemc@13410000 { - compatible = "ingenic,jz4780-nemc"; - reg = <0x13410000 0x10000>; - #address-cells = <2>; + + ahb2: ahb2 { + compatible = "simple-bus"; + #address-cells = <1>; #size-cells = <1>; - ranges = <1 0 0x1b000000 0x1000000 - 2 0 0x1a000000 0x1000000 - 3 0 0x19000000 0x1000000 - 4 0 0x18000000 0x1000000 - 5 0 0x17000000 0x1000000 - 6 0 0x16000000 0x1000000>; + ranges = <>; + + nemc: nemc@13410000 { + compatible = "ingenic,jz4780-nemc"; + reg = <0x13410000 0x10000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0x1b000000 0x1000000 + 2 0 0x1a000000 0x1000000 + 3 0 0x19000000 0x1000000 + 4 0 0x18000000 0x1000000 + 5 0 0x17000000 0x1000000 + 6 0 0x16000000 0x1000000>; + + clocks = <&cgu JZ4780_CLK_NEMC>; + + status = "disabled"; + }; - clocks = <&cgu JZ4780_CLK_NEMC>; + efuse: efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100d0 0xff>; - status = "disabled"; + clocks = <&cgu JZ4780_CLK_AHB2>; + clock-names = "bus_clk"; + }; }; bch: bch@134d0000 {
drivers/nvmem/Kconfig +10 -0
@@ -36,6 +36,16 @@ config NVMEM_IMX_OCOTP This driver can also be built as a module. If so, the module will be called nvmem-imx-ocotp. +config JZ4780_EFUSE + tristate "JZ4780 EFUSE Memory Support" + depends on MACH_JZ4780 || COMPILE_TEST + depends on HAS_IOMEM + help + Say Y here to include support for JZ4780 efuse memory found on + all JZ4780 SoC based devices. + To compile this driver as a module, choose M here: the module + will be called nvmem_jz4780_efuse. + config NVMEM_LPC18XX_EEPROM tristate "NXP LPC18XX EEPROM Memory Support" depends on ARCH_LPC18XX || COMPILE_TEST
drivers/nvmem/Makefile +2 -0
@@ -13,6 +13,8 @@ obj-$(CONFIG_NVMEM_IMX_IIM) += nvmem-imx-iim.o nvmem-imx-iim-y := imx-iim.o obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o nvmem-imx-ocotp-y := imx-ocotp.o +obj-$(CONFIG_JZ4780_EFUSE) += nvmem_jz4780_efuse.o +nvmem_jz4780_efuse-y := jz4780-efuse.o obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o nvmem_lpc18xx_eeprom-y := lpc18xx_eeprom.o obj-$(CONFIG_NVMEM_LPC18XX_OTP) += nvmem_lpc18xx_otp.o
drivers/nvmem/jz4780-efuse.c new file +305 -0
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2.11.0
Re: [PATCH v2 1/2] nvmem: add driver for JZ4780 efuse
Hi Mathieu,
drivers/nvmem/jz4780-efuse.c line 10
Quoted 13 lines · Mathieu Malaterre
drivers/nvmem/jz4780-efuse.c new file +10
-0@@ -0,0 +1,305 @@ +/* +* JZ4780 EFUSE Memory Support driver +* +* Copyright (c) 2017 PrasannaKumar Muralidharan <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +*/ +
Can you use SPDX identifier instead?
Quoted 125 lines
drivers/nvmem/jz4780-efuse.c new file +125
-0+/* +* Currently supports JZ4780 efuse which has 8K programmable bit. +* Efuse is separated into seven segments as below: +* +* ----------------------------------------------------------------------- +* | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit | 2048 bit | +* ----------------------------------------------------------------------- +* +* The rom itself is accessed using a 9 bit address line and an 8 word wide bus +* which reads/writes based on strobes. The strobe is configured in the config +* register and is based on number of cycles of the bus clock. +* +* Driver supports read only as the writes are done in the Factory. +*/ +#include <linux/bitops.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/nvmem-provider.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/timer.h> + +#define JZ_EFUCTRL (0x0)/* Control Register */ +#define JZ_EFUCFG (0x4)/* Configure Register*/ +#define JZ_EFUSTATE (0x8)/* Status Register */ +#define JZ_EFUDATA (n) (0xC + (n)*4) + +#define JZ_EFUSE_START_ADDR 0x200 +#define JZ_EFUSE_SEG1_OFF 0x00/* 64 bit Random Number */ +#define JZ_EFUSE_SEG2_OFF 0x08/* 128 bit Ingenic Chip ID */ +#define JZ_EFUSE_SEG3_OFF 0x18/* 128 bit Customer ID */ +#define JZ_EFUSE_SEG4_OFF 0x28/* 3520 bit Reserved */ +#define JZ_EFUSE_SEG5_OFF 0x1E0/* 8 bit Protect Segment */ +#define JZ_EFUSE_SEG6_OFF 0x1E1/* 2296 bit HDMI Key */ +#define JZ_EFUSE_SEG7_OFF 0x300/* 2048 bit Security boot key */ +#define JZ_EFUSE_END_ADDR 0x5FF + +#define JZ_EFUSE_EFUCTRL_CS BIT(30) +#define JZ_EFUSE_EFUCTRL_ADDR_MASK 0x1FF +#define JZ_EFUSE_EFUCTRL_ADDR_SHIFT 21 +#define JZ_EFUSE_EFUCTRL_LEN_MASK 0x1F +#define JZ_EFUSE_EFUCTRL_LEN_SHIFT 16 +#define JZ_EFUSE_EFUCTRL_PG_EN BIT(15) +#define JZ_EFUSE_EFUCTRL_WR_EN BIT(1) +#define JZ_EFUSE_EFUCTRL_RD_EN BIT(0) + +#define JZ_EFUSE_EFUCFG_INT_EN BIT(31) +#define JZ_EFUSE_EFUCFG_RD_ADJ_MASK 0xF +#define JZ_EFUSE_EFUCFG_RD_ADJ_SHIFT 20 +#define JZ_EFUSE_EFUCFG_RD_STR_MASK 0xF +#define JZ_EFUSE_EFUCFG_RD_STR_SHIFT 16 +#define JZ_EFUSE_EFUCFG_WR_ADJ_MASK 0xF +#define JZ_EFUSE_EFUCFG_WR_ADJ_SHIFT 12 +#define JZ_EFUSE_EFUCFG_WR_STR_MASK 0xFFF +#define JZ_EFUSE_EFUCFG_WR_STR_SHIFT 0 + +#define JZ_EFUSE_EFUSTATE_WR_DONE BIT(1) +#define JZ_EFUSE_EFUSTATE_RD_DONE BIT(0) + +#define JZ_EFUSE_WORD_SIZE 16 +#define JZ_EFUSE_STRIDE 8 + +struct jz4780_efuse { +struct device *dev; +void __iomem *iomem; +struct clk *clk; +unsigned int rd_adj; +unsigned int rd_strobe; +}; + +/* We read 32 byte chunks to avoid complexity in the driver. */ +static int jz4780_efuse_read_32bytes (struct jz4780_efuse *efuse,char *buf, +unsigned int addr) +{ +unsigned int tmp =0 ; +int i =0 ; +int timeout =1000 ; +int size =32 ; + +/* 1. Set config register */ + tmp =readl (efuse->iomem +JZ_EFUCFG ); + tmp &= ~((JZ_EFUSE_EFUCFG_RD_ADJ_MASK <<JZ_EFUSE_EFUCFG_RD_ADJ_SHIFT ) + | (JZ_EFUSE_EFUCFG_RD_STR_MASK <<JZ_EFUSE_EFUCFG_RD_STR_SHIFT )); + tmp |= (efuse->rd_adj <<JZ_EFUSE_EFUCFG_RD_ADJ_SHIFT ) + | (efuse->rd_strobe <<JZ_EFUSE_EFUCFG_RD_STR_SHIFT ); +writel (tmp, efuse->iomem +JZ_EFUCFG ); + +/* +* 2. Set control register to indicate what to read data address, +* read data numbers and read enable. +*/ + tmp =readl (efuse->iomem +JZ_EFUCTRL ); + tmp &= ~(JZ_EFUSE_EFUCFG_RD_STR_SHIFT + | (JZ_EFUSE_EFUCTRL_ADDR_MASK <<JZ_EFUSE_EFUCTRL_ADDR_SHIFT ) + |JZ_EFUSE_EFUCTRL_PG_EN |JZ_EFUSE_EFUCTRL_WR_EN + |JZ_EFUSE_EFUCTRL_WR_EN ); + +/* Need to select CS bit if address accesses upper 4Kbits memory */ +if (addr >= (JZ_EFUSE_START_ADDR +512 )) + tmp |=JZ_EFUSE_EFUCTRL_CS ; + + tmp |= (addr <<JZ_EFUSE_EFUCTRL_ADDR_SHIFT ) + | ((size -1 ) <<JZ_EFUSE_EFUCTRL_LEN_SHIFT ) + |JZ_EFUSE_EFUCTRL_RD_EN ; +writel (tmp, efuse->iomem +JZ_EFUCTRL ); + +/* +* 3. Wait status register RD_DONE set to 1 or EFUSE interrupted, +* software can read EFUSE data buffer 0 - 8 registers. +*/ +do { + tmp =readl (efuse->iomem +JZ_EFUSTATE ); +usleep_range (1000 ,2000 ); +if (timeout--) +break ; + }while (!(tmp &JZ_EFUSE_EFUSTATE_RD_DONE )); + +if (timeout <=0 ) { +dev_err (efuse->dev,"Timed out while reading\n" ); +return -EAGAIN ;
drivers/nvmem/jz4780-efuse.c line 145
Quoted 10 lines
drivers/nvmem/jz4780-efuse.c new file +10
-0+ } + +for (i =0 ; i < (size /4 ); i++) + *((unsigned int *)(buf + i *4 )) + =readl (efuse->iomem +JZ_EFUDATA (i)); + +return 0 ; +} + +static unsigned int segments[][2 ] = {
const?
Quoted 21 lines
drivers/nvmem/jz4780-efuse.c new file +21
-0+/* offset , size in bytes */ + { JZ_EFUSE_SEG1_OFF, 64 >> 3 }, /* bit Random Number */ + { JZ_EFUSE_SEG2_OFF, 128 >> 3 }, /* bit Ingenic Chip ID */ + { JZ_EFUSE_SEG3_OFF, 128 >> 3 }, /* bit Customer ID */ + { JZ_EFUSE_SEG4_OFF, 3520 >> 3 }, /* bit Reserved */ + { JZ_EFUSE_SEG5_OFF, 8 >> 3 }, /* bit Protect Segment */ + { JZ_EFUSE_SEG6_OFF, 2296 >> 3 }, /* bit HDMI Key */ + { JZ_EFUSE_SEG7_OFF, 2048 >> 3 } /* bit Security boot key */ +}; + +#define MAX (x, y) (((x) > (y)) ? (x) : (y)) +#define MIN (x, y) (((x) < (y)) ? (x) : (y)) + +/* PM recommends read/write each segment separately */ +static int jz4780_efuse_read_segment (struct jz4780_efuse *efuse,int segid, +unsigned int *offset,char *out,size_t *bytes) +{ +char buf[32 ]; +unsigned int lpos, buflen, ncount, remain; +unsigned int *segment = segments[segid]; +int j;
drivers/nvmem/jz4780-efuse.c line 176
Quoted 10 lines
drivers/nvmem/jz4780-efuse.c new file +10
-0+char *cur = out; +int ret; + +if (*bytes ==0 || + (*offset < segment[0 ] || *offset >= segment[0 ] + segment[1 ])) { +// nothing to see, move along +return 0 ; + } + lpos =MAX (segment[0 ], *offset); + buflen =MIN (segment[1 ], *bytes);
if *offset > segment[0] then you may read past the current segment.
On the other hand some segments are smaller than 32 bytes, so when jz4780_efuse_read_32bytes() is used, there will often be accesses across segment boundaries.
For this reason I don't see much point in having this split for segment reads. If it is really recommended/required (I haven't read the SoC's PM) then the read_32bytes() method needs to be changed to allow reads of any length (which would allow simplifying this method a lot). Alternatively if there isn't really such requirement, you could just read the whole memory without worrying about segment boundaries.
Quoted 20 lines
drivers/nvmem/jz4780-efuse.c new file +20
-0+ ncount = buflen /32 ; + remain = buflen %32 ; + +for (j =0 ; j < ncount ; ++j) { + ret =jz4780_efuse_read_32bytes (efuse, buf, lpos); +if (ret <0 ) +return ret; + +memcpy (cur, buf,sizeof (buf)); + cur +=sizeof (buf); + lpos +=sizeof (buf); + } +if (remain) { + ret =jz4780_efuse_read_32bytes (efuse, buf, lpos); +if (ret <0 ) +return ret; + +memcpy (cur, buf, remain); + cur += remain; + }
drivers/nvmem/jz4780-efuse.c line 206
Quoted 10 lines
drivers/nvmem/jz4780-efuse.c new file +10
-0+ *offset += buflen; + *bytes -= buflen; +return buflen; +} + +/* main entry point */ +static int jz4780_efuse_read (void *context,unsigned int offset, +void *val,size_t bytes) +{ +static const int nsegments =sizeof (segments) /sizeof (*segments);
any particular reason nsegments is static?
Quoted 100 lines
drivers/nvmem/jz4780-efuse.c new file +99
-0+struct jz4780_efuse *efuse = context; +char *cur = val; +int i, ret; + +for (i =0 ; i < nsegments; ++i) { + ret =jz4780_efuse_read_segment (efuse, i, &offset, cur, &bytes); +if (ret <0 ) +return ret; + cur += ret; + } + +return 0 ; +} + +static struct nvmem_config jz4780_efuse_nvmem_config = { + .name ="jz4780-efuse" , + .read_only = true, + .word_size =JZ_EFUSE_WORD_SIZE , + .stride =JZ_EFUSE_STRIDE , + .owner =THIS_MODULE , + .reg_read = jz4780_efuse_read, +}; + +static int jz4780_efuse_probe (struct platform_device *pdev) +{ +struct nvmem_device *nvmem; +struct jz4780_efuse *efuse; +struct resource *res; +unsigned long clk_rate; +struct device *dev = &pdev->dev; + + efuse =devm_kzalloc (&pdev->dev,sizeof (*efuse),GFP_KERNEL ); +if (!efuse) +return -ENOMEM ; + + res =platform_get_resource (pdev,IORESOURCE_MEM ,0 ); + efuse->iomem =devm_ioremap (&pdev->dev, res->start,resource_size (res)); +if (IS_ERR (efuse->iomem)) +return PTR_ERR (efuse->iomem); + + efuse->clk =devm_clk_get (&pdev->dev,"bus_clk" ); +if (IS_ERR (efuse->clk)) +return PTR_ERR (efuse->clk); + + clk_rate =clk_get_rate (efuse->clk); +/* +* rd_adj and rd_strobe are 4 bit values +* bus clk period * (rd_adj + 1) > 6.5ns +* bus clk period * (rd_adj + 5 + rd_strobe) > 35ns +*/ + efuse->rd_adj = (((6500 * (clk_rate /1000000 )) /1000000 ) +1 ) -1 ; + efuse->rd_strobe = ((((35000 * (clk_rate /1000000 )) /1000000 ) +1 ) + -5 - efuse->rd_adj); + +if ((efuse->rd_adj >0x1F ) || (efuse->rd_strobe >0x1F )) { +dev_err (&pdev->dev,"Cannot set clock configuration\n" ); +return -EINVAL ; + } + efuse->dev = dev; + + jz4780_efuse_nvmem_config.size =1024 ; + jz4780_efuse_nvmem_config.dev = &pdev->dev; + jz4780_efuse_nvmem_config.priv = efuse; + + nvmem =nvmem_register (&jz4780_efuse_nvmem_config); +if (IS_ERR (nvmem)) +return PTR_ERR (nvmem); + +platform_set_drvdata (pdev, nvmem); + +return 0 ; +} + +static int jz4780_efuse_remove (struct platform_device *pdev) +{ +struct nvmem_device *nvmem =platform_get_drvdata (pdev); + +return nvmem_unregister (nvmem); +} + +static const struct of_device_id jz4780_efuse_match[] = { + { .compatible ="ingenic,jz4780-efuse" }, + {/* sentinel */ }, +}; +MODULE_DEVICE_TABLE (of, jz4780_efuse_match); + +static struct platform_driver jz4780_efuse_driver = { + .probe = jz4780_efuse_probe, + .remove = jz4780_efuse_remove, + .driver = { + .name ="jz4780-efuse" , + .of_match_table = jz4780_efuse_match, + }, +}; +module_platform_driver (jz4780_efuse_driver); + +MODULE_AUTHOR ("PrasannaKumar Muralidharan <[email protected]>" ); +MODULE_DESCRIPTION ("Ingenic JZ4780 efuse driver" ); +MODULE_LICENSE ("GPL v2" );
Re: [PATCH v2 1/2] nvmem: add driver for JZ4780 efuse
In reply to Mathieu MalaterreQuoted 9 lines · Mathieu Malaterre
From: PrasannaKumar Muralidharan <[email protected]>
This patch brings support for the JZ4780 efuse. Currently it only expose a read only access to the entire 8K bits efuse memory.
Tested-by Mathieu Malaterre <[email protected]>Signed-off-by PrasannaKumar Muralidharan <[email protected]>Signed-off-by Mathieu Malaterre <[email protected]>---
Please split this patch, as you are mixing code, documentation, dts and MAINTAINER changes here.
Without which patch can not be reviewed!!
Thanks,
Srini
Quoted 9 lines
.../ABI/testing/sysfs-driver-jz4780-efuse | 16 ++.../bindings/nvmem/ingenic,jz4780-efuse.txt | 17 ++ MAINTAINERS | 5 + arch/mips/boot/dts/ingenic/jz4780.dtsi | 40 ++- drivers/nvmem/Kconfig | 10 + drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 305 +++++++++++++++++++++ 7 files changed, 383 insertions(+), 12 deletions(-)
...
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Re: [PATCH v2 1/2] nvmem: add driver for JZ4780 efuse
Hi Srini,
Quoted 14 lines · Srinivas Kandagatla
Quoted 10 lines · Mathieu Malaterre
From: PrasannaKumar Muralidharan <[email protected]>
This patch brings support for the JZ4780 efuse. Currently it only expose a read only access to the entire 8K bits efuse memory.
Tested-by Mathieu Malaterre <[email protected]>Signed-off-by PrasannaKumar Muralidharan <[email protected]>Signed-off-by Mathieu Malaterre <[email protected]>---
Quoted 4 lines
Please split this patch, as you are mixing code, documentation, dts and MAINTAINER changes here.
Without which patch can not be reviewed!!
Sure, will do it soon.
Quoted 16 lines
Thanks,
SriniQuoted 11 lines
.../ABI/testing/sysfs-driver-jz4780-efuse | 16 ++.../bindings/nvmem/ingenic,jz4780-efuse.txt | 17 ++ MAINTAINERS | 5 + arch/mips/boot/dts/ingenic/jz4780.dtsi | 40 ++- drivers/nvmem/Kconfig | 10 + drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 305 +++++++++++++++++++++ 7 files changed, 383 insertions(+), 12 deletions(-)
Quoted 1 line
...
Regards,
PrasannaKumar
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Rob Herring
maintainerRe: [PATCH v2 1/2] nvmem: add driver for JZ4780 efuse
In reply to Mathieu MalaterreQuoted 11 lines · Mathieu Malaterre
From: PrasannaKumar Muralidharan <[email protected]>
This patch brings support for the JZ4780 efuse. Currently it only expose a read only access to the entire 8K bits efuse memory.
Tested-by Mathieu Malaterre <[email protected]>Signed-off-by PrasannaKumar Muralidharan <[email protected]>Signed-off-by Mathieu Malaterre <[email protected]>--- .../ABI/testing/sysfs-driver-jz4780-efuse | 16 ++ .../bindings/nvmem/ingenic,jz4780-efuse.txt | 17 ++
Please split bindings to separate patch.
Quoted 2 lines
MAINTAINERS | 5 + arch/mips/boot/dts/ingenic/jz4780.dtsi | 40 ++-
dts files should also be separate.
Quoted 18 lines
drivers/nvmem/Kconfig | 10 + drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 305 +++++++++++++++++++++ 7 files changed, 383 insertions(+), 12 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt create mode 100644 drivers/nvmem/jz4780-efuse.cDocumentation/ABI/testing/sysfs-driver-jz4780-efuse new file +4
-0@@ -0,0 +1,16 @@ +What: /sys/devices/*/<our-device>/nvmem +Date: December 2017 +Contact: PrasannaKumar Muralidharan <[email protected]> +Description: read-only access to the efuse on the Ingenic JZ4780 SoC
Documentation/ABI/testing/sysfs-driver-jz4780-efuse line 14
Quoted 10 lines
Documentation/ABI/testing/sysfs-driver-jz4780-efuse new file +10
-0+ The SoC has a one time programmable 8K efuse that is + split into segments. The driver supports read only. + The segments are + 0x000 64 bit Random Number + 0x008 128 bit Ingenic Chip ID + 0x018 128 bit Customer ID + 0x028 3520 bit Reserved + 0x1E0 8 bit Protect Segment + 0x1E1 2296 bit HDMI Key + 0x300 2048 bit Security boot key
Why do these need to be exposed to userspace?
sysfs is 1 value per file and this is lots of different things.
We already have ways to feed random data (entropy) to the system. And we have a way to expose SoC ID info to userspace (socdev).
Quoted 30 lines
Documentation/ABI/testing/sysfs-driver-jz4780-efuse new file +2
-0+Users: any user space application which wants to read the Chip + and Customer IDDocumentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt new file +17
-0@@ -0,0 +1,17 @@ +Ingenic JZ EFUSE driver bindings + +Required properties: +- "compatible" Must be set to "ingenic,jz4780-efuse" +- "reg" Register location and length +- "clocks" Handle for the ahb clock for the efuse. +- "clock-names" Must be "bus_clk" + +Example: + +efuse: efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100D0 0xFF>; + + clocks = <&cgu JZ4780_CLK_AHB2>; + clock-names = "bus_clk"; +};MAINTAINERS +0
-0
MAINTAINERS M: Zubair Lutfullah Kakakhel <[email protected]> · line 6908
Quoted 7 lines
MAINTAINERS +4
-0@@ -6902,6 +6902,11 @@ M: Zubair Lutfullah Kakakhel <[email protected]> S: Maintained F: drivers/dma/dma-jz4780.c +INGENIC JZ4780 EFUSE Driver +M: PrasannaKumar Muralidharan <[email protected]> +S: Maintained +F: drivers/nvmem/jz4780-efuse.c
Binding file?
Quoted 9 lines
MAINTAINERS +1
-0+ INGENIC JZ4780 NAND DRIVER M: Harvey Hunt <[email protected]> L: [email protected]arch/mips/boot/dts/ingenic/jz4780.dtsi +0
-0
arch/mips/boot/dts/ingenic/jz4780.dtsi line 229
Quoted 10 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +3
-4@@ -224,21 +224,37 @@ reg = <0x10002000 0x100>; }; - nemc: nemc@13410000 { - compatible = "ingenic,jz4780-nemc"; - reg = <0x13410000 0x10000>; - #address-cells = <2>; + + ahb2: ahb2 { + compatible = "simple-bus";
This is an unrelated change and should be its own patch.
Quoted 21 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +14
-6+ #address-cells = <1>; #size-cells = <1>; - ranges = <1 0 0x1b000000 0x1000000 - 2 0 0x1a000000 0x1000000 - 3 0 0x19000000 0x1000000 - 4 0 0x18000000 0x1000000 - 5 0 0x17000000 0x1000000 - 6 0 0x16000000 0x1000000>; + ranges = <>; + + nemc: nemc@13410000 { + compatible = "ingenic,jz4780-nemc"; + reg = <0x13410000 0x10000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0x1b000000 0x1000000 + 2 0 0x1a000000 0x1000000 + 3 0 0x19000000 0x1000000 + 4 0 0x18000000 0x1000000 + 5 0 0x17000000 0x1000000 + 6 0 0x16000000 0x1000000>;
arch/mips/boot/dts/ingenic/jz4780.dtsi line 253
Quoted 10 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +8
-1+ + clocks = <&cgu JZ4780_CLK_NEMC>; + + status = "disabled"; + }; - clocks = <&cgu JZ4780_CLK_NEMC>; + efuse: efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100d0 0xff>;
You are creating an overlapping region here with nemc above. Don't do that.
Quoted 8 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +3
-1- status = "disabled"; + clocks = <&cgu JZ4780_CLK_AHB2>; + clock-names = "bus_clk"; + }; }; bch: bch@134d0000 {
Re: [PATCH v2 1/2] nvmem: add driver for JZ4780 efuse
Hi Rob,
Quoted 51 lines · Rob Herring
Quoted 11 lines · Mathieu Malaterre
From: PrasannaKumar Muralidharan <[email protected]>
This patch brings support for the JZ4780 efuse. Currently it only expose a read only access to the entire 8K bits efuse memory.
Tested-by Mathieu Malaterre <[email protected]>Signed-off-by PrasannaKumar Muralidharan <[email protected]>Signed-off-by Mathieu Malaterre <[email protected]>--- .../ABI/testing/sysfs-driver-jz4780-efuse | 16 ++ .../bindings/nvmem/ingenic,jz4780-efuse.txt | 17 ++Please split bindings to separate patch.
Quoted 2 lines
MAINTAINERS | 5 + arch/mips/boot/dts/ingenic/jz4780.dtsi | 40 ++-dts files should also be separate.
Quoted 18 lines
drivers/nvmem/Kconfig | 10 + drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 305 +++++++++++++++++++++ 7 files changed, 383 insertions(+), 12 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt create mode 100644 drivers/nvmem/jz4780-efuse.cDocumentation/ABI/testing/sysfs-driver-jz4780-efuse new file +4
-0@@ -0,0 +1,16 @@ +What: /sys/devices/*/<our-device>/nvmem +Date: December 2017 +Contact: PrasannaKumar Muralidharan <[email protected]> +Description: read-only access to the efuse on the Ingenic JZ4780 SoCDocumentation/ABI/testing/sysfs-driver-jz4780-efuse line 14
Quoted 10 lines
Documentation/ABI/testing/sysfs-driver-jz4780-efuse new file +10
-0+ The SoC has a one time programmable 8K efuse that is + split into segments. The driver supports read only. + The segments are + 0x000 64 bit Random Number + 0x008 128 bit Ingenic Chip ID + 0x018 128 bit Customer ID + 0x028 3520 bit Reserved + 0x1E0 8 bit Protect Segment + 0x1E1 2296 bit HDMI Key + 0x300 2048 bit Security boot keyWhy do these need to be exposed to userspace?
Quoted 4 lines
sysfs is 1 value per file and this is lots of different things.
We already have ways to feed random data (entropy) to the system. And we have a way to expose SoC ID info to userspace (socdev).
Currently ingenic chip id is not used anywhere. The vendor BSP exposed only chip id and customer id. Should we do the same? Please provide your suggestion.
Quoted 33 lines
Quoted 33 lines
Documentation/ABI/testing/sysfs-driver-jz4780-efuse new file +2
-0+Users: any user space application which wants to read the Chip + and Customer IDDocumentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt new file +17
-0@@ -0,0 +1,17 @@ +Ingenic JZ EFUSE driver bindings + +Required properties: +- "compatible" Must be set to "ingenic,jz4780-efuse" +- "reg" Register location and length +- "clocks" Handle for the ahb clock for the efuse. +- "clock-names" Must be "bus_clk" + +Example: + +efuse: efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100D0 0xFF>; + + clocks = <&cgu JZ4780_CLK_AHB2>; + clock-names = "bus_clk"; +};MAINTAINERS +0
-0@@ -6902,6 +6902,11 @@ M: Zubair Lutfullah Kakakhel <[email protected]> S: Maintained F: drivers/dma/dma-jz4780.c
Quoted 6 lines
MAINTAINERS M: Zubair Lutfullah Kakakhel <[email protected]> · line 6908
Quoted 4 lines
MAINTAINERS +4
-0+INGENIC JZ4780 EFUSE Driver +M: PrasannaKumar Muralidharan <[email protected]> +S: Maintained +F: drivers/nvmem/jz4780-efuse.cBinding file?
Sorry, missed it. Will add it.
Quoted 12 lines
Quoted 12 lines
MAINTAINERS +1
-0+ INGENIC JZ4780 NAND DRIVER M: Harvey Hunt <[email protected]> L: [email protected]arch/mips/boot/dts/ingenic/jz4780.dtsi +0
-0@@ -224,21 +224,37 @@ reg = <0x10002000 0x100>; };
Quoted 9 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi line 229
Quoted 7 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +3
-4- nemc: nemc@13410000 { - compatible = "ingenic,jz4780-nemc"; - reg = <0x13410000 0x10000>; - #address-cells = <2>; + + ahb2: ahb2 { + compatible = "simple-bus";This is an unrelated change and should be its own patch.
The efuse register address range is a subset of address range of nemc. So decided to make nemc and efuse as nodes with parent node ahb2. This is required for efuse driver to work. I am not able to understand what you mean by unrelated change. Can you please explain it?
Quoted 27 lines
Quoted 27 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +19
-6+ #address-cells = <1>; #size-cells = <1>; - ranges = <1 0 0x1b000000 0x1000000 - 2 0 0x1a000000 0x1000000 - 3 0 0x19000000 0x1000000 - 4 0 0x18000000 0x1000000 - 5 0 0x17000000 0x1000000 - 6 0 0x16000000 0x1000000>; + ranges = <>; + + nemc: nemc@13410000 { + compatible = "ingenic,jz4780-nemc"; + reg = <0x13410000 0x10000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0x1b000000 0x1000000 + 2 0 0x1a000000 0x1000000 + 3 0 0x19000000 0x1000000 + 4 0 0x18000000 0x1000000 + 5 0 0x17000000 0x1000000 + 6 0 0x16000000 0x1000000>; + + clocks = <&cgu JZ4780_CLK_NEMC>; + + status = "disabled"; + };
Quoted 7 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi line 253
Quoted 4 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +3
-1- clocks = <&cgu JZ4780_CLK_NEMC>; + efuse: efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100d0 0xff>;You are creating an overlapping region here with nemc above. Don't do that.
Should "reg = <0x13410000 0x10000>;" be used instead?
Quoted 9 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi line 260
Quoted 9 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +3
-1- status = "disabled"; + clocks = <&cgu JZ4780_CLK_AHB2>; + clock-names = "bus_clk"; + }; }; bch: bch@134d0000 {
Thanks,
PrasannaKumar
Rob Herring
maintainerRe: [PATCH v2 1/2] nvmem: add driver for JZ4780 efuse
Quoted 54 lines · PrasannaKumar Muralidharan
Hi Rob,
Quoted 51 lines · Rob Herring
Quoted 11 lines · Mathieu Malaterre
From: PrasannaKumar Muralidharan <[email protected]>
This patch brings support for the JZ4780 efuse. Currently it only expose a read only access to the entire 8K bits efuse memory.
Tested-by Mathieu Malaterre <[email protected]>Signed-off-by PrasannaKumar Muralidharan <[email protected]>Signed-off-by Mathieu Malaterre <[email protected]>--- .../ABI/testing/sysfs-driver-jz4780-efuse | 16 ++ .../bindings/nvmem/ingenic,jz4780-efuse.txt | 17 ++Please split bindings to separate patch.
Quoted 2 lines
MAINTAINERS | 5 + arch/mips/boot/dts/ingenic/jz4780.dtsi | 40 ++-dts files should also be separate.
Quoted 18 lines
drivers/nvmem/Kconfig | 10 + drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 305 +++++++++++++++++++++ 7 files changed, 383 insertions(+), 12 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt create mode 100644 drivers/nvmem/jz4780-efuse.cDocumentation/ABI/testing/sysfs-driver-jz4780-efuse new file +4
-0@@ -0,0 +1,16 @@ +What: /sys/devices/*/<our-device>/nvmem +Date: December 2017 +Contact: PrasannaKumar Muralidharan <[email protected]> +Description: read-only access to the efuse on the Ingenic JZ4780 SoCDocumentation/ABI/testing/sysfs-driver-jz4780-efuse line 14
Quoted 10 lines
Documentation/ABI/testing/sysfs-driver-jz4780-efuse new file +10
-0+ The SoC has a one time programmable 8K efuse that is + split into segments. The driver supports read only. + The segments are + 0x000 64 bit Random Number + 0x008 128 bit Ingenic Chip ID + 0x018 128 bit Customer ID + 0x028 3520 bit Reserved + 0x1E0 8 bit Protect Segment + 0x1E1 2296 bit HDMI Key + 0x300 2048 bit Security boot keyWhy do these need to be exposed to userspace?
Quoted 8 lines
Quoted 4 lines
sysfs is 1 value per file and this is lots of different things.
We already have ways to feed random data (entropy) to the system. And we have a way to expose SoC ID info to userspace (socdev).
Currently ingenic chip id is not used anywhere. The vendor BSP exposed only chip id and customer id. Should we do the same? Please provide your suggestion.
No. Don't create an ABI if you don't really need it.
Quoted 105 lines
Quoted 34 lines
Quoted 34 lines
Documentation/ABI/testing/sysfs-driver-jz4780-efuse new file +2
-0+Users: any user space application which wants to read the Chip + and Customer IDDocumentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt new file +17
-0@@ -0,0 +1,17 @@ +Ingenic JZ EFUSE driver bindings + +Required properties: +- "compatible" Must be set to "ingenic,jz4780-efuse" +- "reg" Register location and length +- "clocks" Handle for the ahb clock for the efuse. +- "clock-names" Must be "bus_clk" + +Example: + +efuse: efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100D0 0xFF>; + + clocks = <&cgu JZ4780_CLK_AHB2>; + clock-names = "bus_clk"; +};MAINTAINERS +0
-0@@ -6902,6 +6902,11 @@ M: Zubair Lutfullah Kakakhel <[email protected]> S: Maintained F: drivers/dma/dma-jz4780.cQuoted 6 lines
MAINTAINERS M: Zubair Lutfullah Kakakhel <[email protected]> · line 6908
Quoted 4 lines
MAINTAINERS +4
-0+INGENIC JZ4780 EFUSE Driver +M: PrasannaKumar Muralidharan <[email protected]> +S: Maintained +F: drivers/nvmem/jz4780-efuse.cBinding file?
Sorry, missed it. Will add it.
Quoted 12 lines
Quoted 12 lines
MAINTAINERS +1
-0+ INGENIC JZ4780 NAND DRIVER M: Harvey Hunt <[email protected]> L: [email protected]arch/mips/boot/dts/ingenic/jz4780.dtsi +0
-0@@ -224,21 +224,37 @@ reg = <0x10002000 0x100>; };Quoted 9 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi line 229
Quoted 7 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +3
-4- nemc: nemc@13410000 { - compatible = "ingenic,jz4780-nemc"; - reg = <0x13410000 0x10000>; - #address-cells = <2>; + + ahb2: ahb2 { + compatible = "simple-bus";This is an unrelated change and should be its own patch.
The efuse register address range is a subset of address range of nemc. So decided to make nemc and efuse as nodes with parent node ahb2. This is required for efuse driver to work. I am not able to understand what you mean by unrelated change. Can you please explain it?
Quoted 27 lines
Quoted 27 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +19
-6+ #address-cells = <1>; #size-cells = <1>; - ranges = <1 0 0x1b000000 0x1000000 - 2 0 0x1a000000 0x1000000 - 3 0 0x19000000 0x1000000 - 4 0 0x18000000 0x1000000 - 5 0 0x17000000 0x1000000 - 6 0 0x16000000 0x1000000>; + ranges = <>; + + nemc: nemc@13410000 { + compatible = "ingenic,jz4780-nemc"; + reg = <0x13410000 0x10000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0x1b000000 0x1000000 + 2 0 0x1a000000 0x1000000 + 3 0 0x19000000 0x1000000 + 4 0 0x18000000 0x1000000 + 5 0 0x17000000 0x1000000 + 6 0 0x16000000 0x1000000>; + + clocks = <&cgu JZ4780_CLK_NEMC>; + + status = "disabled"; + };Quoted 7 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi line 253
Quoted 4 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +3
-1- clocks = <&cgu JZ4780_CLK_NEMC>; + efuse: efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100d0 0xff>;You are creating an overlapping region here with nemc above. Don't do that.
Quoted 1 line
Should "reg = <
0x134100000x10000>;" be used instead?
No, that still overlaps with nemc. What's in registers 0x00-0xcf and 0x1d0-0xffff? Either get rid of this node altogether and make the driver for nemc also instantiate the efuse driver (DT is not the only way to instantiate drivers), or create sub-nodes under nemc for each distinct h/w block in the 13410000-13420000 address space.
Or a third option is make nemc reg:
reg = <0x13410000 0xd0>, <0x134101d0 0xfe30>;
But I suspect that is wrong and you probably have some other function in there.
Rob
Re: [PATCH v2 1/2] nvmem: add driver for JZ4780 efuse
Hi Rob,
Quoted 172 lines · Rob Herring
Quoted 54 lines · PrasannaKumar Muralidharan
Hi Rob,
Quoted 51 lines · Rob Herring
Quoted 11 lines · Mathieu Malaterre
From: PrasannaKumar Muralidharan <[email protected]>
This patch brings support for the JZ4780 efuse. Currently it only expose a read only access to the entire 8K bits efuse memory.
Tested-by Mathieu Malaterre <[email protected]>Signed-off-by PrasannaKumar Muralidharan <[email protected]>Signed-off-by Mathieu Malaterre <[email protected]>--- .../ABI/testing/sysfs-driver-jz4780-efuse | 16 ++ .../bindings/nvmem/ingenic,jz4780-efuse.txt | 17 ++Please split bindings to separate patch.
Quoted 2 lines
MAINTAINERS | 5 + arch/mips/boot/dts/ingenic/jz4780.dtsi | 40 ++-dts files should also be separate.
Quoted 18 lines
drivers/nvmem/Kconfig | 10 + drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 305 +++++++++++++++++++++ 7 files changed, 383 insertions(+), 12 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt create mode 100644 drivers/nvmem/jz4780-efuse.cDocumentation/ABI/testing/sysfs-driver-jz4780-efuse new file +4
-0@@ -0,0 +1,16 @@ +What: /sys/devices/*/<our-device>/nvmem +Date: December 2017 +Contact: PrasannaKumar Muralidharan <[email protected]> +Description: read-only access to the efuse on the Ingenic JZ4780 SoCDocumentation/ABI/testing/sysfs-driver-jz4780-efuse line 14
Quoted 10 lines
Documentation/ABI/testing/sysfs-driver-jz4780-efuse new file +10
-0+ The SoC has a one time programmable 8K efuse that is + split into segments. The driver supports read only. + The segments are + 0x000 64 bit Random Number + 0x008 128 bit Ingenic Chip ID + 0x018 128 bit Customer ID + 0x028 3520 bit Reserved + 0x1E0 8 bit Protect Segment + 0x1E1 2296 bit HDMI Key + 0x300 2048 bit Security boot keyWhy do these need to be exposed to userspace?
Quoted 8 lines
Quoted 4 lines
sysfs is 1 value per file and this is lots of different things.
We already have ways to feed random data (entropy) to the system. And we have a way to expose SoC ID info to userspace (socdev).
Currently ingenic chip id is not used anywhere. The vendor BSP exposed only chip id and customer id. Should we do the same? Please provide your suggestion.
No. Don't create an ABI if you don't really need it.
Quoted 105 lines
Quoted 34 lines
Quoted 34 lines
Documentation/ABI/testing/sysfs-driver-jz4780-efuse new file +2
-0+Users: any user space application which wants to read the Chip + and Customer IDDocumentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt new file +17
-0@@ -0,0 +1,17 @@ +Ingenic JZ EFUSE driver bindings + +Required properties: +- "compatible" Must be set to "ingenic,jz4780-efuse" +- "reg" Register location and length +- "clocks" Handle for the ahb clock for the efuse. +- "clock-names" Must be "bus_clk" + +Example: + +efuse: efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100D0 0xFF>; + + clocks = <&cgu JZ4780_CLK_AHB2>; + clock-names = "bus_clk"; +};MAINTAINERS +0
-0@@ -6902,6 +6902,11 @@ M: Zubair Lutfullah Kakakhel <[email protected]> S: Maintained F: drivers/dma/dma-jz4780.cQuoted 6 lines
MAINTAINERS M: Zubair Lutfullah Kakakhel <[email protected]> · line 6908
Quoted 4 lines
MAINTAINERS +4
-0+INGENIC JZ4780 EFUSE Driver +M: PrasannaKumar Muralidharan <[email protected]> +S: Maintained +F: drivers/nvmem/jz4780-efuse.cBinding file?
Sorry, missed it. Will add it.
Quoted 12 lines
Quoted 12 lines
MAINTAINERS +1
-0+ INGENIC JZ4780 NAND DRIVER M: Harvey Hunt <[email protected]> L: [email protected]arch/mips/boot/dts/ingenic/jz4780.dtsi +0
-0@@ -224,21 +224,37 @@ reg = <0x10002000 0x100>; };Quoted 9 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi line 229
Quoted 7 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +3
-4- nemc: nemc@13410000 { - compatible = "ingenic,jz4780-nemc"; - reg = <0x13410000 0x10000>; - #address-cells = <2>; + + ahb2: ahb2 { + compatible = "simple-bus";This is an unrelated change and should be its own patch.
The efuse register address range is a subset of address range of nemc. So decided to make nemc and efuse as nodes with parent node ahb2. This is required for efuse driver to work. I am not able to understand what you mean by unrelated change. Can you please explain it?
Quoted 34 lines
Quoted 21 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +14
-6+ #address-cells = <1>; #size-cells = <1>; - ranges = <1 0 0x1b000000 0x1000000 - 2 0 0x1a000000 0x1000000 - 3 0 0x19000000 0x1000000 - 4 0 0x18000000 0x1000000 - 5 0 0x17000000 0x1000000 - 6 0 0x16000000 0x1000000>; + ranges = <>; + + nemc: nemc@13410000 { + compatible = "ingenic,jz4780-nemc"; + reg = <0x13410000 0x10000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0x1b000000 0x1000000 + 2 0 0x1a000000 0x1000000 + 3 0 0x19000000 0x1000000 + 4 0 0x18000000 0x1000000 + 5 0 0x17000000 0x1000000 + 6 0 0x16000000 0x1000000>;arch/mips/boot/dts/ingenic/jz4780.dtsi line 253
Quoted 10 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +8
-1+ + clocks = <&cgu JZ4780_CLK_NEMC>; + + status = "disabled"; + }; - clocks = <&cgu JZ4780_CLK_NEMC>; + efuse: efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100d0 0xff>;You are creating an overlapping region here with nemc above. Don't do that.
Quoted 7 lines
Quoted 1 line
Should "reg = <
0x134100000x10000>;" be used instead?No, that still overlaps with nemc. What's in registers 0x00-0xcf and 0x1d0-0xffff? Either get rid of this node altogether and make the driver for nemc also instantiate the efuse driver (DT is not the only way to instantiate drivers), or create sub-nodes under nemc for each distinct h/w block in the 13410000-13420000 address space.
My idea was not to change nemc driver.
By "create sub-nodes under nemc" do you mean something like below?
nemc: nemc@13410000 {
compatible = "ingenic,jz4780-nemc";
reg = <0x13410000 0x10000>;
<...>
status = "disabled";
efuse: efuse@134101d0 {
compatible = "ingenic,jz4780-efuse";
reg = <0x134100d0 0xff>;
}
}Will this instantiate efuse driver? I do not know how to do that with sub-node. I will explore more on this.
Quoted 7 lines
Or a third option is make nemc reg:
reg = <
0x134100000xd0>, <0x134101d00xfe30>;But I suspect that is wrong and you probably have some other function in there.
Rob
If the efuse block were to use a different base register address (that does not overlap with nemc register range) in future SoC how the node should be? Using nemc to instantiate efuse won't be the best choice if that happens.
Thanks,
PrasannaKumar
Rob Herring
maintainerRe: [PATCH v2 1/2] nvmem: add driver for JZ4780 efuse
Quoted 10 lines · PrasannaKumar Muralidharan
Hi Rob,
Quoted 7 lines · Rob Herring
Quoted 5 lines · PrasannaKumar Muralidharan
Hi Rob,
Quoted 2 lines · Rob Herring
Quoted 1 line · Mathieu Malaterre
From: PrasannaKumar Muralidharan <[email protected]>
[...]
Quoted 33 lines
Quoted 25 lines
Quoted 25 lines
Quoted 24 lines
Quoted 11 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +11
-0+ nemc: nemc@13410000 { + compatible = "ingenic,jz4780-nemc"; + reg = <0x13410000 0x10000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0x1b000000 0x1000000 + 2 0 0x1a000000 0x1000000 + 3 0 0x19000000 0x1000000 + 4 0 0x18000000 0x1000000 + 5 0 0x17000000 0x1000000 + 6 0 0x16000000 0x1000000>;arch/mips/boot/dts/ingenic/jz4780.dtsi line 253
Quoted 10 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +8
-1+ + clocks = <&cgu JZ4780_CLK_NEMC>; + + status = "disabled"; + }; - clocks = <&cgu JZ4780_CLK_NEMC>; + efuse: efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100d0 0xff>;You are creating an overlapping region here with nemc above. Don't do that.
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Should "reg = <
0x134100000x10000>;" be used instead?No, that still overlaps with nemc. What's in registers 0x00-0xcf and 0x1d0-0xffff? Either get rid of this node altogether and make the driver for nemc also instantiate the efuse driver (DT is not the only way to instantiate drivers), or create sub-nodes under nemc for each distinct h/w block in the 13410000-13420000 address space.
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My idea was not to change nemc driver.
By "create sub-nodes under nemc" do you mean something like below?
Yes.
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nemc: nemc@13410000 {
compatible = "ingenic,jz4780-nemc";
reg = <0x13410000 0x10000>;
<...>
status = "disabled";Though having disabled here is strange. We'd normally ignore all the child nodes.
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efuse: efuse@134101d0 { compatible = "ingenic,jz4780-efuse"; reg = <0x134100d0 0xff>; } }Will this instantiate efuse driver? I do not know how to do that with sub-node. I will explore more on this.
The nemc driver just needs to call of_platform_default_populate.
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Or a third option is make nemc reg:
reg = <
0x134100000xd0>, <0x134101d00xfe30>;
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But I suspect that is wrong and you probably have some other function in there.
Rob
If the efuse block were to use a different base register address (that does not overlap with nemc register range) in future SoC how the node should be? Using nemc to instantiate efuse won't be the best choice if that happens.
Then you will have a different compatible for nemc (because it is different) and then the driver should skip the above step.
Rob
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Re: [PATCH v2 1/2] nvmem: add driver for JZ4780 efuse
In reply to Rob HerringQuoted 58 lines · Rob Herring
Quoted 56 lines · PrasannaKumar Muralidharan
Hi Rob,
Quoted 53 lines · Rob Herring
Quoted 11 lines · Mathieu Malaterre
From: PrasannaKumar Muralidharan <[email protected]>
This patch brings support for the JZ4780 efuse. Currently it only expose a read only access to the entire 8K bits efuse memory.
Tested-by Mathieu Malaterre <[email protected]>Signed-off-by PrasannaKumar Muralidharan <[email protected]>Signed-off-by Mathieu Malaterre <[email protected]>--- .../ABI/testing/sysfs-driver-jz4780-efuse | 16 ++ .../bindings/nvmem/ingenic,jz4780-efuse.txt | 17 ++Please split bindings to separate patch.
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MAINTAINERS | 5 + arch/mips/boot/dts/ingenic/jz4780.dtsi | 40 ++-dts files should also be separate.
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drivers/nvmem/Kconfig | 10 + drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 305 +++++++++++++++++++++ 7 files changed, 383 insertions(+), 12 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt create mode 100644 drivers/nvmem/jz4780-efuse.cDocumentation/ABI/testing/sysfs-driver-jz4780-efuse new file +4
-0@@ -0,0 +1,16 @@ +What: /sys/devices/*/<our-device>/nvmem +Date: December 2017 +Contact: PrasannaKumar Muralidharan <[email protected]> +Description: read-only access to the efuse on the Ingenic JZ4780 SoCDocumentation/ABI/testing/sysfs-driver-jz4780-efuse line 14
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Documentation/ABI/testing/sysfs-driver-jz4780-efuse new file +10
-0+ The SoC has a one time programmable 8K efuse that is + split into segments. The driver supports read only. + The segments are + 0x000 64 bit Random Number + 0x008 128 bit Ingenic Chip ID + 0x018 128 bit Customer ID + 0x028 3520 bit Reserved + 0x1E0 8 bit Protect Segment + 0x1E1 2296 bit HDMI Key + 0x300 2048 bit Security boot keyWhy do these need to be exposed to userspace?
sysfs is 1 value per file and this is lots of different things.
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We already have ways to feed random data (entropy) to the system. And we have a way to expose SoC ID info to userspace (socdev).
Currently ingenic chip id is not used anywhere. The vendor BSP exposed only chip id and customer id. Should we do the same? Please provide your suggestion.
No. Don't create an ABI if you don't really need it.
Rob,
MAC address of the ethernet device is stored in customer id segment of efuse. So only customer id is needed. Do you think exposing customer id would suffice?
Srini,
Only user would be dm900 ethernet driver (need to make changes to it once the efuse driver goes in). There is no need to expose it to user space. I am planning to modify nvmem core to not expose efuse if the efuse driver chooses so. Do you think it makes sense? The need to maintain ABI for user space disappears if such a change is introduced.
Thanks,
PrasannaKumar
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PATCH v2 2/2 dts: Probe efuse for CI20
In reply to Mathieu MalaterreMIPS Creator CI20 comes with JZ4780 SoC. Provides access to the efuse block using jz4780 efuse driver.
--- arch/mips/configs/ci20_defconfig | 2 ++ 1 file changed, 2 insertions(+)
arch/mips/configs/ci20_defconfig +2 -0
@@ -171,3 +171,5 @@ CONFIG_STACKTRACE=y # CONFIG_FTRACE is not set CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="earlycon console=ttyS4,115200 clk_ignore_unused" +CONFIG_NVMEM=y +CONFIG_JZ4780_EFUSE=y
Signature · 6 lines
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Rob Herring
maintainerRe: [PATCH v2 2/2] dts: Probe efuse for CI20
Quoted 6 lines · Mathieu Malaterre
MIPS Creator CI20 comes with JZ4780 SoC. Provides access to the efuse block using jz4780 efuse driver.
Signed-off-by Mathieu Malaterre <[email protected]>--- arch/mips/configs/ci20_defconfig | 2 ++
Your subject indicates this is a dts patch which it is not.
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1 file changed, 2 insertions(+)arch/mips/configs/ci20_defconfig +2
-0@@ -171,3 +171,5 @@ CONFIG_STACKTRACE=y # CONFIG_FTRACE is not set CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="earlycon console=ttyS4,115200 clk_ignore_unused" +CONFIG_NVMEM=y +CONFIG_JZ4780_EFUSE=ySignature · 1 line
2.11.0
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Re: [PATCH v2 2/2] dts: Probe efuse for CI20
In reply to Mathieu MalaterreQuoted 13 lines · Mathieu Malaterre
MIPS Creator CI20 comes with JZ4780 SoC. Provides access to the efuse block using jz4780 efuse driver.
Signed-off-by Mathieu Malaterre <[email protected]>--- arch/mips/configs/ci20_defconfig | 2 ++ 1 file changed, 2 insertions(+)arch/mips/configs/ci20_defconfig +0
-0
arch/mips/configs/ci20_defconfig CONFIG_STACKTRACE=y · line 175
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arch/mips/configs/ci20_defconfig +2
-0@@ -171,3 +171,5 @@ CONFIG_STACKTRACE=y # CONFIG_FTRACE is not set CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="earlycon console=ttyS4,115200 clk_ignore_unused" +CONFIG_NVMEM=y +CONFIG_JZ4780_EFUSE=y
NVMEM is already implied by RTC_CLASS (which turns on RTC_NVMEM by default).
I would suggest loading the defconfig:
make ARCH=mips ci20_defconfig
Then enabling the extra configuration options you need, then create a new minimal defconfig:
make ARCH=mips savedefconfig
Then look at the new file called "defconfig" or copy it over arch/mips/configs/ci20_defconfig, and see what changes it adds. That way you'll get the minimum you need and in the right order in the defconfig.
Don't feel like you have to submit other random changes due to config changes since the defconfig was added, but if you do please do it as a separate patch to bring the defconfig up to date (i.e. just load defconfig and save it) before the patch which actually enables the EFUSE.
Cheers
James
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Signature · 1 line
2.11.0
Quoted 5 lines · Mathieu Malaterre
This patchset bring support for read-only access to the JZ4780 efuse as found on MIPS Creator CI20.
To keep the driver as simple as possible, it was not possible to re-use most of the nvmem core functionalities. This driver is not compatible with the original
Can you explain a bit more on not able to re-use nvmem core?
If you are referring to adding nvmem cell entires in sysfs, This should probably go in to nvmem core, rather that in individual providers. This is one of the feature my todo list, will try to come up with some thing soon.
thanks,
srini
Quoted 33 lines
efuse driver as found in the custom linux kernel from upstream (1), in particular it does not expose to the users neither:
/sys/devices/platform/*/chip_idnor/sys/devices/platform/*/user_id.The goal of this driver is to provide access to the MAC address to the dm9000 driver.
(1) https://github.com/ZubairLK/CI20_linux/commit/6efd4ffca7dcfaff0794ab60cd6922ce96c60419
Changes in v2:
Properly handle offset and byte value from the main entry point. Also add a commit message in patch #2.Mathieu Malaterre (1):
dts: Probe efuse for CI20PrasannaKumar Muralidharan (1):
nvmem: add driver for JZ4780 efuse.../ABI/testing/sysfs-driver-jz4780-efuse | 16 ++ .../bindings/nvmem/ingenic,jz4780-efuse.txt | 17 ++ MAINTAINERS | 5 + arch/mips/boot/dts/ingenic/jz4780.dtsi | 40 ++- arch/mips/configs/ci20_defconfig | 2 + drivers/nvmem/Kconfig | 10 + drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 305 +++++++++++++++++++++ 8 files changed, 385 insertions(+), 12 deletions(-)create mode 100644
Documentation/ABI/testing/sysfs-driver-jz4780-efusecreate mode 100644Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txtcreate mode 100644drivers/nvmem/jz4780-efuse.c
Hi Srinivas,
Quoted 13 lines · Srinivas Kandagatla
Quoted 9 lines · Mathieu Malaterre
This patchset bring support for read-only access to the JZ4780 efuse as found
on MIPS Creator CI20.To keep the driver as simple as possible, it was not possible to re-use most of
the nvmem core functionalities. This driver is not compatible with the original
Quoted 6 lines
Can you explain a bit more on not able to re-use nvmem core?
If you are referring to adding nvmem cell entires in sysfs, This should probably go in to nvmem core, rather that in individual providers. This is one of the feature my todo list, will try to come up with some thing soon.
We could not find a way to expose different sized segments using nvmem framework. Do you have any pointers for this?
We were not aware of the fact that nvmem does not expose individual cell entries in sysfs.
Regards,
PrasannaKumar
Quoted 19 lines · PrasannaKumar Muralidharan
Hi Srinivas,
Quoted 15 lines · Srinivas Kandagatla
Quoted 9 lines · Mathieu Malaterre
This patchset bring support for read-only access to the JZ4780 efuse as found
on MIPS Creator CI20.To keep the driver as simple as possible, it was not possible to re-use most of
the nvmem core functionalities. This driver is not compatible with the originalCan you explain a bit more on not able to re-use nvmem core?
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If you are referring to adding nvmem cell entires in sysfs, This should probably go in to nvmem core, rather that in individual providers. This is one of the feature my todo list, will try to come up with some thing soon.
We could not find a way to expose different sized segments using nvmem framework. Do you have any pointers for this?
This does not exist at the moment, but it should be very much doable to add this functionality to nvmem core.
I will keep you loop if I manage to post this patch soon.
--srini
Quoted 6 lines
We were not aware of the fact that nvmem does not expose individual cell entries in sysfs.
Regards,
PrasannaKumar