Armada 7K/8K CP110 DT de-duplication

Hello,

This series aims at de-duplicating the Armada CP110 Device Tree description, which is currently duplicated between armada-cp110-master.dtsi and armada-cp110-slave.dtsi, even though they are almost identical. Indeed, one concept of Marvell SoCs is that they are made of HW blocks composed of a variety of IPs (network, PCIe, SATA, XOR, SPI, I2C, etc.), and those HW blocks can be duplicated several times within a given SoC. The Armada 7K SoC has a single CP110 (so no duplication), while the Armada 8K SoC has two CP110. In the future, SoCs with more than 2 CP110s will be introduced.

This duplication issue has been discussed at the DT workshop [1] in Prague last October, and I presented on this topic [2]. The solution of using the C pre-processor to avoid this duplication has been validated by the people present in this DT workshop, and this patch series simply submits what has been presented.

- The first four patches are fixes for existing issues/inconsistencies in the Device Tree files. Since they don't fix any visible problems, they are not marked for -stable.

- The fifth patch is a minor improvement.

- The sixth patch making use of aliases for SPI busses simply aims at reducing the number of changes between the CP110 master and CP110 slave description, by avoiding the need for the cell-index property in the SPI controller DT nodes.

- The seventh patch implements the de-duplication itself, by introducing an armada-cp110.dtsi file included twice on Armada 8K platforms, once for the master CP110 and once for the slave CP110.

- The last patch renames cpm to cp0 and cps to cp1, as the concept of master/slave CPs does not apply to future SoCs that have more than 2 CPs.

Changes since v1:

- Rebase on top of mvebu/dt64, since the NAND controller changes will only be submitted for 4.17.

- Add patches fixing NAND related typos/inconsistencies:
arm64: dts: marvell: fix typos in comment describing the NAND controller
arm64: dts: marvell: fix compatible string list for Armada CP110 slave NAND

- Improve the de-duplication patch by removing armada-cp110-master.dtsi and armada-cp110-slave.dtsi, since the concept of master/slave will no longer exist when we will have more than 2 CPs.

- Add a patch renaming cpm -> cp0, cps -> cp1.

Best regards,

Thomas

[1] https://elinux.org/Device_tree_kernel_summit_2017_etherpad
[2] https://elinux.org/images/1/14/DTWorkshop2017-duplicate-data.pdf

Thomas Petazzoni (8):
arm64: dts: marvell: fix watchdog unit address in Armada AP806
arm64: dts: marvell: use lower case for unit address and reg property
arm64: dts: marvell: fix typos in comment describing the NAND
controller
arm64: dts: marvell: fix compatible string list for Armada CP110 slave
NAND
arm64: dts: marvell: use mvebu-icu.h where possible
arm64: dts: marvell: use aliases for SPI busses on Armada 7K/8K
arm64: dts: marvell: de-duplicate CP110 description
arm64: dts: marvell: replace cpm by cp0, cps by cp1

 arch/arm64/boot/dts/marvell/armada-7040-db.dts     |  46 +--
 arch/arm64/boot/dts/marvell/armada-70x0.dtsi       |  37 +-
 arch/arm64/boot/dts/marvell/armada-8020.dtsi       |   2 +-
 arch/arm64/boot/dts/marvell/armada-8040-db.dts     |  80 ++--
 arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts  |  76 ++--
 arch/arm64/boot/dts/marvell/armada-8040.dtsi       |   2 +-
 arch/arm64/boot/dts/marvell/armada-80x0.dtsi       |  80 +++-
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi      |   8 +-
 arch/arm64/boot/dts/marvell/armada-common.dtsi     |  10 +
 .../boot/dts/marvell/armada-cp110-master.dtsi      | 449 ---------------------
 .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 448 --------------------
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi      | 422 +++++++++++++++++++
 12 files changed, 635 insertions(+), 1025 deletions(-)
 create mode 100644 arch/arm64/boot/dts/marvell/armada-common.dtsi
 delete mode 100644 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
 delete mode 100644 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-cp110.dtsi

2.14.3

This fixes the following DTC warning:

Warning (simple_bus_reg): Node /ap806/config-space at f0000000/watchdog at 600000 simple-bus unit address format error, expected "610000"

---
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index bbc5a4d3acac..36f6d7fbb310 100644
@@ -241,7 +241,7 @@
 
 			};
 
-			watchdog: watchdog at 600000 {
+			watchdog: watchdog at 610000 {
 				compatible = "arm,sbsa-gwdt";
 				reg = <0x610000 0x1000>, <0x600000 0x1000>;
 				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;

2.14.3

This fixes the following DTC warning:

<stdout>: Warning (simple_bus_reg): Node /ap806/config-space at f0000000/thermal at 6f808C simple-bus unit address format error, expected "6f808c"

---
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

index 36f6d7fbb310..0575207cafee 100644
@@ -286,9 +286,9 @@
 				};
 			};
 
-			ap_thermal: thermal at 6f808C {
+			ap_thermal: thermal at 6f808c {
 				compatible = "marvell,armada-ap806-thermal";
-				reg = <0x6f808C 0x4>,
+				reg = <0x6f808c 0x4>,
 				      <0x6f8084 0x8>;
 			};
 		};

2.14.3

---
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 2 +-
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

index ecbc76d26dff..a0b2cec2823f 100644
@@ -317,7 +317,7 @@
 
 			cpm_nand: nand at 720000 {
 				/*
-				 * Due to the limiation of the pin available
+				 * Due to the limitation of the pins available
 				 * this controller is only usable on the CPM
 				 * for A7K and on the CPS for A8K.
 				 */

index 6a07c786b788..0624ec2de496 100644
@@ -318,7 +318,7 @@
 
 			cps_nand: nand at 720000 {
 				/*
-				 * Due to the limiation of the pin available
+				 * Due to the limitation of the pins available
 				 * this controller is only usable on the CPM
 				 * for A7K and on the CPS for A8K.
 				 */

2.14.3

The Armada CP110 slave NAND controller Device Tree description lists the compatible string in the wrong order: marvell,armada-8k-nand should come first. This commit alignes the slave CP110 description with the master CP110 description from that respect.

---
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

index 0624ec2de496..3eda62d482fc 100644
@@ -322,8 +322,8 @@
 				 * this controller is only usable on the CPM
 				 * for A7K and on the CPS for A8K.
 				 */
-				compatible = "marvell,armada370-nand",
-					     "marvell,armada-8k-nand";
+				compatible = "marvell,armada-8k-nand",
+					     "marvell,armada370-nand";
 				reg = <0x720000 0x54>;
 				#address-cells = <1>;
 				#size-cells = <1>;

2.14.3

Back when the ICU Device Tree binding was introduced, we could not use mvebu-icu.h from the Device Tree files, because the DT files and mvebu-icu.h were following different merge routes towards Linus tree. Now that both have been merged, we can switch the Marvell Armada CP110 Device Tree files to use the mvebu-icu.h header instead of duplicating the ICU_GRP_NSR definition.

---
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 2 +-
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

index a0b2cec2823f..f89053577bcc 100644
@@ -44,7 +44,7 @@
  * Device Tree file for Marvell Armada CP110 Master.
  */
 
-#define ICU_GRP_NSR 0x0
+#include <dt-bindings/interrupt-controller/mvebu-icu.h>
 
 / {
 	cp110-master {

index 3eda62d482fc..a658b72b0229 100644
@@ -44,7 +44,7 @@
  * Device Tree file for Marvell Armada CP110 Slave.
  */
 
-#define ICU_GRP_NSR 0x0
+#include <dt-bindings/interrupt-controller/mvebu-icu.h>
 
 / {
 	cp110-slave {

2.14.3

We are currently using the cell-index DT property to assign SPI bus numbers. This property is specific to the spi-orion driver, and requires each SPI controller to have a unique ID defined in the Device Tree.

As we are about to merge armada-cp110-master.dtsi and armada-cp110-slave.dtsi into a single file, those cell-index properties that differ between the master CP110 and the slave CP110 are a difference that would have to be handled.

In order to avoid this, we switch to using the "aliases" DT node to assign a unique number to each SPI controller. This is more generic, and directly handled by the SPI core.

---
 arch/arm64/boot/dts/marvell/armada-70x0.dtsi         | 2 ++
 arch/arm64/boot/dts/marvell/armada-80x0.dtsi         | 4 ++++
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi        | 2 +-
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 2 --
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  | 2 --
 5 files changed, 7 insertions(+), 5 deletions(-)

index 0e1a1e5be399..815e64b3a874 100644
@@ -50,6 +50,8 @@
 	aliases {
 		gpio1 = &cpm_gpio1;
 		gpio2 = &cpm_gpio2;
+		spi1 = &cpm_spi0;
+		spi2 = &cpm_spi1;
 	};
 };
 

index b280ddd3c397..de9c34333cd4 100644
@@ -51,6 +51,10 @@
 	aliases {
 		gpio1 = &cps_gpio1;
 		gpio2 = &cpm_gpio2;
+		spi1 = &cpm_spi0;
+		spi2 = &cpm_spi1;
+		spi3 = &cps_spi0;
+		spi4 = &cps_spi1;
 	};
 };
 

index 0575207cafee..f9b66b81f9fc 100644
@@ -58,6 +58,7 @@
 		serial0 = &uart0;
 		serial1 = &uart1;
 		gpio0 = &ap_gpio;
+		spi0 = &spi0;
 	};
 
 	psci {

@@ -203,7 +204,6 @@
 				reg = <0x510600 0x50>;
 				#address-cells = <1>;
 				#size-cells = <0>;
-				cell-index = <0>;
 				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&ap_clk 3>;
 				status = "disabled";

index f89053577bcc..162e6c228bd9 100644
@@ -280,7 +280,6 @@
 				reg = <0x700600 0x50>;
 				#address-cells = <0x1>;
 				#size-cells = <0x0>;
-				cell-index = <1>;
 				clocks = <&cpm_clk 1 21>;
 				status = "disabled";
 			};

@@ -290,7 +289,6 @@
 				reg = <0x700680 0x50>;
 				#address-cells = <1>;
 				#size-cells = <0>;
-				cell-index = <2>;
 				clocks = <&cpm_clk 1 21>;
 				status = "disabled";
 			};

index a658b72b0229..207b6f444e24 100644
@@ -281,7 +281,6 @@
 				reg = <0x700600 0x50>;
 				#address-cells = <0x1>;
 				#size-cells = <0x0>;
-				cell-index = <3>;
 				clocks = <&cps_clk 1 21>;
 				status = "disabled";
 			};

@@ -291,7 +290,6 @@
 				reg = <0x700680 0x50>;
 				#address-cells = <1>;
 				#size-cells = <0>;
-				cell-index = <4>;
 				clocks = <&cps_clk 1 21>;
 				status = "disabled";
 			};

2.14.3

One concept of Marvell Armada 7K/8K SoCs is that they are made of HW blocks composed of a variety of IPs (network, PCIe, SATA, XOR, SPI, I2C, etc.), and those HW blocks can be duplicated several times within a given SoC. The Armada 7K SoC has a single CP110 (so no duplication), while the Armada 8K SoC has two CP110. In the future, SoCs with more than 2 CP110s will be introduced.

In current kernel versions, the master CP110 is described in armada-cp110-master.dtsi and the slave CP110 is described in armada-cp110-slave.dtsi. Those files are basically exactly the same, since they describe the same hardware. They only have a few differences:

- Base address of the registers is different for the "config-space"

- Base address of the PCIe registers, MEM, CONF and IO areas were different

- Labels (and phandles pointing to them) of the nodes were different ("cpm" prefix in the master CP, "cps" prefix in the slave CP)

This duplication issue has been discussed at the DT workshop [1] in Prague last October, and we presented on this topic [2]. The solution of using the C pre-processor to avoid this duplication has been validated by the people present in this DT workshop, and this patch simply implements what has been presented.

We handle differences between the master CP and slave CP description using the C pre-processor, by defining a set of macros with different values armada-cp110.dtsi is included to instantiate one of the master or slave CP110.

There are a few aspects that deserve additional explanations:

- PCIe needs to be handled separately because it is not part of the config-space {...} node, since it has registers outside of the range covered by config-space {...}.

- We need to defined CP110_BASE, CP110_PCIEx_BASE without 0x, because they are used for the unit address part of some DT nodes. But since they are also used for the "reg" property of the same nodes, we have an ADDRESSIFY() macro that prepends 0x to those values.

We compared the resulting .dtb for armada-8040-db.dtb before and after this patch is applied, and the result is exactly the same, except for a few differences:

- the SDHCI controller that was only described in the master CP110 is now also described in the slave CP110. Even though the SDHCI controller from the slave CP110 is indeed not usable (as it isn't wired to the outside world) it is technically part of the silicon, and therefore it is reasonable to also describe it to be part of the slave CP110. In addition, if we wanted to get this correct for the SDHCI controller, we should also do it for the NAND controller, for which the situation is even more complicated: in a single CP110 configuration (Armada 7K), the usable NAND controller is in the master CP110, while in a dual CP110 configuration (Armada 8K), the usable NAND controller is in the slave CP110. Since that would add a lot of additional complexity for no good reason, and since the IP blocks are in fact really present in both CPs, we simply describe them in both CPs at the DT level.

- the cp110-master and cp110-slave nodes are now named cpm and cps. We could have kept cp110-master and cp110-slave, but that would have required adding another CP110_xyz define, which didn't seem very useful.

Note that this commit also gets rid of the armada-cp110-master.dtsi and armada-cp110-slave.dtsi files, as future SoCs will have more than 2 CPs. Instead, we instantiate the CPs directly from the SoC-specific .dtsi files, i.e armada-70x0.dtsi and armada-80x0.dtsi.

[1] https://elinux.org/Device_tree_kernel_summit_2017_etherpad
[2] https://elinux.org/images/1/14/DTWorkshop2017-duplicate-data.pdf

---
 arch/arm64/boot/dts/marvell/armada-70x0.dtsi       |  23 +-
 arch/arm64/boot/dts/marvell/armada-80x0.dtsi       |  56 ++-
 arch/arm64/boot/dts/marvell/armada-common.dtsi     |  10 +
 .../boot/dts/marvell/armada-cp110-master.dtsi      | 447 ---------------------
 .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 446 --------------------
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi      | 422 +++++++++++++++++++
 6 files changed, 506 insertions(+), 898 deletions(-)
 create mode 100644 arch/arm64/boot/dts/marvell/armada-common.dtsi
 delete mode 100644 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
 delete mode 100644 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-cp110.dtsi

index 815e64b3a874..9917cff3dae6 100644
@@ -44,8 +44,6 @@
  * Device Tree file for the Armada 70x0 SoC
  */
 
-#include "armada-cp110-master.dtsi"
-
 / {
 	aliases {
 		gpio1 = &cpm_gpio1;

@@ -55,6 +53,27 @@
 	};
 };
 
+/*
+ * Instantiate the CP110
+ */
+#define CP110_NAME		cpm
+#define CP110_BASE		f2000000
+#define CP110_PCIE_IO_BASE	0xf9000000
+#define CP110_PCIE_MEM_BASE	0xf6000000
+#define CP110_PCIE0_BASE	f2600000
+#define CP110_PCIE1_BASE	f2620000
+#define CP110_PCIE2_BASE	f2640000
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NAME
+#undef CP110_BASE
+#undef CP110_PCIE_IO_BASE
+#undef CP110_PCIE_MEM_BASE
+#undef CP110_PCIE0_BASE
+#undef CP110_PCIE1_BASE
+#undef CP110_PCIE2_BASE
+
 &cpm_gpio1 {
 	status = "okay";
 };

new file mode 100644
index 000000000000..c6dd1d81c68d
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ */
+
+/* Common definitions used by Armada 7K/8K DTs */
+#define PASTER(x, y) x ## y
+#define EVALUATOR(x, y) PASTER(x, y)
+#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))
+#define ADDRESSIFY(addr) EVALUATOR(0x, addr)

2.14.3

In preparation for the introduction of more than 2 CPs in upcoming SoCs, it makes sense to move away from the "CP master" (cpm) and "CP slave" (cps) naming, and use instead cp0/cp1.

This commit is the result of:

sed 's%cpm%cp0g%' arch/arm64/boot/dts/marvell/*
sed 's%cps%cp1g%' arch/arm64/boot/dts/marvell/*

So it is a purely mechaninal change.

---
 arch/arm64/boot/dts/marvell/armada-7040-db.dts    | 46 ++++++-------
 arch/arm64/boot/dts/marvell/armada-70x0.dtsi      | 18 ++---
 arch/arm64/boot/dts/marvell/armada-8020.dtsi      |  2 +-
 arch/arm64/boot/dts/marvell/armada-8040-db.dts    | 80 +++++++++++------------
 arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 76 ++++++++++-----------
 arch/arm64/boot/dts/marvell/armada-8040.dtsi      |  2 +-
 arch/arm64/boot/dts/marvell/armada-80x0.dtsi      | 34 +++++-----
 7 files changed, 129 insertions(+), 129 deletions(-)

index 52b5341cb270..44c95b97a422 100644
@@ -61,7 +61,7 @@
 		reg = <0x0 0x0 0x0 0x80000000>;
 	};
 
-	cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
+	cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
 		compatible = "regulator-fixed";
 		regulator-name = "usb3h0-vbus";
 		regulator-min-microvolt = <5000000>;

@@ -70,7 +70,7 @@
 		gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
 	};
 
-	cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
+	cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
 		compatible = "regulator-fixed";
 		regulator-name = "usb3h1-vbus";
 		regulator-min-microvolt = <5000000>;

@@ -79,14 +79,14 @@
 		gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
 	};
 
-	cpm_usb3_0_phy: cpm-usb3-0-phy {
+	cp0_usb3_0_phy: cp0-usb3-0-phy {
 		compatible = "usb-nop-xceiv";
-		vcc-supply = <&cpm_reg_usb3_0_vbus>;
+		vcc-supply = <&cp0_reg_usb3_0_vbus>;
 	};
 
-	cpm_usb3_1_phy: cpm-usb3-1-phy {
+	cp0_usb3_1_phy: cp0-usb3-1-phy {
 		compatible = "usb-nop-xceiv";
-		vcc-supply = <&cpm_reg_usb3_1_vbus>;
+		vcc-supply = <&cp0_reg_usb3_1_vbus>;
 	};
 };
 

@@ -129,11 +129,11 @@
 };
 
 
-&cpm_pcie2 {
+&cp0_pcie2 {
 	status = "okay";
 };
 
-&cpm_i2c0 {
+&cp0_i2c0 {
 	status = "okay";
 	clock-frequency = <100000>;
 

@@ -156,7 +156,7 @@
 	};
 };
 
-&cpm_nand {
+&cp0_nand {
 	/*
 	 * SPI on CPM and NAND have common pins on this board. We can
 	 * use only one at a time. To enable the NAND (whihch will

@@ -186,7 +186,7 @@
 };
 
 
-&cpm_spi1 {
+&cp0_spi1 {
 	status = "okay";
 
 	spi-flash at 0 {

@@ -214,17 +214,17 @@
 	};
 };
 
-&cpm_sata0 {
+&cp0_sata0 {
 	status = "okay";
 };
 
-&cpm_usb3_0 {
-	usb-phy = <&cpm_usb3_0_phy>;
+&cp0_usb3_0 {
+	usb-phy = <&cp0_usb3_0_phy>;
 	status = "okay";
 };
 
-&cpm_usb3_1 {
-	usb-phy = <&cpm_usb3_1_phy>;
+&cp0_usb3_1 {
+	usb-phy = <&cp0_usb3_1_phy>;
 	status = "okay";
 };
 

@@ -235,14 +235,14 @@
 	non-removable;
 };
 
-&cpm_sdhci0 {
+&cp0_sdhci0 {
 	status = "okay";
 	bus-width = <4>;
 	no-1-8-v;
 	cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
 };
 
-&cpm_mdio {
+&cp0_mdio {
 	status = "okay";
 
 	phy0: ethernet-phy at 0 {

@@ -253,28 +253,28 @@
 	};
 };
 
-&cpm_ethernet {
+&cp0_ethernet {
 	status = "okay";
 };
 
-&cpm_eth0 {
+&cp0_eth0 {
 	status = "okay";
 	/* Network PHY */
 	phy-mode = "10gbase-kr";
 	/* Generic PHY, providing serdes lanes */
-	phys = <&cpm_comphy2 0>;
+	phys = <&cp0_comphy2 0>;
 };
 
-&cpm_eth1 {
+&cp0_eth1 {
 	status = "okay";
 	/* Network PHY */
 	phy = <&phy0>;
 	phy-mode = "sgmii";
 	/* Generic PHY, providing serdes lanes */
-	phys = <&cpm_comphy0 1>;
+	phys = <&cp0_comphy0 1>;
 };
 
-&cpm_eth2 {
+&cp0_eth2 {
 	status = "okay";
 	phy = <&phy1>;
 	phy-mode = "rgmii-id";

index 9917cff3dae6..f63b4fbd642b 100644
@@ -46,17 +46,17 @@
 
 / {
 	aliases {
-		gpio1 = &cpm_gpio1;
-		gpio2 = &cpm_gpio2;
-		spi1 = &cpm_spi0;
-		spi2 = &cpm_spi1;
+		gpio1 = &cp0_gpio1;
+		gpio2 = &cp0_gpio2;
+		spi1 = &cp0_spi0;
+		spi2 = &cp0_spi1;
 	};
 };
 
 /*
  * Instantiate the CP110
  */
-#define CP110_NAME		cpm
+#define CP110_NAME		cp0
 #define CP110_BASE		f2000000
 #define CP110_PCIE_IO_BASE	0xf9000000
 #define CP110_PCIE_MEM_BASE	0xf6000000

@@ -74,16 +74,16 @@
 #undef CP110_PCIE1_BASE
 #undef CP110_PCIE2_BASE
 
-&cpm_gpio1 {
+&cp0_gpio1 {
 	status = "okay";
 };
 
-&cpm_gpio2 {
+&cp0_gpio2 {
 	status = "okay";
 };
 
-&cpm_syscon0 {
-	cpm_pinctrl: pinctrl {
+&cp0_syscon0 {
+	cp0_pinctrl: pinctrl {
 		compatible = "marvell,armada-7k-pinctrl";
 
 		nand_pins: nand-pins {

index 0ba0bc942598..3318d6b0214b 100644
@@ -60,6 +60,6 @@
  * oscillator so this one is let enabled.
  */
 
-&cpm_rtc {
+&cp0_rtc {
 	status = "disabled";
 };

index 60fe84f5cbcc..83d2b40e5981 100644
@@ -59,6 +59,6 @@
  * disable it. However, the RTC clock in CP slave is connected to the
  * oscillator so this one is let enabled.
  */
-&cpm_rtc {
+&cp0_rtc {
 	status = "disabled";
 };

index 5e038e7b7b30..0d36b0fa7153 100644
@@ -46,19 +46,19 @@
 
 / {
 	aliases {
-		gpio1 = &cps_gpio1;
-		gpio2 = &cpm_gpio2;
-		spi1 = &cpm_spi0;
-		spi2 = &cpm_spi1;
-		spi3 = &cps_spi0;
-		spi4 = &cps_spi1;
+		gpio1 = &cp1_gpio1;
+		gpio2 = &cp0_gpio2;
+		spi1 = &cp0_spi0;
+		spi2 = &cp0_spi1;
+		spi3 = &cp1_spi0;
+		spi4 = &cp1_spi1;
 	};
 };
 
 /*
  * Instantiate the master CP110
  */
-#define CP110_NAME		cpm
+#define CP110_NAME		cp0
 #define CP110_BASE		f2000000
 #define CP110_PCIE_IO_BASE	0xf9000000
 #define CP110_PCIE_MEM_BASE	0xf6000000

@@ -79,7 +79,7 @@
 /*
  * Instantiate the slave CP110
  */
-#define CP110_NAME		cps
+#define CP110_NAME		cp1
 #define CP110_BASE		f4000000
 #define CP110_PCIE_IO_BASE	0xfd000000
 #define CP110_PCIE_MEM_BASE	0xfa000000

@@ -98,23 +98,23 @@
 #undef CP110_PCIE2_BASE
 
 /* The 80x0 has two CP blocks, but uses only one block from each. */
-&cps_gpio1 {
+&cp1_gpio1 {
 	status = "okay";
 };
 
-&cpm_gpio2 {
+&cp0_gpio2 {
 	status = "okay";
 };
 
-&cpm_syscon0 {
-	cpm_pinctrl: pinctrl {
-		compatible = "marvell,armada-8k-cpm-pinctrl";
+&cp0_syscon0 {
+	cp0_pinctrl: pinctrl {
+		compatible = "marvell,armada-8k-cp0-pinctrl";
 	};
 };
 
-&cps_syscon0 {
-	cps_pinctrl: pinctrl {
-		compatible = "marvell,armada-8k-cps-pinctrl";
+&cp1_syscon0 {
+	cp1_pinctrl: pinctrl {
+		compatible = "marvell,armada-8k-cp1-pinctrl";
 
 		nand_pins: nand-pins {
 			marvell,pins =

@@ -135,7 +135,7 @@
 	};
 };
 
-&cps_crypto {
+&cp1_crypto {
 	/*
 	 * The cryptographic engine found on the cp110
 	 * master is enabled by default at the SoC

2.14.3

Hi Thomas,

I applied all the series on mvebu/dt64. The only change I made was adding a commit log to the patch 3:
"Fix the same typo duplicated in both master and slave version of armada-cp110-*.dtsi file: s/limiation/limitation/."

Thanks,

Gregory

Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Hello,

Thanks!

I would recommend you to ask people submitting DT changes for this cycle to base their changes on your mvebu/dt64 branch, because most DT changes for 7K/8K are going to conflict with this de-duplication + renaming patch series.

Thomas

Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com