at91: move reset vector to board code

88 lines not on this page · raw message

135 lines not on this page · raw message

index 1b146da62..3b8b0a298 100644
@@ -14,6 +14,7 @@
 #include <mach/at91sam9_sdramc.h>
 #include <mach/at91sam9_matrix.h>
 #include <mach/at91_lowlevel_init.h>
+#include <mach/at91sam9263_matrix.h>
 
 #define MASTER_CLOCK		180
 

index 6b37e49e9..d72dfff38 100644
@@ -35,7 +35,7 @@ struct at91sam926x_lowlevel_cfg {
 	u32 rstc_rmr;
 };
 
-#ifdef CONFIG_HAVE_AT91_LOWLEVEL_INIT
+#ifdef CONFIG_AT91SAM926X_LWL
 void at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg);
 void at91sam926x_lowlevel_init(struct at91sam926x_lowlevel_cfg *cfg);
 #else

deleted file mode 100644
index 48e69f947..000000000
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
- *
- * Under GPLv2
-  */
-
-#define __LOWLEVEL_INIT__
-
-#include <common.h>
-#include <asm/system.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/at91sam9_ddrsdr.h>
-#include <init.h>
-#include <linux/sizes.h>
-
-void __naked __bare_init barebox_arm_reset_vector(void)
-{
-	arm_cpu_lowlevel_init();
-
-	arm_setup_stack(AT91SAM9X5_SRAM_BASE + AT91SAM9X5_SRAM_SIZE - 16);
-
-	barebox_arm_entry(AT91_CHIPSELECT_1, at91sam9x5_get_ddram_size(), NULL);
-}

new file mode 100644
index 000000000..54d67404c
@@ -0,0 +1,222 @@
+#ifndef __AT91SAM926X_BOARD_INIT_H__
+#define __AT91SAM926X_BOARD_INIT_H__
+/*
+ * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
+ * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_pio.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91_wdt.h>
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+
+struct at91sam926x_board_cfg {
+	/* SoC specific */
+	void __iomem *pio;
+	void __iomem *sdramc;
+	u32 ebi_pio_is_peripha;
+	u32 matrix_csa;
+
+	/* board specific */
+	u32 wdt_mr;
+	u32 ebi_pio_pdr;
+	u32 ebi_pio_ppudr;
+	u32 ebi_csa;
+	u32 smc_cs;
+	u32 smc_mode;
+	u32 smc_cycle;
+	u32 smc_pulse;
+	u32 smc_setup;
+	u32 pmc_mor;
+	u32 pmc_pllar;
+	u32 pmc_mckr1;
+	u32 pmc_mckr2;
+	u32 sdrc_cr;
+	u32 sdrc_tr1;
+	u32 sdrc_mdr;
+	u32 sdrc_tr2;
+	u32 rstc_rmr;
+};
+
+
+static void __always_inline access_sdram(void)
+{
+	writel(0x00000000, AT91_SDRAM_BASE);
+}
+
+static void __always_inline pmc_check_mckrdy(void)
+{
+	u32 r;
+
+	do {
+		r = at91_pmc_read(AT91_PMC_SR);
+	} while (!(r & AT91_PMC_MCKRDY));
+}
+
+static int __always_inline running_in_sram(void)
+{
+	u32 addr = get_pc();
+
+	addr >>= 28;
+	return addr == 0;
+}
+
+#define at91_sdramc_read(field) \
+	__raw_readl(cfg->sdramc + field)
+
+#define at91_sdramc_write(field, value) \
+	__raw_writel(value, cfg->sdramc + field)
+
+static void __always_inline at91sam926x_sdramc_init(struct at91sam926x_board_cfg *cfg)
+{
+	u32 r;
+	int i;
+	int in_sram = running_in_sram();
+
+	/*
+	 * SDRAMC Check if Refresh Timer Counter is already initialized
+	 */
+	r = at91_sdramc_read(AT91_SDRAMC_TR);
+	if (r && !in_sram)
+		return;
+
+	/* SDRAMC_MR : Normal Mode */
+	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
+
+	/* SDRAMC_TR - Refresh Timer register */
+	at91_sdramc_write(AT91_SDRAMC_TR, cfg->sdrc_tr1);
+
+	/* SDRAMC_CR - Configuration register*/
+	at91_sdramc_write(AT91_SDRAMC_CR, cfg->sdrc_cr);
+
+	/* Memory Device Type */
+	at91_sdramc_write(AT91_SDRAMC_MDR, cfg->sdrc_mdr);
+
+	/* SDRAMC_MR : Precharge All */
+	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
+
+	/* access SDRAM */
+	access_sdram();
+
+	/* SDRAMC_MR : refresh */
+	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);
+
+	/* access SDRAM 8 times */
+	for (i = 0; i < 8; i++)
+		access_sdram();
+
+	/* SDRAMC_MR : Load Mode Register */
+	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);
+
+	/* access SDRAM */
+	access_sdram();
+
+	/* SDRAMC_MR : Normal Mode */
+	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
+
+	/* access SDRAM */
+	access_sdram();
+
+	/* SDRAMC_TR : Refresh Timer Counter */
+	at91_sdramc_write(AT91_SDRAMC_TR, cfg->sdrc_tr2);
+
+	/* access SDRAM */
+	access_sdram();
+}
+
+static void __always_inline at91sam926x_board_init(struct at91sam926x_board_cfg *cfg)
+{
+	u32 r;
+
+	if (!IS_ENABLED(CONFIG_AT91SAM926X_BOARD_INIT))
+		return;
+
+	__raw_writel(cfg->wdt_mr, AT91_BASE_WDT + AT91_WDT_MR);
+
+	/* configure PIOx as EBI0 D[16-31] */
+	at91_mux_gpio_disable(cfg->pio, cfg->ebi_pio_pdr);
+	at91_mux_set_pullup(cfg->pio, cfg->ebi_pio_ppudr, true);
+	if (cfg->ebi_pio_is_peripha)
+		at91_mux_set_A_periph(cfg->pio, cfg->ebi_pio_ppudr);
+
+	at91_sys_write(cfg->matrix_csa, cfg->ebi_csa);
+
+	/* flash */
+	at91_smc_write(cfg->smc_cs, AT91_SAM9_SMC_MODE, cfg->smc_mode);
+
+	at91_smc_write(cfg->smc_cs, AT91_SMC_CYCLE, cfg->smc_cycle);
+
+	at91_smc_write(cfg->smc_cs, AT91_SMC_PULSE, cfg->smc_pulse);
+
+	at91_smc_write(cfg->smc_cs, AT91_SMC_SETUP, cfg->smc_setup);
+
+	/*
+	 * PMC Check if the PLL is already initialized
+	 */
+	r = at91_pmc_read(AT91_PMC_MCKR);
+	if ((r & AT91_PMC_CSS) && !running_in_sram())
+		return;
+
+	/*
+	 * Enable the Main Oscillator
+	 */
+	at91_pmc_write(AT91_CKGR_MOR, cfg->pmc_mor);
+
+	do {
+		r = at91_pmc_read(AT91_PMC_SR);
+	} while (!(r & AT91_PMC_MOSCS));
+
+	/*
+	 * PLLAR: x MHz for PCK
+	 */
+	at91_pmc_write(AT91_CKGR_PLLAR, cfg->pmc_pllar);
+
+	do {
+		r = at91_pmc_read(AT91_PMC_SR);
+	} while (!(r & AT91_PMC_LOCKA));
+
+	/*
+	 * PCK/x = MCK Master Clock from SLOW
+	 */
+	at91_pmc_write(AT91_PMC_MCKR, cfg->pmc_mckr1);
+
+	pmc_check_mckrdy();
+
+	/*
+	 * PCK/x = MCK Master Clock from PLLA
+	 */
+	at91_pmc_write(AT91_PMC_MCKR, cfg->pmc_mckr2);
+
+	pmc_check_mckrdy();
+
+	/*
+	 * Init SDRAM
+	 */
+	at91sam926x_sdramc_init(cfg);
+
+	/* User reset enable*/
+	at91_sys_write(AT91_RSTC_MR, cfg->rstc_rmr);
+
+#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
+	/* MATRIX_MCFG - REMAP all masters */
+	at91_sys_write(AT91_MATRIX_MCFG0, 0x1FF);
+#endif
+	/*
+	 * When boot from external boot
+	 * we need to enable mck and ohter clock
+	 * so enable all of them
+	 * We will shutdown what we don't need later
+	 */
+	at91_pmc_write(AT91_PMC_PCER, 0xffffffff);
+}
+
+#endif /* __AT91SAM926X_BOARD_INIT_H__ */

index 54d67404c..70ae90337 100644
@@ -70,66 +70,50 @@ static int __always_inline running_in_sram(void)
 	return addr == 0;
 }
 
-#define at91_sdramc_read(field) \
-	__raw_readl(cfg->sdramc + field)
-
-#define at91_sdramc_write(field, value) \
-	__raw_writel(value, cfg->sdramc + field)
-
 static void __always_inline at91sam926x_sdramc_init(struct at91sam926x_board_cfg *cfg)
 {
 	u32 r;
 	int i;
 	int in_sram = running_in_sram();
 
-	/*
-	 * SDRAMC Check if Refresh Timer Counter is already initialized
-	 */
-	r = at91_sdramc_read(AT91_SDRAMC_TR);
+	/* SDRAMC Check if Refresh Timer Counter is already initialized */
+	r = __raw_readl(cfg->sdramc + AT91_SDRAMC_TR);
 	if (r && !in_sram)
 		return;
 
 	/* SDRAMC_MR : Normal Mode */
-	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
+	__raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_NORMAL);
 
 	/* SDRAMC_TR - Refresh Timer register */
-	at91_sdramc_write(AT91_SDRAMC_TR, cfg->sdrc_tr1);
+	__raw_writel(AT91_SDRAMC_TR, cfg->sdramc + cfg->sdrc_tr1);
 
 	/* SDRAMC_CR - Configuration register*/
-	at91_sdramc_write(AT91_SDRAMC_CR, cfg->sdrc_cr);
+	__raw_writel(AT91_SDRAMC_CR, cfg->sdramc + cfg->sdrc_cr);
 
 	/* Memory Device Type */
-	at91_sdramc_write(AT91_SDRAMC_MDR, cfg->sdrc_mdr);
+	__raw_writel(AT91_SDRAMC_MDR, cfg->sdramc + cfg->sdrc_mdr);
 
 	/* SDRAMC_MR : Precharge All */
-	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
-
-	/* access SDRAM */
+	__raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_PRECHARGE);
 	access_sdram();
 
 	/* SDRAMC_MR : refresh */
-	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);
+	__raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_REFRESH);
 
 	/* access SDRAM 8 times */
 	for (i = 0; i < 8; i++)
 		access_sdram();
 
 	/* SDRAMC_MR : Load Mode Register */
-	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);
-
-	/* access SDRAM */
+	__raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_LMR);
 	access_sdram();
 
 	/* SDRAMC_MR : Normal Mode */
-	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
-
-	/* access SDRAM */
+	__raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_NORMAL);
 	access_sdram();
 
 	/* SDRAMC_TR : Refresh Timer Counter */
-	at91_sdramc_write(AT91_SDRAMC_TR, cfg->sdrc_tr2);
-
-	/* access SDRAM */
+	__raw_writel(AT91_SDRAMC_TR, cfg->sdramc + cfg->sdrc_tr2);
 	access_sdram();
 }
 

@@ -152,64 +136,41 @@ static void __always_inline at91sam926x_board_init(struct at91sam926x_board_cfg
 
 	/* flash */
 	at91_smc_write(cfg->smc_cs, AT91_SAM9_SMC_MODE, cfg->smc_mode);
-
 	at91_smc_write(cfg->smc_cs, AT91_SMC_CYCLE, cfg->smc_cycle);
-
 	at91_smc_write(cfg->smc_cs, AT91_SMC_PULSE, cfg->smc_pulse);
-
 	at91_smc_write(cfg->smc_cs, AT91_SMC_SETUP, cfg->smc_setup);
 
-	/*
-	 * PMC Check if the PLL is already initialized
-	 */
+	/* PMC Check if the PLL is already initialized */
 	r = at91_pmc_read(AT91_PMC_MCKR);
 	if ((r & AT91_PMC_CSS) && !running_in_sram())
 		return;
 
-	/*
-	 * Enable the Main Oscillator
-	 */
+	/* Enable the Main Oscillator */
 	at91_pmc_write(AT91_CKGR_MOR, cfg->pmc_mor);
-
 	do {
 		r = at91_pmc_read(AT91_PMC_SR);
 	} while (!(r & AT91_PMC_MOSCS));
 
-	/*
-	 * PLLAR: x MHz for PCK
-	 */
+	/* PLLAR: x MHz for PCK */
 	at91_pmc_write(AT91_CKGR_PLLAR, cfg->pmc_pllar);
-
 	do {
 		r = at91_pmc_read(AT91_PMC_SR);
 	} while (!(r & AT91_PMC_LOCKA));
 
-	/*
-	 * PCK/x = MCK Master Clock from SLOW
-	 */
+	/* PCK/x = MCK Master Clock from SLOW */
 	at91_pmc_write(AT91_PMC_MCKR, cfg->pmc_mckr1);
-
 	pmc_check_mckrdy();
 
-	/*
-	 * PCK/x = MCK Master Clock from PLLA
-	 */
+	/* PCK/x = MCK Master Clock from PLLA */
 	at91_pmc_write(AT91_PMC_MCKR, cfg->pmc_mckr2);
-
 	pmc_check_mckrdy();
 
-	/*
-	 * Init SDRAM
-	 */
+	/* Init SDRAM */
 	at91sam926x_sdramc_init(cfg);
 
 	/* User reset enable*/
 	at91_sys_write(AT91_RSTC_MR, cfg->rstc_rmr);
 
-#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
-	/* MATRIX_MCFG - REMAP all masters */
-	at91_sys_write(AT91_MATRIX_MCFG0, 0x1FF);
-#endif
 	/*
 	 * When boot from external boot
 	 * we need to enable mck and ohter clock

index 2f8b312d3..70e0da3b1 100644
@@ -4,21 +4,17 @@
  * Under GPLv2
  */
 
-#include <common.h>
-#include <init.h>
-#include <mach/hardware.h>
-#include <mach/at91_rstc.h>
-#include <mach/at91_wdt.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91sam9_sdramc.h>
-#include <mach/at91sam9_matrix.h>
-#include <mach/at91_lowlevel_init.h>
+#include <linux/sizes.h>
+
+#include <asm/barebox-arm.h>
+
+#include <mach/at91sam926x_board_init.h>
+#include <mach/at91sam9263_matrix.h>
 
 #define MASTER_PLL_MUL		171
 #define MASTER_PLL_DIV		14
 
-void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
+static void __bare_init at91sam9263ek_board_config(struct at91sam926x_board_cfg *cfg)
 {
 	/* Disable Watchdog */
 	cfg->wdt_mr =

@@ -102,3 +98,28 @@ void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_c
 		AT91_RSTC_RSTTYP_WAKEUP |
 		AT91_RSTC_RSTTYP_WATCHDOG;
 }
+
+static void __bare_init at91sam9263ek_init(void)
+{
+	struct at91sam926x_board_cfg cfg;
+
+	cfg.pio = IOMEM(AT91SAM9263_BASE_PIOD);
+	cfg.sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0);
+	cfg.ebi_pio_is_peripha = true;
+	cfg.matrix_csa = AT91_MATRIX_EBI0CSA;
+
+	at91sam9263ek_board_config(&cfg);
+	at91sam926x_board_init(&cfg);
+
+	barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc),
+	                  NULL);
+}
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE - 16);
+
+	at91sam9263ek_init();
+}

56 lines not on this page · raw message

index 91a64b415..a4cb8af69 100644
@@ -4,22 +4,16 @@
  * Under GPLv2
  */
 
-#include <common.h>
-#include <init.h>
-#include <mach/hardware.h>
-#include <mach/at91_rstc.h>
-#include <mach/at91_wdt.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91sam9_sdramc.h>
+#include <asm/barebox-arm.h>
+
+#include <mach/at91sam926x_board_init.h>
 #include <mach/at91sam9_matrix.h>
-#include <mach/at91_lowlevel_init.h>
 
 #define MASTER_PLL_DIV		15
 #define MASTER_PLL_MUL		162
 #define MAIN_PLL_DIV		2
 
-void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
+static void __bare_init pm9261_board_config(struct at91sam926x_board_cfg *cfg)
 {
 	/* Disable Watchdog */
 	cfg->wdt_mr =

@@ -100,3 +94,28 @@ void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_c
 		AT91_RSTC_RSTTYP_WAKEUP |
 		AT91_RSTC_RSTTYP_WATCHDOG;
 }
+
+static void __bare_init pm9261_init(void)
+{
+	struct at91sam926x_board_cfg cfg;
+
+	cfg.pio = IOMEM(AT91SAM9261_BASE_PIOC);
+	cfg.sdramc = IOMEM(AT91SAM9261_BASE_SDRAMC);
+	cfg.ebi_pio_is_peripha = false;
+	cfg.matrix_csa = AT91_MATRIX_EBICSA;
+
+	pm9261_board_config(&cfg);
+	at91sam926x_board_init(&cfg);
+
+	barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc),
+	                  NULL);
+}
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 16);
+
+	pm9261_init();
+}

48 lines not on this page · raw message

index 6336d5106..6849f0a5b 100644
@@ -4,22 +4,18 @@
  * Under GPLv2
  */
 
-#include <common.h>
-#include <init.h>
-#include <mach/hardware.h>
-#include <mach/at91_rstc.h>
-#include <mach/at91_wdt.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91sam9_sdramc.h>
-#include <mach/at91sam9_matrix.h>
-#include <mach/at91_lowlevel_init.h>
+#include <linux/sizes.h>
+
+#include <asm/barebox-arm.h>
+
+#include <mach/at91sam926x_board_init.h>
+#include <mach/at91sam9263_matrix.h>
 
 #define MASTER_PLL_DIV		6
 #define MASTER_PLL_MUL		65
 #define MAIN_PLL_DIV		2	/* 2 or 4 */
 
-void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
+static void __bare_init pm9263_board_config(struct at91sam926x_board_cfg *cfg)
 {
 	/* Disable Watchdog */
 	cfg->wdt_mr =

@@ -119,3 +115,28 @@ void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_c
 		AT91_RSTC_RSTTYP_WAKEUP |
 		AT91_RSTC_RSTTYP_WATCHDOG;
 }
+
+static void __bare_init pm9263_board_init(void)
+{
+	struct at91sam926x_board_cfg cfg;
+
+	cfg.pio = IOMEM(AT91SAM9263_BASE_PIOD);
+	cfg.sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0);
+	cfg.ebi_pio_is_peripha = true;
+	cfg.matrix_csa = AT91_MATRIX_EBI0CSA;
+
+	pm9263_board_config(&cfg);
+	at91sam926x_board_init(&cfg);
+
+	barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc),
+	                  NULL);
+}
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE - 16);
+
+	pm9263_board_init();
+}

new file mode 100644
index 000000000..b16ef31bf
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9260.h>
+#include <mach/hardware.h>
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16);
+
+	barebox_arm_entry(AT91_CHIPSELECT_1,
+			  at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)),
+			  NULL);
+}

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new file mode 100644
index 000000000..b16ef31bf
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9260.h>
+#include <mach/hardware.h>
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16);
+
+	barebox_arm_entry(AT91_CHIPSELECT_1,
+			  at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)),
+			  NULL);
+}

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new file mode 100644
index 000000000..b16ef31bf
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9260.h>
+#include <mach/hardware.h>
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16);
+
+	barebox_arm_entry(AT91_CHIPSELECT_1,
+			  at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)),
+			  NULL);
+}

new file mode 100644
index 000000000..b16ef31bf
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9260.h>
+#include <mach/hardware.h>
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16);
+
+	barebox_arm_entry(AT91_CHIPSELECT_1,
+			  at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)),
+			  NULL);
+}

similarity index 85%
rename from arch/arm/mach-at91/sama5d3_lowlevel_init.c
rename to arch/arm/boards/sama5d3_xplained/lowlevel.c
index 01d28514d..b791f2a03 100644
@@ -2,18 +2,16 @@
  * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
  *
  * Under GPLv2
-  */
-
-#define __LOWLEVEL_INIT__
+ */
 
 #include <common.h>
-#include <linux/sizes.h>
 #include <init.h>
-#include <asm/system.h>
-#include <asm/barebox-arm.h>
+
 #include <asm/barebox-arm-head.h>
-#include <mach/hardware.h>
+#include <asm/barebox-arm.h>
+
 #include <mach/at91sam9_ddrsdr.h>
+#include <mach/hardware.h>
 
 void __naked __bare_init barebox_arm_reset_vector(void)
 {

new file mode 100644
index 000000000..b791f2a03
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+
+#include <mach/at91sam9_ddrsdr.h>
+#include <mach/hardware.h>
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
+
+	barebox_arm_entry(SAMA5_DDRCS, at91sama5_get_ddram_size(), NULL);
+}

new file mode 100644
index 000000000..b791f2a03
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+
+#include <mach/at91sam9_ddrsdr.h>
+#include <mach/hardware.h>
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
+
+	barebox_arm_entry(SAMA5_DDRCS, at91sama5_get_ddram_size(), NULL);
+}

new file mode 100644
index 000000000..b791f2a03
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+
+#include <mach/at91sam9_ddrsdr.h>
+#include <mach/hardware.h>
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
+
+	barebox_arm_entry(SAMA5_DDRCS, at91sama5_get_ddram_size(), NULL);
+}

similarity index 83%
rename from arch/arm/mach-at91/at91sam9n12_lowlevel_init.c
rename to arch/arm/boards/at91sam9n12ek/lowlevel.c
index 2b5cb158b..47079336e 100644
@@ -2,19 +2,16 @@
  * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
  *
  * Under GPLv2
-  */
-
-#define __LOWLEVEL_INIT__
+ */
 
 #include <common.h>
-#include <asm/system.h>
-#include <asm/barebox-arm.h>
+#include <init.h>
+
 #include <asm/barebox-arm-head.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
+#include <asm/barebox-arm.h>
+
 #include <mach/at91sam9_ddrsdr.h>
-#include <init.h>
-#include <linux/sizes.h>
+#include <mach/hardware.h>
 
 void __naked __bare_init barebox_arm_reset_vector(void)
 {

new file mode 100644
index 000000000..b16ef31bf
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9260.h>
+#include <mach/hardware.h>
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16);
+
+	barebox_arm_entry(AT91_CHIPSELECT_1,
+			  at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)),
+			  NULL);
+}

similarity index 83%
rename from arch/arm/mach-at91/at91sam9g45_lowlevel_init.c
rename to arch/arm/boards/at91sam9m10g45ek/lowlevel.c
index 2cdb7a6a5..478ff11e1 100644
@@ -2,19 +2,16 @@
  * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
  *
  * Under GPLv2
-  */
-
-#define __LOWLEVEL_INIT__
+ */
 
 #include <common.h>
-#include <asm/system.h>
-#include <asm/barebox-arm.h>
+#include <init.h>
+
 #include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+
 #include <mach/hardware.h>
-#include <mach/io.h>
 #include <mach/at91sam9_ddrsdr.h>
-#include <init.h>
-#include <linux/sizes.h>
 
 void __naked __bare_init barebox_arm_reset_vector(void)
 {

new file mode 100644
index 000000000..d5940b987
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+
+#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91sam9g45.h>
+#include <mach/hardware.h>
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9G45_SRAM_BASE + AT91SAM9G45_SRAM_SIZE - 16);
+
+	barebox_arm_entry(AT91_CHIPSELECT_6, at91sam9g45_get_ddram_size(1),
+	                  NULL);
+}

new file mode 100644
index 000000000..67454bde2
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+
+#include <mach/at91sam9_ddrsdr.h>
+#include <mach/hardware.h>
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9G45_SRAM_BASE + AT91SAM9G45_SRAM_SIZE - 16);
+
+	barebox_arm_entry(AT91_CHIPSELECT_6, at91sam9g45_get_ddram_size(1),
+	                  NULL);
+}

new file mode 100644
index 000000000..b16ef31bf
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9260.h>
+#include <mach/hardware.h>
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16);
+
+	barebox_arm_entry(AT91_CHIPSELECT_1,
+			  at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)),
+			  NULL);
+}

new file mode 100644
index 000000000..b16ef31bf
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9260.h>
+#include <mach/hardware.h>
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16);
+
+	barebox_arm_entry(AT91_CHIPSELECT_1,
+			  at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)),
+			  NULL);
+}

new file mode 100644
index 000000000..b16ef31bf
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9260.h>
+#include <mach/hardware.h>
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16);
+
+	barebox_arm_entry(AT91_CHIPSELECT_1,
+			  at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)),
+			  NULL);
+}

similarity index 97%
rename from arch/arm/mach-at91/at91rm9200_lowlevel_init.c
rename to arch/arm/boards/at91rm9200ek/lowlevel.c
index f78e36808..a85a22e79 100644
@@ -4,19 +4,17 @@
  * Under GPLv2
  */
 
-#define __LOWLEVEL_INIT__
-
 #include <common.h>
-#include <asm/system.h>
-#include <asm/barebox-arm.h>
+#include <init.h>
+
 #include <asm/barebox-arm-head.h>
-#include <mach/hardware.h>
-#include <mach/at91rm9200.h>
+#include <asm/barebox-arm.h>
+
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91rm9200.h>
 #include <mach/at91_pio.h>
 #include <mach/at91_pmc.h>
-#include <mach/io.h>
-#include <init.h>
+#include <mach/hardware.h>
 
 void static inline access_sdram(void)
 {

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