imx: add i.MX8M support and i.MX8MQ EVK

index 69026df763..b62dfbf6bf 100644
@@ -6,27 +6,22 @@
 
 #include <common.h>
 #include <command.h>
+#include <linux/compiler.h>
 
 /* Allow for arch specific config before we boot */
-static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+int __weak arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
 {
 	/* please define platform specific arch_auxiliary_core_up() */
 	return CMD_RET_FAILURE;
 }
 
-int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
-	__attribute__((weak, alias("__arch_auxiliary_core_up")));
-
 /* Allow for arch specific config before we boot */
-static int __arch_auxiliary_core_check_up(u32 core_id)
+int __weak arch_auxiliary_core_check_up(u32 core_id)
 {
 	/* please define platform specific arch_auxiliary_core_check_up() */
 	return 0;
 }
 
-int arch_auxiliary_core_check_up(u32 core_id)
-	__attribute__((weak, alias("__arch_auxiliary_core_check_up")));
-
 /*
  * To i.MX6SX and i.MX7D, the image supported by bootaux needs
  * the reset vector at the head for the image, with SP and PC

@@ -40,7 +35,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
  * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
  * accessing the M4 TCMUL.
  */
-int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	ulong addr;
 	int ret, up;

index 610098c175..284f6d4cde 100644
@@ -911,10 +911,11 @@ void mxc_set_sata_internal_clock(void)
 }
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Dump some core clockes.
  */
-int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	u32 freq;
 

@@ -947,3 +948,4 @@ U_BOOT_CMD(
 	"display clocks",
 	""
 );
+#endif

index 8150faa1a3..c11042d6f5 100644
@@ -1096,6 +1096,7 @@ void epdc_clock_disable(void)
 }
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Dump some core clockes.
  */

@@ -1131,3 +1132,4 @@ U_BOOT_CMD(
 	"display clocks",
 	""
 );
+#endif

index 77b282addd..553d62149d 100644
@@ -323,6 +323,7 @@ void hab_caam_clock_enable(unsigned char enable)
 }
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Dump some core clockes.
  */

@@ -363,3 +364,4 @@ U_BOOT_CMD(
 	"display clocks",
 	""
 );
+#endif

new file mode 100644
index 0000000000..a10034cc35
@@ -0,0 +1,468 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX8M_REGS_H__
+#define __ASM_ARCH_MX8M_REGS_H__
+
+#include <asm/mach-imx/regs-lcdif.h>
+
+#define ROM_VERSION_A0		0x800
+#define ROM_VERSION_B0		0x83C
+
+#define M4_BOOTROM_BASE_ADDR	0x007E0000
+
+#define SAI1_BASE_ADDR		0x30010000
+#define SAI6_BASE_ADDR		0x30030000
+#define SAI5_BASE_ADDR		0x30040000
+#define SAI4_BASE_ADDR		0x30050000
+#define SPBA2_BASE_ADDR		0x300F0000
+#define AIPS1_BASE_ADDR		0x301F0000
+#define GPIO1_BASE_ADDR		0X30200000
+#define GPIO2_BASE_ADDR		0x30210000
+#define GPIO3_BASE_ADDR		0x30220000
+#define GPIO4_BASE_ADDR		0x30230000
+#define GPIO5_BASE_ADDR		0x30240000
+#define ANA_TSENSOR_BASE_ADDR	0x30260000
+#define ANA_OSC_BASE_ADDR	0x30270000
+#define WDOG1_BASE_ADDR		0x30280000
+#define WDOG2_BASE_ADDR		0x30290000
+#define WDOG3_BASE_ADDR		0x302A0000
+#define SDMA2_BASE_ADDR		0x302C0000
+#define GPT1_BASE_ADDR		0x302D0000
+#define GPT2_BASE_ADDR		0x302E0000
+#define GPT3_BASE_ADDR		0x302F0000
+#define ROMCP_BASE_ADDR		0x30310000
+#define LCDIF_BASE_ADDR		0x30320000
+#define IOMUXC_BASE_ADDR	0x30330000
+#define IOMUXC_GPR_BASE_ADDR	0x30340000
+#define OCOTP_BASE_ADDR		0x30350000
+#define ANATOP_BASE_ADDR	0x30360000
+#define SNVS_HP_BASE_ADDR	0x30370000
+#define CCM_BASE_ADDR		0x30380000
+#define SRC_BASE_ADDR		0x30390000
+#define GPC_BASE_ADDR		0x303A0000
+#define SEMAPHORE1_BASE_ADDR	0x303B0000
+#define SEMAPHORE2_BASE_ADDR	0x303C0000
+#define RDC_BASE_ADDR		0x303D0000
+#define CSU_BASE_ADDR		0x303E0000
+
+#define AIPS2_BASE_ADDR		0x305F0000
+#define PWM1_BASE_ADDR		0x30660000
+#define PWM2_BASE_ADDR		0x30670000
+#define PWM3_BASE_ADDR		0x30680000
+#define PWM4_BASE_ADDR		0x30690000
+#define SYSCNT_RD_BASE_ADDR	0x306A0000
+#define SYSCNT_CMP_BASE_ADDR	0x306B0000
+#define SYSCNT_CTRL_BASE_ADDR	0x306C0000
+#define GPT6_BASE_ADDR		0x306E0000
+#define GPT5_BASE_ADDR		0x306F0000
+#define GPT4_BASE_ADDR		0x30700000
+#define PERFMON1_BASE_ADDR	0x307C0000
+#define PERFMON2_BASE_ADDR	0x307D0000
+#define QOSC_BASE_ADDR		0x307F0000
+
+#define SPDIF1_BASE_ADDR	0x30810000
+#define ECSPI1_BASE_ADDR	0x30820000
+#define ECSPI2_BASE_ADDR	0x30830000
+#define ECSPI3_BASE_ADDR	0x30840000
+#define UART1_BASE_ADDR		0x30860000
+#define UART3_BASE_ADDR		0x30880000
+#define UART2_BASE_ADDR		0x30890000
+#define SPDIF2_BASE_ADDR	0x308A0000
+#define SAI2_BASE_ADDR		0x308B0000
+#define SAI3_BASE_ADDR		0x308C0000
+#define SPBA1_BASE_ADDR		0x308F0000
+#define CAAM_BASE_ADDR		0x30900000
+#define AIPS3_BASE_ADDR		0x309F0000
+#define MIPI_PHY_BASE_ADDR	0x30A00000
+#define MIPI_DSI_BASE_ADDR	0x30A10000
+#define I2C1_BASE_ADDR		0x30A20000
+#define I2C2_BASE_ADDR		0x30A30000
+#define I2C3_BASE_ADDR		0x30A40000
+#define I2C4_BASE_ADDR		0x30A50000
+#define UART4_BASE_ADDR		0x30A60000
+#define MIPI_CSI_BASE_ADDR	0x30A70000
+#define MIPI_CSI_PHY1_BASE_ADDR	0x30A80000
+#define CSI1_BASE_ADDR		0x30A90000
+#define MU_A_BASE_ADDR		0x30AA0000
+#define MU_B_BASE_ADDR		0x30AB0000
+#define SEMAPHOR_HS_BASE_ADDR	0x30AC0000
+#define USDHC1_BASE_ADDR	0x30B40000
+#define USDHC2_BASE_ADDR	0x30B50000
+#define MIPI_CS2_BASE_ADDR	0x30B60000
+#define MIPI_CSI_PHY2_BASE_ADDR	0x30B70000
+#define CSI2_BASE_ADDR		0x30B80000
+#define QSPI0_BASE_ADDR		0x30BB0000
+#define QSPI0_AMBA_BASE		0x08000000
+#define SDMA1_BASE_ADDR		0x30BD0000
+#define ENET1_BASE_ADDR		0x30BE0000
+
+#define HDMI_CTRL_BASE_ADDR	0x32C00000
+#define AIPS4_BASE_ADDR		0x32DF0000
+#define DC1_BASE_ADDR		0x32E00000
+#define DC2_BASE_ADDR		0x32E10000
+#define DC3_BASE_ADDR		0x32E20000
+#define HDMI_SEC_BASE_ADDR	0x32E40000
+#define TZASC_BASE_ADDR		0x32F80000
+#define MTR_BASE_ADDR		0x32FB0000
+#define PLATFORM_CTRL_BASE_ADDR	0x32FE0000
+
+#define MXS_APBH_BASE		0x33000000
+#define MXS_GPMI_BASE		0x33002000
+#define MXS_BCH_BASE		0x33004000
+
+#define USB1_BASE_ADDR		0x38100000
+#define USB2_BASE_ADDR		0x38200000
+#define USB1_PHY_BASE_ADDR	0x381F0000
+#define USB2_PHY_BASE_ADDR	0x382F0000
+
+#define MXS_LCDIF_BASE		LCDIF_BASE_ADDR
+
+#define SRC_IPS_BASE_ADDR	0x30390000
+#define SRC_DDRC_RCR_ADDR	0x30391000
+#define SRC_DDRC2_RCR_ADDR	0x30391004
+
+#define DDRC_DDR_SS_GPR0	0x3d000000
+#define DDRC_IPS_BASE_ADDR(X)	(0x3d400000 + ((X) * 0x2000000))
+#define DDR_CSD1_BASE_ADDR	0x40000000
+
+#if !defined(__ASSEMBLY__)
+#include <asm/types.h>
+#include <linux/bitops.h>
+#include <stdbool.h>
+
+#define GPR_TZASC_EN		BIT(0)
+#define GPR_TZASC_EN_LOCK	BIT(16)
+
+#define SRC_SCR_M4_ENABLE_OFFSET	3
+#define SRC_SCR_M4_ENABLE_MASK		BIT(3)
+#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET	0
+#define SRC_SCR_M4C_NON_SCLR_RST_MASK	BIT(0)
+#define SRC_DDR1_ENABLE_MASK		0x8F000000UL
+#define SRC_DDR2_ENABLE_MASK		0x8F000000UL
+#define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK	BIT(3)
+#define SRC_DDR1_RCR_PHY_RESET_MASK	BIT(2)
+#define SRC_DDR1_RCR_CORE_RESET_N_MASK	BIT(1)
+#define SRC_DDR1_RCR_PRESET_N_MASK	BIT(0)
+
+struct iomuxc_gpr_base_regs {
+	u32 gpr[47];
+};
+
+struct ocotp_regs {
+	u32	ctrl;
+	u32	ctrl_set;
+	u32     ctrl_clr;
+	u32	ctrl_tog;
+	u32	timing;
+	u32     rsvd0[3];
+	u32     data;
+	u32     rsvd1[3];
+	u32     read_ctrl;
+	u32     rsvd2[3];
+	u32	read_fuse_data;
+	u32     rsvd3[3];
+	u32	sw_sticky;
+	u32     rsvd4[3];
+	u32     scs;
+	u32     scs_set;
+	u32     scs_clr;
+	u32     scs_tog;
+	u32     crc_addr;
+	u32     rsvd5[3];
+	u32     crc_value;
+	u32     rsvd6[3];
+	u32     version;
+	u32     rsvd7[0xdb];
+
+	/* fuse banks */
+	struct fuse_bank {
+		u32	fuse_regs[0x10];
+	} bank[0];
+};
+
+struct fuse_bank0_regs {
+	u32 lock;
+	u32 rsvd0[3];
+	u32 uid_low;
+	u32 rsvd1[3];
+	u32 uid_high;
+	u32 rsvd2[7];
+};
+
+struct fuse_bank1_regs {
+	u32 tester3;
+	u32 rsvd0[3];
+	u32 tester4;
+	u32 rsvd1[3];
+	u32 tester5;
+	u32 rsvd2[3];
+	u32 cfg0;
+	u32 rsvd3[3];
+};
+
+struct anamix_pll {
+	u32 audio_pll1_cfg0;
+	u32 audio_pll1_cfg1;
+	u32 audio_pll2_cfg0;
+	u32 audio_pll2_cfg1;
+	u32 video_pll_cfg0;
+	u32 video_pll_cfg1;
+	u32 gpu_pll_cfg0;
+	u32 gpu_pll_cfg1;
+	u32 vpu_pll_cfg0;
+	u32 vpu_pll_cfg1;
+	u32 arm_pll_cfg0;
+	u32 arm_pll_cfg1;
+	u32 sys_pll1_cfg0;
+	u32 sys_pll1_cfg1;
+	u32 sys_pll1_cfg2;
+	u32 sys_pll2_cfg0;
+	u32 sys_pll2_cfg1;
+	u32 sys_pll2_cfg2;
+	u32 sys_pll3_cfg0;
+	u32 sys_pll3_cfg1;
+	u32 sys_pll3_cfg2;
+	u32 video_pll2_cfg0;
+	u32 video_pll2_cfg1;
+	u32 video_pll2_cfg2;
+	u32 dram_pll_cfg0;
+	u32 dram_pll_cfg1;
+	u32 dram_pll_cfg2;
+	u32 digprog;
+	u32 osc_misc_cfg;
+	u32 pllout_monitor_cfg;
+	u32 frac_pllout_div_cfg;
+	u32 sscg_pllout_div_cfg;
+};
+
+struct fuse_bank9_regs {
+	u32 mac_addr0;
+	u32 rsvd0[3];
+	u32 mac_addr1;
+	u32 rsvd1[11];
+};
+
+/* System Reset Controller (SRC) */
+struct src {
+	u32 scr;
+	u32 a53rcr;
+	u32 a53rcr1;
+	u32 m4rcr;
+	u32 reserved1[4];
+	u32 usbophy1_rcr;
+	u32 usbophy2_rcr;
+	u32 mipiphy_rcr;
+	u32 pciephy_rcr;
+	u32 hdmi_rcr;
+	u32 disp_rcr;
+	u32 reserved2[2];
+	u32 gpu_rcr;
+	u32 vpu_rcr;
+	u32 pcie2_rcr;
+	u32 mipiphy1_rcr;
+	u32 mipiphy2_rcr;
+	u32 reserved3;
+	u32 sbmr1;
+	u32 srsr;
+	u32 reserved4[2];
+	u32 sisr;
+	u32 simr;
+	u32 sbmr2;
+	u32 gpr1;
+	u32 gpr2;
+	u32 gpr3;
+	u32 gpr4;
+	u32 gpr5;
+	u32 gpr6;
+	u32 gpr7;
+	u32 gpr8;
+	u32 gpr9;
+	u32 gpr10;
+	u32 reserved5[985];
+	u32 ddr1_rcr;
+	u32 ddr2_rcr;
+};
+
+struct gpc_reg {
+	u32 lpcr_bsc;
+	u32 lpcr_ad;
+	u32 lpcr_cpu1;
+	u32 lpcr_cpu2;
+	u32 lpcr_cpu3;
+	u32 slpcr;
+	u32 mst_cpu_mapping;
+	u32 mmdc_cpu_mapping;
+	u32 mlpcr;
+	u32 pgc_ack_sel;
+	u32 pgc_ack_sel_m4;
+	u32 gpc_misc;
+	u32 imr1_core0;
+	u32 imr2_core0;
+	u32 imr3_core0;
+	u32 imr4_core0;
+	u32 imr1_core1;
+	u32 imr2_core1;
+	u32 imr3_core1;
+	u32 imr4_core1;
+	u32 imr1_cpu1;
+	u32 imr2_cpu1;
+	u32 imr3_cpu1;
+	u32 imr4_cpu1;
+	u32 imr1_cpu3;
+	u32 imr2_cpu3;
+	u32 imr3_cpu3;
+	u32 imr4_cpu3;
+	u32 isr1_cpu0;
+	u32 isr2_cpu0;
+	u32 isr3_cpu0;
+	u32 isr4_cpu0;
+	u32 isr1_cpu1;
+	u32 isr2_cpu1;
+	u32 isr3_cpu1;
+	u32 isr4_cpu1;
+	u32 isr1_cpu2;
+	u32 isr2_cpu2;
+	u32 isr3_cpu2;
+	u32 isr4_cpu2;
+	u32 isr1_cpu3;
+	u32 isr2_cpu3;
+	u32 isr3_cpu3;
+	u32 isr4_cpu3;
+	u32 slt0_cfg;
+	u32 slt1_cfg;
+	u32 slt2_cfg;
+	u32 slt3_cfg;
+	u32 slt4_cfg;
+	u32 slt5_cfg;
+	u32 slt6_cfg;
+	u32 slt7_cfg;
+	u32 slt8_cfg;
+	u32 slt9_cfg;
+	u32 slt10_cfg;
+	u32 slt11_cfg;
+	u32 slt12_cfg;
+	u32 slt13_cfg;
+	u32 slt14_cfg;
+	u32 pgc_cpu_0_1_mapping;
+	u32 cpu_pgc_up_trg;
+	u32 mix_pgc_up_trg;
+	u32 pu_pgc_up_trg;
+	u32 cpu_pgc_dn_trg;
+	u32 mix_pgc_dn_trg;
+	u32 pu_pgc_dn_trg;
+	u32 lpcr_bsc2;
+	u32 pgc_cpu_2_3_mapping;
+	u32 lps_cpu0;
+	u32 lps_cpu1;
+	u32 lps_cpu2;
+	u32 lps_cpu3;
+	u32 gpc_gpr;
+	u32 gtor;
+	u32 debug_addr1;
+	u32 debug_addr2;
+	u32 cpu_pgc_up_status1;
+	u32 mix_pgc_up_status0;
+	u32 mix_pgc_up_status1;
+	u32 mix_pgc_up_status2;
+	u32 m4_mix_pgc_up_status0;
+	u32 m4_mix_pgc_up_status1;
+	u32 m4_mix_pgc_up_status2;
+	u32 pu_pgc_up_status0;
+	u32 pu_pgc_up_status1;
+	u32 pu_pgc_up_status2;
+	u32 m4_pu_pgc_up_status0;
+	u32 m4_pu_pgc_up_status1;
+	u32 m4_pu_pgc_up_status2;
+	u32 a53_lp_io_0;
+	u32 a53_lp_io_1;
+	u32 a53_lp_io_2;
+	u32 cpu_pgc_dn_status1;
+	u32 mix_pgc_dn_status0;
+	u32 mix_pgc_dn_status1;
+	u32 mix_pgc_dn_status2;
+	u32 m4_mix_pgc_dn_status0;
+	u32 m4_mix_pgc_dn_status1;
+	u32 m4_mix_pgc_dn_status2;
+	u32 pu_pgc_dn_status0;
+	u32 pu_pgc_dn_status1;
+	u32 pu_pgc_dn_status2;
+	u32 m4_pu_pgc_dn_status0;
+	u32 m4_pu_pgc_dn_status1;
+	u32 m4_pu_pgc_dn_status2;
+	u32 res[3];
+	u32 mix_pdn_flg;
+	u32 pu_pdn_flg;
+	u32 m4_mix_pdn_flg;
+	u32 m4_pu_pdn_flg;
+	u32 imr1_core2;
+	u32 imr2_core2;
+	u32 imr3_core2;
+	u32 imr4_core2;
+	u32 imr1_core3;
+	u32 imr2_core3;
+	u32 imr3_core3;
+	u32 imr4_core3;
+	u32 pgc_ack_sel_pu;
+	u32 pgc_ack_sel_m4_pu;
+	u32 slt15_cfg;
+	u32 slt16_cfg;
+	u32 slt17_cfg;
+	u32 slt18_cfg;
+	u32 slt19_cfg;
+	u32 gpc_pu_pwrhsk;
+	u32 slt0_cfg_pu;
+	u32 slt1_cfg_pu;
+	u32 slt2_cfg_pu;
+	u32 slt3_cfg_pu;
+	u32 slt4_cfg_pu;
+	u32 slt5_cfg_pu;
+	u32 slt6_cfg_pu;
+	u32 slt7_cfg_pu;
+	u32 slt8_cfg_pu;
+	u32 slt9_cfg_pu;
+	u32 slt10_cfg_pu;
+	u32 slt11_cfg_pu;
+	u32 slt12_cfg_pu;
+	u32 slt13_cfg_pu;
+	u32 slt14_cfg_pu;
+	u32 slt15_cfg_pu;
+	u32 slt16_cfg_pu;
+	u32 slt17_cfg_pu;
+	u32 slt18_cfg_pu;
+	u32 slt19_cfg_pu;
+};
+
+#define WDOG_WDT_MASK	BIT(3)
+#define WDOG_WDZST_MASK	BIT(0)
+struct wdog_regs {
+	u16	wcr;	/* Control */
+	u16	wsr;	/* Service */
+	u16	wrsr;	/* Reset Status */
+	u16	wicr;	/* Interrupt Control */
+	u16	wmcr;	/* Miscellaneous Control */
+};
+
+struct bootrom_sw_info {
+	u8 reserved_1;
+	u8 boot_dev_instance;
+	u8 boot_dev_type;
+	u8 reserved_2;
+	u32 core_freq;
+	u32 axi_freq;
+	u32 ddr_freq;
+	u32 tick_freq;
+	u32 reserved_3[3];
+};
+
+#define ROM_SW_INFO_ADDR_B0	0x00000968
+#define ROM_SW_INFO_ADDR_A0	0x000009e8
+
+#define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
+		(struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
+		(struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0
+#endif
+#endif

new file mode 100644
index 0000000000..062bea7299
@@ -0,0 +1,623 @@
+/*
+ * Copyright (C) 2017 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX8MQ_PINS_H__
+#define __ASM_ARCH_MX8MQ_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+		IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0                    = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT    = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO00__XTALOSC_REF_CLK_32K          = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO00__CCM_EXT_CLK1                 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO00__JTAG_FAIL                    = IOMUX_PAD(0x0290, 0x0028, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1                    = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO01__PWM1_OUT                     = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO01__XTALOSC_REF_CLK_24M          = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO01__CCM_EXT_CLK2                 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO01__JTAG_ACTIVE                  = IOMUX_PAD(0x0294, 0x002C, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO02__GPIO1_IO2                    = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B                 = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_ANY               = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO02__JTAG_DE_B                    = IOMUX_PAD(0x0298, 0x0030, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3                    = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO03__USDHC1_VSELECT               = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0             = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO03__XTALOSC_XTAL_OK              = IOMUX_PAD(0x029C, 0x0034, 6, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO03__JTAG_DONE                    = IOMUX_PAD(0x029C, 0x0034, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4                    = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT               = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1             = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO04__XTALOSC_XTAL_OK_1V           = IOMUX_PAD(0x02A0, 0x0038, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5                    = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO05__ARM_PLATFORM_CM4_NMI         = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO05__CCM_PMIC_READY               = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO05__SRC_INT_BOOT                 = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6                    = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO06__ENET_MDC                     = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO06__USDHC1_CD_B                  = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO06__CCM_EXT_CLK3                 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7                    = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO07__ENET_MDIO                    = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO07__USDHC1_WP                    = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO07__CCM_EXT_CLK4                 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8                    = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO08__ENET_1588_EVENT0_IN          = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO08__USDHC2_RESET_B               = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO08__CCM_WAIT                     = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9                    = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO09__ENET_1588_EVENT0_OUT         = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO09__SDMA2_EXT_EVENT0             = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO09__CCM_STOP                     = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10                   = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO10__USB1_OTG_ID                  = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11                   = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO11__USB2_OTG_ID                  = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO11__CCM_PMIC_READY               = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0),
+
+		IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12                   = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO12__USB1_OTG_PWR                 = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO12__SDMA2_EXT_EVENT1             = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT0           = IOMUX_PAD(0x02C0, 0x0058, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13                   = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO13__USB1_OTG_OC                  = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO13__PWM2_OUT                     = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT1           = IOMUX_PAD(0x02C4, 0x005C, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14                   = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO14__USB2_OTG_PWR                 = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO14__PWM3_OUT                     = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO14__CCM_CLKO1                    = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT2           = IOMUX_PAD(0x02C8, 0x0060, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO15__GPIO1_IO15                   = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO15__USB2_OTG_OC                  = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO15__PWM4_OUT                     = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO15__CCM_CLKO2                    = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO15__CSU_CSU_INT_DEB              = IOMUX_PAD(0x02CC, 0x0064, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_MDC__ENET_MDC                       = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_MDC__GPIO1_IO16                     = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_MDIO__ENET_MDIO                     = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0),
+		IMX8MQ_PAD_ENET_MDIO__GPIO1_IO17                    = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_TD3__ENET_RGMII_TD3                 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TD3__GPIO1_IO18                     = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_TD2__ENET_RGMII_TD2                 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TD2__ENET_TX_CLK                    = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TD2__GPIO1_IO19                     = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_TD1__ENET_RGMII_TD1                 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TD1__GPIO1_IO20                     = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_TD0__ENET_RGMII_TD0                 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TD0__GPIO1_IO21                     = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_TX_CTL__ENET_RGMII_TX_CTL           = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TX_CTL__GPIO1_IO22                  = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_TXC__ENET_RGMII_TXC                 = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TXC__ENET_TX_ER                     = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TXC__GPIO1_IO23                     = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL           = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24                  = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC                 = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RXC__ENET_RX_ER                     = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RXC__GPIO1_IO25                     = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0                 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RD0__GPIO1_IO26                     = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1                 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RD1__GPIO1_IO27                     = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2                 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RD2__GPIO1_IO28                     = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3                 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RD3__GPIO1_IO29                     = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_CLK__USDHC1_CLK                      = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_CLK__GPIO2_IO0                       = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_CMD__USDHC1_CMD                      = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_CMD__GPIO2_IO1                       = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0                  = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA0__GPIO2_IO2                     = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1                  = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA1__GPIO2_IO3                     = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2                  = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA2__GPIO2_IO4                     = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3                  = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA3__GPIO2_IO5                     = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4                  = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA4__GPIO2_IO6                     = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5                  = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA5__GPIO2_IO7                     = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6                  = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA6__GPIO2_IO8                     = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7                  = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA7__GPIO2_IO9                     = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_RESET_B__USDHC1_RESET_B              = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10                  = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_STROBE__USDHC1_STROBE                = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_STROBE__GPIO2_IO11                   = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_CD_B__USDHC2_CD_B                    = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12                     = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_CLK__USDHC2_CLK                      = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_CLK__GPIO2_IO13                      = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_CMD__USDHC2_CMD                      = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_CMD__GPIO2_IO14                      = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0                  = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA0__GPIO2_IO15                    = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1                  = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA1__GPIO2_IO16                    = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA1__CCM_WAIT                      = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2                  = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA2__GPIO2_IO17                    = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA2__CCM_STOP                      = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3                  = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA3__GPIO2_IO18                    = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA3__SRC_EARLY_RESET               = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_RESET_B__USDHC2_RESET_B              = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19                  = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_RESET_B__SRC_SYSTEM_RESET            = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_WP__USDHC2_WP                        = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_WP__GPIO2_IO20                       = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE                    = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK                    = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_ALE__GPIO3_IO0                      = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B                = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B                 = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE0_B__GPIO3_IO1                    = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_CE1_B__RAWNAND_CE1_B                = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE1_B__QSPI_A_SS1_B                 = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2                    = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_CE2_B__RAWNAND_CE2_B                = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE2_B__QSPI_B_SS0_B                 = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE2_B__GPIO3_IO3                    = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_CE3_B__RAWNAND_CE3_B                = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE3_B__QSPI_B_SS1_B                 = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4                    = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE                    = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CLE__QSPI_B_SCLK                    = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CLE__GPIO3_IO5                      = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00              = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0                = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA00__GPIO3_IO6                   = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01              = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1                = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7                   = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02              = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2                = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8                   = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03              = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3                = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9                   = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04              = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA04__QSPI_B_DATA0                = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10                  = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05              = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA05__QSPI_B_DATA1                = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11                  = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06              = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA06__QSPI_B_DATA2                = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12                  = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07              = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA07__QSPI_B_DATA3                = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13                  = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DQS__RAWNAND_DQS                    = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DQS__QSPI_A_DQS                     = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DQS__GPIO3_IO14                     = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B                  = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_RE_B__QSPI_B_DQS                    = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15                    = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B            = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16                 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B                  = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17                    = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B                  = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18                    = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_RXFS__SAI5_RX_SYNC                  = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0),
+		IMX8MQ_PAD_SAI5_RXFS__SAI1_TX_DATA0                 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19                    = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_RXC__SAI5_RX_BCLK                   = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0),
+		IMX8MQ_PAD_SAI5_RXC__SAI1_TX_DATA1                  = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20                     = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_RXD0__SAI5_RX_DATA0                 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD0__SAI1_TX_DATA2                 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21                    = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_RXD1__SAI5_RX_DATA1                 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_DATA3                 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_SYNC                  = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD1__SAI5_TX_SYNC                  = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22                    = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_RXD2__SAI5_RX_DATA2                 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_DATA4                 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_SYNC                  = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0),
+		IMX8MQ_PAD_SAI5_RXD2__SAI5_TX_BCLK                  = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23                    = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_RXD3__SAI5_RX_DATA3                 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_DATA5                 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_SYNC                  = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0),
+		IMX8MQ_PAD_SAI5_RXD3__SAI5_TX_DATA0                 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24                    = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_MCLK__SAI5_MCLK                     = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0),
+		IMX8MQ_PAD_SAI5_MCLK__SAI1_TX_BCLK                  = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0),
+		IMX8MQ_PAD_SAI5_MCLK__SAI4_MCLK                     = IOMUX_PAD(0x03C0, 0x0158, 2, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25                    = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_MCLK__SRC_TESTER_ACK                = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXFS__SAI1_RX_SYNC                  = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0),
+		IMX8MQ_PAD_SAI1_RXFS__SAI5_RX_SYNC                  = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0),
+		IMX8MQ_PAD_SAI1_RXFS__ARM_PLATFORM_TRACE_CLK        = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXFS__GPIO4_IO0                     = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXC__SAI1_RX_BCLK                   = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXC__SAI5_RX_BCLK                   = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0),
+		IMX8MQ_PAD_SAI1_RXC__ARM_PLATFORM_TRACE_CTL         = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXC__GPIO4_IO1                      = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD0__SAI1_RX_DATA0                 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD0__SAI5_RX_DATA0                 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0),
+		IMX8MQ_PAD_SAI1_RXD0__ARM_PLATFORM_TRACE0           = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD0__GPIO4_IO2                     = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD0__SRC_BOOT_CFG0                 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD1__SAI1_RX_DATA1                 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD1__SAI5_RX_DATA1                 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0),
+		IMX8MQ_PAD_SAI1_RXD1__ARM_PLATFORM_TRACE1           = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD1__GPIO4_IO3                     = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD1__SRC_BOOT_CFG1                 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD2__SAI1_RX_DATA2                 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD2__SAI5_RX_DATA2                 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0),
+		IMX8MQ_PAD_SAI1_RXD2__ARM_PLATFORM_TRACE2           = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD2__GPIO4_IO4                     = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD2__SRC_BOOT_CFG2                 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD3__SAI1_RX_DATA3                 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x04E0, 1, 0),
+		IMX8MQ_PAD_SAI1_RXD3__SAI5_RX_DATA3                 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD3__ARM_PLATFORM_TRACE3           = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD3__GPIO4_IO5                     = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD3__SRC_BOOT_CFG3                 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD4__SAI1_RX_DATA4                 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD4__SAI6_TX_BCLK                  = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD4__SAI6_RX_BCLK                  = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD4__ARM_PLATFORM_TRACE4           = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD4__GPIO4_IO6                     = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD4__SRC_BOOT_CFG4                 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_DATA5                 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD5__SAI6_TX_DATA0                 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD5__SAI6_RX_DATA0                 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_SYNC                  = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0),
+		IMX8MQ_PAD_SAI1_RXD5__ARM_PLATFORM_TRACE5           = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD5__GPIO4_IO7                     = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD5__SRC_BOOT_CFG5                 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD6__SAI1_RX_DATA6                 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD6__SAI6_TX_SYNC                  = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD6__SAI6_RX_SYNC                  = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD6__ARM_PLATFORM_TRACE6           = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD6__GPIO4_IO8                     = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD6__SRC_BOOT_CFG6                 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD7__SAI1_RX_DATA7                 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD7__SAI6_MCLK                     = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_SYNC                  = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0),
+		IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_DATA4                 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD7__ARM_PLATFORM_TRACE7           = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD7__GPIO4_IO9                     = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD7__SRC_BOOT_CFG7                 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXFS__SAI1_TX_SYNC                  = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0),
+		IMX8MQ_PAD_SAI1_TXFS__SAI5_TX_SYNC                  = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0),
+		IMX8MQ_PAD_SAI1_TXFS__ARM_PLATFORM_EVENTO           = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10                    = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXC__SAI1_TX_BCLK                   = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0),
+		IMX8MQ_PAD_SAI1_TXC__SAI5_TX_BCLK                   = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0),
+		IMX8MQ_PAD_SAI1_TXC__ARM_PLATFORM_EVENTI            = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11                     = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD0__SAI1_TX_DATA0                 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD0__SAI5_TX_DATA0                 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD0__ARM_PLATFORM_TRACE8           = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD0__GPIO4_IO12                    = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD0__SRC_BOOT_CFG8                 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD1__SAI1_TX_DATA1                 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD1__SAI5_TX_DATA1                 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD1__ARM_PLATFORM_TRACE9           = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD1__GPIO4_IO13                    = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD1__SRC_BOOT_CFG9                 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD2__SAI1_TX_DATA2                 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD2__SAI5_TX_DATA2                 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD2__ARM_PLATFORM_TRACE10          = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD2__GPIO4_IO14                    = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD2__SRC_BOOT_CFG10                = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD3__SAI1_TX_DATA3                 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD3__SAI5_TX_DATA3                 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD3__ARM_PLATFORM_TRACE11          = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD3__GPIO4_IO15                    = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD3__SRC_BOOT_CFG11                = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD4__SAI1_TX_DATA4                 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD4__SAI6_RX_BCLK                  = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0),
+		IMX8MQ_PAD_SAI1_TXD4__SAI6_TX_BCLK                  = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0),
+		IMX8MQ_PAD_SAI1_TXD4__ARM_PLATFORM_TRACE12          = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD4__GPIO4_IO16                    = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD4__SRC_BOOT_CFG12                = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD5__SAI1_TX_DATA5                 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD5__SAI6_RX_DATA0                 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0),
+		IMX8MQ_PAD_SAI1_TXD5__SAI6_TX_DATA0                 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD5__ARM_PLATFORM_TRACE13          = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD5__GPIO4_IO17                    = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD5__SRC_BOOT_CFG13                = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD6__SAI1_TX_DATA6                 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD6__SAI6_RX_SYNC                  = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0),
+		IMX8MQ_PAD_SAI1_TXD6__SAI6_TX_SYNC                  = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0),
+		IMX8MQ_PAD_SAI1_TXD6__ARM_PLATFORM_TRACE14          = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD6__GPIO4_IO18                    = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD6__SRC_BOOT_CFG14                = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD7__SAI1_TX_DATA7                 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD7__SAI6_MCLK                     = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0),
+		IMX8MQ_PAD_SAI1_TXD7__ARM_PLATFORM_TRACE15          = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD7__GPIO4_IO19                    = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD7__SRC_BOOT_CFG15                = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_MCLK__SAI1_MCLK                     = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_MCLK__SAI5_MCLK                     = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0),
+		IMX8MQ_PAD_SAI1_MCLK__SAI1_TX_BCLK                  = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0),
+		IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20                    = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_RXFS__SAI2_RX_SYNC                  = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_RXFS__SAI5_TX_SYNC                  = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0),
+		IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21                    = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_RXC__SAI2_RX_BCLK                   = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_RXC__SAI5_TX_BCLK                   = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0),
+		IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22                     = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_RXD0__SAI2_RX_DATA0                 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_RXD0__SAI5_TX_DATA0                 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_RXD0__GPIO4_IO23                    = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_TXFS__SAI2_TX_SYNC                  = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_TXFS__SAI5_TX_DATA1                 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_TXFS__GPIO4_IO24                    = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_TXC__SAI2_TX_BCLK                   = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_TXC__SAI5_TX_DATA2                  = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_TXC__GPIO4_IO25                     = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_TXD0__SAI2_TX_DATA0                 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_TXD0__SAI5_TX_DATA3                 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_TXD0__GPIO4_IO26                    = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_MCLK__SAI2_MCLK                     = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_MCLK__SAI5_MCLK                     = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0),
+		IMX8MQ_PAD_SAI2_MCLK__GPIO4_IO27                    = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_RXFS__SAI3_RX_SYNC                  = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_RXFS__GPT1_CAPTURE1                 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_RXFS__SAI5_RX_SYNC                  = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0),
+		IMX8MQ_PAD_SAI3_RXFS__GPIO4_IO28                    = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_RXC__SAI3_RX_BCLK                   = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_RXC__GPT1_CAPTURE2                  = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_RXC__SAI5_RX_BCLK                   = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0),
+		IMX8MQ_PAD_SAI3_RXC__GPIO4_IO29                     = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_RXD__SAI3_RX_DATA0                  = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_RXD__GPT1_COMPARE1                  = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_RXD__SAI5_RX_DATA0                  = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0),
+		IMX8MQ_PAD_SAI3_RXD__GPIO4_IO30                     = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_TXFS__SAI3_TX_SYNC                  = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_TXFS__GPT1_CLK                      = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_TXFS__SAI5_RX_DATA1                 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0),
+		IMX8MQ_PAD_SAI3_TXFS__GPIO4_IO31                    = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_TXC__SAI3_TX_BCLK                   = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_TXC__GPT1_COMPARE2                  = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_TXC__SAI5_RX_DATA2                  = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0),
+		IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0                      = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_TXD__SAI3_TX_DATA0                  = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_TXD__GPT1_COMPARE3                  = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_TXD__SAI5_RX_DATA3                  = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0),
+		IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1                      = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_MCLK__SAI3_MCLK                     = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_MCLK__PWM4_OUT                      = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_MCLK__SAI5_MCLK                     = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0),
+		IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2                     = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SPDIF_TX__SPDIF1_OUT                     = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SPDIF_TX__PWM3_OUT                       = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3                      = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SPDIF_RX__SPDIF1_IN                      = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SPDIF_RX__PWM2_OUT                       = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4                      = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SPDIF_EXT_CLK__SPDIF1_EXT_CLK            = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SPDIF_EXT_CLK__PWM1_OUT                  = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SPDIF_EXT_CLK__GPIO5_IO5                 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK                 = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI1_SCLK__UART3_RX                    = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0),
+		IMX8MQ_PAD_ECSPI1_SCLK__GPIO5_IO6                   = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI                 = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI1_MOSI__UART3_TX                    = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0),
+		IMX8MQ_PAD_ECSPI1_MOSI__GPIO5_IO7                   = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO                 = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B                 = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0),
+		IMX8MQ_PAD_ECSPI1_MISO__GPIO5_IO8                   = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI1_SS0__ECSPI1_SS0                   = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI1_SS0__UART3_RTS_B                  = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0),
+		IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9                    = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI2_SCLK__ECSPI2_SCLK                 = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX                    = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0),
+		IMX8MQ_PAD_ECSPI2_SCLK__GPIO5_IO10                  = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI2_MOSI__ECSPI2_MOSI                 = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX                    = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0),
+		IMX8MQ_PAD_ECSPI2_MOSI__GPIO5_IO11                  = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI2_MISO__ECSPI2_MISO                 = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B                 = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0),
+		IMX8MQ_PAD_ECSPI2_MISO__GPIO5_IO12                  = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI2_SS0__ECSPI2_SS0                   = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B                  = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0),
+		IMX8MQ_PAD_ECSPI2_SS0__GPIO5_IO13                   = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C1_SCL__I2C1_SCL                       = IOMUX_PAD(0x047C, 0x0214, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C1_SCL__ENET_MDC                       = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14                     = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C1_SDA__I2C1_SDA                       = IOMUX_PAD(0x0480, 0x0218, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C1_SDA__ENET_MDIO                      = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0),
+		IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15                     = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C2_SCL__I2C2_SCL                       = IOMUX_PAD(0x0484, 0x021C, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C2_SCL__ENET_1588_EVENT1_IN            = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16                     = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C2_SDA__I2C2_SDA                       = IOMUX_PAD(0x0488, 0x0220, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C2_SDA__ENET_1588_EVENT1_OUT           = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17                     = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C3_SCL__I2C3_SCL                       = IOMUX_PAD(0x048C, 0x0224, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C3_SCL__PWM4_OUT                       = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C3_SCL__GPT2_CLK                       = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18                     = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C3_SDA__I2C3_SDA                       = IOMUX_PAD(0x0490, 0x0228, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C3_SDA__PWM3_OUT                       = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C3_SDA__GPT3_CLK                       = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19                     = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C4_SCL__I2C4_SCL                       = IOMUX_PAD(0x0494, 0x022C, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C4_SCL__PWM2_OUT                       = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C4_SCL__PCIE1_CLKREQ_B                 = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0),
+		IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20                     = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C4_SDA__I2C4_SDA                       = IOMUX_PAD(0x0498, 0x0230, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C4_SDA__PWM1_OUT                       = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C4_SDA__PCIE2_CLKREQ_B                 = IOMUX_PAD(0x0498, 0x0230, 2, 0x0528, 0, 0),
+		IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21                     = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART1_RXD__UART1_RX                      = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0),
+		IMX8MQ_PAD_UART1_RXD__ECSPI3_SCLK                   = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART1_RXD__GPIO5_IO22                    = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART1_TXD__UART1_TX                      = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART1_TXD__ECSPI3_MOSI                   = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART1_TXD__GPIO5_IO23                    = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART2_RXD__UART2_RX                      = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0),
+		IMX8MQ_PAD_UART2_RXD__ECSPI3_MISO                   = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART2_RXD__GPIO5_IO24                    = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART2_TXD__UART2_TX                      = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART2_TXD__ECSPI3_SS0                    = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART2_TXD__GPIO5_IO25                    = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART3_RXD__UART3_RX                      = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0),
+		IMX8MQ_PAD_UART3_RXD__UART1_CTS_B                   = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0),
+		IMX8MQ_PAD_UART3_RXD__GPIO5_IO26                    = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART3_TXD__UART3_TX                      = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART3_TXD__UART1_RTS_B                   = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0),
+		IMX8MQ_PAD_UART3_TXD__GPIO5_IO27                    = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART4_RXD__UART4_RX                      = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0),
+		IMX8MQ_PAD_UART4_RXD__UART2_CTS_B                   = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0),
+		IMX8MQ_PAD_UART4_RXD__PCIE1_CLKREQ_B                = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0),
+		IMX8MQ_PAD_UART4_RXD__GPIO5_IO28                    = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART4_TXD__UART4_TX                      = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART4_TXD__UART2_RTS_B                   = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0),
+		IMX8MQ_PAD_UART4_TXD__PCIE2_CLKREQ_B                = IOMUX_PAD(0x04B8, 0x0250, 2, 0x0528, 1, 0),
+		IMX8MQ_PAD_UART4_TXD__GPIO5_IO29                    = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0),
+};
+#endif

index 3dcd435d0d..b08fcb8c09 100644
@@ -21,4 +21,8 @@ static inline void ndelay(unsigned long nsec)
 	udelay(DIV_ROUND_UP(nsec, 1000));
 }
 
+int wait_mask_set_timeout(void *addr, u32 mask, u32 timeout);
+
+int wait_mask_clr_timeout(void *addr, u32 mask, u32 timeout);
+
 #endif /* defined(_LINUX_DELAY_H) */

index aed1a091f2..9701287629 100644
@@ -171,3 +171,33 @@ void udelay(unsigned long usec)
 		usec -= kv;
 	} while(usec);
 }
+
+int wait_mask_set_timeout(void *addr, u32 mask, u32 timeout)
+{
+	unsigned long long end_tick;
+	u32 val;
+
+	end_tick = usec_to_tick(timeout) + get_ticks();
+	do {
+		val = readl(addr);
+		if ((val & mask) == mask)
+			return 0;
+	} while (end_tick > get_ticks());
+
+	return -ETIMEDOUT;
+}
+
+int wait_mask_clr_timeout(void *addr, u32 mask, u32 timeout)
+{
+	unsigned long long end_tick;
+	u32 val;
+
+	end_tick = usec_to_tick(timeout) + get_ticks();
+	do {
+		val = readl(addr);
+		if (!(val & mask))
+			return 0;
+	} while (end_tick > get_ticks());
+
+	return -ETIMEDOUT;
+}

new file mode 100644
index 0000000000..555512b453
@@ -0,0 +1,657 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_IMX8M_CLOCK_H
+#define _ASM_ARCH_IMX8M_CLOCK_H
+
+#include <linux/bitops.h>
+
+enum pll_clocks {
+	ANATOP_ARM_PLL,
+	ANATOP_GPU_PLL,
+	ANATOP_SYSTEM_PLL1,
+	ANATOP_SYSTEM_PLL2,
+	ANATOP_SYSTEM_PLL3,
+	ANATOP_AUDIO_PLL1,
+	ANATOP_AUDIO_PLL2,
+	ANATOP_VIDEO_PLL1,
+	ANATOP_VIDEO_PLL2,
+	ANATOP_DRAM_PLL,
+};
+
+enum clk_slice_type {
+	CORE_CLOCK_SLICE,
+	BUS_CLOCK_SLICE,
+	IP_CLOCK_SLICE,
+	AHB_CLOCK_SLICE,
+	IPG_CLOCK_SLICE,
+	CORE_SEL_CLOCK_SLICE,
+	DRAM_SEL_CLOCK_SLICE,
+};
+
+enum clk_root_index {
+	MXC_ARM_CLK			= 0,
+	ARM_A53_CLK_ROOT		= 0,
+	ARM_M4_CLK_ROOT			= 1,
+	VPU_A53_CLK_ROOT		= 2,
+	GPU_CORE_CLK_ROOT		= 3,
+	GPU_SHADER_CLK_ROOT		= 4,
+	MAIN_AXI_CLK_ROOT		= 16,
+	ENET_AXI_CLK_ROOT		= 17,
+	NAND_USDHC_BUS_CLK_ROOT		= 18,
+	VPU_BUS_CLK_ROOT		= 19,
+	DISPLAY_AXI_CLK_ROOT		= 20,
+	DISPLAY_APB_CLK_ROOT		= 21,
+	DISPLAY_RTRM_CLK_ROOT		= 22,
+	USB_BUS_CLK_ROOT		= 23,
+	GPU_AXI_CLK_ROOT		= 24,
+	GPU_AHB_CLK_ROOT		= 25,
+	NOC_CLK_ROOT			= 26,
+	NOC_APB_CLK_ROOT		= 27,
+	AHB_CLK_ROOT			= 32,
+	IPG_CLK_ROOT			= 33,
+	MXC_IPG_CLK			= 33,
+	AUDIO_AHB_CLK_ROOT		= 34,
+	MIPI_DSI_ESC_RX_CLK_ROOT	= 36,
+	DRAM_SEL_CFG			= 48,
+	CORE_SEL_CFG			= 49,
+	DRAM_ALT_CLK_ROOT		= 64,
+	DRAM_APB_CLK_ROOT		= 65,
+	VPU_G1_CLK_ROOT			= 66,
+	VPU_G2_CLK_ROOT			= 67,
+	DISPLAY_DTRC_CLK_ROOT		= 68,
+	DISPLAY_DC8000_CLK_ROOT		= 69,
+	PCIE1_CTRL_CLK_ROOT		= 70,
+	PCIE1_PHY_CLK_ROOT		= 71,
+	PCIE1_AUX_CLK_ROOT		= 72,
+	DC_PIXEL_CLK_ROOT		= 73,
+	LCDIF_PIXEL_CLK_ROOT		= 74,
+	SAI1_CLK_ROOT			= 75,
+	SAI2_CLK_ROOT			= 76,
+	SAI3_CLK_ROOT			= 77,
+	SAI4_CLK_ROOT			= 78,
+	SAI5_CLK_ROOT			= 79,
+	SAI6_CLK_ROOT			= 80,
+	SPDIF1_CLK_ROOT			= 81,
+	SPDIF2_CLK_ROOT			= 82,
+	ENET_REF_CLK_ROOT		= 83,
+	ENET_TIMER_CLK_ROOT		= 84,
+	ENET_PHY_REF_CLK_ROOT		= 85,
+	NAND_CLK_ROOT			= 86,
+	QSPI_CLK_ROOT			= 87,
+	MXC_ESDHC_CLK			= 88,
+	USDHC1_CLK_ROOT			= 88,
+	MXC_ESDHC2_CLK			= 89,
+	USDHC2_CLK_ROOT			= 89,
+	I2C1_CLK_ROOT			= 90,
+	MXC_I2C_CLK			= 90,
+	I2C2_CLK_ROOT			= 91,
+	I2C3_CLK_ROOT			= 92,
+	I2C4_CLK_ROOT			= 93,
+	UART1_CLK_ROOT			= 94,
+	UART2_CLK_ROOT			= 95,
+	UART3_CLK_ROOT			= 96,
+	UART4_CLK_ROOT			= 97,
+	USB_CORE_REF_CLK_ROOT		= 98,
+	USB_PHY_REF_CLK_ROOT		= 99,
+	GIC_CLK_ROOT			= 100,
+	ECSPI1_CLK_ROOT			= 101,
+	ECSPI2_CLK_ROOT			= 102,
+	PWM1_CLK_ROOT			= 103,
+	PWM2_CLK_ROOT			= 104,
+	PWM3_CLK_ROOT			= 105,
+	PWM4_CLK_ROOT			= 106,
+	GPT1_CLK_ROOT			= 107,
+	GPT2_CLK_ROOT			= 108,
+	GPT3_CLK_ROOT			= 109,
+	GPT4_CLK_ROOT			= 110,
+	GPT5_CLK_ROOT			= 111,
+	GPT6_CLK_ROOT			= 112,
+	TRACE_CLK_ROOT			= 113,
+	WDOG_CLK_ROOT			= 114,
+	WRCLK_CLK_ROOT			= 115,
+	IPP_DO_CLKO1			= 116,
+	IPP_DO_CLKO2			= 117,
+	MIPI_DSI_CORE_CLK_ROOT		= 118,
+	MIPI_DSI_PHY_REF_CLK_ROOT	= 119,
+	MIPI_DSI_DBI_CLK_ROOT		= 120,
+	OLD_MIPI_DSI_ESC_CLK_ROOT	= 121,
+	MIPI_CSI1_CORE_CLK_ROOT		= 122,
+	MIPI_CSI1_PHY_REF_CLK_ROOT	= 123,
+	MIPI_CSI1_ESC_CLK_ROOT		= 124,
+	MIPI_CSI2_CORE_CLK_ROOT		= 125,
+	MIPI_CSI2_PHY_REF_CLK_ROOT	= 126,
+	MIPI_CSI2_ESC_CLK_ROOT		= 127,
+	PCIE2_CTRL_CLK_ROOT		= 128,
+	PCIE2_PHY_CLK_ROOT		= 129,
+	PCIE2_AUX_CLK_ROOT		= 130,
+	ECSPI3_CLK_ROOT			= 131,
+	OLD_MIPI_DSI_ESC_RX_ROOT	= 132,
+	DISPLAY_HDMI_CLK_ROOT		= 133,
+	CLK_ROOT_MAX,
+};
+
+enum clk_root_src {
+	OSC_25M_CLK,
+	ARM_PLL_CLK,
+	DRAM_PLL1_CLK,
+	VIDEO_PLL2_CLK,
+	VPU_PLL_CLK,
+	GPU_PLL_CLK,
+	SYSTEM_PLL1_800M_CLK,
+	SYSTEM_PLL1_400M_CLK,
+	SYSTEM_PLL1_266M_CLK,
+	SYSTEM_PLL1_200M_CLK,
+	SYSTEM_PLL1_160M_CLK,
+	SYSTEM_PLL1_133M_CLK,
+	SYSTEM_PLL1_100M_CLK,
+	SYSTEM_PLL1_80M_CLK,
+	SYSTEM_PLL1_40M_CLK,
+	SYSTEM_PLL2_1000M_CLK,
+	SYSTEM_PLL2_500M_CLK,
+	SYSTEM_PLL2_333M_CLK,
+	SYSTEM_PLL2_250M_CLK,
+	SYSTEM_PLL2_200M_CLK,
+	SYSTEM_PLL2_166M_CLK,
+	SYSTEM_PLL2_125M_CLK,
+	SYSTEM_PLL2_100M_CLK,
+	SYSTEM_PLL2_50M_CLK,
+	SYSTEM_PLL3_CLK,
+	AUDIO_PLL1_CLK,
+	AUDIO_PLL2_CLK,
+	VIDEO_PLL_CLK,
+	OSC_32K_CLK,
+	EXT_CLK_1,
+	EXT_CLK_2,
+	EXT_CLK_3,
+	EXT_CLK_4,
+	OSC_27M_CLK,
+};
+
+/* CCGR index */
+enum clk_ccgr_index {
+	CCGR_DVFS = 0,
+	CCGR_ANAMIX = 1,
+	CCGR_CPU = 2,
+	CCGR_CSU = 4,
+	CCGR_DRAM1 = 5,
+	CCGR_DRAM2_OBSOLETE = 6,
+	CCGR_ECSPI1 = 7,
+	CCGR_ECSPI2 = 8,
+	CCGR_ECSPI3 = 9,
+	CCGR_ENET1 = 10,
+	CCGR_GPIO1 = 11,
+	CCGR_GPIO2 = 12,
+	CCGR_GPIO3 = 13,
+	CCGR_GPIO4 = 14,
+	CCGR_GPIO5 = 15,
+	CCGR_GPT1 = 16,
+	CCGR_GPT2 = 17,
+	CCGR_GPT3 = 18,
+	CCGR_GPT4 = 19,
+	CCGR_GPT5 = 20,
+	CCGR_GPT6 = 21,
+	CCGR_HS = 22,
+	CCGR_I2C1 = 23,
+	CCGR_I2C2 = 24,
+	CCGR_I2C3 = 25,
+	CCGR_I2C4 = 26,
+	CCGR_IOMUX = 27,
+	CCGR_IOMUX1 = 28,
+	CCGR_IOMUX2 = 29,
+	CCGR_IOMUX3 = 30,
+	CCGR_IOMUX4 = 31,
+	CCGR_M4 = 32,
+	CCGR_MU = 33,
+	CCGR_OCOTP = 34,
+	CCGR_OCRAM = 35,
+	CCGR_OCRAM_S = 36,
+	CCGR_PCIE = 37,
+	CCGR_PERFMON1 = 38,
+	CCGR_PERFMON2 = 39,
+	CCGR_PWM1 = 40,
+	CCGR_PWM2 = 41,
+	CCGR_PWM3 = 42,
+	CCGR_PWM4 = 43,
+	CCGR_QOS = 44,
+	CCGR_DISMIX = 45,
+	CCGR_MEGAMIX = 46,
+	CCGR_QSPI = 47,
+	CCGR_RAWNAND = 48,
+	CCGR_RDC = 49,
+	CCGR_ROM = 50,
+	CCGR_SAI1 = 51,
+	CCGR_SAI2 = 52,
+	CCGR_SAI3 = 53,
+	CCGR_SAI4 = 54,
+	CCGR_SAI5 = 55,
+	CCGR_SAI6 = 56,
+	CCGR_SCTR = 57,
+	CCGR_SDMA1 = 58,
+	CCGR_SDMA2 = 59,
+	CCGR_SEC_DEBUG = 60,
+	CCGR_SEMA1 = 61,
+	CCGR_SEMA2 = 62,
+	CCGR_SIM_DISPLAY = 63,
+	CCGR_SIM_ENET = 64,
+	CCGR_SIM_M = 65,
+	CCGR_SIM_MAIN = 66,
+	CCGR_SIM_S = 67,
+	CCGR_SIM_WAKEUP = 68,
+	CCGR_SIM_USB = 69,
+	CCGR_SIM_VPU = 70,
+	CCGR_SNVS = 71,
+	CCGR_TRACE = 72,
+	CCGR_UART1 = 73,
+	CCGR_UART2 = 74,
+	CCGR_UART3 = 75,
+	CCGR_UART4 = 76,
+	CCGR_USB_CTRL1 = 77,
+	CCGR_USB_CTRL2 = 78,
+	CCGR_USB_PHY1 = 79,
+	CCGR_USB_PHY2 = 80,
+	CCGR_USDHC1 = 81,
+	CCGR_USDHC2 = 82,
+	CCGR_WDOG1 = 83,
+	CCGR_WDOG2 = 84,
+	CCGR_WDOG3 = 85,
+	CCGR_VA53 = 86,
+	CCGR_GPU = 87,
+	CCGR_HEVC = 88,
+	CCGR_AVC = 89,
+	CCGR_VP9 = 90,
+	CCGR_HEVC_INTER = 91,
+	CCGR_GIC = 92,
+	CCGR_DISPLAY = 93,
+	CCGR_HDMI = 94,
+	CCGR_HDMI_PHY = 95,
+	CCGR_XTAL = 96,
+	CCGR_PLL = 97,
+	CCGR_TSENSOR = 98,
+	CCGR_VPU_DEC = 99,
+	CCGR_PCIE2 = 100,
+	CCGR_MIPI_CSI1 = 101,
+	CCGR_MIPI_CSI2 = 102,
+	CCGR_MAX,
+};
+
+/* src index */
+enum clk_src_index {
+	CLK_SRC_CKIL_SYNC_REQ = 0,
+	CLK_SRC_ARM_PLL_EN = 1,
+	CLK_SRC_GPU_PLL_EN = 2,
+	CLK_SRC_VPU_PLL_EN = 3,
+	CLK_SRC_DRAM_PLL_EN = 4,
+	CLK_SRC_SYSTEM_PLL1_EN = 5,
+	CLK_SRC_SYSTEM_PLL2_EN = 6,
+	CLK_SRC_SYSTEM_PLL3_EN = 7,
+	CLK_SRC_AUDIO_PLL1_EN = 8,
+	CLK_SRC_AUDIO_PLL2_EN = 9,
+	CLK_SRC_VIDEO_PLL1_EN = 10,
+	CLK_SRC_VIDEO_PLL2_EN = 11,
+	CLK_SRC_ARM_PLL = 12,
+	CLK_SRC_GPU_PLL = 13,
+	CLK_SRC_VPU_PLL = 14,
+	CLK_SRC_DRAM_PLL = 15,
+	CLK_SRC_SYSTEM_PLL1_800M = 16,
+	CLK_SRC_SYSTEM_PLL1_400M = 17,
+	CLK_SRC_SYSTEM_PLL1_266M = 18,
+	CLK_SRC_SYSTEM_PLL1_200M = 19,
+	CLK_SRC_SYSTEM_PLL1_160M = 20,
+	CLK_SRC_SYSTEM_PLL1_133M = 21,
+	CLK_SRC_SYSTEM_PLL1_100M = 22,
+	CLK_SRC_SYSTEM_PLL1_80M = 23,
+	CLK_SRC_SYSTEM_PLL1_40M = 24,
+	CLK_SRC_SYSTEM_PLL2_1000M = 25,
+	CLK_SRC_SYSTEM_PLL2_500M = 26,
+	CLK_SRC_SYSTEM_PLL2_333M = 27,
+	CLK_SRC_SYSTEM_PLL2_250M = 28,
+	CLK_SRC_SYSTEM_PLL2_200M = 29,
+	CLK_SRC_SYSTEM_PLL2_166M = 30,
+	CLK_SRC_SYSTEM_PLL2_125M = 31,
+	CLK_SRC_SYSTEM_PLL2_100M = 32,
+	CLK_SRC_SYSTEM_PLL2_50M = 33,
+	CLK_SRC_SYSTEM_PLL3 = 34,
+	CLK_SRC_AUDIO_PLL1 = 35,
+	CLK_SRC_AUDIO_PLL2 = 36,
+	CLK_SRC_VIDEO_PLL1 = 37,
+	CLK_SRC_VIDEO_PLL2 = 38,
+	CLK_SRC_OSC_25M = 39,
+	CLK_SRC_OSC_27M = 40,
+};
+
+enum root_pre_div {
+	CLK_ROOT_PRE_DIV1 = 0,
+	CLK_ROOT_PRE_DIV2,
+	CLK_ROOT_PRE_DIV3,
+	CLK_ROOT_PRE_DIV4,
+	CLK_ROOT_PRE_DIV5,
+	CLK_ROOT_PRE_DIV6,
+	CLK_ROOT_PRE_DIV7,
+	CLK_ROOT_PRE_DIV8,
+};
+
+enum root_post_div {
+	CLK_ROOT_POST_DIV1 = 0,
+	CLK_ROOT_POST_DIV2,
+	CLK_ROOT_POST_DIV3,
+	CLK_ROOT_POST_DIV4,
+	CLK_ROOT_POST_DIV5,
+	CLK_ROOT_POST_DIV6,
+	CLK_ROOT_POST_DIV7,
+	CLK_ROOT_POST_DIV8,
+	CLK_ROOT_POST_DIV9,
+	CLK_ROOT_POST_DIV10,
+	CLK_ROOT_POST_DIV11,
+	CLK_ROOT_POST_DIV12,
+	CLK_ROOT_POST_DIV13,
+	CLK_ROOT_POST_DIV14,
+	CLK_ROOT_POST_DIV15,
+	CLK_ROOT_POST_DIV16,
+	CLK_ROOT_POST_DIV17,
+	CLK_ROOT_POST_DIV18,
+	CLK_ROOT_POST_DIV19,
+	CLK_ROOT_POST_DIV20,
+	CLK_ROOT_POST_DIV21,
+	CLK_ROOT_POST_DIV22,
+	CLK_ROOT_POST_DIV23,
+	CLK_ROOT_POST_DIV24,
+	CLK_ROOT_POST_DIV25,
+	CLK_ROOT_POST_DIV26,
+	CLK_ROOT_POST_DIV27,
+	CLK_ROOT_POST_DIV28,
+	CLK_ROOT_POST_DIV29,
+	CLK_ROOT_POST_DIV30,
+	CLK_ROOT_POST_DIV31,
+	CLK_ROOT_POST_DIV32,
+	CLK_ROOT_POST_DIV33,
+	CLK_ROOT_POST_DIV34,
+	CLK_ROOT_POST_DIV35,
+	CLK_ROOT_POST_DIV36,
+	CLK_ROOT_POST_DIV37,
+	CLK_ROOT_POST_DIV38,
+	CLK_ROOT_POST_DIV39,
+	CLK_ROOT_POST_DIV40,
+	CLK_ROOT_POST_DIV41,
+	CLK_ROOT_POST_DIV42,
+	CLK_ROOT_POST_DIV43,
+	CLK_ROOT_POST_DIV44,
+	CLK_ROOT_POST_DIV45,
+	CLK_ROOT_POST_DIV46,
+	CLK_ROOT_POST_DIV47,
+	CLK_ROOT_POST_DIV48,
+	CLK_ROOT_POST_DIV49,
+	CLK_ROOT_POST_DIV50,
+	CLK_ROOT_POST_DIV51,
+	CLK_ROOT_POST_DIV52,
+	CLK_ROOT_POST_DIV53,
+	CLK_ROOT_POST_DIV54,
+	CLK_ROOT_POST_DIV55,
+	CLK_ROOT_POST_DIV56,
+	CLK_ROOT_POST_DIV57,
+	CLK_ROOT_POST_DIV58,
+	CLK_ROOT_POST_DIV59,
+	CLK_ROOT_POST_DIV60,
+	CLK_ROOT_POST_DIV61,
+	CLK_ROOT_POST_DIV62,
+	CLK_ROOT_POST_DIV63,
+	CLK_ROOT_POST_DIV64,
+};
+
+struct clk_root_map {
+	enum clk_root_index entry;
+	enum clk_slice_type slice_type;
+	u32 slice_index;
+	u8 src_mux[8];
+};
+
+struct ccm_ccgr {
+	u32 ccgr;
+	u32 ccgr_set;
+	u32 ccgr_clr;
+	u32 ccgr_tog;
+};
+
+struct ccm_root {
+	u32 target_root;
+	u32 target_root_set;
+	u32 target_root_clr;
+	u32 target_root_tog;
+	u32 misc;
+	u32 misc_set;
+	u32 misc_clr;
+	u32 misc_tog;
+	u32 nm_post;
+	u32 nm_post_root_set;
+	u32 nm_post_root_clr;
+	u32 nm_post_root_tog;
+	u32 nm_pre;
+	u32 nm_pre_root_set;
+	u32 nm_pre_root_clr;
+	u32 nm_pre_root_tog;
+	u32 db_post;
+	u32 db_post_root_set;
+	u32 db_post_root_clr;
+	u32 db_post_root_tog;
+	u32 db_pre;
+	u32 db_pre_root_set;
+	u32 db_pre_root_clr;
+	u32 db_pre_root_tog;
+	u32 reserved[4];
+	u32 access_ctrl;
+	u32 access_ctrl_root_set;
+	u32 access_ctrl_root_clr;
+	u32 access_ctrl_root_tog;
+};
+
+struct ccm_reg {
+	u32 reserved_0[4096];
+	struct ccm_ccgr ccgr_array[192];
+	u32 reserved_1[3328];
+	struct ccm_root core_root[5];
+	u32 reserved_2[352];
+	struct ccm_root bus_root[12];
+	u32 reserved_3[128];
+	struct ccm_root ahb_ipg_root[4];
+	u32 reserved_4[384];
+	struct ccm_root dram_sel;
+	struct ccm_root core_sel;
+	u32 reserved_5[448];
+	struct ccm_root ip_root[78];
+};
+
+#define CCGR_CLK_ON_MASK	0x03
+#define CLK_SRC_ON_MASK		0x03
+
+#define CLK_ROOT_ON		BIT(28)
+#define CLK_ROOT_OFF		(0 << 28)
+#define CLK_ROOT_ENABLE_MASK	BIT(28)
+#define CLK_ROOT_ENABLE_SHIFT	28
+#define CLK_ROOT_SOURCE_SEL(n)	(((n) & 0x7) << 24)
+
+/* For SEL, only use 1 bit */
+#define CLK_ROOT_SRC_MUX_MASK	0x07000000
+#define CLK_ROOT_SRC_MUX_SHIFT	24
+#define CLK_ROOT_SRC_0		0x00000000
+#define CLK_ROOT_SRC_1		0x01000000
+#define CLK_ROOT_SRC_2		0x02000000
+#define CLK_ROOT_SRC_3		0x03000000
+#define CLK_ROOT_SRC_4		0x04000000
+#define CLK_ROOT_SRC_5		0x05000000
+#define CLK_ROOT_SRC_6		0x06000000
+#define CLK_ROOT_SRC_7		0x07000000
+
+#define CLK_ROOT_PRE_DIV_MASK	(0x00070000)
+#define CLK_ROOT_PRE_DIV_SHIFT	16
+#define CLK_ROOT_PRE_DIV(n)	(((n) << 16) & 0x00070000)
+
+#define CLK_ROOT_AUDO_SLOW_EN	0x1000
+
+#define CLK_ROOT_AUDO_DIV_MASK	0x700
+#define CLK_ROOT_AUDO_DIV_SHIFT	0x8
+#define CLK_ROOT_AUDO_DIV(n)	(((n) << 8) & 0x700)
+
+/* For CORE: mask is 0x7; For IPG: mask is 0x3 */
+#define CLK_ROOT_POST_DIV_MASK		0x3f
+#define CLK_ROOT_CORE_POST_DIV_MASK	0x7
+#define CLK_ROOT_IPG_POST_DIV_MASK	0x3
+#define CLK_ROOT_POST_DIV_SHIFT		0
+#define CLK_ROOT_POST_DIV(n)		((n) & 0x3f)
+
+/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
+#define FRAC_PLL_LOCK_MASK		BIT(31)
+#define FRAC_PLL_CLKE_MASK		BIT(21)
+#define FRAC_PLL_PD_MASK		BIT(19)
+#define FRAC_PLL_REFCLK_SEL_MASK	BIT(16)
+#define FRAC_PLL_LOCK_SEL_MASK		BIT(15)
+#define FRAC_PLL_BYPASS_MASK		BIT(14)
+#define FRAC_PLL_COUNTCLK_SEL_MASK	BIT(13)
+#define FRAC_PLL_NEWDIV_VAL_MASK	BIT(12)
+#define FRAC_PLL_NEWDIV_ACK_MASK	BIT(11)
+#define FRAC_PLL_REFCLK_DIV_VAL(n)	(((n) << 5) & (0x3f << 5))
+#define FRAC_PLL_REFCLK_DIV_VAL_MASK	(0x3f << 5)
+#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT	5
+#define FRAC_PLL_OUTPUT_DIV_VAL_MASK	0x1f
+#define FRAC_PLL_OUTPUT_DIV_VAL(n)	((n) & 0x1f)
+
+#define FRAC_PLL_REFCLK_SEL_OSC_25M	(0 << 16)
+#define FRAC_PLL_REFCLK_SEL_OSC_27M	BIT(16)
+#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
+#define FRAC_PLL_REFCLK_SEL_CLK_PN	(3 << 16)
+
+#define FRAC_PLL_FRAC_DIV_CTL_MASK	(0x1ffffff << 7)
+#define FRAC_PLL_FRAC_DIV_CTL_SHIFT	7
+#define FRAC_PLL_INT_DIV_CTL_MASK	0x7f
+#define FRAC_PLL_INT_DIV_CTL_VAL(n)	((n) & 0x7f)
+
+/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
+#define SSCG_PLL_LOCK_MASK		BIT(31)
+#define SSCG_PLL_CLKE_MASK		BIT(25)
+#define SSCG_PLL_DIV2_CLKE_MASK		BIT(23)
+#define SSCG_PLL_DIV3_CLKE_MASK		BIT(21)
+#define SSCG_PLL_DIV4_CLKE_MASK		BIT(19)
+#define SSCG_PLL_DIV5_CLKE_MASK		BIT(17)
+#define SSCG_PLL_DIV6_CLKE_MASK		BIT(15)
+#define SSCG_PLL_DIV8_CLKE_MASK		BIT(13)
+#define SSCG_PLL_DIV10_CLKE_MASK	BIT(11)
+#define SSCG_PLL_DIV20_CLKE_MASK	BIT(9)
+#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK	BIT(9)
+#define SSCG_PLL_DRAM_PLL_CLKE_MASK	BIT(9)
+#define SSCG_PLL_PLL3_CLKE_MASK		BIT(9)
+#define SSCG_PLL_PD_MASK		BIT(7)
+#define SSCG_PLL_BYPASS1_MASK		BIT(5)
+#define SSCG_PLL_BYPASS2_MASK		BIT(4)
+#define SSCG_PLL_LOCK_SEL_MASK		BIT(3)
+#define SSCG_PLL_COUNTCLK_SEL_MASK	BIT(2)
+#define SSCG_PLL_REFCLK_SEL_MASK	0x3
+#define SSCG_PLL_REFCLK_SEL_OSC_25M	(0 << 16)
+#define SSCG_PLL_REFCLK_SEL_OSC_27M	BIT(16)
+#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
+#define SSCG_PLL_REFCLK_SEL_CLK_PN	(3 << 16)
+
+#define SSCG_PLL_SSDS_MASK		BIT(8)
+#define SSCG_PLL_SSMD_MASK		(0x7 << 5)
+#define SSCG_PLL_SSMF_MASK		(0xf << 1)
+#define SSCG_PLL_SSE_MASK		0x1
+
+#define SSCG_PLL_REF_DIVR1_MASK		(0x7 << 25)
+#define SSCG_PLL_REF_DIVR1_SHIFT	25
+#define SSCG_PLL_REF_DIVR1_VAL(n)	(((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
+#define SSCG_PLL_REF_DIVR2_MASK		(0x3f << 19)
+#define SSCG_PLL_REF_DIVR2_SHIFT	19
+#define SSCG_PLL_REF_DIVR2_VAL(n)	(((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
+#define SSCG_PLL_FEEDBACK_DIV_F1_MASK	(0x3f << 13)
+#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT	13
+#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n)	(((n) << 13) & \
+					 SSCG_PLL_FEEDBACK_DIV_F1_MASK)
+#define SSCG_PLL_FEEDBACK_DIV_F2_MASK	(0x3f << 7)
+#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT	7
+#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n)	(((n) << 7) & \
+					 SSCG_PLL_FEEDBACK_DIV_F2_MASK)
+#define SSCG_PLL_OUTPUT_DIV_VAL_MASK	(0x3f << 1)
+#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT	1
+#define SSCG_PLL_OUTPUT_DIV_VAL(n)	(((n) << 1) & \
+					 SSCG_PLL_OUTPUT_DIV_VAL_MASK)
+#define SSCG_PLL_FILTER_RANGE_MASK	0x1
+
+#define HW_DIGPROG_MAJOR_UPPER_MASK	(0xff << 16)
+#define HW_DIGPROG_MAJOR_LOWER_MASK	(0xff << 8)
+#define HW_DIGPROG_MINOR_MASK		0xff
+
+#define HW_OSC_27M_CLKE_MASK		BIT(4)
+#define HW_OSC_25M_CLKE_MASK		BIT(2)
+#define HW_OSC_32K_SEL_MASK		0x1
+#define HW_OSC_32K_SEL_RTC		0x1
+#define HW_OSC_32K_SEL_25M_DIV800	0x0
+
+#define HW_FRAC_ARM_PLL_DIV_MASK	(0x7 << 20)
+#define HW_FRAC_ARM_PLL_DIV_SHIFT	20
+#define HW_FRAC_VPU_PLL_DIV_MASK	(0x7 << 16)
+#define HW_FRAC_VPU_PLL_DIV_SHIFT	16
+#define HW_FRAC_GPU_PLL_DIV_MASK	(0x7 << 12)
+#define HW_FRAC_GPU_PLL_DIV_SHIFT	12
+#define HW_FRAC_VIDEO_PLL1_DIV_MASK	(0x7 << 10)
+#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT	10
+#define HW_FRAC_AUDIO_PLL2_DIV_MASK	(0x7 << 4)
+#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT	4
+#define HW_FRAC_AUDIO_PLL1_DIV_MASK	0x7
+#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT	0
+
+#define HW_SSCG_VIDEO_PLL2_DIV_MASK	(0x7 << 16)
+#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT	16
+#define HW_SSCG_DRAM_PLL_DIV_MASK	(0x7 << 14)
+#define HW_SSCG_DRAM_PLL_DIV_SHIFT	14
+#define HW_SSCG_SYSTEM_PLL3_DIV_MASK	(0x7 << 8)
+#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT	8
+#define HW_SSCG_SYSTEM_PLL2_DIV_MASK	(0x7 << 4)
+#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT	4
+#define HW_SSCG_SYSTEM_PLL1_DIV_MASK	0x7
+#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT	0
+
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x01000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK		0x02000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK		0x03000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x07000000
+#define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M			0x01000000
+#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK	0x01000000
+
+enum enet_freq {
+	ENET_25MHZ = 0,
+	ENET_50MHZ,
+	ENET_125MHZ,
+};
+
+enum frac_pll_out_val {
+	FRAC_PLL_OUT_1000M,
+	FRAC_PLL_OUT_1600M,
+};
+
+u32 imx_get_fecclk(void);
+u32 imx_get_uartclk(void);
+int clock_init(void);
+void init_clk_usdhc(u32 index);
+void init_uart_clk(u32 index);
+void init_wdog_clk(void);
+unsigned int mxc_get_clock(enum clk_root_index clk);
+int clock_enable(enum clk_ccgr_index index, bool enable);
+int clock_root_enabled(enum clk_root_index clock_id);
+int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
+		   enum root_post_div post_div, enum clk_root_src clock_src);
+int clock_set_target_val(enum clk_root_index clock_id, u32 val);
+int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
+int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
+int clock_get_postdiv(enum clk_root_index clock_id,
+		      enum root_post_div *post_div);
+int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
+void mxs_set_lcdclk(u32 base_addr, u32 freq);
+int set_clk_qspi(void);
+void enable_ocotp_clk(unsigned char enable);
+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
+int set_clk_enet(enum enet_freq type);
+#endif