Convert STM3F4 to DT and driver model
Subsystems (10)
cover Convert STM3F4 to DT and driver model
From: Patrice Chotard <[email protected]>
Resend series send on 30/11/2017, due to an unknow issue, only patch 1 of this series was visible on patchwork.
This is the final step to convert STM32F4 to device tree and driver model:
_ add stm32f429-discovery device tree files from kernel v4.15-rc1. _ switch to DM driver (pinctrl, serial, gpio, clock, reset, sdram)
and clean-up stm32f429-discovery.c board file.
_ update STM32 sdram driver needed for stm32f469-disco board. _ add support for new stm32f469-disco board.
_ update stm32f469-discovery device tree to enable MMC support.
Patrice Chotard (14):
ARM: DTS: stm32: add STM32F429 SoC and its Discovery board support
ARM: DTS: stm32: add stm32f429-disco-u-boot dts file
board: stm32f429-discovery: switch to DM STM32 sdram driver
pinctrl: stm32: add stm32f4 pinctrl compatible strings
configs: stm32f429-disco: enable MISC,STM32_RCC,DM_RESET and
STM32_RESET
board: stm32f429-disco: switch to DM STM32 serial driver
mach-stm32: stmf32f4: timer: remove clock_get() call
board: stm32f429-disco: switch to DM STM32 clock driver
board: stm32f429-disco: switch to DM STM32 pinctrl and gpio driver
ram: stm32: add memory mapping selection support
ARM: DTS: add STM32F469 Discovery board support
ARM: DTS: stm32: add stm32f469-disco-u-boot dts file
board: stm32: add stm32f469-discovery board support
ARM: DTS: stm32: add SDIO controller support for stm32f469-disco
arch/arm/dts/Makefile | 3 + arch/arm/dts/stm32f4-pinctrl.dtsi | 375 +++++++++++ arch/arm/dts/stm32f429-disco-u-boot.dtsi | 204 ++++++ arch/arm/dts/stm32f429-disco.dts | 124 ++++ arch/arm/dts/stm32f429-pinctrl.dtsi | 96 +++ arch/arm/dts/stm32f429.dtsi | 711 +++++++++++++++++++++ arch/arm/dts/stm32f469-disco-u-boot.dtsi | 230 +++++++ arch/arm/dts/stm32f469-disco.dts | 145 +++++ arch/arm/dts/stm32f469-pinctrl.dtsi | 97 +++ arch/arm/include/asm/arch-stm32f4/gpio.h | 20 +- arch/arm/include/asm/arch-stm32f4/stm32.h | 35 - arch/arm/mach-stm32/stm32f4/Kconfig | 4 + arch/arm/mach-stm32/stm32f4/Makefile | 2 +- arch/arm/mach-stm32/stm32f4/clock.c | 258 -------- arch/arm/mach-stm32/stm32f4/timer.c | 8 +- board/st/stm32f429-discovery/stm32f429-discovery.c | 277 +------- board/st/stm32f469-discovery/Kconfig | 19 + board/st/stm32f469-discovery/MAINTAINERS | 6 + board/st/stm32f469-discovery/Makefile | 8 + board/st/stm32f469-discovery/stm32f469-discovery.c | 74 +++ configs/stm32f429-discovery_defconfig | 16 +- configs/stm32f469-discovery_defconfig | 42 ++ drivers/clk/clk_stm32f.c | 7 +- drivers/gpio/Makefile | 1 - drivers/gpio/stm32_gpio.c | 182 ------ drivers/pinctrl/pinctrl_stm32.c | 2 + drivers/ram/stm32_sdram.c | 25 + drivers/serial/serial_stm32.c | 117 ---- include/configs/stm32f429-discovery.h | 3 - include/configs/stm32f469-discovery.h | 68 ++ include/dt-bindings/memory/stm32-sdram.h | 2 + include/dt-bindings/mfd/stm32f4-rcc.h | 108 ++++ include/dt-bindings/pinctrl/stm32-pinfunc.h | 30 + 33 files changed, 2426 insertions(+), 873 deletions(-) create mode 100644 arch/arm/dts/stm32f4-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32f429-disco-u-boot.dtsi create mode 100644 arch/arm/dts/stm32f429-disco.dts create mode 100644 arch/arm/dts/stm32f429-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32f429.dtsi create mode 100644 arch/arm/dts/stm32f469-disco-u-boot.dtsi create mode 100644 arch/arm/dts/stm32f469-disco.dts create mode 100644 arch/arm/dts/stm32f469-pinctrl.dtsi delete mode 100644 arch/arm/mach-stm32/stm32f4/clock.c create mode 100644 board/st/stm32f469-discovery/Kconfig create mode 100644 board/st/stm32f469-discovery/MAINTAINERS create mode 100644 board/st/stm32f469-discovery/Makefile create mode 100644 board/st/stm32f469-discovery/stm32f469-discovery.c create mode 100644 configs/stm32f469-discovery_defconfig delete mode 100644 drivers/gpio/stm32_gpio.c delete mode 100644 drivers/serial/serial_stm32.c create mode 100644 include/configs/stm32f469-discovery.h create mode 100644 include/dt-bindings/mfd/stm32f4-rcc.h create mode 100644 include/dt-bindings/pinctrl/stm32-pinfunc.h
Signature · 1 line
1.9.1
PATCH RESEND 1/14 ARM: DTS: stm32: add STM32F429 SoC and its Discovery board support
From: Patrice Chotard <[email protected]>
All these files comes from kernel v4.15-rc1.
Update some header with correct STMicroelectronics Copyright.
Remove the paragraph about writing to the Free Software Foundation's mailing address as requested by checkpatch.
--- arch/arm/dts/Makefile | 2 + arch/arm/dts/stm32f4-pinctrl.dtsi | 344 ++++++++++++++ arch/arm/dts/stm32f429-disco.dts | 124 +++++ arch/arm/dts/stm32f429-pinctrl.dtsi | 96 ++++ arch/arm/dts/stm32f429.dtsi | 699 ++++++++++++++++++++++++++++ include/dt-bindings/mfd/stm32f4-rcc.h | 108 +++++ include/dt-bindings/pinctrl/stm32-pinfunc.h | 30 ++ 7 files changed, 1403 insertions(+) create mode 100644 arch/arm/dts/stm32f4-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32f429-disco.dts create mode 100644 arch/arm/dts/stm32f429-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32f429.dtsi create mode 100644 include/dt-bindings/mfd/stm32f4-rcc.h create mode 100644 include/dt-bindings/pinctrl/stm32-pinfunc.h
arch/arm/dts/Makefile +2 -0
@@ -213,6 +213,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb +dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb + dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \ stm32f769-disco.dtb dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
arch/arm/dts/stm32f4-pinctrl.dtsi new file +344 -0
344 lines not on this page · raw message
arch/arm/dts/stm32f429-disco.dts new file +124 -0
124 lines not on this page · raw message
arch/arm/dts/stm32f429-pinctrl.dtsi new file +96 -0
96 lines not on this page · raw message
arch/arm/dts/stm32f429.dtsi new file +699 -0
699 lines not on this page · raw message
include/dt-bindings/mfd/stm32f4-rcc.h new file +108 -0
108 lines not on this page · raw message
include/dt-bindings/pinctrl/stm32-pinfunc.h new file +30 -0
@@ -0,0 +1,30 @@ +#ifndef _DT_BINDINGS_STM32_PINFUNC_H +#define _DT_BINDINGS_STM32_PINFUNC_H + +/* define PIN modes */ +#define GPIO 0x0 +#define AF0 0x1 +#define AF1 0x2 +#define AF2 0x3 +#define AF3 0x4 +#define AF4 0x5 +#define AF5 0x6 +#define AF6 0x7 +#define AF7 0x8 +#define AF8 0x9 +#define AF9 0xa +#define AF10 0xb +#define AF11 0xc +#define AF12 0xd +#define AF13 0xe +#define AF14 0xf +#define AF15 0x10 +#define ANALOG 0x11 + +/* define Pins number*/ +#define PIN_NO (port, line) (((port) - 'A') * 0x10 + (line)) + +#define STM32_PINMUX (port, line, mode) (((PIN_NO(port, line)) << 8) | (mode)) + +#endif /* _DT_BINDINGS_STM32_PINFUNC_H */ +
Signature · 1 line
1.9.1
PATCH RESEND 1/14 ARM: DTS: stm32: add STM32F429 SoC and its Discovery board support
Quoted 10 lines · patrice.chotard at st.com
From: Patrice Chotard <[email protected]>
All these files comes from kernel v4.15-rc1.
Update some header with correct STMicroelectronics Copyright.
Remove the paragraph about writing to the Free Software Foundation's mailing address as requested by checkpatch.
Signed-off-by Patrice Chotard <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH RESEND 2/14 ARM: DTS: stm32: add stm32f429-disco-u-boot dts file
In reply to patrice.chotard at st.comFrom: Patrice Chotard <[email protected]>
_ Add gpio compatible and aliases for stm32f429
_ Add FMC sdram node with associated new bindings value to
manage second bank (ie bank 1).
_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.
--- arch/arm/dts/stm32f429-disco-u-boot.dtsi | 204 +++++++++++++++++++++++++++++++ include/dt-bindings/memory/stm32-sdram.h | 2 + 2 files changed, 206 insertions(+) create mode 100644 arch/arm/dts/stm32f429-disco-u-boot.dtsi
arch/arm/dts/stm32f429-disco-u-boot.dtsi new file +204 -0
@@ -0,0 +1,204 @@ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, <[email protected]> for STMicroelectronics. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/memory/stm32-sdram.h> +/{ + clocks { + u-boot,dm-pre-reloc; + }; + + aliases { + /* Aliases for gpios so as to use sequence */ + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + }; + + soc { + u-boot,dm-pre-reloc; + pin-controller { + u-boot,dm-pre-reloc; + }; + + fmc: fmc at A0000000 { + compatible = "st,stm32-fmc"; + reg = <0xA0000000 0x1000>; + clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>; + pinctrl-0 = <&fmc_pins>; + pinctrl-names = "default"; + u-boot,dm-pre-reloc; + + /* + * Memory configuration from sdram datasheet + * IS42S16400J + */ + bank1: bank at 1 { + st,sdram-control = /bits/ 8 <NO_COL_8 + NO_ROW_12 + MWIDTH_16 + BANKS_4 + CAS_3 + SDCLK_2 + RD_BURST_EN + RD_PIPE_DL_0>; + st,sdram-timing = /bits/ 8 <TMRD_3 + TXSR_7 + TRAS_4 + TRC_6 + TWR_2 + TRP_2 TRCD_2>; + st,sdram-refcount = < 1386 >; + }; + }; + }; +}; + +&clk_hse { + u-boot,dm-pre-reloc; +}; + +&clk_lse { + u-boot,dm-pre-reloc; +}; + +&clk_i2s_ckin { + u-boot,dm-pre-reloc; +}; + +&pwrcfg { + u-boot,dm-pre-reloc; +}; + +&rcc { + u-boot,dm-pre-reloc; +}; + +&gpioa { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiob { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioc { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiod { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioe { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiof { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiog { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioh { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioi { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioj { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiok { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&pinctrl { + usart1_pins_a: usart1 at 0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; + }; + + fmc_pins: fmc at 0 { + u-boot,dm-pre-reloc; + pins + { + pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */ + <STM32_PINMUX('D', 9, AF12)>, /* D14 */ + <STM32_PINMUX('D', 8, AF12)>, /* D13 */ + <STM32_PINMUX('E',15, AF12)>, /* D12 */ + <STM32_PINMUX('E',14, AF12)>, /* D11 */ + <STM32_PINMUX('E',13, AF12)>, /* D10 */ + <STM32_PINMUX('E',12, AF12)>, /* D09 */ + <STM32_PINMUX('E',11, AF12)>, /* D08 */ + <STM32_PINMUX('E',10, AF12)>, /* D07 */ + <STM32_PINMUX('E', 9, AF12)>, /* D06 */ + <STM32_PINMUX('E', 8, AF12)>, /* D05 */ + <STM32_PINMUX('E', 7, AF12)>, /* D04 */ + <STM32_PINMUX('D', 1, AF12)>, /* D03 */ + <STM32_PINMUX('D', 0, AF12)>, /* D02 */ + <STM32_PINMUX('D',15, AF12)>, /* D01 */ + <STM32_PINMUX('D',14, AF12)>, /* D00 */ + + <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */ + <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */ + + <STM32_PINMUX('G', 5, AF12)>, /* BA1 */ + <STM32_PINMUX('G', 4, AF12)>, /* BA0 */ + + <STM32_PINMUX('G', 1, AF12)>, /* A11 */ + <STM32_PINMUX('G', 0, AF12)>, /* A10 */ + <STM32_PINMUX('F',15, AF12)>, /* A09 */ + <STM32_PINMUX('F',14, AF12)>, /* A08 */ + <STM32_PINMUX('F',13, AF12)>, /* A07 */ + <STM32_PINMUX('F',12, AF12)>, /* A06 */ + <STM32_PINMUX('F', 5, AF12)>, /* A05 */ + <STM32_PINMUX('F', 4, AF12)>, /* A04 */ + <STM32_PINMUX('F', 3, AF12)>, /* A03 */ + <STM32_PINMUX('F', 2, AF12)>, /* A02 */ + <STM32_PINMUX('F', 1, AF12)>, /* A01 */ + <STM32_PINMUX('F', 0, AF12)>, /* A00 */ + + <STM32_PINMUX('B', 6, AF12)>, /* SDNE1 */ + <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */ + <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */ + <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */ + <STM32_PINMUX('B', 5, AF12)>, /* SDCKE1 */ + <STM32_PINMUX('G', 8, AF12)>; /* SDCLK */ + slew-rate = <2>; + u-boot,dm-pre-reloc; + }; + }; +};
include/dt-bindings/memory/stm32-sdram.h +2 -0
@@ -30,8 +30,10 @@/* Timing = value +1 cycles */ #define TMRD_1 (1 - 1)#define TMRD_2 (2 - 1) +#define TMRD_3 (3 - 1)#define TXSR_1 (1 - 1)#define TXSR_6 (6 - 1) +#define TXSR_7 (7 - 1)#define TRAS_1 (1 - 1)#define TRAS_4 (4 - 1)#define TRC_6 (6 - 1)
Signature · 1 line
1.9.1
PATCH RESEND 2/14 ARM: DTS: stm32: add stm32f429-disco-u-boot dts file
Quoted 11 lines · patrice.chotard at st.com
From: Patrice Chotard <[email protected]>
_ Add gpio compatible and aliases for stm32f429
_ Add FMC sdram node with associated new bindings value to
manage second bank (ie bank 1)._ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.Signed-off-by Patrice Chotard <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH RESEND 3/14 board: stm32f429-discovery: switch to DM STM32 sdram driver
In reply to patrice.chotard at st.comFrom: Patrice Chotard <[email protected]>
Use available DM stm32_sdram.c driver instead of board SDRAM initialization.
For that, enable OF_CONTROL, OF_EMBED and STM32_SDRAM flags.
--- board/st/stm32f429-discovery/stm32f429-discovery.c | 136 +++------------------ configs/stm32f429-discovery_defconfig | 6 +- include/configs/stm32f429-discovery.h | 1 - 3 files changed, 19 insertions(+), 124 deletions(-)
board/st/stm32f429-discovery/stm32f429-discovery.c +14 -122
@@ -15,10 +15,8 @@#include <dm.h> #include <stm32_rcc.h> #include <asm/io.h> -#include <asm/armv7m.h> #include <asm/arch/stm32.h> #include <asm/arch/gpio.h> -#include <asm/arch/fmc.h> #include <dm/platform_data/serial_stm32.h> #include <asm/arch/stm32_periph.h> #include <asm/arch/stm32_defs.h>
@@ -140,56 +138,10 @@ out:*/ #define STM32_RCC_ENR_FMC (1 << 0)/* FMC module clock */ -static inline u32 _ns2clk (u32 ns,u32 freq) -{ -u32 tmp = freq/1000000 ; -return (tmp * ns) /1000 ; -} - -#define NS2CLK (ns) (_ns2clk(ns, freq)) - -/* -* Following are timings for IS42S16400J, from corresponding datasheet -*/ -#define SDRAM_CAS 3/* 3 cycles */ -#define SDRAM_NB 1/* Number of banks */ -#define SDRAM_MWID 1/* 16 bit memory */ - -#define SDRAM_NR 0x1/* 12-bit row */ -#define SDRAM_NC 0x0/* 8-bit col */ -#define SDRAM_RBURST 0x1/* Single read requests always as bursts */ -#define SDRAM_RPIPE 0x0/* No HCLK clock cycle delay */ - -#define SDRAM_TRRD (NS2CLK(14) - 1) -#define SDRAM_TRCD (NS2CLK(15) - 1) -#define SDRAM_TRP (NS2CLK(15) - 1) -#define SDRAM_TRAS (NS2CLK(42) - 1) -#define SDRAM_TRC (NS2CLK(63) - 1) -#define SDRAM_TRFC (NS2CLK(63) - 1) -#define SDRAM_TCDL (1 - 1) -#define SDRAM_TRDL (2 - 1) -#define SDRAM_TBDL (1 - 1) -#define SDRAM_TREF 1386 -#define SDRAM_TCCD (1 - 1) - -#define SDRAM_TXSR (NS2CLK(70) - 1)/* Row cycle time after precharge */ -#define SDRAM_TMRD (3 - 1)/* Page 10, Mode Register Set */ - -/* Last data-in to row precharge, need also comply ineq from RM 37.7.5 */ -#define SDRAM_TWR max(\ - (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD - 1)), \ - (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP - 2)\ -) - -#define SDRAM_MODE_BL_SHIFT 0 -#define SDRAM_MODE_CAS_SHIFT 4 -#define SDRAM_MODE_BL 0 -#define SDRAM_MODE_CAS SDRAM_CAS -int dram_init (void ) { -u32 freq;int rv; +struct udevice *dev; rv =fmc_setup_gpio ();if (rv)
@@ -197,83 +149,23 @@ int dram_init(void)setbits_le32 (&STM32_RCC ->ahb3enr,STM32_RCC_ENR_FMC ); -/* -* Get frequency for NS2CLK calculation. -*/ - freq =clock_get (CLOCK_AHB ) /CONFIG_SYS_RAM_FREQ_DIV ; - -writel (CONFIG_SYS_RAM_FREQ_DIV <<FMC_SDCR_SDCLK_SHIFT - |SDRAM_RPIPE <<FMC_SDCR_RPIPE_SHIFT - |SDRAM_RBURST <<FMC_SDCR_RBURST_SHIFT , - &STM32_SDRAM_FMC ->sdcr1); - -writel (CONFIG_SYS_RAM_FREQ_DIV <<FMC_SDCR_SDCLK_SHIFT - |SDRAM_CAS <<FMC_SDCR_CAS_SHIFT - |SDRAM_NB <<FMC_SDCR_NB_SHIFT - |SDRAM_MWID <<FMC_SDCR_MWID_SHIFT - |SDRAM_NR <<FMC_SDCR_NR_SHIFT - |SDRAM_NC <<FMC_SDCR_NC_SHIFT - |SDRAM_RPIPE <<FMC_SDCR_RPIPE_SHIFT - |SDRAM_RBURST <<FMC_SDCR_RBURST_SHIFT , - &STM32_SDRAM_FMC ->sdcr2); - -writel (SDRAM_TRP <<FMC_SDTR_TRP_SHIFT - |SDRAM_TRC <<FMC_SDTR_TRC_SHIFT , - &STM32_SDRAM_FMC ->sdtr1); - -writel (SDRAM_TRCD <<FMC_SDTR_TRCD_SHIFT - |SDRAM_TRP <<FMC_SDTR_TRP_SHIFT - |SDRAM_TWR <<FMC_SDTR_TWR_SHIFT - |SDRAM_TRC <<FMC_SDTR_TRC_SHIFT - |SDRAM_TRAS <<FMC_SDTR_TRAS_SHIFT - |SDRAM_TXSR <<FMC_SDTR_TXSR_SHIFT - |SDRAM_TMRD <<FMC_SDTR_TMRD_SHIFT , - &STM32_SDRAM_FMC ->sdtr2); - -writel (FMC_SDCMR_BANK_2 |FMC_SDCMR_MODE_START_CLOCK , - &STM32_SDRAM_FMC ->sdcmr); - -udelay (200 );/* 200 us delay, page 10, "Power-Up" */ -FMC_BUSY_WAIT (); - -writel (FMC_SDCMR_BANK_2 |FMC_SDCMR_MODE_PRECHARGE , - &STM32_SDRAM_FMC ->sdcmr); - -udelay (100 ); -FMC_BUSY_WAIT (); - -writel ((FMC_SDCMR_BANK_2 |FMC_SDCMR_MODE_AUTOREFRESH - |7 <<FMC_SDCMR_NRFS_SHIFT ), &STM32_SDRAM_FMC ->sdcmr); - -udelay (100 ); -FMC_BUSY_WAIT (); - -writel (FMC_SDCMR_BANK_2 | (SDRAM_MODE_BL <<SDRAM_MODE_BL_SHIFT - |SDRAM_MODE_CAS <<SDRAM_MODE_CAS_SHIFT ) - <<FMC_SDCMR_MODE_REGISTER_SHIFT |FMC_SDCMR_MODE_WRITE_MODE , - &STM32_SDRAM_FMC ->sdcmr); - -udelay (100 ); - -FMC_BUSY_WAIT (); - -writel (FMC_SDCMR_BANK_2 |FMC_SDCMR_MODE_NORMAL , - &STM32_SDRAM_FMC ->sdcmr); - -FMC_BUSY_WAIT (); + rv =uclass_get_device (UCLASS_RAM ,0 , &dev); +if (rv) { +debug ("DRAM init failed: %d\n" , rv); +return rv; + } -/* Refresh timer */ -writel (SDRAM_TREF , &STM32_SDRAM_FMC ->sdrtr); +if (fdtdec_setup_memory_size () !=0 ) + rv = -EINVAL ; -/* -* Fill in global info with description of SRAM configuration -*/ - gd->bd->bi_dram[0 ].start =CONFIG_SYS_RAM_BASE ; - gd->bd->bi_dram[0 ].size =CONFIG_SYS_RAM_SIZE ; +return rv; +} - gd->ram_size =CONFIG_SYS_RAM_SIZE ; +int dram_init_banksize (void ) +{ +fdtdec_setup_memory_banksize (); -return rv; +return 0 ; }static const struct stm32_serial_platdata serial_platdata = {
configs/stm32f429-discovery_defconfig +5 -1
@@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_STM32=y CONFIG_STM32F4=y CONFIG_TARGET_STM32F429_DISCOVERY=y +CONFIG_DEFAULT_DEVICE_TREE="stm32f429-disco" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
@@ -14,7 +15,10 @@ CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_IMLS=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIMER=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FLASH=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y -CONFIG_OF_LIBFDT=y +CONFIG_RAM=y +CONFIG_STM32_SDRAM=y
include/configs/stm32f429-discovery.h +0 -1
@@ -24,7 +24,6 @@* Configuration of the external SDRAM memory */ #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_RAM_SIZE (8 << 20)#define CONFIG_SYS_RAM_CS 1#define CONFIG_SYS_RAM_FREQ_DIV 2#define CONFIG_SYS_RAM_BASE 0xD0000000
Signature · 1 line
1.9.1
PATCH RESEND 3/14 board: stm32f429-discovery: switch to DM STM32 sdram driver
Quoted 7 lines · patrice.chotard at st.com
From: Patrice Chotard <[email protected]>
Use available DM
stm32_sdram.cdriver instead of board SDRAM initialization.
For that, enableOF_CONTROL,OF_EMBEDandSTM32_SDRAMflags.Signed-off-by Patrice Chotard <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH RESEND 4/14 pinctrl: stm32: add stm32f4 pinctrl compatible strings
In reply to patrice.chotard at st.comFrom: Patrice Chotard <[email protected]>
STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs.
We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c.
--- drivers/pinctrl/pinctrl_stm32.c | 2 ++ 1 file changed, 2 insertions(+)
drivers/pinctrl/pinctrl_stm32.c +2 -0
@@ -182,6 +182,8 @@ static struct pinctrl_ops stm32_pinctrl_ops = { };static const struct udevice_id stm32_pinctrl_ids[] = { + { .compatible ="st,stm32f429-pinctrl" }, + { .compatible ="st,stm32f469-pinctrl" }, { .compatible ="st,stm32f746-pinctrl" }, { .compatible ="st,stm32h743-pinctrl" }, { }
Signature · 1 line
1.9.1
PATCH RESEND 4/14 pinctrl: stm32: add stm32f4 pinctrl compatible strings
Quoted 8 lines · patrice.chotard at st.com
From: Patrice Chotard <[email protected]>
STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs.
We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string intopinctrl_stm32.c.Signed-off-by Patrice Chotard <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH RESEND 5/14 configs: stm32f429-disco: enable MISC, STM32_RCC, DM_RESET and STM32_RESET
In reply to patrice.chotard at st.comFrom: Patrice Chotard <[email protected]>
This allows to support rcc MFD driver.
By enabling all these flags, we need to increase malloc area to avoid crash during early stage.
--- configs/stm32f429-discovery_defconfig | 5 +++++ 1 file changed, 5 insertions(+)
configs/stm32f429-discovery_defconfig +5 -0
@@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_STM32=y +CONFIG_SYS_MALLOC_F_LEN=0xF00 CONFIG_STM32F4=y CONFIG_TARGET_STM32F429_DISCOVERY=y CONFIG_DEFAULT_DEVICE_TREE="stm32f429-disco"
@@ -18,7 +19,11 @@ CONFIG_CMD_TIMER=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FLASH=y +CONFIG_MISC=y +CONFIG_STM32_RCC=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_RAM=y CONFIG_STM32_SDRAM=y +CONFIG_DM_RESET=y +CONFIG_STM32_RESET=y
Signature · 1 line
1.9.1
PATCH RESEND 5/14 configs: stm32f429-disco: enable MISC, STM32_RCC, DM_RESET and STM32_RESET
Quoted 7 lines · patrice.chotard at st.com
From: Patrice Chotard <[email protected]>
This allows to support rcc MFD driver.
By enabling all these flags, we need to increase malloc area to avoid crash during early stage.Signed-off-by Patrice Chotard <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH RESEND 6/14 board: stm32f429-disco: switch to DM STM32 serial driver
In reply to patrice.chotard at st.comFrom: Patrice Chotard <[email protected]>
Remove serial_stm32.c driver and uart init from board file, use available DM serial_stm32x7.c driver compatible for STM32F4/F7 and H7 SoCs.
The serial_stm32x7.c driver will be renamed later with a more generic name as it's shared with all STM32 Socs.
--- arch/arm/include/asm/arch-stm32f4/stm32.h | 8 -- board/st/stm32f429-discovery/stm32f429-discovery.c | 10 -- configs/stm32f429-discovery_defconfig | 1 + drivers/serial/serial_stm32.c | 117 --------------------- include/configs/stm32f429-discovery.h | 1 - 5 files changed, 1 insertion(+), 136 deletions(-) delete mode 100644 drivers/serial/serial_stm32.c
arch/arm/include/asm/arch-stm32f4/stm32.h +0 -8
@@ -59,14 +59,6 @@ struct stm32_pwr_regs {#define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000)#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE) -/* -* Peripheral base addresses -*/ -#define STM32_USART1_BASE (STM32_APB2PERIPH_BASE + 0x1000) -#define STM32_USART2_BASE (STM32_APB1PERIPH_BASE + 0x4400) -#define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800) -#define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400) -#define FLASH_CNTL_BASE (STM32_AHB1PERIPH_BASE + 0x3C00)static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT ] = {
board/st/stm32f429-discovery/stm32f429-discovery.c +0 -10
@@ -17,7 +17,6 @@#include <asm/io.h> #include <asm/arch/stm32.h> #include <asm/arch/gpio.h> -#include <dm/platform_data/serial_stm32.h> #include <asm/arch/stm32_periph.h> #include <asm/arch/stm32_defs.h>
@@ -168,15 +167,6 @@ int dram_init_banksize(void)return 0 ; } -static const struct stm32_serial_platdata serial_platdata = { - .base = (struct stm32_usart *)STM32_USART1_BASE , -}; - -U_BOOT_DEVICE (stm32_serials) = { - .name ="serial_stm32" , - .platdata = &serial_platdata, -}; -u32 get_board_rev (void ) {return 0 ;
configs/stm32f429-discovery_defconfig +1 -0
@@ -27,3 +27,4 @@ CONFIG_RAM=y CONFIG_STM32_SDRAM=y CONFIG_DM_RESET=y CONFIG_STM32_RESET=y +CONFIG_STM32X7_SERIAL=y
drivers/serial/serial_stm32.c deleted +0 -117
117 lines not on this page · raw message
include/configs/stm32f429-discovery.h +0 -1
@@ -43,7 +43,6 @@#define CONFIG_STM32_GPIO #define CONFIG_STM32_FLASH -#define CONFIG_STM32_SERIAL #define CONFIG_STM32_HSE_HZ 8000000
Signature · 1 line
1.9.1
PATCH RESEND 6/14 board: stm32f429-disco: switch to DM STM32 serial driver
Quoted 10 lines · patrice.chotard at st.com
From: Patrice Chotard <[email protected]>
Remove
serial_stm32.cdriver and uart init from board file, use available DMserial_stm32x7.cdriver compatible for STM32F4/F7 and H7 SoCs.The
serial_stm32x7.cdriver will be renamed later with a more generic name as it's shared with all STM32 Socs.Signed-off-by Patrice Chotard <[email protected]>
Applied to u-boot/master, thanks!
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PATCH RESEND 7/14 mach-stm32: stmf32f4: timer: remove clock_get() call
In reply to patrice.chotard at st.comFrom: Patrice Chotard <[email protected]>
In order to use common clock driver between STM32F4 and STM32F7, remove clock_get() call
As APB_PSC is always set to 2, only case when clock_get(CLOCK_AHB) != clock_get(CLOCK_APB1) is kept
--- arch/arm/mach-stm32/stm32f4/timer.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-)
arch/arm/mach-stm32/stm32f4/timer.c +2 -6
@@ -51,12 +51,8 @@ int timer_init(void)setbits_le32 (&STM32_RCC ->apb1enr,RCC_APB1ENR_TIM2EN ); -if (clock_get (CLOCK_AHB ) ==clock_get (CLOCK_APB1 )) -writel ((clock_get (CLOCK_APB1 ) /CONFIG_SYS_HZ_CLOCK ) -1 , - &tim->psc); -else -writel (((clock_get (CLOCK_APB1 ) *2 ) /CONFIG_SYS_HZ_CLOCK ) -1 , - &tim->psc); +writel (((CONFIG_SYS_CLK_FREQ /2 ) /CONFIG_SYS_HZ_CLOCK ) -1 , + &tim->psc);writel (0xFFFFFFFF , &tim->arr);writel (TIM_CR1_CEN , &tim->cr1);
Signature · 1 line
1.9.1
PATCH RESEND 7/14 mach-stm32: stmf32f4: timer: remove clock_get() call
Quoted 8 lines · patrice.chotard at st.com
From: Patrice Chotard <[email protected]>
In order to use common clock driver between STM32F4 and STM32F7, remove
clock_get()call
AsAPB_PSCis always set to 2, only case whenclock_get(CLOCK_AHB)!=clock_get(CLOCK_APB1)is keptSigned-off-by Patrice Chotard <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH RESEND 8/14 board: stm32f429-disco: switch to DM STM32 clock driver
In reply to patrice.chotard at st.comFrom: Patrice Chotard <[email protected]>
Use available DM clk_stm32f.c driver instead of dedicated mach-stm32/stm32f4/clock.c.
Migrate periph_clock defines from stm32_periph.h directly in CLK driver. These periph_clock defines will be removed when STMMAC, TIMER2 and SYSCFG drivers will support DM CLK.
Enable also CLK flag.
--- arch/arm/include/asm/arch-stm32f4/stm32.h | 17 -- arch/arm/mach-stm32/stm32f4/Makefile | 2 +- arch/arm/mach-stm32/stm32f4/clock.c | 258 --------------------- board/st/stm32f429-discovery/stm32f429-discovery.c | 24 +- configs/stm32f429-discovery_defconfig | 1 + drivers/clk/clk_stm32f.c | 7 +- 6 files changed, 9 insertions(+), 300 deletions(-) delete mode 100644 arch/arm/mach-stm32/stm32f4/clock.c
arch/arm/include/asm/arch-stm32f4/stm32.h +0 -17
@@ -42,11 +42,6 @@ struct stm32_u_id_regs {u32 u_id_high; }; -struct stm32_pwr_regs { -u32 cr; -u32 csr; -}; -/* * Registers access macros */
@@ -56,9 +51,6 @@ struct stm32_pwr_regs {#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800)#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE) -#define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000) -#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE) -#define FLASH_CNTL_BASE (STM32_AHB1PERIPH_BASE + 0x3C00)static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT ] = {
@@ -67,15 +59,6 @@ static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { [5 ... 11] = 128 * 1024 }; -enum clock { -CLOCK_CORE , -CLOCK_AHB , -CLOCK_APB1 , -CLOCK_APB2 -}; - -int configure_clocks (void ); -unsigned long clock_get (enum clock clck);void stm32_flash_latency_cfg (int latency);#endif /* _MACH_STM32_H_ */
arch/arm/mach-stm32/stm32f4/Makefile +1 -1
@@ -8,4 +8,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += clock.o timer.o +obj-y += timer.o
arch/arm/mach-stm32/stm32f4/clock.c deleted +0 -258
258 lines not on this page · raw message
board/st/stm32f429-discovery/stm32f429-discovery.c +1 -23
@@ -13,12 +13,10 @@#include <common.h> #include <dm.h> -#include <stm32_rcc.h> +#include <asm/io.h> #include <asm/arch/stm32.h> #include <asm/arch/gpio.h> -#include <asm/arch/stm32_periph.h> -#include <asm/arch/stm32_defs.h> DECLARE_GLOBAL_DATA_PTR ;
@@ -48,7 +46,6 @@ int uart_setup_gpio(void)int i;int rv =0 ; -clock_setup (GPIO_A_CLOCK_CFG );for (i =0 ; i <ARRAY_SIZE (usart_gpio); i++) { rv =stm32_gpio_config (&usart_gpio[i], &gpio_ctl_usart);if (rv)
@@ -114,13 +111,6 @@ static int fmc_setup_gpio(void)int rv =0 ;int i; -clock_setup (GPIO_B_CLOCK_CFG ); -clock_setup (GPIO_C_CLOCK_CFG ); -clock_setup (GPIO_D_CLOCK_CFG ); -clock_setup (GPIO_E_CLOCK_CFG ); -clock_setup (GPIO_F_CLOCK_CFG ); -clock_setup (GPIO_G_CLOCK_CFG ); -for (i =0 ; i <ARRAY_SIZE (ext_ram_fmc_gpio); i++) { rv =stm32_gpio_config (&ext_ram_fmc_gpio[i], &gpio_ctl_fmc);
@@ -132,11 +122,6 @@ out:return rv; } -/* -* STM32 RCC FMC specific definitions -*/ -#define STM32_RCC_ENR_FMC (1 << 0)/* FMC module clock */ -int dram_init (void ) {int rv;
@@ -145,9 +130,6 @@ int dram_init(void) rv =fmc_setup_gpio ();if (rv)return rv; - -setbits_le32 (&STM32_RCC ->ahb3enr,STM32_RCC_ENR_FMC ); - rv =uclass_get_device (UCLASS_RAM ,0 , &dev);if (rv) {debug ("DRAM init failed: %d\n" , rv);
@@ -176,13 +158,9 @@ int board_early_init_f(void) {int res; -configure_clocks (); - res =uart_setup_gpio ();if (res)return res; -clock_setup (USART1_CLOCK_CFG ); -return 0 ; }
configs/stm32f429-discovery_defconfig +1 -0
@@ -19,6 +19,7 @@ CONFIG_CMD_TIMER=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FLASH=y +CONFIG_CLK=y CONFIG_MISC=y CONFIG_STM32_RCC=y # CONFIG_MMC is not set
drivers/clk/clk_stm32f.c +6 -1
@@ -12,7 +12,6 @@#include <asm/io.h> #include <asm/arch/stm32.h> -#include <asm/arch/stm32_periph.h> #include <asm/arch/stm32_pwr.h> #include <dt-bindings/mfd/stm32f7-rcc.h>
@@ -88,6 +87,12 @@*/ #define RCC_APB2ENR_SYSCFGEN BIT(14) +enum periph_clock { +SYSCFG_CLOCK_CFG , +TIMER2_CLOCK_CFG , +STMMAC_CLOCK_CFG , +}; +struct stm32_clk_info stm32f4_clk_info = {/* 180 MHz */ .sys_pll_psc = {
Signature · 1 line
1.9.1
PATCH RESEND 8/14 board: stm32f429-disco: switch to DM STM32 clock driver
Quoted 5 lines · patrice.chotard at st.com
From: Patrice Chotard <[email protected]>
Use available DM
clk_stm32f.cdriver instead of dedicatedmach-stm32/stm32f4/clock.c.
Quoted 7 lines
Migrate
periph_clockdefines fromstm32_periph.hdirectly in CLK driver. Theseperiph_clockdefines will be removed when STMMAC, TIMER2 and SYSCFG drivers will support DM CLK.Enable also CLK flag.
Signed-off-by Patrice Chotard <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH RESEND 9/14 board: stm32f429-disco: switch to DM STM32 pinctrl and gpio driver
In reply to patrice.chotard at st.comFrom: Patrice Chotard <[email protected]>
Use available DM stm32f7_gpio.c and pinctrl_stm32.c drivers instead of board GPIO initialization.
Remove stm32_gpio.c which is no more used and migrate structs stm32_gpio_regs and stm32_gpio_priv into arch-stm32f4/gpio.h to not break compilation.
--- arch/arm/include/asm/arch-stm32f4/gpio.h | 20 ++- arch/arm/include/asm/arch-stm32f4/stm32.h | 10 -- board/st/stm32f429-discovery/stm32f429-discovery.c | 111 ------------- configs/stm32f429-discovery_defconfig | 3 + drivers/gpio/Makefile | 1 - drivers/gpio/stm32_gpio.c | 182 --------------------- include/configs/stm32f429-discovery.h | 1 - 7 files changed, 19 insertions(+), 309 deletions(-) delete mode 100644 drivers/gpio/stm32_gpio.c
arch/arm/include/asm/arch-stm32f4/gpio.h +16 -4
@@ -131,6 +131,22 @@ struct stm32_gpio_ctl {enum stm32_gpio_af af; }; +struct stm32_gpio_regs { +u32 moder;/* GPIO port mode */ +u32 otyper;/* GPIO port output type */ +u32 ospeedr;/* GPIO port output speed */ +u32 pupdr;/* GPIO port pull-up/pull-down */ +u32 idr;/* GPIO port input data */ +u32 odr;/* GPIO port output data */ +u32 bsrr;/* GPIO port bit set/reset */ +u32 lckr;/* GPIO port configuration lock */ +u32 afr[2 ];/* GPIO alternate function */ +}; + +struct stm32_gpio_priv { +struct stm32_gpio_regs *regs; +}; +static inline unsigned stm32_gpio_to_port (unsigned gpio) {return gpio /16 ;
@@ -141,8 +157,4 @@ static inline unsigned stm32_gpio_to_pin(unsigned gpio) return gpio % 16; } -int stm32_gpio_config (const struct stm32_gpio_dsc *gpio_dsc, -const struct stm32_gpio_ctl *gpio_ctl); -int stm32_gpout_set (const struct stm32_gpio_dsc *gpio_dsc,int state); -#endif /* _STM32_GPIO_H_ */
arch/arm/include/asm/arch-stm32f4/stm32.h +0 -10
@@ -23,16 +23,6 @@#define STM32_BUS_MASK 0xFFFF0000 -#define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000) -#define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400) -#define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800) -#define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00) -#define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000) -#define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400) -#define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800) -#define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00) -#define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000) -/* * Register maps */
board/st/stm32f429-discovery/stm32f429-discovery.c +0 -111
131 lines not on this page · raw message
configs/stm32f429-discovery_defconfig +3 -0
@@ -20,10 +20,13 @@ CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_CLK=y +CONFIG_DM_GPIO=y CONFIG_MISC=y CONFIG_STM32_RCC=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_STM32=y CONFIG_RAM=y CONFIG_STM32_SDRAM=y CONFIG_DM_RESET=y
drivers/gpio/Makefile +0 -1
@@ -48,7 +48,6 @@ obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o obj-$(CONFIG_TCA642X) += tca642x.o obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o -obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o obj-$(CONFIG_STM32F7_GPIO) += stm32f7_gpio.o obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o
drivers/gpio/stm32_gpio.c deleted +0 -182
182 lines not on this page · raw message
include/configs/stm32f429-discovery.h +0 -1
@@ -41,7 +41,6 @@#define CONFIG_RED_LED 110#define CONFIG_GREEN_LED 109 -#define CONFIG_STM32_GPIO #define CONFIG_STM32_FLASH #define CONFIG_STM32_HSE_HZ 8000000
Signature · 1 line
1.9.1
PATCH RESEND 9/14 board: stm32f429-disco: switch to DM STM32 pinctrl and gpio driver
Quoted 10 lines · patrice.chotard at st.com
From: Patrice Chotard <[email protected]>
Use available DM
stm32f7_gpio.candpinctrl_stm32.cdrivers instead of board GPIO initialization.Remove
stm32_gpio.cwhich is no more used and migrate structsstm32_gpio_regsandstm32_gpio_privintoarch-stm32f4/gpio.hto not break compilation.Signed-off-by Patrice Chotard <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH RESEND 10/14 ram: stm32: add memory mapping selection support
In reply to patrice.chotard at st.comFrom: Patrice Chotard <[email protected]>
This allows to controls the memory internal mapping at address 0x0000 0000.
We can either map at 0x0000 0000 :
_ main flash memory
_ system flash memory
_ FMC bank1 (NOR/PSRAM 1 and 2)
_ embedded SRAM
_ FMC/SDRAM bank1
This is needed for future STM32F469-disco board
--- drivers/ram/stm32_sdram.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)
drivers/ram/stm32_sdram.c +25 -0
@@ -11,6 +11,9 @@#include <ram.h> #include <asm/io.h> +#define MEM_MODE_MASK GENMASK(2, 0) +#define NOT_FOUND 0xff +DECLARE_GLOBAL_DATA_PTR ;struct stm32_fmc_regs {
@@ -253,9 +256,31 @@ static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) {struct stm32_sdram_params *params =dev_get_platdata (dev);struct bank_params *bank_params; +struct ofnode_phandle_args args; +u32 *syscfg_base; +u32 mem_remap;ofnode bank_node;char *bank_name;u8 bank =0 ; +int ret; + + mem_remap =dev_read_u32_default (dev,"st,mem_remap" ,NOT_FOUND ); +if (mem_remap !=NOT_FOUND ) { + ret =dev_read_phandle_with_args (dev,"st,syscfg" ,NULL ,0 ,0 , + &args); +if (ret) { +debug ("%s: can't find syscon device (%d)\n" , __func__, + ret); +return ret; + } + + syscfg_base = (u32 *)ofnode_get_addr (args.node); + +/* set memory mapping selection */ +clrsetbits_le32 (syscfg_base,MEM_MODE_MASK , mem_remap); + }else { +debug ("%s: cannot find st,mem_remap property\n" , __func__); + }dev_for_each_subnode (bank_node, dev) {/* extract the bank index from DT */
Signature · 1 line
1.9.1
PATCH RESEND 10/14 ram: stm32: add memory mapping selection support
Quoted 11 lines · patrice.chotard at st.com
From: Patrice Chotard <[email protected]>
This allows to controls the memory internal mapping at address
0x00000000.
We can either map at0x00000000 :
_ main flash memory
_ system flash memory
_ FMC bank1 (NOR/PSRAM 1 and 2)
_ embedded SRAM
_ FMC/SDRAM bank1
Quoted 3 lines
This is needed for future STM32F469-disco board
Signed-off-by Patrice Chotard <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH RESEND 11/14 ARM: DTS: add STM32F469 Discovery board support
In reply to patrice.chotard at st.comFrom: Patrice Chotard <[email protected]>
This DT file comes from kernel v4.15-rc1
stm32f469-pinctrl.dtsi header has been updated with correct STMicroelectronics Copyright.
Remove the paragraph about writing to the Free Software Foundation's mailing address as requested by checkpatch.
--- arch/arm/dts/Makefile | 3 +- arch/arm/dts/stm32f469-disco.dts | 129 ++++++++++++++++++++++++++++++++++++ arch/arm/dts/stm32f469-pinctrl.dtsi | 97 +++++++++++++++++++++++++++ 3 files changed, 228 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/stm32f469-disco.dts create mode 100644 arch/arm/dts/stm32f469-pinctrl.dtsi
arch/arm/dts/Makefile +2 -1
@@ -213,7 +213,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb -dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb +dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \ + stm32f469-disco.dtb dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \ stm32f769-disco.dtb
arch/arm/dts/stm32f469-disco.dts new file +129 -0
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arch/arm/dts/stm32f469-pinctrl.dtsi new file +97 -0
97 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH RESEND 11/14 ARM: DTS: add STM32F469 Discovery board support
Quoted 11 lines · patrice.chotard at st.com
From: Patrice Chotard <[email protected]>
This DT file comes from kernel v4.15-rc1
stm32f469-pinctrl.dtsiheader has been updated with correct STMicroelectronics Copyright.Remove the paragraph about writing to the Free Software Foundation's mailing address as requested by checkpatch.
Signed-off-by Patrice Chotard <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH RESEND 12/14 ARM: DTS: stm32: add stm32f469-disco-u-boot dts file
In reply to patrice.chotard at st.comFrom: Patrice Chotard <[email protected]>
_ Add gpio compatible and aliases for stm32f469
_ Add FMC sdram node
_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.
--- arch/arm/dts/stm32f469-disco-u-boot.dtsi | 230 +++++++++++++++++++++++++++++++ 1 file changed, 230 insertions(+) create mode 100644 arch/arm/dts/stm32f469-disco-u-boot.dtsi
arch/arm/dts/stm32f469-disco-u-boot.dtsi new file +230 -0
@@ -0,0 +1,230 @@ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, <[email protected]> for STMicroelectronics. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/memory/stm32-sdram.h> +/{ + clocks { + u-boot,dm-pre-reloc; + }; + + aliases { + /* Aliases for gpios so as to use sequence */ + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + }; + + soc { + u-boot,dm-pre-reloc; + pin-controller { + u-boot,dm-pre-reloc; + }; + + fmc: fmc at A0000000 { + compatible = "st,stm32-fmc"; + reg = <0xA0000000 0x1000>; + clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>; + st,syscfg = <&syscfg>; + pinctrl-0 = <&fmc_pins_d32>; + pinctrl-names = "default"; + st,mem_remap = <4>; + u-boot,dm-pre-reloc; + + /* + * Memory configuration from sdram + * MICRON MT48LC4M32B2B5-6A + */ + bank0: bank at 0 { + st,sdram-control = /bits/ 8 <NO_COL_8 + NO_ROW_12 + MWIDTH_32 + BANKS_4 + CAS_3 + SDCLK_2 + RD_BURST_EN + RD_PIPE_DL_0>; + st,sdram-timing = /bits/ 8 <TMRD_2 + TXSR_6 + TRAS_4 + TRC_6 + TWR_2 + TRP_2 + TRCD_2>; + st,sdram-refcount = < 1292 >; + }; + }; + }; +}; + +&clk_hse { + u-boot,dm-pre-reloc; +}; + +&clk_lse { + u-boot,dm-pre-reloc; +}; + +&clk_i2s_ckin { + u-boot,dm-pre-reloc; +}; + +&pwrcfg { + u-boot,dm-pre-reloc; +}; + +&syscfg { + u-boot,dm-pre-reloc; +}; + +&rcc { + u-boot,dm-pre-reloc; +}; + +&gpioa { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiob { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioc { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiod { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioe { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiof { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiog { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioh { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioi { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioj { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiok { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&pinctrl { + usart3_pins_a: usart3 at 0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; + }; + + fmc_pins_d32: fmc_d32 at 0 { + u-boot,dm-pre-reloc; + pins + { + pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */ + <STM32_PINMUX('I', 9, AF12)>, /* D30 */ + <STM32_PINMUX('I', 7, AF12)>, /* D29 */ + <STM32_PINMUX('I', 6, AF12)>, /* D28 */ + <STM32_PINMUX('I', 3, AF12)>, /* D27 */ + <STM32_PINMUX('I', 2, AF12)>, /* D26 */ + <STM32_PINMUX('I', 1, AF12)>, /* D25 */ + <STM32_PINMUX('I', 0, AF12)>, /* D24 */ + <STM32_PINMUX('H',15, AF12)>, /* D23 */ + <STM32_PINMUX('H',14, AF12)>, /* D22 */ + <STM32_PINMUX('H',13, AF12)>, /* D21 */ + <STM32_PINMUX('H',12, AF12)>, /* D20 */ + <STM32_PINMUX('H',11, AF12)>, /* D19 */ + <STM32_PINMUX('H',10, AF12)>, /* D18 */ + <STM32_PINMUX('H', 9, AF12)>, /* D17 */ + <STM32_PINMUX('H', 8, AF12)>, /* D16 */ + + <STM32_PINMUX('D',10, AF12)>, /* D15 */ + <STM32_PINMUX('D', 9, AF12)>, /* D14 */ + <STM32_PINMUX('D', 8, AF12)>, /* D13 */ + <STM32_PINMUX('E',15, AF12)>, /* D12 */ + <STM32_PINMUX('E',14, AF12)>, /* D11 */ + <STM32_PINMUX('E',13, AF12)>, /* D10 */ + <STM32_PINMUX('E',12, AF12)>, /* D09 */ + <STM32_PINMUX('E',11, AF12)>, /* D08 */ + <STM32_PINMUX('E',10, AF12)>, /* D07 */ + <STM32_PINMUX('E', 9, AF12)>, /* D06 */ + <STM32_PINMUX('E', 8, AF12)>, /* D05 */ + <STM32_PINMUX('E', 7, AF12)>, /* D04 */ + <STM32_PINMUX('D', 1, AF12)>, /* D03 */ + <STM32_PINMUX('D', 0, AF12)>, /* D02 */ + <STM32_PINMUX('D',15, AF12)>, /* D01 */ + <STM32_PINMUX('D',14, AF12)>, /* D00 */ + + <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */ + <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */ + <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */ + <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */ + + <STM32_PINMUX('G', 5, AF12)>, /* BA1 */ + <STM32_PINMUX('G', 4, AF12)>, /* BA0 */ + + <STM32_PINMUX('G', 1, AF12)>, /* A11 */ + <STM32_PINMUX('G', 0, AF12)>, /* A10 */ + <STM32_PINMUX('F',15, AF12)>, /* A09 */ + <STM32_PINMUX('F',14, AF12)>, /* A08 */ + <STM32_PINMUX('F',13, AF12)>, /* A07 */ + <STM32_PINMUX('F',12, AF12)>, /* A06 */ + <STM32_PINMUX('F', 5, AF12)>, /* A05 */ + <STM32_PINMUX('F', 4, AF12)>, /* A04 */ + <STM32_PINMUX('F', 3, AF12)>, /* A03 */ + <STM32_PINMUX('F', 2, AF12)>, /* A02 */ + <STM32_PINMUX('F', 1, AF12)>, /* A01 */ + <STM32_PINMUX('F', 0, AF12)>, /* A00 */ + + <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */ + <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */ + <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */ + <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */ + <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */ + <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */ + slew-rate = <2>; + u-boot,dm-pre-reloc; + }; + }; +};
Signature · 1 line
1.9.1
PATCH RESEND 12/14 ARM: DTS: stm32: add stm32f469-disco-u-boot dts file
Quoted 10 lines · patrice.chotard at st.com
From: Patrice Chotard <[email protected]>
_ Add gpio compatible and aliases for stm32f469
_ Add FMC sdram node
_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.Signed-off-by Patrice Chotard <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH RESEND 13/14 board: stm32: add stm32f469-discovery board support
In reply to patrice.chotard at st.comFrom: Patrice Chotard <[email protected]>
This board offers :
_ STM32F469NIH6 microcontroller featuring 2 Mbytes of Flash memory
and 324 Kbytes of RAM in BGA216 package
_ On-board ST-LINK/V2-1 SWD debugger, supporting USB reenumeration capability:
_ Mbed-enabled (mbed.org)
_ USB functions: USB virtual COM port, mass storage, debug port
_ 4 inches 800x480 pixel TFT color LCD with MIPI DSI interface and capacitive
touch screen
_ SAI Audio DAC, with a stereo headphone output jack
_ 3 MEMS microphones
_ MicroSD card connector
_ I2C extension connector
_ 4Mx32bit SDRAM
_ 128-Mbit Quad-SPI NOR Flash
_ Reset and wake-up buttons
_ 4 color user LEDs
_ USB OTG FS with Micro-AB connector
_ Three power supply options:
_ Expansion connectors and Arduinoâ„¢ UNO V3 connectors
--- arch/arm/mach-stm32/stm32f4/Kconfig | 4 ++ board/st/stm32f469-discovery/Kconfig | 19 ++++++ board/st/stm32f469-discovery/MAINTAINERS | 6 ++ board/st/stm32f469-discovery/Makefile | 8 +++ board/st/stm32f469-discovery/stm32f469-discovery.c | 74 ++++++++++++++++++++++ configs/stm32f469-discovery_defconfig | 42 ++++++++++++ include/configs/stm32f469-discovery.h | 68 ++++++++++++++++++++ 7 files changed, 221 insertions(+) create mode 100644 board/st/stm32f469-discovery/Kconfig create mode 100644 board/st/stm32f469-discovery/MAINTAINERS create mode 100644 board/st/stm32f469-discovery/Makefile create mode 100644 board/st/stm32f469-discovery/stm32f469-discovery.c create mode 100644 configs/stm32f469-discovery_defconfig create mode 100644 include/configs/stm32f469-discovery.h
arch/arm/mach-stm32/stm32f4/Kconfig +4 -0
@@ -3,6 +3,10 @@ if STM32F4 config TARGET_STM32F429_DISCOVERY bool "STM32F429 Discovery board" +config TARGET_STM32F469_DISCOVERY + bool "STM32F469 Discovery board" + source "board/st/stm32f429-discovery/Kconfig" +source "board/st/stm32f469-discovery/Kconfig" endif
board/st/stm32f469-discovery/Kconfig new file +19 -0
@@ -0,0 +1,19 @@ +if TARGET_STM32F469_DISCOVERY + +config SYS_BOARD + string + default "stm32f469-discovery" + +config SYS_VENDOR + string + default "st" + +config SYS_SOC + string + default "stm32f4" + +config SYS_CONFIG_NAME + string + default "stm32f469-discovery" + +endif
board/st/stm32f469-discovery/MAINTAINERS new file +6 -0
@@ -0,0 +1,6 @@ +STM32F469-DISCOVERY BOARD +M: Patrice Chotard <[email protected]> +S: Maintained +F: board/st/stm32f469-discovery/ +F: include/configs/stm32f469-discovery.h +F: configs/stm32f469-discovery_defconfig
board/st/stm32f469-discovery/Makefile new file +8 -0
@@ -0,0 +1,8 @@ +# +# Copyright (C) STMicroelectronics SA 2017 +# Author(s): Patrice CHOTARD, <[email protected]> for STMicroelectronics. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := stm32f469-discovery.o
board/st/stm32f469-discovery/stm32f469-discovery.c new file +74 -0
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configs/stm32f469-discovery_defconfig new file +42 -0
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include/configs/stm32f469-discovery.h new file +68 -0
68 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH RESEND 13/14 board: stm32: add stm32f469-discovery board support
Quoted 23 lines · patrice.chotard at st.com
From: Patrice Chotard <[email protected]>
This board offers :
_ STM32F469NIH6 microcontroller featuring 2 Mbytes of Flash memory
and 324 Kbytes of RAM in BGA216 package
_ On-board ST-LINK/V2-1 SWD debugger, supporting USB reenumeration capability:
_ Mbed-enabled (mbed.org)
_ USB functions: USB virtual COM port, mass storage, debug port
_ 4 inches 800x480 pixel TFT color LCD with MIPI DSI interface and capacitive
touch screen
_ SAI Audio DAC, with a stereo headphone output jack
_ 3 MEMS microphones
_ MicroSD card connector
_ I2C extension connector
_ 4Mx32bit SDRAM
_ 128-Mbit Quad-SPI NOR Flash
_ Reset and wake-up buttons
_ 4 color user LEDs
_ USB OTG FS with Micro-AB connector
_ Three power supply options:
_ Expansion connectors and Arduinoâ„¢ UNO V3 connectors
Quoted 1 line
Signed-off-by Patrice Chotard <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH RESEND 14/14 ARM: DTS: stm32: add SDIO controller support for stm32f469-disco
In reply to patrice.chotard at st.comFrom: Patrice Chotard <[email protected]>
STM32F469 SoC uses an arm_pl180_mmci SDIO controller.
--- arch/arm/dts/stm32f4-pinctrl.dtsi | 31 +++++++++++++++++++++++++++++++ arch/arm/dts/stm32f429.dtsi | 12 ++++++++++++ arch/arm/dts/stm32f469-disco.dts | 16 ++++++++++++++++ 3 files changed, 59 insertions(+)
arch/arm/dts/stm32f4-pinctrl.dtsi +31 -0
@@ -339,6 +339,37 @@ slew-rate = <3>; }; }; + + sdio_pins: sdio_pins at 0 { + pins { + pinmux = <STM32_PINMUX('C', 8, AF12)>, + <STM32_PINMUX('C', 9, AF12)>, + <STM32_PINMUX('C', 10, AF12)>, + <STM32_PINMUX('c', 11, AF12)>, + <STM32_PINMUX('C', 12, AF12)>, + <STM32_PINMUX('D', 2, AF12)>; + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdio_pins_od: sdio_pins_od at 0 { + pins1 { + pinmux = <STM32_PINMUX('C', 8, AF12)>, + <STM32_PINMUX('C', 9, AF12)>, + <STM32_PINMUX('C', 10, AF12)>, + <STM32_PINMUX('C', 11, AF12)>, + <STM32_PINMUX('C', 12, AF12)>; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = <STM32_PINMUX('D', 2, AF12)>; + drive-open-drain; + slew-rate = <2>; + }; + }; }; }; };
arch/arm/dts/stm32f429.dtsi +12 -0
@@ -576,6 +576,18 @@ reg = <0x40007000 0x400>; }; + sdio: sdio at 40012c00 { + compatible = "st,stm32f4xx-sdio"; + reg = <0x40012c00 0x400>; + clocks = <&rcc 0 171>; + interrupts = <49>; + status = "disabled"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_pins_od>; + pinctrl-names = "default", "opendrain"; + max-frequency = <48000000>; + }; + ltdc: display-controller at 40016800 { compatible = "st,stm32-ltdc"; reg = <0x40016800 0x200>;
arch/arm/dts/stm32f469-disco.dts +16 -0
@@ -61,6 +61,13 @@ serial0 = &usart3; }; + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + soc { dma-ranges = <0xc0000000 0x0 0x10000000>; };
@@ -115,6 +122,15 @@ }; }; +&sdio { + status = "okay"; + vmmc-supply = <&mmc_vcard>; + pinctrl-names = "default", "opendrain"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_pins_od>; + bus-width = <4>; +}; + &usart3 { pinctrl-0 = <&usart3_pins_a>; pinctrl-names = "default";
Signature · 1 line
1.9.1
PATCH RESEND 14/14 ARM: DTS: stm32: add SDIO controller support for stm32f469-disco
Quoted 7 lines · patrice.chotard at st.com
From: Patrice Chotard <[email protected]>
STM32F469 SoC uses an
arm_pl180_mmciSDIO controller.Signed-off-by Andrea Merello <[email protected]>Signed-off-by Alexandre Torgue <[email protected]>Signed-off-by Patrice Chotard <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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