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ARM: socfpga: Convert callers of cm_write_with_phase for wait_for_bit_le32

PATCH New Tom Rini 2 participants 3 messages Jan 26, 2018

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Tom Rini

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#0 lore raw

PATCH 1/1 ARM: socfpga: Convert callers of cm_write_with_phase for wait_for_bit_le32

Now that we have and use wait_for_bit_le32() available, the callers of cm_write_with_phase() should not be casting values to u32 and instead we expect a const void *, so provide that directly.

Fixes 48263504c8d5 ("wait_bit: use wait_for_bit_le32 and remove wait_for_bit")
Cc Marek Vasut <[email protected]>
---
 arch/arm/mach-socfpga/clock_manager_gen5.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)
arch/arm/mach-socfpga/clock_manager_gen5.c +5 -5
index 3d048ba3e432..4e5b6d169371 100644
@@ -33,7 +33,7 @@ static void cm_write_ctrl(u32 val)
 }
 
 /* function to write a clock register that has phase information */
-static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask)
+static int cm_write_with_phase(u32 value, const void *reg_address, u32 mask)
 {
 	int ret;
 
@@ -268,26 +268,26 @@ int cm_basic_init(const struct cm_config * const cfg)
 	 * are aligned nicely; so we can change any phase.
 	 */
 	ret = cm_write_with_phase(cfg->ddrdqsclk,
-				  (u32)&clock_manager_base->sdr_pll.ddrdqsclk,
+				  &clock_manager_base->sdr_pll.ddrdqsclk,
 				  CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
 	if (ret)
 		return ret;
 
 	/* SDRAM DDR2XDQSCLK */
 	ret = cm_write_with_phase(cfg->ddr2xdqsclk,
-				  (u32)&clock_manager_base->sdr_pll.ddr2xdqsclk,
+				  &clock_manager_base->sdr_pll.ddr2xdqsclk,
 				  CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
 	if (ret)
 		return ret;
 
 	ret = cm_write_with_phase(cfg->ddrdqclk,
-				  (u32)&clock_manager_base->sdr_pll.ddrdqclk,
+				  &clock_manager_base->sdr_pll.ddrdqclk,
 				  CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
 	if (ret)
 		return ret;
 
 	ret = cm_write_with_phase(cfg->s2fuser2clk,
-				  (u32)&clock_manager_base->sdr_pll.s2fuser2clk,
+				  &clock_manager_base->sdr_pll.s2fuser2clk,
 				  CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
 	if (ret)
 		return ret;
Signature · 1 line
2.7.4
#1 lore raw

PATCH 1/1 ARM: socfpga: Convert callers of cm_write_with_phase for wait_for_bit_le32

Quoted 7 lines · Tom Rini

Now that we have and use wait_for_bit_le32() available, the callers of cm_write_with_phase() should not be casting values to u32 and instead we expect a const void *, so provide that directly.

Fixes 48263504c8d5 ("wait_bit: use wait_for_bit_le32 and remove wait_for_bit")
Cc Marek Vasut <[email protected]>
Quoted 49 lines
---
 arch/arm/mach-socfpga/clock_manager_gen5.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)
arch/arm/mach-socfpga/clock_manager_gen5.c +5 -5
index 3d048ba3e432..4e5b6d169371 100644
@@ -33,7 +33,7 @@ static void cm_write_ctrl(u32 val)
 }
 
 /* function to write a clock register that has phase information */
-static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask)
+static int cm_write_with_phase(u32 value, const void *reg_address, u32 mask)
 {
 	int ret;
 
@@ -268,26 +268,26 @@ int cm_basic_init(const struct cm_config * const cfg)
 	 * are aligned nicely; so we can change any phase.
 	 */
 	ret = cm_write_with_phase(cfg->ddrdqsclk,
-				  (u32)&clock_manager_base->sdr_pll.ddrdqsclk,
+				  &clock_manager_base->sdr_pll.ddrdqsclk,
 				  CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
 	if (ret)
 		return ret;
 
 	/* SDRAM DDR2XDQSCLK */
 	ret = cm_write_with_phase(cfg->ddr2xdqsclk,
-				  (u32)&clock_manager_base->sdr_pll.ddr2xdqsclk,
+				  &clock_manager_base->sdr_pll.ddr2xdqsclk,
 				  CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
 	if (ret)
 		return ret;
 
 	ret = cm_write_with_phase(cfg->ddrdqclk,
-				  (u32)&clock_manager_base->sdr_pll.ddrdqclk,
+				  &clock_manager_base->sdr_pll.ddrdqclk,
 				  CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
 	if (ret)
 		return ret;
 
 	ret = cm_write_with_phase(cfg->s2fuser2clk,
-				  (u32)&clock_manager_base->sdr_pll.s2fuser2clk,
+				  &clock_manager_base->sdr_pll.s2fuser2clk,
 				  CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
 	if (ret)
 		return ret;
Signature · 2 lines
Best regards,
Marek Vasut
author
#2 lore raw

PATCH 1/1 ARM: socfpga: Convert callers of cm_write_with_phase for wait_for_bit_le32

In reply to Tom Rini
Quoted 7 lines · Tom Rini

Now that we have and use wait_for_bit_le32() available, the callers of cm_write_with_phase() should not be casting values to u32 and instead we expect a const void *, so provide that directly.

Fixes 48263504c8d5 ("wait_bit: use wait_for_bit_le32 and remove wait_for_bit")

Applied to u-boot/master, thanks!

Signature · 8 lines
Tom
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